xhci_pci.c revision 331722 
1/*-
2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26#include <sys/cdefs.h>
27__FBSDID("$FreeBSD: stable/11/sys/dev/usb/controller/xhci_pci.c 331722 2018-03-29 02:50:57Z eadler $");
28
29#include <sys/stdint.h>
30#include <sys/stddef.h>
31#include <sys/param.h>
32#include <sys/queue.h>
33#include <sys/types.h>
34#include <sys/systm.h>
35#include <sys/kernel.h>
36#include <sys/bus.h>
37#include <sys/module.h>
38#include <sys/lock.h>
39#include <sys/mutex.h>
40#include <sys/condvar.h>
41#include <sys/sysctl.h>
42#include <sys/sx.h>
43#include <sys/unistd.h>
44#include <sys/callout.h>
45#include <sys/malloc.h>
46#include <sys/priv.h>
47
48#include <dev/usb/usb.h>
49#include <dev/usb/usbdi.h>
50
51#include <dev/usb/usb_core.h>
52#include <dev/usb/usb_busdma.h>
53#include <dev/usb/usb_process.h>
54#include <dev/usb/usb_util.h>
55
56#include <dev/usb/usb_controller.h>
57#include <dev/usb/usb_bus.h>
58#include <dev/usb/usb_pci.h>
59#include <dev/usb/controller/xhci.h>
60#include <dev/usb/controller/xhcireg.h>
61#include "usb_if.h"
62
63static device_probe_t xhci_pci_probe;
64static device_attach_t xhci_pci_attach;
65static device_detach_t xhci_pci_detach;
66static usb_take_controller_t xhci_pci_take_controller;
67
68static device_method_t xhci_device_methods[] = {
69	/* device interface */
70	DEVMETHOD(device_probe, xhci_pci_probe),
71	DEVMETHOD(device_attach, xhci_pci_attach),
72	DEVMETHOD(device_detach, xhci_pci_detach),
73	DEVMETHOD(device_suspend, bus_generic_suspend),
74	DEVMETHOD(device_resume, bus_generic_resume),
75	DEVMETHOD(device_shutdown, bus_generic_shutdown),
76	DEVMETHOD(usb_take_controller, xhci_pci_take_controller),
77
78	DEVMETHOD_END
79};
80
81static driver_t xhci_driver = {
82	.name = "xhci",
83	.methods = xhci_device_methods,
84	.size = sizeof(struct xhci_softc),
85};
86
87static devclass_t xhci_devclass;
88
89DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, NULL, NULL);
90MODULE_DEPEND(xhci, usb, 1, 1, 1);
91
92static const char *
93xhci_pci_match(device_t self)
94{
95	uint32_t device_id = pci_get_devid(self);
96
97	switch (device_id) {
98	case 0x145c1022:
99		return ("AMD KERNCZ USB 3.0 controller");
100	case 0x43bb1022:
101		return ("AMD 300 Series USB 3.0 controller");
102	case 0x78141022:
103		return ("AMD FCH USB 3.0 controller");
104
105	case 0x01941033:
106		return ("NEC uPD720200 USB 3.0 controller");
107	case 0x00151912:
108		return ("NEC uPD720202 USB 3.0 controller");
109
110	case 0x10001b73:
111		return ("Fresco Logic FL1000G USB 3.0 controller");
112
113	case 0x10421b21:
114		return ("ASMedia ASM1042 USB 3.0 controller");
115	case 0x11421b21:
116		return ("ASMedia ASM1042A USB 3.0 controller");
117
118	case 0x0f358086:
119		return ("Intel BayTrail USB 3.0 controller");
120	case 0x19d08086:
121		return ("Intel Denverton USB 3.0 controller");
122	case 0x9c318086:
123	case 0x1e318086:
124		return ("Intel Panther Point USB 3.0 controller");
125	case 0x22b58086:
126		return ("Intel Braswell USB 3.0 controller");
127	case 0x5aa88086:
128		return ("Intel Apollo Lake USB 3.0 controller");
129	case 0x8c318086:
130		return ("Intel Lynx Point USB 3.0 controller");
131	case 0x8cb18086:
132		return ("Intel Wildcat Point USB 3.0 controller");
133	case 0x8d318086:
134		return ("Intel Wellsburg USB 3.0 controller");
135	case 0x9cb18086:
136		return ("Broadwell Integrated PCH-LP chipset USB 3.0 controller");
137	case 0x9d2f8086:
138		return ("Intel Sunrise Point-LP USB 3.0 controller");
139	case 0xa12f8086:
140		return ("Intel Sunrise Point USB 3.0 controller");
141	case 0xa1af8086:
142		return ("Intel Lewisburg USB 3.0 controller");
143	case 0xa2af8086:
144		return ("Intel Union Point USB 3.0 controller");
145
146	case 0xa01b177d:
147		return ("Cavium ThunderX USB 3.0 controller");
148
149	default:
150		break;
151	}
152
153	if ((pci_get_class(self) == PCIC_SERIALBUS)
154	    && (pci_get_subclass(self) == PCIS_SERIALBUS_USB)
155	    && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) {
156		return ("XHCI (generic) USB 3.0 controller");
157	}
158	return (NULL);			/* dunno */
159}
160
161static int
162xhci_pci_probe(device_t self)
163{
164	const char *desc = xhci_pci_match(self);
165
166	if (desc) {
167		device_set_desc(self, desc);
168		return (BUS_PROBE_DEFAULT);
169	} else {
170		return (ENXIO);
171	}
172}
173
174static int xhci_use_msi = 1;
175TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi);
176static int xhci_use_msix = 1;
177TUNABLE_INT("hw.usb.xhci.msix", &xhci_use_msix);
178
179static void
180xhci_interrupt_poll(void *_sc)
181{
182	struct xhci_softc *sc = _sc;
183	USB_BUS_UNLOCK(&sc->sc_bus);
184	xhci_interrupt(sc);
185	USB_BUS_LOCK(&sc->sc_bus);
186	usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc);
187}
188
189static int
190xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear)
191{
192	uint32_t temp;
193	uint32_t usb3_mask;
194	uint32_t usb2_mask;
195
196	temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) |
197	    pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4);
198
199	temp |= set;
200	temp &= ~clear;
201
202	/* Don't set bits which the hardware doesn't support */
203	usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4);
204	usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4);
205
206	pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4);
207	pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4);
208
209	device_printf(self, "Port routing mask set to 0x%08x\n", temp);
210
211	return (0);
212}
213
214static int
215xhci_pci_attach(device_t self)
216{
217	struct xhci_softc *sc = device_get_softc(self);
218	int count, err, msix_table, rid;
219	uint8_t usemsi = 1;
220	uint8_t usedma32 = 0;
221
222	rid = PCI_XHCI_CBMEM;
223	sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
224	    RF_ACTIVE);
225	if (!sc->sc_io_res) {
226		device_printf(self, "Could not map memory\n");
227		return (ENOMEM);
228	}
229	sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
230	sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
231	sc->sc_io_size = rman_get_size(sc->sc_io_res);
232
233	switch (pci_get_devid(self)) {
234	case 0x01941033:	/* NEC uPD720200 USB 3.0 controller */
235	case 0x00141912:	/* NEC uPD720201 USB 3.0 controller */
236		/* Don't use 64-bit DMA on these controllers. */
237		usedma32 = 1;
238		break;
239	case 0x10001b73:	/* FL1000G */
240		/* Fresco Logic host doesn't support MSI. */
241		usemsi = 0;
242		break;
243	case 0x0f358086:	/* BayTrail */
244	case 0x9c318086:	/* Panther Point */
245	case 0x1e318086:	/* Panther Point */
246	case 0x8c318086:	/* Lynx Point */
247	case 0x8cb18086:	/* Wildcat Point */
248	case 0x9cb18086:	/* Broadwell Mobile Integrated */
249		/*
250		 * On Intel chipsets, reroute ports from EHCI to XHCI
251		 * controller and use a different IMOD value.
252		 */
253		sc->sc_port_route = &xhci_pci_port_route;
254		sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP;
255		break;
256	}
257
258	if (xhci_init(sc, self, usedma32)) {
259		device_printf(self, "Could not initialize softc\n");
260		bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
261		    sc->sc_io_res);
262		return (ENXIO);
263	}
264
265	pci_enable_busmaster(self);
266
267	usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0);
268
269	rid = 0;
270	if (xhci_use_msix && (msix_table = pci_msix_table_bar(self)) >= 0) {
271		sc->sc_msix_res = bus_alloc_resource_any(self, SYS_RES_MEMORY,
272		    &msix_table, RF_ACTIVE);
273		if (sc->sc_msix_res == NULL) {
274			/* May not be enabled */
275			device_printf(self,
276			    "Unable to map MSI-X table \n");
277		} else {
278			count = 1;
279			if (pci_alloc_msix(self, &count) == 0) {
280				if (bootverbose)
281					device_printf(self, "MSI-X enabled\n");
282				rid = 1;
283			} else {
284				bus_release_resource(self, SYS_RES_MEMORY,
285				    msix_table, sc->sc_msix_res);
286				sc->sc_msix_res = NULL;
287			}
288		}
289	}
290	if (rid == 0 && xhci_use_msi && usemsi) {
291		count = 1;
292		if (pci_alloc_msi(self, &count) == 0) {
293			if (bootverbose)
294				device_printf(self, "MSI enabled\n");
295			rid = 1;
296		}
297	}
298	sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
299	    RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
300	if (sc->sc_irq_res == NULL) {
301		pci_release_msi(self);
302		device_printf(self, "Could not allocate IRQ\n");
303		/* goto error; FALLTHROUGH - use polling */
304	}
305	sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
306	if (sc->sc_bus.bdev == NULL) {
307		device_printf(self, "Could not add USB device\n");
308		goto error;
309	}
310	device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
311
312	sprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self));
313
314	if (sc->sc_irq_res != NULL) {
315		err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
316		    NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl);
317		if (err != 0) {
318			bus_release_resource(self, SYS_RES_IRQ,
319			    rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
320			sc->sc_irq_res = NULL;
321			pci_release_msi(self);
322			device_printf(self, "Could not setup IRQ, err=%d\n", err);
323			sc->sc_intr_hdl = NULL;
324		}
325	}
326	if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) {
327		if (xhci_use_polling() != 0) {
328			device_printf(self, "Interrupt polling at %dHz\n", hz);
329			USB_BUS_LOCK(&sc->sc_bus);
330			xhci_interrupt_poll(sc);
331			USB_BUS_UNLOCK(&sc->sc_bus);
332		} else
333			goto error;
334	}
335
336	xhci_pci_take_controller(self);
337
338	err = xhci_halt_controller(sc);
339
340	if (err == 0)
341		err = xhci_start_controller(sc);
342
343	if (err == 0)
344		err = device_probe_and_attach(sc->sc_bus.bdev);
345
346	if (err) {
347		device_printf(self, "XHCI halt/start/probe failed err=%d\n", err);
348		goto error;
349	}
350	return (0);
351
352error:
353	xhci_pci_detach(self);
354	return (ENXIO);
355}
356
357static int
358xhci_pci_detach(device_t self)
359{
360	struct xhci_softc *sc = device_get_softc(self);
361
362	/* during module unload there are lots of children leftover */
363	device_delete_children(self);
364
365	usb_callout_drain(&sc->sc_callout);
366	xhci_halt_controller(sc);
367	xhci_reset_controller(sc);
368
369	pci_disable_busmaster(self);
370
371	if (sc->sc_irq_res && sc->sc_intr_hdl) {
372		bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
373		sc->sc_intr_hdl = NULL;
374	}
375	if (sc->sc_irq_res) {
376		bus_release_resource(self, SYS_RES_IRQ,
377		    rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
378		sc->sc_irq_res = NULL;
379		pci_release_msi(self);
380	}
381	if (sc->sc_io_res) {
382		bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
383		    sc->sc_io_res);
384		sc->sc_io_res = NULL;
385	}
386	if (sc->sc_msix_res) {
387		bus_release_resource(self, SYS_RES_MEMORY,
388		    rman_get_rid(sc->sc_msix_res), sc->sc_msix_res);
389		sc->sc_msix_res = NULL;
390	}
391
392	xhci_uninit(sc);
393
394	return (0);
395}
396
397static int
398xhci_pci_take_controller(device_t self)
399{
400	struct xhci_softc *sc = device_get_softc(self);
401	uint32_t cparams;
402	uint32_t eecp;
403	uint32_t eec;
404	uint16_t to;
405	uint8_t bios_sem;
406
407	cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0);
408
409	eec = -1;
410
411	/* Synchronise with the BIOS if it owns the controller. */
412	for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
413	    eecp += XHCI_XECP_NEXT(eec) << 2) {
414		eec = XREAD4(sc, capa, eecp);
415
416		if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
417			continue;
418		bios_sem = XREAD1(sc, capa, eecp +
419		    XHCI_XECP_BIOS_SEM);
420		if (bios_sem == 0)
421			continue;
422		device_printf(sc->sc_bus.bdev, "waiting for BIOS "
423		    "to give up control\n");
424		XWRITE1(sc, capa, eecp +
425		    XHCI_XECP_OS_SEM, 1);
426		to = 500;
427		while (1) {
428			bios_sem = XREAD1(sc, capa, eecp +
429			    XHCI_XECP_BIOS_SEM);
430			if (bios_sem == 0)
431				break;
432
433			if (--to == 0) {
434				device_printf(sc->sc_bus.bdev,
435				    "timed out waiting for BIOS\n");
436				break;
437			}
438			usb_pause_mtx(NULL, hz / 100);	/* wait 10ms */
439		}
440	}
441	return (0);
442}
443