bus_space_generic.c revision 330897 
1/*	$NetBSD: obio_space.c,v 1.6 2003/07/15 00:25:05 lukem Exp $	*/
2
3/*-
4 * SPDX-License-Identifier: BSD-4-Clause
5 *
6 * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
7 * All rights reserved.
8 *
9 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 *    notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 *    notice, this list of conditions and the following disclaimer in the
18 *    documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 *    must display the following acknowledgement:
21 *	This product includes software developed for the NetBSD Project by
22 *	Wasabi Systems, Inc.
23 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
24 *    or promote products derived from this software without specific prior
25 *    written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40#include <sys/cdefs.h>
41__FBSDID("$FreeBSD: stable/11/sys/arm/arm/bus_space_generic.c 330897 2018-03-14 03:19:51Z eadler $");
42
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/bus.h>
46#include <sys/kernel.h>
47#include <sys/malloc.h>
48#include <sys/devmap.h>
49
50#include <vm/vm.h>
51#include <vm/pmap.h>
52#include <vm/vm_kern.h>
53#include <vm/vm_extern.h>
54
55#include <machine/bus.h>
56#include <machine/cpufunc.h>
57
58void
59generic_bs_unimplemented(void)
60{
61
62	panic("unimplemented bus_space function called");
63}
64
65/* Prototypes for all the bus_space structure functions */
66bs_protos(generic);
67
68int
69generic_bs_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size, int flags,
70    bus_space_handle_t *bshp)
71{
72	void *va;
73
74	/*
75	 * We don't even examine the passed-in flags.  For ARM, the CACHEABLE
76	 * flag doesn't make sense (we create VM_MEMATTR_DEVICE mappings), and
77	 * the LINEAR flag is just implied because we use kva_alloc(size).
78	 */
79	if ((va = pmap_mapdev(bpa, size)) == NULL)
80		return (ENOMEM);
81	*bshp = (bus_space_handle_t)va;
82	return (0);
83}
84
85int
86generic_bs_alloc(bus_space_tag_t t, bus_addr_t rstart, bus_addr_t rend, bus_size_t size,
87    bus_size_t alignment, bus_size_t boundary, int flags, bus_addr_t *bpap,
88    bus_space_handle_t *bshp)
89{
90
91	panic("generic_bs_alloc(): not implemented");
92}
93
94
95void
96generic_bs_unmap(bus_space_tag_t t, bus_space_handle_t h, bus_size_t size)
97{
98
99	pmap_unmapdev((vm_offset_t)h, size);
100}
101
102void
103generic_bs_free(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size)
104{
105
106	panic("generic_bs_free(): not implemented");
107}
108
109int
110generic_bs_subregion(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t offset,
111    bus_size_t size, bus_space_handle_t *nbshp)
112{
113
114	*nbshp = bsh + offset;
115	return (0);
116}
117
118void
119generic_bs_barrier(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t offset,
120    bus_size_t len, int flags)
121{
122
123	/*
124	 * dsb() will drain the L1 write buffer and establish a memory access
125	 * barrier point on platforms where that has meaning.  On a write we
126	 * also need to drain the L2 write buffer, because most on-chip memory
127	 * mapped devices are downstream of the L2 cache.  Note that this needs
128	 * to be done even for memory mapped as Device type, because while
129	 * Device memory is not cached, writes to it are still buffered.
130	 */
131	dsb();
132	if (flags & BUS_SPACE_BARRIER_WRITE) {
133		cpu_l2cache_drain_writebuf();
134	}
135}
136