if_lge.c revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2000, 2001 6 * Bill Paul <william.paul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36#include <sys/cdefs.h> 37__FBSDID("$FreeBSD: stable/11/sys/dev/lge/if_lge.c 330897 2018-03-14 03:19:51Z eadler $"); 38 39/* 40 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 41 * documentation not available, but ask me nicely. 42 * 43 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 44 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 45 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 46 * are three supported methods for data transfer between host and 47 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 48 * Propulsion Technology (tm) DMA. The latter mechanism is a form 49 * of double buffer DMA where the packet data is copied to a 50 * pre-allocated DMA buffer who's physical address has been loaded 51 * into a table at device initialization time. The rationale is that 52 * the virtual to physical address translation needed for normal 53 * scatter/gather DMA is more expensive than the data copy needed 54 * for double buffering. This may be true in Windows NT and the like, 55 * but it isn't true for us, at least on the x86 arch. This driver 56 * uses the scatter/gather I/O method for both TX and RX. 57 * 58 * The LXT1001 only supports TCP/IP checksum offload on receive. 59 * Also, the VLAN tagging is done using a 16-entry table which allows 60 * the chip to perform hardware filtering based on VLAN tags. Sadly, 61 * our vlan support doesn't currently play well with this kind of 62 * hardware support. 63 * 64 * Special thanks to: 65 * - Jeff James at Intel, for arranging to have the LXT1001 manual 66 * released (at long last) 67 * - Beny Chen at D-Link, for actually sending it to me 68 * - Brad Short and Keith Alexis at SMC, for sending me sample 69 * SMC9462SX and SMC9462TX adapters for testing 70 * - Paul Saab at Y!, for not killing me (though it remains to be seen 71 * if in fact he did me much of a favor) 72 */ 73 74#include <sys/param.h> 75#include <sys/systm.h> 76#include <sys/sockio.h> 77#include <sys/mbuf.h> 78#include <sys/malloc.h> 79#include <sys/kernel.h> 80#include <sys/module.h> 81#include <sys/socket.h> 82 83#include <net/if.h> 84#include <net/if_var.h> 85#include <net/if_arp.h> 86#include <net/ethernet.h> 87#include <net/if_dl.h> 88#include <net/if_media.h> 89#include <net/if_types.h> 90 91#include <net/bpf.h> 92 93#include <vm/vm.h> /* for vtophys */ 94#include <vm/pmap.h> /* for vtophys */ 95#include <machine/bus.h> 96#include <machine/resource.h> 97#include <sys/bus.h> 98#include <sys/rman.h> 99 100#include <dev/mii/mii.h> 101#include <dev/mii/miivar.h> 102 103#include <dev/pci/pcireg.h> 104#include <dev/pci/pcivar.h> 105 106#define LGE_USEIOSPACE 107 108#include <dev/lge/if_lgereg.h> 109 110/* "device miibus" required. See GENERIC if you get errors here. */ 111#include "miibus_if.h" 112 113/* 114 * Various supported device vendors/types and their names. 115 */ 116static const struct lge_type lge_devs[] = { 117 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 118 { 0, 0, NULL } 119}; 120 121static int lge_probe(device_t); 122static int lge_attach(device_t); 123static int lge_detach(device_t); 124 125static int lge_alloc_jumbo_mem(struct lge_softc *); 126static void lge_free_jumbo_mem(struct lge_softc *); 127static void *lge_jalloc(struct lge_softc *); 128static void lge_jfree(struct mbuf *, void *, void *); 129 130static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *); 131static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 132static void lge_rxeof(struct lge_softc *, int); 133static void lge_rxeoc(struct lge_softc *); 134static void lge_txeof(struct lge_softc *); 135static void lge_intr(void *); 136static void lge_tick(void *); 137static void lge_start(struct ifnet *); 138static void lge_start_locked(struct ifnet *); 139static int lge_ioctl(struct ifnet *, u_long, caddr_t); 140static void lge_init(void *); 141static void lge_init_locked(struct lge_softc *); 142static void lge_stop(struct lge_softc *); 143static void lge_watchdog(struct lge_softc *); 144static int lge_shutdown(device_t); 145static int lge_ifmedia_upd(struct ifnet *); 146static void lge_ifmedia_upd_locked(struct ifnet *); 147static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 148 149static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 150static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 151 152static int lge_miibus_readreg(device_t, int, int); 153static int lge_miibus_writereg(device_t, int, int, int); 154static void lge_miibus_statchg(device_t); 155 156static void lge_setmulti(struct lge_softc *); 157static void lge_reset(struct lge_softc *); 158static int lge_list_rx_init(struct lge_softc *); 159static int lge_list_tx_init(struct lge_softc *); 160 161#ifdef LGE_USEIOSPACE 162#define LGE_RES SYS_RES_IOPORT 163#define LGE_RID LGE_PCI_LOIO 164#else 165#define LGE_RES SYS_RES_MEMORY 166#define LGE_RID LGE_PCI_LOMEM 167#endif 168 169static device_method_t lge_methods[] = { 170 /* Device interface */ 171 DEVMETHOD(device_probe, lge_probe), 172 DEVMETHOD(device_attach, lge_attach), 173 DEVMETHOD(device_detach, lge_detach), 174 DEVMETHOD(device_shutdown, lge_shutdown), 175 176 /* MII interface */ 177 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 178 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 179 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 180 181 DEVMETHOD_END 182}; 183 184static driver_t lge_driver = { 185 "lge", 186 lge_methods, 187 sizeof(struct lge_softc) 188}; 189 190static devclass_t lge_devclass; 191 192DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0); 193DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 194MODULE_DEPEND(lge, pci, 1, 1, 1); 195MODULE_DEPEND(lge, ether, 1, 1, 1); 196MODULE_DEPEND(lge, miibus, 1, 1, 1); 197 198#define LGE_SETBIT(sc, reg, x) \ 199 CSR_WRITE_4(sc, reg, \ 200 CSR_READ_4(sc, reg) | (x)) 201 202#define LGE_CLRBIT(sc, reg, x) \ 203 CSR_WRITE_4(sc, reg, \ 204 CSR_READ_4(sc, reg) & ~(x)) 205 206#define SIO_SET(x) \ 207 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 208 209#define SIO_CLR(x) \ 210 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 211 212/* 213 * Read a word of data stored in the EEPROM at address 'addr.' 214 */ 215static void 216lge_eeprom_getword(sc, addr, dest) 217 struct lge_softc *sc; 218 int addr; 219 u_int16_t *dest; 220{ 221 register int i; 222 u_int32_t val; 223 224 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 225 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 226 227 for (i = 0; i < LGE_TIMEOUT; i++) 228 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 229 break; 230 231 if (i == LGE_TIMEOUT) { 232 device_printf(sc->lge_dev, "EEPROM read timed out\n"); 233 return; 234 } 235 236 val = CSR_READ_4(sc, LGE_EEDATA); 237 238 if (addr & 1) 239 *dest = (val >> 16) & 0xFFFF; 240 else 241 *dest = val & 0xFFFF; 242 243 return; 244} 245 246/* 247 * Read a sequence of words from the EEPROM. 248 */ 249static void 250lge_read_eeprom(sc, dest, off, cnt, swap) 251 struct lge_softc *sc; 252 caddr_t dest; 253 int off; 254 int cnt; 255 int swap; 256{ 257 int i; 258 u_int16_t word = 0, *ptr; 259 260 for (i = 0; i < cnt; i++) { 261 lge_eeprom_getword(sc, off + i, &word); 262 ptr = (u_int16_t *)(dest + (i * 2)); 263 if (swap) 264 *ptr = ntohs(word); 265 else 266 *ptr = word; 267 } 268 269 return; 270} 271 272static int 273lge_miibus_readreg(dev, phy, reg) 274 device_t dev; 275 int phy, reg; 276{ 277 struct lge_softc *sc; 278 int i; 279 280 sc = device_get_softc(dev); 281 282 /* 283 * If we have a non-PCS PHY, pretend that the internal 284 * autoneg stuff at PHY address 0 isn't there so that 285 * the miibus code will find only the GMII PHY. 286 */ 287 if (sc->lge_pcs == 0 && phy == 0) 288 return(0); 289 290 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 291 292 for (i = 0; i < LGE_TIMEOUT; i++) 293 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 294 break; 295 296 if (i == LGE_TIMEOUT) { 297 device_printf(sc->lge_dev, "PHY read timed out\n"); 298 return(0); 299 } 300 301 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 302} 303 304static int 305lge_miibus_writereg(dev, phy, reg, data) 306 device_t dev; 307 int phy, reg, data; 308{ 309 struct lge_softc *sc; 310 int i; 311 312 sc = device_get_softc(dev); 313 314 CSR_WRITE_4(sc, LGE_GMIICTL, 315 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 316 317 for (i = 0; i < LGE_TIMEOUT; i++) 318 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 319 break; 320 321 if (i == LGE_TIMEOUT) { 322 device_printf(sc->lge_dev, "PHY write timed out\n"); 323 return(0); 324 } 325 326 return(0); 327} 328 329static void 330lge_miibus_statchg(dev) 331 device_t dev; 332{ 333 struct lge_softc *sc; 334 struct mii_data *mii; 335 336 sc = device_get_softc(dev); 337 mii = device_get_softc(sc->lge_miibus); 338 339 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 340 switch (IFM_SUBTYPE(mii->mii_media_active)) { 341 case IFM_1000_T: 342 case IFM_1000_SX: 343 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 344 break; 345 case IFM_100_TX: 346 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 347 break; 348 case IFM_10_T: 349 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 350 break; 351 default: 352 /* 353 * Choose something, even if it's wrong. Clearing 354 * all the bits will hose autoneg on the internal 355 * PHY. 356 */ 357 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 358 break; 359 } 360 361 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 362 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 363 } else { 364 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 365 } 366 367 return; 368} 369 370static void 371lge_setmulti(sc) 372 struct lge_softc *sc; 373{ 374 struct ifnet *ifp; 375 struct ifmultiaddr *ifma; 376 u_int32_t h = 0, hashes[2] = { 0, 0 }; 377 378 ifp = sc->lge_ifp; 379 LGE_LOCK_ASSERT(sc); 380 381 /* Make sure multicast hash table is enabled. */ 382 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 383 384 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 385 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 386 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 387 return; 388 } 389 390 /* first, zot all the existing hash bits */ 391 CSR_WRITE_4(sc, LGE_MAR0, 0); 392 CSR_WRITE_4(sc, LGE_MAR1, 0); 393 394 /* now program new ones */ 395 if_maddr_rlock(ifp); 396 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 397 if (ifma->ifma_addr->sa_family != AF_LINK) 398 continue; 399 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 400 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 401 if (h < 32) 402 hashes[0] |= (1 << h); 403 else 404 hashes[1] |= (1 << (h - 32)); 405 } 406 if_maddr_runlock(ifp); 407 408 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 409 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 410 411 return; 412} 413 414static void 415lge_reset(sc) 416 struct lge_softc *sc; 417{ 418 register int i; 419 420 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 421 422 for (i = 0; i < LGE_TIMEOUT; i++) { 423 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 424 break; 425 } 426 427 if (i == LGE_TIMEOUT) 428 device_printf(sc->lge_dev, "reset never completed\n"); 429 430 /* Wait a little while for the chip to get its brains in order. */ 431 DELAY(1000); 432 433 return; 434} 435 436/* 437 * Probe for a Level 1 chip. Check the PCI vendor and device 438 * IDs against our list and return a device name if we find a match. 439 */ 440static int 441lge_probe(dev) 442 device_t dev; 443{ 444 const struct lge_type *t; 445 446 t = lge_devs; 447 448 while(t->lge_name != NULL) { 449 if ((pci_get_vendor(dev) == t->lge_vid) && 450 (pci_get_device(dev) == t->lge_did)) { 451 device_set_desc(dev, t->lge_name); 452 return(BUS_PROBE_DEFAULT); 453 } 454 t++; 455 } 456 457 return(ENXIO); 458} 459 460/* 461 * Attach the interface. Allocate softc structures, do ifmedia 462 * setup and ethernet/BPF attach. 463 */ 464static int 465lge_attach(dev) 466 device_t dev; 467{ 468 u_char eaddr[ETHER_ADDR_LEN]; 469 struct lge_softc *sc; 470 struct ifnet *ifp = NULL; 471 int error = 0, rid; 472 473 sc = device_get_softc(dev); 474 sc->lge_dev = dev; 475 476 mtx_init(&sc->lge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 477 MTX_DEF); 478 callout_init_mtx(&sc->lge_stat_callout, &sc->lge_mtx, 0); 479 480 /* 481 * Map control/status registers. 482 */ 483 pci_enable_busmaster(dev); 484 485 rid = LGE_RID; 486 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE); 487 488 if (sc->lge_res == NULL) { 489 device_printf(dev, "couldn't map ports/memory\n"); 490 error = ENXIO; 491 goto fail; 492 } 493 494 sc->lge_btag = rman_get_bustag(sc->lge_res); 495 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 496 497 /* Allocate interrupt */ 498 rid = 0; 499 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 500 RF_SHAREABLE | RF_ACTIVE); 501 502 if (sc->lge_irq == NULL) { 503 device_printf(dev, "couldn't map interrupt\n"); 504 error = ENXIO; 505 goto fail; 506 } 507 508 /* Reset the adapter. */ 509 lge_reset(sc); 510 511 /* 512 * Get station address from the EEPROM. 513 */ 514 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 515 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 516 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 517 518 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 519 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 520 521 if (sc->lge_ldata == NULL) { 522 device_printf(dev, "no memory for list buffers!\n"); 523 error = ENXIO; 524 goto fail; 525 } 526 527 /* Try to allocate memory for jumbo buffers. */ 528 if (lge_alloc_jumbo_mem(sc)) { 529 device_printf(dev, "jumbo buffer allocation failed\n"); 530 error = ENXIO; 531 goto fail; 532 } 533 534 ifp = sc->lge_ifp = if_alloc(IFT_ETHER); 535 if (ifp == NULL) { 536 device_printf(dev, "can not if_alloc()\n"); 537 error = ENOSPC; 538 goto fail; 539 } 540 ifp->if_softc = sc; 541 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 542 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 543 ifp->if_ioctl = lge_ioctl; 544 ifp->if_start = lge_start; 545 ifp->if_init = lge_init; 546 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 547 ifp->if_capabilities = IFCAP_RXCSUM; 548 ifp->if_capenable = ifp->if_capabilities; 549 550 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 551 sc->lge_pcs = 1; 552 else 553 sc->lge_pcs = 0; 554 555 /* 556 * Do MII setup. 557 */ 558 error = mii_attach(dev, &sc->lge_miibus, ifp, lge_ifmedia_upd, 559 lge_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 560 if (error != 0) { 561 device_printf(dev, "attaching PHYs failed\n"); 562 goto fail; 563 } 564 565 /* 566 * Call MI attach routine. 567 */ 568 ether_ifattach(ifp, eaddr); 569 570 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET | INTR_MPSAFE, 571 NULL, lge_intr, sc, &sc->lge_intrhand); 572 573 if (error) { 574 ether_ifdetach(ifp); 575 device_printf(dev, "couldn't set up irq\n"); 576 goto fail; 577 } 578 return (0); 579 580fail: 581 lge_free_jumbo_mem(sc); 582 if (sc->lge_ldata) 583 contigfree(sc->lge_ldata, 584 sizeof(struct lge_list_data), M_DEVBUF); 585 if (ifp) 586 if_free(ifp); 587 if (sc->lge_irq) 588 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 589 if (sc->lge_res) 590 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 591 mtx_destroy(&sc->lge_mtx); 592 return(error); 593} 594 595static int 596lge_detach(dev) 597 device_t dev; 598{ 599 struct lge_softc *sc; 600 struct ifnet *ifp; 601 602 sc = device_get_softc(dev); 603 ifp = sc->lge_ifp; 604 605 LGE_LOCK(sc); 606 lge_reset(sc); 607 lge_stop(sc); 608 LGE_UNLOCK(sc); 609 callout_drain(&sc->lge_stat_callout); 610 ether_ifdetach(ifp); 611 612 bus_generic_detach(dev); 613 device_delete_child(dev, sc->lge_miibus); 614 615 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 616 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 617 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 618 619 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 620 if_free(ifp); 621 lge_free_jumbo_mem(sc); 622 mtx_destroy(&sc->lge_mtx); 623 624 return(0); 625} 626 627/* 628 * Initialize the transmit descriptors. 629 */ 630static int 631lge_list_tx_init(sc) 632 struct lge_softc *sc; 633{ 634 struct lge_list_data *ld; 635 struct lge_ring_data *cd; 636 int i; 637 638 cd = &sc->lge_cdata; 639 ld = sc->lge_ldata; 640 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 641 ld->lge_tx_list[i].lge_mbuf = NULL; 642 ld->lge_tx_list[i].lge_ctl = 0; 643 } 644 645 cd->lge_tx_prod = cd->lge_tx_cons = 0; 646 647 return(0); 648} 649 650 651/* 652 * Initialize the RX descriptors and allocate mbufs for them. Note that 653 * we arralge the descriptors in a closed ring, so that the last descriptor 654 * points back to the first. 655 */ 656static int 657lge_list_rx_init(sc) 658 struct lge_softc *sc; 659{ 660 struct lge_list_data *ld; 661 struct lge_ring_data *cd; 662 int i; 663 664 ld = sc->lge_ldata; 665 cd = &sc->lge_cdata; 666 667 cd->lge_rx_prod = cd->lge_rx_cons = 0; 668 669 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 670 671 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 672 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 673 break; 674 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 675 return(ENOBUFS); 676 } 677 678 /* Clear possible 'rx command queue empty' interrupt. */ 679 CSR_READ_4(sc, LGE_ISR); 680 681 return(0); 682} 683 684/* 685 * Initialize an RX descriptor and attach an MBUF cluster. 686 */ 687static int 688lge_newbuf(sc, c, m) 689 struct lge_softc *sc; 690 struct lge_rx_desc *c; 691 struct mbuf *m; 692{ 693 struct mbuf *m_new = NULL; 694 caddr_t *buf = NULL; 695 696 if (m == NULL) { 697 MGETHDR(m_new, M_NOWAIT, MT_DATA); 698 if (m_new == NULL) { 699 device_printf(sc->lge_dev, "no memory for rx list " 700 "-- packet dropped!\n"); 701 return(ENOBUFS); 702 } 703 704 /* Allocate the jumbo buffer */ 705 buf = lge_jalloc(sc); 706 if (buf == NULL) { 707#ifdef LGE_VERBOSE 708 device_printf(sc->lge_dev, "jumbo allocation failed " 709 "-- packet dropped!\n"); 710#endif 711 m_freem(m_new); 712 return(ENOBUFS); 713 } 714 /* Attach the buffer to the mbuf */ 715 m_new->m_data = (void *)buf; 716 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 717 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, 718 buf, (struct lge_softc *)sc, 0, EXT_NET_DRV); 719 } else { 720 m_new = m; 721 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 722 m_new->m_data = m_new->m_ext.ext_buf; 723 } 724 725 /* 726 * Adjust alignment so packet payload begins on a 727 * longword boundary. Mandatory for Alpha, useful on 728 * x86 too. 729 */ 730 m_adj(m_new, ETHER_ALIGN); 731 732 c->lge_mbuf = m_new; 733 c->lge_fragptr_hi = 0; 734 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 735 c->lge_fraglen = m_new->m_len; 736 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 737 c->lge_sts = 0; 738 739 /* 740 * Put this buffer in the RX command FIFO. To do this, 741 * we just write the physical address of the descriptor 742 * into the RX descriptor address registers. Note that 743 * there are two registers, one high DWORD and one low 744 * DWORD, which lets us specify a 64-bit address if 745 * desired. We only use a 32-bit address for now. 746 * Writing to the low DWORD register is what actually 747 * causes the command to be issued, so we do that 748 * last. 749 */ 750 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 751 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 752 753 return(0); 754} 755 756static int 757lge_alloc_jumbo_mem(sc) 758 struct lge_softc *sc; 759{ 760 caddr_t ptr; 761 register int i; 762 struct lge_jpool_entry *entry; 763 764 /* Grab a big chunk o' storage. */ 765 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 766 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 767 768 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 769 device_printf(sc->lge_dev, "no memory for jumbo buffers!\n"); 770 return(ENOBUFS); 771 } 772 773 SLIST_INIT(&sc->lge_jfree_listhead); 774 SLIST_INIT(&sc->lge_jinuse_listhead); 775 776 /* 777 * Now divide it up into 9K pieces and save the addresses 778 * in an array. 779 */ 780 ptr = sc->lge_cdata.lge_jumbo_buf; 781 for (i = 0; i < LGE_JSLOTS; i++) { 782 sc->lge_cdata.lge_jslots[i] = ptr; 783 ptr += LGE_JLEN; 784 entry = malloc(sizeof(struct lge_jpool_entry), 785 M_DEVBUF, M_NOWAIT); 786 if (entry == NULL) { 787 device_printf(sc->lge_dev, "no memory for jumbo " 788 "buffer queue!\n"); 789 return(ENOBUFS); 790 } 791 entry->slot = i; 792 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 793 entry, jpool_entries); 794 } 795 796 return(0); 797} 798 799static void 800lge_free_jumbo_mem(sc) 801 struct lge_softc *sc; 802{ 803 struct lge_jpool_entry *entry; 804 805 if (sc->lge_cdata.lge_jumbo_buf == NULL) 806 return; 807 808 while ((entry = SLIST_FIRST(&sc->lge_jinuse_listhead))) { 809 device_printf(sc->lge_dev, 810 "asked to free buffer that is in use!\n"); 811 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 812 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, 813 jpool_entries); 814 } 815 while (!SLIST_EMPTY(&sc->lge_jfree_listhead)) { 816 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 817 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 818 free(entry, M_DEVBUF); 819 } 820 821 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 822 823 return; 824} 825 826/* 827 * Allocate a jumbo buffer. 828 */ 829static void * 830lge_jalloc(sc) 831 struct lge_softc *sc; 832{ 833 struct lge_jpool_entry *entry; 834 835 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 836 837 if (entry == NULL) { 838#ifdef LGE_VERBOSE 839 device_printf(sc->lge_dev, "no free jumbo buffers\n"); 840#endif 841 return(NULL); 842 } 843 844 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 845 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 846 return(sc->lge_cdata.lge_jslots[entry->slot]); 847} 848 849/* 850 * Release a jumbo buffer. 851 */ 852static void 853lge_jfree(struct mbuf *m, void *buf, void *args) 854{ 855 struct lge_softc *sc; 856 int i; 857 struct lge_jpool_entry *entry; 858 859 /* Extract the softc struct pointer. */ 860 sc = args; 861 862 if (sc == NULL) 863 panic("lge_jfree: can't find softc pointer!"); 864 865 /* calculate the slot this buffer belongs to */ 866 i = ((vm_offset_t)buf 867 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 868 869 if ((i < 0) || (i >= LGE_JSLOTS)) 870 panic("lge_jfree: asked to free buffer that we don't manage!"); 871 872 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 873 if (entry == NULL) 874 panic("lge_jfree: buffer not in use!"); 875 entry->slot = i; 876 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 877 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 878} 879 880/* 881 * A frame has been uploaded: pass the resulting mbuf chain up to 882 * the higher level protocols. 883 */ 884static void 885lge_rxeof(sc, cnt) 886 struct lge_softc *sc; 887 int cnt; 888{ 889 struct mbuf *m; 890 struct ifnet *ifp; 891 struct lge_rx_desc *cur_rx; 892 int c, i, total_len = 0; 893 u_int32_t rxsts, rxctl; 894 895 ifp = sc->lge_ifp; 896 897 /* Find out how many frames were processed. */ 898 c = cnt; 899 i = sc->lge_cdata.lge_rx_cons; 900 901 /* Suck them in. */ 902 while(c) { 903 struct mbuf *m0 = NULL; 904 905 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 906 rxctl = cur_rx->lge_ctl; 907 rxsts = cur_rx->lge_sts; 908 m = cur_rx->lge_mbuf; 909 cur_rx->lge_mbuf = NULL; 910 total_len = LGE_RXBYTES(cur_rx); 911 LGE_INC(i, LGE_RX_LIST_CNT); 912 c--; 913 914 /* 915 * If an error occurs, update stats, clear the 916 * status word and leave the mbuf cluster in place: 917 * it should simply get re-used next time this descriptor 918 * comes up in the ring. 919 */ 920 if (rxctl & LGE_RXCTL_ERRMASK) { 921 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 922 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 923 continue; 924 } 925 926 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 927 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 928 ifp, NULL); 929 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 930 if (m0 == NULL) { 931 device_printf(sc->lge_dev, "no receive buffers " 932 "available -- packet dropped!\n"); 933 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 934 continue; 935 } 936 m = m0; 937 } else { 938 m->m_pkthdr.rcvif = ifp; 939 m->m_pkthdr.len = m->m_len = total_len; 940 } 941 942 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 943 944 /* Do IP checksum checking. */ 945 if (rxsts & LGE_RXSTS_ISIP) 946 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 947 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 948 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 949 if ((rxsts & LGE_RXSTS_ISTCP && 950 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 951 (rxsts & LGE_RXSTS_ISUDP && 952 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 953 m->m_pkthdr.csum_flags |= 954 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 955 m->m_pkthdr.csum_data = 0xffff; 956 } 957 958 LGE_UNLOCK(sc); 959 (*ifp->if_input)(ifp, m); 960 LGE_LOCK(sc); 961 } 962 963 sc->lge_cdata.lge_rx_cons = i; 964 965 return; 966} 967 968static void 969lge_rxeoc(sc) 970 struct lge_softc *sc; 971{ 972 struct ifnet *ifp; 973 974 ifp = sc->lge_ifp; 975 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 976 lge_init_locked(sc); 977 return; 978} 979 980/* 981 * A frame was downloaded to the chip. It's safe for us to clean up 982 * the list buffers. 983 */ 984 985static void 986lge_txeof(sc) 987 struct lge_softc *sc; 988{ 989 struct lge_tx_desc *cur_tx = NULL; 990 struct ifnet *ifp; 991 u_int32_t idx, txdone; 992 993 ifp = sc->lge_ifp; 994 995 /* Clear the timeout timer. */ 996 sc->lge_timer = 0; 997 998 /* 999 * Go through our tx list and free mbufs for those 1000 * frames that have been transmitted. 1001 */ 1002 idx = sc->lge_cdata.lge_tx_cons; 1003 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1004 1005 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1006 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1007 1008 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1009 if (cur_tx->lge_mbuf != NULL) { 1010 m_freem(cur_tx->lge_mbuf); 1011 cur_tx->lge_mbuf = NULL; 1012 } 1013 cur_tx->lge_ctl = 0; 1014 1015 txdone--; 1016 LGE_INC(idx, LGE_TX_LIST_CNT); 1017 sc->lge_timer = 0; 1018 } 1019 1020 sc->lge_cdata.lge_tx_cons = idx; 1021 1022 if (cur_tx != NULL) 1023 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1024 1025 return; 1026} 1027 1028static void 1029lge_tick(xsc) 1030 void *xsc; 1031{ 1032 struct lge_softc *sc; 1033 struct mii_data *mii; 1034 struct ifnet *ifp; 1035 1036 sc = xsc; 1037 ifp = sc->lge_ifp; 1038 LGE_LOCK_ASSERT(sc); 1039 1040 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1041 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, CSR_READ_4(sc, LGE_STATSVAL)); 1042 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1043 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, CSR_READ_4(sc, LGE_STATSVAL)); 1044 1045 if (!sc->lge_link) { 1046 mii = device_get_softc(sc->lge_miibus); 1047 mii_tick(mii); 1048 if (mii->mii_media_status & IFM_ACTIVE && 1049 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1050 sc->lge_link++; 1051 if (bootverbose && 1052 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1053 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)) 1054 device_printf(sc->lge_dev, "gigabit link up\n"); 1055 if (ifp->if_snd.ifq_head != NULL) 1056 lge_start_locked(ifp); 1057 } 1058 } 1059 1060 if (sc->lge_timer != 0 && --sc->lge_timer == 0) 1061 lge_watchdog(sc); 1062 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc); 1063 1064 return; 1065} 1066 1067static void 1068lge_intr(arg) 1069 void *arg; 1070{ 1071 struct lge_softc *sc; 1072 struct ifnet *ifp; 1073 u_int32_t status; 1074 1075 sc = arg; 1076 ifp = sc->lge_ifp; 1077 LGE_LOCK(sc); 1078 1079 /* Suppress unwanted interrupts */ 1080 if (!(ifp->if_flags & IFF_UP)) { 1081 lge_stop(sc); 1082 LGE_UNLOCK(sc); 1083 return; 1084 } 1085 1086 for (;;) { 1087 /* 1088 * Reading the ISR register clears all interrupts, and 1089 * clears the 'interrupts enabled' bit in the IMR 1090 * register. 1091 */ 1092 status = CSR_READ_4(sc, LGE_ISR); 1093 1094 if ((status & LGE_INTRS) == 0) 1095 break; 1096 1097 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1098 lge_txeof(sc); 1099 1100 if (status & LGE_ISR_RXDMA_DONE) 1101 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1102 1103 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1104 lge_rxeoc(sc); 1105 1106 if (status & LGE_ISR_PHY_INTR) { 1107 sc->lge_link = 0; 1108 callout_stop(&sc->lge_stat_callout); 1109 lge_tick(sc); 1110 } 1111 } 1112 1113 /* Re-enable interrupts. */ 1114 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1115 1116 if (ifp->if_snd.ifq_head != NULL) 1117 lge_start_locked(ifp); 1118 1119 LGE_UNLOCK(sc); 1120 return; 1121} 1122 1123/* 1124 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1125 * pointers to the fragment pointers. 1126 */ 1127static int 1128lge_encap(sc, m_head, txidx) 1129 struct lge_softc *sc; 1130 struct mbuf *m_head; 1131 u_int32_t *txidx; 1132{ 1133 struct lge_frag *f = NULL; 1134 struct lge_tx_desc *cur_tx; 1135 struct mbuf *m; 1136 int frag = 0, tot_len = 0; 1137 1138 /* 1139 * Start packing the mbufs in this chain into 1140 * the fragment pointers. Stop when we run out 1141 * of fragments or hit the end of the mbuf chain. 1142 */ 1143 m = m_head; 1144 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1145 frag = 0; 1146 1147 for (m = m_head; m != NULL; m = m->m_next) { 1148 if (m->m_len != 0) { 1149 tot_len += m->m_len; 1150 f = &cur_tx->lge_frags[frag]; 1151 f->lge_fraglen = m->m_len; 1152 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1153 f->lge_fragptr_hi = 0; 1154 frag++; 1155 } 1156 } 1157 1158 if (m != NULL) 1159 return(ENOBUFS); 1160 1161 cur_tx->lge_mbuf = m_head; 1162 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1163 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1164 1165 /* Queue for transmit */ 1166 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1167 1168 return(0); 1169} 1170 1171/* 1172 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1173 * to the mbuf data regions directly in the transmit lists. We also save a 1174 * copy of the pointers since the transmit list fragment pointers are 1175 * physical addresses. 1176 */ 1177 1178static void 1179lge_start(ifp) 1180 struct ifnet *ifp; 1181{ 1182 struct lge_softc *sc; 1183 1184 sc = ifp->if_softc; 1185 LGE_LOCK(sc); 1186 lge_start_locked(ifp); 1187 LGE_UNLOCK(sc); 1188} 1189 1190static void 1191lge_start_locked(ifp) 1192 struct ifnet *ifp; 1193{ 1194 struct lge_softc *sc; 1195 struct mbuf *m_head = NULL; 1196 u_int32_t idx; 1197 1198 sc = ifp->if_softc; 1199 1200 if (!sc->lge_link) 1201 return; 1202 1203 idx = sc->lge_cdata.lge_tx_prod; 1204 1205 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1206 return; 1207 1208 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1209 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1210 break; 1211 1212 IF_DEQUEUE(&ifp->if_snd, m_head); 1213 if (m_head == NULL) 1214 break; 1215 1216 if (lge_encap(sc, m_head, &idx)) { 1217 IF_PREPEND(&ifp->if_snd, m_head); 1218 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1219 break; 1220 } 1221 1222 /* 1223 * If there's a BPF listener, bounce a copy of this frame 1224 * to him. 1225 */ 1226 BPF_MTAP(ifp, m_head); 1227 } 1228 1229 sc->lge_cdata.lge_tx_prod = idx; 1230 1231 /* 1232 * Set a timeout in case the chip goes out to lunch. 1233 */ 1234 sc->lge_timer = 5; 1235 1236 return; 1237} 1238 1239static void 1240lge_init(xsc) 1241 void *xsc; 1242{ 1243 struct lge_softc *sc = xsc; 1244 1245 LGE_LOCK(sc); 1246 lge_init_locked(sc); 1247 LGE_UNLOCK(sc); 1248} 1249 1250static void 1251lge_init_locked(sc) 1252 struct lge_softc *sc; 1253{ 1254 struct ifnet *ifp = sc->lge_ifp; 1255 1256 LGE_LOCK_ASSERT(sc); 1257 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1258 return; 1259 1260 /* 1261 * Cancel pending I/O and free all RX/TX buffers. 1262 */ 1263 lge_stop(sc); 1264 lge_reset(sc); 1265 1266 /* Set MAC address */ 1267 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[0])); 1268 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[4])); 1269 1270 /* Init circular RX list. */ 1271 if (lge_list_rx_init(sc) == ENOBUFS) { 1272 device_printf(sc->lge_dev, "initialization failed: no " 1273 "memory for rx buffers\n"); 1274 lge_stop(sc); 1275 return; 1276 } 1277 1278 /* 1279 * Init tx descriptors. 1280 */ 1281 lge_list_tx_init(sc); 1282 1283 /* Set initial value for MODE1 register. */ 1284 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1285 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1286 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1287 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1288 1289 /* If we want promiscuous mode, set the allframes bit. */ 1290 if (ifp->if_flags & IFF_PROMISC) { 1291 CSR_WRITE_4(sc, LGE_MODE1, 1292 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1293 } else { 1294 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1295 } 1296 1297 /* 1298 * Set the capture broadcast bit to capture broadcast frames. 1299 */ 1300 if (ifp->if_flags & IFF_BROADCAST) { 1301 CSR_WRITE_4(sc, LGE_MODE1, 1302 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1303 } else { 1304 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1305 } 1306 1307 /* Packet padding workaround? */ 1308 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1309 1310 /* No error frames */ 1311 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1312 1313 /* Receive large frames */ 1314 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1315 1316 /* Workaround: disable RX/TX flow control */ 1317 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1318 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1319 1320 /* Make sure to strip CRC from received frames */ 1321 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1322 1323 /* Turn off magic packet mode */ 1324 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1325 1326 /* Turn off all VLAN stuff */ 1327 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1328 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1329 1330 /* Workarond: FIFO overflow */ 1331 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1332 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1333 1334 /* 1335 * Load the multicast filter. 1336 */ 1337 lge_setmulti(sc); 1338 1339 /* 1340 * Enable hardware checksum validation for all received IPv4 1341 * packets, do not reject packets with bad checksums. 1342 */ 1343 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1344 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1345 LGE_MODE2_RX_ERRCSUM); 1346 1347 /* 1348 * Enable the delivery of PHY interrupts based on 1349 * link/speed/duplex status chalges. 1350 */ 1351 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1352 1353 /* Enable receiver and transmitter. */ 1354 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1355 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1356 1357 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1358 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1359 1360 /* 1361 * Enable interrupts. 1362 */ 1363 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1364 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1365 1366 lge_ifmedia_upd_locked(ifp); 1367 1368 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1369 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1370 1371 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc); 1372 1373 return; 1374} 1375 1376/* 1377 * Set media options. 1378 */ 1379static int 1380lge_ifmedia_upd(ifp) 1381 struct ifnet *ifp; 1382{ 1383 struct lge_softc *sc; 1384 1385 sc = ifp->if_softc; 1386 LGE_LOCK(sc); 1387 lge_ifmedia_upd_locked(ifp); 1388 LGE_UNLOCK(sc); 1389 1390 return(0); 1391} 1392 1393static void 1394lge_ifmedia_upd_locked(ifp) 1395 struct ifnet *ifp; 1396{ 1397 struct lge_softc *sc; 1398 struct mii_data *mii; 1399 struct mii_softc *miisc; 1400 1401 sc = ifp->if_softc; 1402 1403 LGE_LOCK_ASSERT(sc); 1404 mii = device_get_softc(sc->lge_miibus); 1405 sc->lge_link = 0; 1406 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1407 PHY_RESET(miisc); 1408 mii_mediachg(mii); 1409} 1410 1411/* 1412 * Report current media status. 1413 */ 1414static void 1415lge_ifmedia_sts(ifp, ifmr) 1416 struct ifnet *ifp; 1417 struct ifmediareq *ifmr; 1418{ 1419 struct lge_softc *sc; 1420 struct mii_data *mii; 1421 1422 sc = ifp->if_softc; 1423 1424 LGE_LOCK(sc); 1425 mii = device_get_softc(sc->lge_miibus); 1426 mii_pollstat(mii); 1427 ifmr->ifm_active = mii->mii_media_active; 1428 ifmr->ifm_status = mii->mii_media_status; 1429 LGE_UNLOCK(sc); 1430 1431 return; 1432} 1433 1434static int 1435lge_ioctl(ifp, command, data) 1436 struct ifnet *ifp; 1437 u_long command; 1438 caddr_t data; 1439{ 1440 struct lge_softc *sc = ifp->if_softc; 1441 struct ifreq *ifr = (struct ifreq *) data; 1442 struct mii_data *mii; 1443 int error = 0; 1444 1445 switch(command) { 1446 case SIOCSIFMTU: 1447 LGE_LOCK(sc); 1448 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1449 error = EINVAL; 1450 else 1451 ifp->if_mtu = ifr->ifr_mtu; 1452 LGE_UNLOCK(sc); 1453 break; 1454 case SIOCSIFFLAGS: 1455 LGE_LOCK(sc); 1456 if (ifp->if_flags & IFF_UP) { 1457 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1458 ifp->if_flags & IFF_PROMISC && 1459 !(sc->lge_if_flags & IFF_PROMISC)) { 1460 CSR_WRITE_4(sc, LGE_MODE1, 1461 LGE_MODE1_SETRST_CTL1| 1462 LGE_MODE1_RX_PROMISC); 1463 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1464 !(ifp->if_flags & IFF_PROMISC) && 1465 sc->lge_if_flags & IFF_PROMISC) { 1466 CSR_WRITE_4(sc, LGE_MODE1, 1467 LGE_MODE1_RX_PROMISC); 1468 } else { 1469 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1470 lge_init_locked(sc); 1471 } 1472 } else { 1473 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1474 lge_stop(sc); 1475 } 1476 sc->lge_if_flags = ifp->if_flags; 1477 LGE_UNLOCK(sc); 1478 error = 0; 1479 break; 1480 case SIOCADDMULTI: 1481 case SIOCDELMULTI: 1482 LGE_LOCK(sc); 1483 lge_setmulti(sc); 1484 LGE_UNLOCK(sc); 1485 error = 0; 1486 break; 1487 case SIOCGIFMEDIA: 1488 case SIOCSIFMEDIA: 1489 mii = device_get_softc(sc->lge_miibus); 1490 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1491 break; 1492 default: 1493 error = ether_ioctl(ifp, command, data); 1494 break; 1495 } 1496 1497 return(error); 1498} 1499 1500static void 1501lge_watchdog(sc) 1502 struct lge_softc *sc; 1503{ 1504 struct ifnet *ifp; 1505 1506 LGE_LOCK_ASSERT(sc); 1507 ifp = sc->lge_ifp; 1508 1509 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1510 if_printf(ifp, "watchdog timeout\n"); 1511 1512 lge_stop(sc); 1513 lge_reset(sc); 1514 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1515 lge_init_locked(sc); 1516 1517 if (ifp->if_snd.ifq_head != NULL) 1518 lge_start_locked(ifp); 1519} 1520 1521/* 1522 * Stop the adapter and free any mbufs allocated to the 1523 * RX and TX lists. 1524 */ 1525static void 1526lge_stop(sc) 1527 struct lge_softc *sc; 1528{ 1529 register int i; 1530 struct ifnet *ifp; 1531 1532 LGE_LOCK_ASSERT(sc); 1533 ifp = sc->lge_ifp; 1534 sc->lge_timer = 0; 1535 callout_stop(&sc->lge_stat_callout); 1536 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1537 1538 /* Disable receiver and transmitter. */ 1539 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1540 sc->lge_link = 0; 1541 1542 /* 1543 * Free data in the RX lists. 1544 */ 1545 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1546 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1547 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1548 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1549 } 1550 } 1551 bzero((char *)&sc->lge_ldata->lge_rx_list, 1552 sizeof(sc->lge_ldata->lge_rx_list)); 1553 1554 /* 1555 * Free the TX list buffers. 1556 */ 1557 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1558 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1559 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1560 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1561 } 1562 } 1563 1564 bzero((char *)&sc->lge_ldata->lge_tx_list, 1565 sizeof(sc->lge_ldata->lge_tx_list)); 1566 1567 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1568 1569 return; 1570} 1571 1572/* 1573 * Stop all chip I/O so that the kernel's probe routines don't 1574 * get confused by errant DMAs when rebooting. 1575 */ 1576static int 1577lge_shutdown(dev) 1578 device_t dev; 1579{ 1580 struct lge_softc *sc; 1581 1582 sc = device_get_softc(dev); 1583 1584 LGE_LOCK(sc); 1585 lge_reset(sc); 1586 lge_stop(sc); 1587 LGE_UNLOCK(sc); 1588 1589 return (0); 1590} 1591