acphyreg.h revision 331722
1/*- 2 * Copyright (c) 2001 Semen Ustimenko (semenu@FreeBSD.org) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/11/sys/dev/mii/acphyreg.h 331722 2018-03-29 02:50:57Z eadler $ 27 */ 28 29#ifndef _DEV_MII_ACPHYREG_H_ 30#define _DEV_MII_ACPHYREG_H_ 31 32/* 33 * Register definitions for the Altima Communications AC101 34 */ 35 36#define MII_ACPHY_POL 0x10 /* Polarity int level */ 37 38/* High byte is interrupt mask register */ 39#define MII_ACPHY_INT 0x11 /* Interrupt control/status */ 40#define AC_INT_ACOMP 0x0001 /* Autoneg complete */ 41#define AC_INT_REM_FLT 0x0002 /* Remote fault */ 42#define AC_INT_LINK_DOWN 0x0004 /* Link not OK */ 43#define AC_INT_LP_ACK 0x0008 /* FLP ack recved */ 44#define AC_INT_PD_FLT 0x0010 /* Parallel detect fault */ 45#define AC_INT_PAGE_RECV 0x0020 /* New page recved */ 46#define AC_INT_RX_ER 0x0040 /* RX_ER transitions high */ 47#define AC_INT_JAB 0x0080 /* Jabber detected */ 48 49#define MII_ACPHY_DIAG 0x12 /* Diagnostic */ 50#define AC_DIAG_RX_LOCK 0x0100 51#define AC_DIAG_RX_PASS 0x0200 52#define AC_DIAG_SPEED 0x0400 /* Aneg speed result */ 53#define AC_DIAG_DUPLEX 0x0800 /* Aneg duplex result */ 54 55#define MII_ACPHY_PWRLOOP 0x13 /* Power/Loopback */ 56#define MII_ACPHY_CBLMEAS 0x14 /* Cable meas. */ 57 58#define MII_ACPHY_MCTL 0x15 /* Mode control */ 59#define AC_MCTL_FX_SEL 0x0001 /* FX mode */ 60#define AC_MCTL_BYP_PCS 0x0002 /* Bypass PCS */ 61#define AC_MCTL_SCRMBL 0x0004 /* Data scrambling */ 62#define AC_MCTL_REM_LOOP 0x0008 /* Remote loopback */ 63#define AC_MCTL_DIS_WDT 0x0010 /* Disable watchdog timer */ 64#define AC_MCTL_DIS_REC 0x0020 /* Disable recv error counter */ 65#define AC_MCTL_REC_FULL 0x0040 /* Recv error counter full */ 66#define AC_MCTL_FRC_FEF 0x0080 /* Force Far End Fault Insert. */ 67#define AC_MCTL_DIS_FEF 0x0100 /* Disable FEF Insertion */ 68#define AC_MCTL_LED_SEL 0x0200 /* Compat LED config */ 69#define AC_MCTL_ALED_SEL 0x0400 /* ActLED RX&TX - RX only */ 70#define AC_MCTL_10BT_SEL 0x0800 /* Enable 7-wire interface */ 71#define AC_MCTL_DIS_JAB 0x1000 /* Disable jabber */ 72#define AC_MCTL_FRC_LINK 0x2000 /* Force TX link up */ 73#define AC_MCTL_DIS_NLP 0x4000 /* Disable NLP check */ 74 75#define MII_ACPHY_REC 0x18 /* Recv error counter */ 76 77#endif /* _DEV_MII_ACPHYREG_H_ */ 78