ppcreg.h revision 330897 
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2001 Alcove - Nicolas Souchu
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD: stable/11/sys/dev/ppc/ppcreg.h 330897 2018-03-14 03:19:51Z eadler $
29 *
30 */
31#ifndef __PPCREG_H
32#define __PPCREG_H
33
34#include <sys/_lock.h>
35#include <sys/_mutex.h>
36
37/*
38 * Parallel Port Chipset type.
39 */
40#define SMC_LIKE	0
41#define SMC_37C665GT	1
42#define SMC_37C666GT	2
43#define NS_PC87332	3
44#define NS_PC87306	4
45#define INTEL_820191AA	5	/* XXX not implemented */
46#define GENERIC		6
47#define WINB_W83877F	7
48#define WINB_W83877AF	8
49#define WINB_UNKNOWN	9
50#define NS_PC87334	10
51#define SMC_37C935	11
52#define NS_PC87303	12
53
54/*
55 * Parallel Port Chipset Type. SMC versus GENERIC (others)
56 */
57#define PPC_TYPE_SMCLIKE 0
58#define PPC_TYPE_GENERIC 1
59
60/*
61 * Generic structure to hold parallel port chipset info.
62 */
63struct ppc_data {
64	device_t ppc_dev;
65	int ppc_model;		/* chipset model if detected */
66	int ppc_type;		/* generic or smclike chipset type */
67
68	int ppc_mode;		/* chipset current mode */
69	int ppc_avm;		/* chipset available modes */
70	int ppc_dtm;		/* chipset detected modes */
71
72#define PPC_IRQ_NONE		0x0
73#define PPC_IRQ_nACK		0x1
74#define PPC_IRQ_DMA		0x2
75#define PPC_IRQ_FIFO		0x4
76#define PPC_IRQ_nFAULT		0x8
77	int ppc_irqstat;	/* remind irq settings */
78
79#define PPC_DMA_INIT		0x01
80#define PPC_DMA_STARTED		0x02
81#define PPC_DMA_COMPLETE	0x03
82#define PPC_DMA_INTERRUPTED	0x04
83#define PPC_DMA_ERROR		0x05
84	int ppc_dmastat;	/* dma state */
85	int ppc_dmachan;	/* dma channel */
86	int ppc_dmaflags;	/* dma transfer flags */
87	caddr_t ppc_dmaddr;	/* buffer address */
88	u_int ppc_dmacnt;	/* count of bytes sent with dma */
89	void (*ppc_dmadone)(struct ppc_data*);
90
91#define PPC_PWORD_MASK	0x30
92#define PPC_PWORD_16	0x00
93#define PPC_PWORD_8	0x10
94#define PPC_PWORD_32	0x20
95	char ppc_pword;		/* PWord size */
96	short ppc_fifo;		/* FIFO threshold */
97
98	short ppc_wthr;		/* writeIntrThresold */
99	short ppc_rthr;		/* readIntrThresold */
100
101	char *ppc_ptr;		/* microseq current pointer */
102	int ppc_accum;		/* microseq accumulator */
103	int ppc_base;		/* parallel port base address */
104	int ppc_epp;		/* EPP mode (1.7 or 1.9) */
105	int ppc_irq;
106
107	unsigned char ppc_flags;
108
109	device_t ppbus;		/* parallel port chipset corresponding ppbus */
110
111  	int rid_irq, rid_drq, rid_ioport;
112	struct resource *res_irq, *res_drq, *res_ioport;
113
114	void *intr_cookie;
115
116	ppc_intr_handler ppc_intr_hook;
117	void *ppc_intr_arg;
118
119	struct mtx ppc_lock;
120};
121
122#define	PPC_LOCK(data)		mtx_lock(&(data)->ppc_lock)
123#define	PPC_UNLOCK(data)	mtx_unlock(&(data)->ppc_lock)
124#define	PPC_ASSERT_LOCKED(data)	mtx_assert(&(data)->ppc_lock, MA_OWNED)
125
126/*
127 * Parallel Port Chipset registers.
128 */
129#define PPC_SPP_DTR	0	/* SPP data register */
130#define PPC_ECP_A_FIFO	0	/* ECP Address fifo register */
131#define PPC_SPP_STR	1	/* SPP status register */
132#define PPC_SPP_CTR	2	/* SPP control register */
133#define PPC_EPP_ADDR	3	/* EPP address register (8 bit) */
134#define PPC_EPP_DATA	4	/* EPP data register (8, 16 or 32 bit) */
135#if defined(__i386__) && defined(PC98)
136#define PPC_1284_ENABLE	0x09	/* IEEE STD 1284 Enable register */
137#define PPC_ECP_D_FIFO	0x0c	/* ECP Data fifo register */
138#define PPC_ECP_CNFGA	0x0c	/* Configuration register A */
139#define PPC_ECP_CNFGB	0x0d	/* Configuration register B */
140#define PPC_ECP_ECR	0x0e	/* ECP extended control register */
141#else
142#define PPC_ECP_D_FIFO	0x400	/* ECP Data fifo register */
143#define PPC_ECP_CNFGA	0x400	/* Configuration register A */
144#define PPC_ECP_CNFGB	0x401	/* Configuration register B */
145#define PPC_ECP_ECR	0x402	/* ECP extended control register */
146#endif
147
148#define PPC_FIFO_EMPTY	0x1	/* ecr register - bit 0 */
149#define PPC_FIFO_FULL	0x2	/* ecr register - bit 1 */
150#define PPC_SERVICE_INTR 0x4	/* ecr register - bit 2 */
151#define PPC_ENABLE_DMA	0x8	/* ecr register - bit 3 */
152#define PPC_nFAULT_INTR	0x10	/* ecr register - bit 4 */
153#define PPC_ECR_STD	0x0
154#define PPC_ECR_PS2	0x20
155#define PPC_ECR_FIFO	0x40
156#define PPC_ECR_ECP	0x60
157#define PPC_ECR_EPP	0x80
158
159#define PPC_DISABLE_INTR	(PPC_SERVICE_INTR | PPC_nFAULT_INTR)
160#define PPC_ECR_RESET		(PPC_ECR_PS2 | PPC_DISABLE_INTR)
161
162#define r_dtr(ppc) (bus_read_1((ppc)->res_ioport, PPC_SPP_DTR))
163#define r_str(ppc) (bus_read_1((ppc)->res_ioport, PPC_SPP_STR))
164#define r_ctr(ppc) (bus_read_1((ppc)->res_ioport, PPC_SPP_CTR))
165
166#define r_epp_A(ppc) (bus_read_1((ppc)->res_ioport, PPC_EPP_ADDR))
167#define r_epp_D(ppc) (bus_read_1((ppc)->res_ioport, PPC_EPP_DATA))
168#define r_cnfgA(ppc) (bus_read_1((ppc)->res_ioport, PPC_ECP_CNFGA))
169#define r_cnfgB(ppc) (bus_read_1((ppc)->res_ioport, PPC_ECP_CNFGB))
170#define r_ecr(ppc) (bus_read_1((ppc)->res_ioport, PPC_ECP_ECR))
171#define r_fifo(ppc) (bus_read_1((ppc)->res_ioport, PPC_ECP_D_FIFO))
172
173#define w_dtr(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_SPP_DTR, byte))
174#define w_str(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_SPP_STR, byte))
175#define w_ctr(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_SPP_CTR, byte))
176
177#define w_epp_A(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_EPP_ADDR, byte))
178#define w_epp_D(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_EPP_DATA, byte))
179#define w_ecr(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_ECP_ECR, byte))
180#define w_fifo(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_ECP_D_FIFO, byte))
181
182/*
183 * Register defines for the PC873xx parts
184 */
185
186#define PC873_FER	0x00
187#define PC873_PPENABLE	(1<<0)
188#define PC873_FAR	0x01
189#define PC873_PTR	0x02
190#define PC873_CFGLOCK	(1<<6)
191#define PC873_EPPRDIR	(1<<7)
192#define PC873_EXTENDED	(1<<7)
193#define PC873_LPTBIRQ7	(1<<3)
194#define PC873_FCR	0x03
195#define PC873_ZWS	(1<<5)
196#define PC873_ZWSPWDN	(1<<6)
197#define PC873_PCR	0x04
198#define PC873_EPPEN	(1<<0)
199#define PC873_EPP19	(1<<1)
200#define PC873_ECPEN	(1<<2)
201#define PC873_ECPCLK	(1<<3)
202#define PC873_PMC	0x06
203#define PC873_TUP	0x07
204#define PC873_SID	0x08
205#define PC873_PNP0	0x1b
206#define PC873_PNP1	0x1c
207#define PC873_LPTBA	0x19
208
209/*
210 * Register defines for the SMC FDC37C66xGT parts
211 */
212
213/* Init codes */
214#define SMC665_iCODE	0x55
215#define SMC666_iCODE	0x44
216
217/* Base configuration ports */
218#define SMC66x_CSR	0x3F0
219#define SMC666_CSR	0x370		/* hard-configured value for 666 */
220
221/* Bits */
222#define SMC_CR1_ADDR	0x3		/* bit 0 and 1 */
223#define SMC_CR1_MODE	(1<<3)		/* bit 3 */
224#define SMC_CR4_EMODE	0x3		/* bits 0 and 1 */
225#define SMC_CR4_EPPTYPE	(1<<6)		/* bit 6 */
226
227/* Extended modes */
228#define SMC_SPP		0x0		/* SPP */
229#define SMC_EPPSPP	0x1		/* EPP and SPP */
230#define SMC_ECP		0x2 		/* ECP */
231#define SMC_ECPEPP	0x3		/* ECP and EPP */
232
233/*
234 * Register defines for the SMC FDC37C935 parts
235 */
236
237/* Configuration ports */
238#define SMC935_CFG	0x370
239#define SMC935_IND	0x370
240#define SMC935_DAT	0x371
241
242/* Registers */
243#define SMC935_LOGDEV	0x7
244#define SMC935_ID	0x20
245#define SMC935_PORTHI	0x60
246#define SMC935_PORTLO	0x61
247#define SMC935_PPMODE	0xf0
248
249/* Parallel port modes */
250#define SMC935_SPP	0x38 + 0
251#define SMC935_EPP19SPP	0x38 + 1
252#define SMC935_ECP	0x38 + 2
253#define SMC935_ECPEPP19	0x38 + 3
254#define SMC935_CENT	0x38 + 4
255#define SMC935_EPP17SPP	0x38 + 5
256#define SMC935_UNUSED	0x38 + 6
257#define SMC935_ECPEPP17	0x38 + 7
258
259/*
260 * Register defines for the Winbond W83877F parts
261 */
262
263#define WINB_W83877F_ID		0xa
264#define WINB_W83877AF_ID	0xb
265
266/* Configuration bits */
267#define WINB_HEFERE	(1<<5)		/* CROC bit 5 */
268#define WINB_HEFRAS	(1<<0)		/* CR16 bit 0 */
269
270#define WINB_PNPCVS	(1<<2)		/* CR16 bit 2 */
271#define WINB_CHIPID	0xf		/* CR9 bits 0-3 */
272
273#define WINB_PRTMODS0	(1<<2)		/* CR0 bit 2 */
274#define WINB_PRTMODS1	(1<<3)		/* CR0 bit 3 */
275#define WINB_PRTMODS2	(1<<7)		/* CR9 bit 7 */
276
277/* W83877F modes: CR9/bit7 | CR0/bit3 | CR0/bit2 */
278#define WINB_W83757	0x0
279#define WINB_EXTFDC	0x4
280#define WINB_EXTADP	0x8
281#define WINB_EXT2FDD	0xc
282#define WINB_JOYSTICK	0x80
283
284#define WINB_PARALLEL	0x80
285#define WINB_EPP_SPP	0x4
286#define WINB_ECP	0x8
287#define WINB_ECP_EPP	0xc
288
289#endif
290