xgehal-config.h revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2002-2007 Neterion, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: stable/11/sys/dev/nxge/include/xgehal-config.h 330897 2018-03-14 03:19:51Z eadler $ 29 */ 30 31#ifndef XGE_HAL_CONFIG_H 32#define XGE_HAL_CONFIG_H 33 34#include <dev/nxge/include/xge-os-pal.h> 35#include <dev/nxge/include/xgehal-types.h> 36#include <dev/nxge/include/xge-queue.h> 37 38__EXTERN_BEGIN_DECLS 39 40#define XGE_HAL_DEFAULT_USE_HARDCODE -1 41 42#define XGE_HAL_MAX_VIRTUAL_PATHS 8 43#define XGE_HAL_MAX_INTR_PER_VP 4 44 45 46/** 47 * struct xge_hal_tti_config_t - Xframe Tx interrupt configuration. 48 * @enabled: Set to 1, if TTI feature is enabled. 49 * @urange_a: Link utilization range A. The value from 0 to 100%. 50 * @ufc_a: Frame count for the utilization range A. Interrupt will be generated 51 * each time when (and only when) the line is utilized no more 52 * than @urange_a percent in the transmit direction, 53 * and number of transmitted frames is greater or equal @ufc_a. 54 * @urange_b: Link utilization range B. 55 * @ufc_b: Frame count for the utilization range B. 56 * @urange_c: Link utilization range C. 57 * @ufc_c: Frame count for the utilization range C. 58 * @urange_d: Link utilization range D. 59 * @ufc_d: Frame count for the utilization range D. 60 * @timer_val_us: Interval of time, in microseconds, at which transmit timer 61 * interrupt is to be generated. Note that unless @timer_ci_en 62 * is set, the timer interrupt is generated only in presence 63 * of the transmit traffic. Note also that timer interrupt 64 * and utilization interrupt are two separate interrupt 65 * sources. 66 * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization 67 * interrupt was generated during the interval. 68 * @timer_ci_en: Enable/disable continuous interrupt. Set this value 69 * to 1 in order to generate continuous interrupt 70 * at fixed @timer_val intervals of time, independently 71 * of whether there is transmit traffic or not. 72 * @enabled: Set to 1, if TTI feature is enabled. 73 * 74 * Xframe transmit interrupt configuration. 75 * See Xframe User Guide, Section 3.5 "Device Interrupts" 76 * for more details. Note also (min, max) 77 * ranges in the body of the xge_hal_tx_intr_config_t structure. 78 * Note: Valid (min, max) range for each attribute is specified in the body of 79 * the xge_hal_tti_config_t{} structure. Please refer to the 80 * corresponding header file. 81 */ 82typedef struct xge_hal_tti_config_t { 83 84 int enabled; 85#define XGE_HAL_TTI_ENABLE 1 86#define XGE_HAL_TTI_DISABLE 0 87 88 /* Line utilization interrupts */ 89 90 int urange_a; 91#define XGE_HAL_MIN_TX_URANGE_A 0 92#define XGE_HAL_MAX_TX_URANGE_A 100 93 94 int ufc_a; 95#define XGE_HAL_MIN_TX_UFC_A 0 96#define XGE_HAL_MAX_TX_UFC_A 65535 97 98 int urange_b; 99#define XGE_HAL_MIN_TX_URANGE_B 0 100#define XGE_HAL_MAX_TX_URANGE_B 100 101 102 int ufc_b; 103#define XGE_HAL_MIN_TX_UFC_B 0 104#define XGE_HAL_MAX_TX_UFC_B 65535 105 106 int urange_c; 107#define XGE_HAL_MIN_TX_URANGE_C 0 108#define XGE_HAL_MAX_TX_URANGE_C 100 109 110 int ufc_c; 111#define XGE_HAL_MIN_TX_UFC_C 0 112#define XGE_HAL_MAX_TX_UFC_C 65535 113 114 int ufc_d; 115#define XGE_HAL_MIN_TX_UFC_D 0 116#define XGE_HAL_MAX_TX_UFC_D 65535 117 118 int timer_val_us; 119#define XGE_HAL_MIN_TX_TIMER_VAL 0 120#define XGE_HAL_MAX_TX_TIMER_VAL 65535 121 122 int timer_ac_en; 123#define XGE_HAL_MIN_TX_TIMER_AC_EN 0 124#define XGE_HAL_MAX_TX_TIMER_AC_EN 1 125 126 int timer_ci_en; 127#define XGE_HAL_MIN_TX_TIMER_CI_EN 0 128#define XGE_HAL_MAX_TX_TIMER_CI_EN 1 129 130 131} xge_hal_tti_config_t; 132 133/** 134 * struct xge_hal_rti_config_t - Xframe Rx interrupt configuration. 135 * @urange_a: Link utilization range A. The value from 0 to 100%. 136 * @ufc_a: Frame count for the utilization range A. Interrupt will be generated 137 * each time when (and only when) the line is utilized no more 138 * than @urange_a percent inbound, 139 * and number of received frames is greater or equal @ufc_a. 140 * @urange_b: Link utilization range B. 141 * @ufc_b: Frame count for the utilization range B. 142 * @urange_c: Link utilization range C. 143 * @ufc_c: Frame count for the utilization range C. 144 * @urange_d: Link utilization range D. 145 * @ufc_d: Frame count for the utilization range D. 146 * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization 147 * interrupt was generated during the interval. 148 * @timer_val_us: Interval of time, in microseconds, at which receive timer 149 * interrupt is to be generated. The timer interrupt is generated 150 * only in presence of the inbound traffic. Note also that timer 151 * interrupt and utilization interrupt are two separate interrupt 152 * sources. 153 * 154 * Xframe receive interrupt configuration. 155 * See Xframe User Guide, Section 3.5 "Device Interrupts" 156 * for more details. Note also (min, max) 157 * ranges in the body of the xge_hal_intr_config_t structure. 158 * Note: Valid (min, max) range for each attribute is specified in the body of 159 * the xge_hal_rti_config_t{} structure. Please refer to the 160 * corresponding header file. 161 */ 162typedef struct xge_hal_rti_config_t { 163 164 int urange_a; 165#define XGE_HAL_MIN_RX_URANGE_A 0 166#define XGE_HAL_MAX_RX_URANGE_A 127 167 168 int ufc_a; 169#define XGE_HAL_MIN_RX_UFC_A 0 170#define XGE_HAL_MAX_RX_UFC_A 65535 171 172 int urange_b; 173#define XGE_HAL_MIN_RX_URANGE_B 0 174#define XGE_HAL_MAX_RX_URANGE_B 127 175 176 int ufc_b; 177#define XGE_HAL_MIN_RX_UFC_B 0 178#define XGE_HAL_MAX_RX_UFC_B 65535 179 180 int urange_c; 181#define XGE_HAL_MIN_RX_URANGE_C 0 182#define XGE_HAL_MAX_RX_URANGE_C 127 183 184 int ufc_c; 185#define XGE_HAL_MIN_RX_UFC_C 0 186#define XGE_HAL_MAX_RX_UFC_C 65535 187 188 int ufc_d; 189#define XGE_HAL_MIN_RX_UFC_D 0 190#define XGE_HAL_MAX_RX_UFC_D 65535 191 192 int timer_ac_en; 193#define XGE_HAL_MIN_RX_TIMER_AC_EN 0 194#define XGE_HAL_MAX_RX_TIMER_AC_EN 1 195 196 int timer_val_us; 197#define XGE_HAL_MIN_RX_TIMER_VAL 0 198#define XGE_HAL_MAX_RX_TIMER_VAL 65535 199 200} xge_hal_rti_config_t; 201 202/** 203 * struct xge_hal_fifo_queue_t - Single fifo configuration. 204 * @max: Max numbers of TxDLs (that is, lists of Tx descriptors) per queue. 205 * @initial: Initial numbers of TxDLs per queue (can grow up to @max). 206 * @intr: Boolean. Use 1 to generate interrupt for each completed TxDL. 207 * Use 0 otherwise. 208 * @intr_vector: TBD 209 * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation, 210 * which generally improves latency of the host bridge operation 211 * (see PCI specification). For valid values please refer 212 * to xge_hal_fifo_queue_t{} in the driver sources. 213 * @priority: TBD 214 * @configured: Boolean. Use 1 to specify that the fifo is configured. 215 * Only "configured" fifos can be activated and used to post 216 * Tx descriptors. Any subset of 8 available fifos can be 217 * "configured". 218 * @tti: TBD 219 * 220 * Single fifo configuration. 221 * Note: Valid (min, max) range for each attribute is specified in the body of 222 * the xge_hal_fifo_queue_t{} structure. Please refer to the 223 * corresponding header file. 224 * See also: xge_hal_fifo_config_t{} 225 */ 226typedef struct xge_hal_fifo_queue_t { 227 int max; 228 int initial; 229#define XGE_HAL_MIN_FIFO_QUEUE_LENGTH 2 230#define XGE_HAL_MAX_FIFO_QUEUE_LENGTH 8192 231 232 int intr; 233#define XGE_HAL_MIN_FIFO_QUEUE_INTR 0 234#define XGE_HAL_MAX_FIFO_QUEUE_INTR 1 235 236 int intr_vector; 237#define XGE_HAL_MIN_FIFO_QUEUE_INTR_VECTOR 0 238#define XGE_HAL_MAX_FIFO_QUEUE_INTR_VECTOR 64 239 240 int no_snoop_bits; 241#define XGE_HAL_MIN_FIFO_QUEUE_NO_SNOOP_DISABLED 0 242#define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_TXD 1 243#define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_BUFFER 2 244#define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_ALL 3 245 246 int priority; 247#define XGE_HAL_MIN_FIFO_PRIORITY 0 248#define XGE_HAL_MAX_FIFO_PRIORITY 63 249 250 int configured; 251#define XGE_HAL_MIN_FIFO_CONFIGURED 0 252#define XGE_HAL_MAX_FIFO_CONFIGURED 1 253 254#define XGE_HAL_MAX_FIFO_TTI_NUM 7 255#define XGE_HAL_MAX_FIFO_TTI_RING_0 56 256 xge_hal_tti_config_t tti[XGE_HAL_MAX_FIFO_TTI_NUM]; 257 258} xge_hal_fifo_queue_t; 259 260/** 261 * struct xge_hal_fifo_config_t - Configuration of all 8 fifos. 262 * @max_frags: Max number of Tx buffers per TxDL (that is, per single 263 * transmit operation). 264 * No more than 256 transmit buffers can be specified. 265 * @max_aligned_frags: Number of fragments to be aligned out of 266 * maximum fragments (see @max_frags). 267 * @reserve_threshold: Descriptor reservation threshold. 268 * At least @reserve_threshold descriptors will remain 269 * unallocated at all times. 270 * @memblock_size: Fifo descriptors are allocated in blocks of @mem_block_size 271 * bytes. Setting @memblock_size to page size ensures 272 * by-page allocation of descriptors. 128K bytes is the 273 * maximum supported block size. 274 * @queue: Array of per-fifo configurations. 275 * @alignment_size: per Tx fragment DMA-able memory used to align transmit data 276 * (e.g., to align on a cache line). 277 * 278 * Configuration of all Xframe fifos. Includes array of xge_hal_fifo_queue_t 279 * structures. 280 * Note: Valid (min, max) range for each attribute is specified in the body of 281 * the xge_hal_fifo_config_t{} structure. Please refer to the 282 * corresponding header file. 283 * See also: xge_hal_ring_queue_t{}. 284 */ 285typedef struct xge_hal_fifo_config_t { 286 int max_frags; 287#define XGE_HAL_MIN_FIFO_FRAGS 1 288#define XGE_HAL_MAX_FIFO_FRAGS 256 289 290 int reserve_threshold; 291#define XGE_HAL_MIN_FIFO_RESERVE_THRESHOLD 0 292#define XGE_HAL_MAX_FIFO_RESERVE_THRESHOLD 8192 293 294 int memblock_size; 295#define XGE_HAL_MIN_FIFO_MEMBLOCK_SIZE 4096 296#define XGE_HAL_MAX_FIFO_MEMBLOCK_SIZE 131072 297 298 int alignment_size; 299#define XGE_HAL_MIN_ALIGNMENT_SIZE 0 300#define XGE_HAL_MAX_ALIGNMENT_SIZE 65536 301 302 int max_aligned_frags; 303 /* range: (1, @max_frags) */ 304 305#define XGE_HAL_MIN_FIFO_NUM 1 306#define XGE_HAL_MAX_FIFO_NUM_HERC 8 307#define XGE_HAL_MAX_FIFO_NUM_TITAN (XGE_HAL_MAX_VIRTUAL_PATHS - 1) 308#define XGE_HAL_MAX_FIFO_NUM (XGE_HAL_MAX_VIRTUAL_PATHS) 309 xge_hal_fifo_queue_t queue[XGE_HAL_MAX_FIFO_NUM]; 310} xge_hal_fifo_config_t; 311 312/** 313 * struct xge_hal_rts_port_t - RTS port entry 314 * @num: Port number 315 * @udp: Port is UDP (default TCP) 316 * @src: Port is Source (default Destination) 317 */ 318typedef struct xge_hal_rts_port_t { 319 int num; 320 int udp; 321 int src; 322} xge_hal_rts_port_t; 323 324/** 325 * struct xge_hal_ring_queue_t - Single ring configuration. 326 * @max: Max numbers of RxD blocks per queue 327 * @initial: Initial numbers of RxD blocks per queue 328 * (can grow up to @max) 329 * @buffer_mode: Receive buffer mode (1, 2, 3, or 5); for details please refer 330 * to Xframe User Guide. 331 * @dram_size_mb: Size (in MB) of Xframe DRAM used for _that_ ring. 332 * Note that 64MB of available 333 * on-board DRAM is shared between receive rings. 334 * If a single ring is used, @dram_size_mb can be set to 64. 335 * Sum of all rings' @dram_size_mb cannot exceed 64. 336 * @intr_vector: TBD 337 * @backoff_interval_us: Time (in microseconds), after which Xframe 338 * tries to download RxDs posted by the host. 339 * Note that the "backoff" does not happen if host posts receive 340 * descriptors in the timely fashion. 341 * @max_frm_len: Maximum frame length that can be received on _that_ ring. 342 * Setting this field to -1 ensures that the ring will 343 * "accept" MTU-size frames (note that MTU can be changed at 344 * runtime). 345 * Any value other than (-1) specifies a certain "hard" 346 * limit on the receive frame sizes. 347 * The field can be used to activate receive frame-length based 348 * steering. 349 * @priority: Ring priority. 0 - highest, 7 - lowest. The value is used 350 * to give prioritized access to PCI-X. See Xframe documentation 351 * for details. 352 * @rth_en: Enable Receive Traffic Hashing (RTH). 353 * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation, 354 * which generally improves latency of the host bridge operation 355 * (see PCI specification). For valid values please refer 356 * to xge_hal_ring_queue_t{} in the driver sources. 357 * @indicate_max_pkts: Sets maximum number of received frames to be processed 358 * within single interrupt. 359 * @configured: Boolean. Use 1 to specify that the ring is configured. 360 * Only "configured" rings can be activated and used to post 361 * Rx descriptors. Any subset of 8 available rings can be 362 * "configured". 363 * @rts_mac_en: 1 - To enable Receive MAC address steering. 364 * 0 - To disable Receive MAC address steering. 365 * @rth_en: TBD 366 * @rts_port_en: TBD 367 * @rts_ports: TBD 368 * @rti: Xframe receive interrupt configuration. 369 * 370 * Single ring configuration. 371 * Note: Valid (min, max) range for each attribute is specified in the body of 372 * the xge_hal_ring_queue_t{} structure. Please refer to the 373 * corresponding header file. 374 * See also: xge_hal_fifo_config_t{}. 375 */ 376typedef struct xge_hal_ring_queue_t { 377 int max; 378 int initial; 379#define XGE_HAL_MIN_RING_QUEUE_BLOCKS 1 380#define XGE_HAL_MAX_RING_QUEUE_BLOCKS 64 381 382 int buffer_mode; 383#define XGE_HAL_RING_QUEUE_BUFFER_MODE_1 1 384#define XGE_HAL_RING_QUEUE_BUFFER_MODE_2 2 385#define XGE_HAL_RING_QUEUE_BUFFER_MODE_3 3 386#define XGE_HAL_RING_QUEUE_BUFFER_MODE_5 5 387 388 int dram_size_mb; 389#define XGE_HAL_MIN_RING_QUEUE_SIZE 0 390#define XGE_HAL_MAX_RING_QUEUE_SIZE_XENA 64 391#define XGE_HAL_MAX_RING_QUEUE_SIZE_HERC 32 392 393 int intr_vector; 394#define XGE_HAL_MIN_RING_QUEUE_INTR_VECTOR 0 395#define XGE_HAL_MAX_RING_QUEUE_INTR_VECTOR 64 396 397 int backoff_interval_us; 398#define XGE_HAL_MIN_BACKOFF_INTERVAL_US 1 399#define XGE_HAL_MAX_BACKOFF_INTERVAL_US 125000 400 401 int max_frm_len; 402#define XGE_HAL_MIN_MAX_FRM_LEN -1 403#define XGE_HAL_MAX_MAX_FRM_LEN 9622 404 405 int priority; 406#define XGE_HAL_MIN_RING_PRIORITY 0 407#define XGE_HAL_MAX_RING_PRIORITY 7 408 409 int no_snoop_bits; 410#define XGE_HAL_MIN_RING_QUEUE_NO_SNOOP_DISABLED 0 411#define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_RXD 1 412#define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_BUFFER 2 413#define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_ALL 3 414 415 int indicate_max_pkts; 416#define XGE_HAL_MIN_RING_INDICATE_MAX_PKTS 1 417#define XGE_HAL_MAX_RING_INDICATE_MAX_PKTS 65536 418 419 int configured; 420#define XGE_HAL_MIN_RING_CONFIGURED 0 421#define XGE_HAL_MAX_RING_CONFIGURED 1 422 423 int rts_mac_en; 424#define XGE_HAL_MIN_RING_RTS_MAC_EN 0 425#define XGE_HAL_MAX_RING_RTS_MAC_EN 1 426 427 int rth_en; 428#define XGE_HAL_MIN_RING_RTH_EN 0 429#define XGE_HAL_MAX_RING_RTH_EN 1 430 431 int rts_port_en; 432#define XGE_HAL_MIN_RING_RTS_PORT_EN 0 433#define XGE_HAL_MAX_RING_RTS_PORT_EN 1 434 435#define XGE_HAL_MAX_STEERABLE_PORTS 32 436 xge_hal_rts_port_t rts_ports[XGE_HAL_MAX_STEERABLE_PORTS]; 437 438 xge_hal_rti_config_t rti; 439 440} xge_hal_ring_queue_t; 441 442/** 443 * struct xge_hal_ring_config_t - Array of ring configurations. 444 * @memblock_size: Ring descriptors are allocated in blocks of @mem_block_size 445 * bytes. Setting @memblock_size to page size ensures 446 * by-page allocation of descriptors. 128K bytes is the 447 * upper limit. 448 * @scatter_mode: Xframe supports two receive scatter modes: A and B. 449 * For details please refer to Xframe User Guide. 450 * @strip_vlan_tag: TBD 451 * @queue: Array of all Xframe ring configurations. 452 * 453 * Array of ring configurations. 454 * See also: xge_hal_ring_queue_t{}. 455 */ 456typedef struct xge_hal_ring_config_t { 457 458 int memblock_size; 459#define XGE_HAL_MIN_RING_MEMBLOCK_SIZE 4096 460#define XGE_HAL_MAX_RING_MEMBLOCK_SIZE 131072 461 462 int scatter_mode; 463#define XGE_HAL_RING_QUEUE_SCATTER_MODE_A 0 464#define XGE_HAL_RING_QUEUE_SCATTER_MODE_B 1 465 466 int strip_vlan_tag; 467#define XGE_HAL_RING_DONOT_STRIP_VLAN_TAG 0 468#define XGE_HAL_RING_STRIP_VLAN_TAG 1 469 470#define XGE_HAL_MIN_RING_NUM 1 471#define XGE_HAL_MAX_RING_NUM_HERC 8 472#define XGE_HAL_MAX_RING_NUM_TITAN (XGE_HAL_MAX_VIRTUAL_PATHS - 1) 473#define XGE_HAL_MAX_RING_NUM (XGE_HAL_MAX_VIRTUAL_PATHS) 474 xge_hal_ring_queue_t queue[XGE_HAL_MAX_RING_NUM]; 475 476} xge_hal_ring_config_t; 477 478/** 479 * struct xge_hal_mac_config_t - MAC configuration. 480 * @media: Transponder type. 481 * @tmac_util_period: The sampling period over which the transmit utilization 482 * is calculated. 483 * @rmac_util_period: The sampling period over which the receive utilization 484 * is calculated. 485 * @rmac_strip_pad: Determines whether padding of received frames is removed by 486 * the MAC or sent to the host. 487 * @rmac_bcast_en: Enable frames containing broadcast address to be 488 * passed to the host. 489 * @rmac_pause_gen_en: Received pause generation enable. 490 * @rmac_pause_rcv_en: Receive pause enable. 491 * @rmac_pause_time: The value to be inserted in outgoing pause frames. 492 * Has units of pause quanta (one pause quanta = 512 bit times). 493 * @mc_pause_threshold_q0q3: Contains thresholds for pause frame generation 494 * for queues 0 through 3. The threshold value indicates portion of the 495 * individual receive buffer queue size. Thresholds have a range of 0 to 496 * 255, allowing 256 possible watermarks in a queue. 497 * @mc_pause_threshold_q4q7: Contains thresholds for pause frame generation 498 * for queues 4 through 7. The threshold value indicates portion of the 499 * individual receive buffer queue size. Thresholds have a range of 0 to 500 * 255, allowing 256 possible watermarks in a queue. 501 * 502 * MAC configuration. This includes various aspects of configuration, including: 503 * - Pause frame threshold; 504 * - sampling rate to calculate link utilization; 505 * - enabling/disabling broadcasts. 506 * 507 * See Xframe User Guide for more details. 508 * Note: Valid (min, max) range for each attribute is specified in the body of 509 * the xge_hal_mac_config_t{} structure. Please refer to the 510 * corresponding include file. 511 */ 512typedef struct xge_hal_mac_config_t { 513 int media; 514#define XGE_HAL_MIN_MEDIA 0 515#define XGE_HAL_MEDIA_SR 0 516#define XGE_HAL_MEDIA_SW 1 517#define XGE_HAL_MEDIA_LR 2 518#define XGE_HAL_MEDIA_LW 3 519#define XGE_HAL_MEDIA_ER 4 520#define XGE_HAL_MEDIA_EW 5 521#define XGE_HAL_MAX_MEDIA 5 522 523 int tmac_util_period; 524#define XGE_HAL_MIN_TMAC_UTIL_PERIOD 0 525#define XGE_HAL_MAX_TMAC_UTIL_PERIOD 15 526 527 int rmac_util_period; 528#define XGE_HAL_MIN_RMAC_UTIL_PERIOD 0 529#define XGE_HAL_MAX_RMAC_UTIL_PERIOD 15 530 531 int rmac_bcast_en; 532#define XGE_HAL_MIN_RMAC_BCAST_EN 0 533#define XGE_HAL_MAX_RMAC_BCAST_EN 1 534 535 int rmac_pause_gen_en; 536#define XGE_HAL_MIN_RMAC_PAUSE_GEN_EN 0 537#define XGE_HAL_MAX_RMAC_PAUSE_GEN_EN 1 538 539 int rmac_pause_rcv_en; 540#define XGE_HAL_MIN_RMAC_PAUSE_RCV_EN 0 541#define XGE_HAL_MAX_RMAC_PAUSE_RCV_EN 1 542 543 int rmac_pause_time; 544#define XGE_HAL_MIN_RMAC_HIGH_PTIME 16 545#define XGE_HAL_MAX_RMAC_HIGH_PTIME 65535 546 547 int mc_pause_threshold_q0q3; 548#define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q0Q3 0 549#define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q0Q3 254 550 551 int mc_pause_threshold_q4q7; 552#define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q4Q7 0 553#define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q4Q7 254 554 555} xge_hal_mac_config_t; 556 557/** 558 * struct xge_hal_device_config_t - Device configuration. 559 * @mtu: Current mtu size. 560 * @isr_polling_cnt: Maximum number of times to "poll" for Tx and Rx 561 * completions. Used in xge_hal_device_handle_irq(). 562 * @latency_timer: Specifies, in units of PCI bus clocks, and in conformance 563 * with the PCI Specification, the value of the Latency Timer 564 * for this PCI bus master. 565 * Specify either zero or -1 to use BIOS default. 566 * @napi_weight: (TODO) 567 * @max_splits_trans: Maximum number of PCI-X split transactions. 568 * Specify (-1) to use BIOS default. 569 * @mmrb_count: Maximum Memory Read Byte Count. Use (-1) to use default 570 * BIOS value. Otherwise: mmrb_count = 0 corresponds to 512B; 571 * 1 - 1KB, 2 - 2KB, and 3 - 4KB. 572 * @shared_splits: The number of Outstanding Split Transactions that is 573 * shared by Tx and Rx requests. The device stops issuing Tx 574 * requests once the number of Outstanding Split Transactions is 575 * equal to the value of Shared_Splits. 576 * A value of zero indicates that the Tx and Rx share all allocated 577 * Split Requests, i.e. the device can issue both types (Tx and Rx) 578 * of read requests until the number of Maximum Outstanding Split 579 * Transactions is reached. 580 * @stats_refresh_time_sec: Sets the default interval for automatic stats transfer 581 * to the host. This includes MAC stats as well as PCI stats. 582 * See xge_hal_stats_hw_info_t{}. 583 * @pci_freq_mherz: PCI clock frequency, e.g.: 133 for 133MHz. 584 * @intr_mode: Line, MSI, or MSI-X interrupt. 585 * @sched_timer_us: If greater than zero, specifies time interval 586 * (in microseconds) for the device to generate 587 * interrupt. Note that unlike tti and rti interrupts, 588 * the scheduled interrupt is generated independently of 589 * whether there is transmit or receive traffic, respectively. 590 * @sched_timer_one_shot: 1 - generate scheduled interrupt only once. 591 * 0 - generate scheduled interrupt periodically at the specified 592 * @sched_timer_us interval. 593 * 594 * @ring: See xge_hal_ring_config_t{}. 595 * @mac: See xge_hal_mac_config_t{}. 596 * @tti: See xge_hal_tti_config_t{}. 597 * @fifo: See xge_hal_fifo_config_t{}. 598 * 599 * @dump_on_serr: Dump adapter state ("about", statistics, registers) on SERR#. 600 * @dump_on_eccerr: Dump adapter state ("about", statistics, registers) on 601 * ECC error. 602 * @dump_on_parityerr: Dump adapter state ("about", statistics, registers) on 603 * parity error. 604 * @rth_en: Enable Receive Traffic Hashing(RTH) using IT(Indirection Table). 605 * @rth_bucket_size: RTH bucket width (in bits). For valid range please see 606 * xge_hal_device_config_t{} in the driver sources. 607 * @rth_spdm_en: Enable Receive Traffic Hashing(RTH) using SPDM(Socket Pair 608 * Direct Match). 609 * @rth_spdm_use_l4: Set to 1, if the L4 ports are used in the calculation of 610 * hash value in the RTH SPDM based steering. 611 * @rxufca_intr_thres: (TODO) 612 * @rxufca_lo_lim: (TODO) 613 * @rxufca_hi_lim: (TODO) 614 * @rxufca_lbolt_period: (TODO) 615 * @link_valid_cnt: link-valid counting is done only at device-open time, 616 * to determine with the specified certainty that the link is up. See also 617 * @link_retry_cnt. 618 * @link_retry_cnt: Max number of polls for link-up. Done only at device 619 * open time. Reducing this value as well as the previous @link_valid_cnt, 620 * speeds up device startup, which may be important if the driver 621 * is compiled into OS. 622 * @link_stability_period: Specify the period for which the link must be 623 * stable in order for the adapter to declare "LINK UP". 624 * The enumerated settings (see Xframe-II UG) are: 625 * 0 ........... instantaneous 626 * 1 ........... 500 ��s 627 * 2 ........... 1 ms 628 * 3 ........... 64 ms 629 * 4 ........... 256 ms 630 * 5 ........... 512 ms 631 * 6 ........... 1 s 632 * 7 ........... 2 s 633 * @device_poll_millis: Specify the interval (in mulliseconds) between 634 * successive xge_hal_device_poll() runs. 635 * stable in order for the adapter to declare "LINK UP". 636 * @no_isr_events: TBD 637 * @lro_sg_size: TBD 638 * @lro_frm_len: TBD 639 * @bimodal_interrupts: Enable bimodal interrupts in device 640 * @bimodal_timer_lo_us: TBD 641 * @bimodal_timer_hi_us: TBD 642 * @rts_mac_en: Enable Receive Traffic Steering using MAC destination address 643 * @rts_qos_en: TBD 644 * @rts_port_en: TBD 645 * @vp_config: Configuration for virtual paths 646 * @max_cqe_groups: The maximum number of adapter CQE group blocks a CQRQ 647 * can own at any one time. 648 * @max_num_wqe_od_groups: The maximum number of WQE Headers/OD Groups that 649 * this S-RQ can own at any one time. 650 * @no_wqe_threshold: Maximum number of times adapter polls WQE Hdr blocks for 651 * WQEs before generating a message or interrupt. 652 * @refill_threshold_high:This field provides a hysteresis upper bound for 653 * automatic adapter refill operations. 654 * @refill_threshold_low:This field provides a hysteresis lower bound for 655 * automatic adapter refill operations. 656 * @eol_policy:This field sets the policy for handling the end of list condition. 657 * 2'b00 - When EOL is reached,poll until last block wrapper size is no longer 0. 658 * 2'b01 - Send UMQ message when EOL is reached. 659 * 2'b1x - Poll until the poll_count_max is reached and if still EOL,send UMQ message 660 * @eol_poll_count_max:sets the maximum number of times the queue manager will poll for 661 * a non-zero block wrapper before giving up and sending a UMQ message 662 * @ack_blk_limit: Limit on the maximum number of ACK list blocks that can be held 663 * by a session at any one time. 664 * @poll_or_doorbell: TBD 665 * 666 * Xframe configuration. 667 * Contains per-device configuration parameters, including: 668 * - latency timer (settable via PCI configuration space); 669 * - maximum number of split transactions; 670 * - maximum number of shared splits; 671 * - stats sampling interval, etc. 672 * 673 * In addition, xge_hal_device_config_t{} includes "subordinate" 674 * configurations, including: 675 * - fifos and rings; 676 * - MAC (see xge_hal_mac_config_t{}). 677 * 678 * See Xframe User Guide for more details. 679 * Note: Valid (min, max) range for each attribute is specified in the body of 680 * the xge_hal_device_config_t{} structure. Please refer to the 681 * corresponding include file. 682 * See also: xge_hal_tti_config_t{}, xge_hal_stats_hw_info_t{}, 683 * xge_hal_mac_config_t{}. 684 */ 685typedef struct xge_hal_device_config_t { 686 int mtu; 687#define XGE_HAL_MIN_INITIAL_MTU XGE_HAL_MIN_MTU 688#define XGE_HAL_MAX_INITIAL_MTU XGE_HAL_MAX_MTU 689 690 int isr_polling_cnt; 691#define XGE_HAL_MIN_ISR_POLLING_CNT 0 692#define XGE_HAL_MAX_ISR_POLLING_CNT 65536 693 694 int latency_timer; 695#define XGE_HAL_USE_BIOS_DEFAULT_LATENCY -1 696#define XGE_HAL_MIN_LATENCY_TIMER 8 697#define XGE_HAL_MAX_LATENCY_TIMER 255 698 699 int napi_weight; 700#define XGE_HAL_DEF_NAPI_WEIGHT 64 701 702 int max_splits_trans; 703#define XGE_HAL_USE_BIOS_DEFAULT_SPLITS -1 704#define XGE_HAL_ONE_SPLIT_TRANSACTION 0 705#define XGE_HAL_TWO_SPLIT_TRANSACTION 1 706#define XGE_HAL_THREE_SPLIT_TRANSACTION 2 707#define XGE_HAL_FOUR_SPLIT_TRANSACTION 3 708#define XGE_HAL_EIGHT_SPLIT_TRANSACTION 4 709#define XGE_HAL_TWELVE_SPLIT_TRANSACTION 5 710#define XGE_HAL_SIXTEEN_SPLIT_TRANSACTION 6 711#define XGE_HAL_THIRTYTWO_SPLIT_TRANSACTION 7 712 713 int mmrb_count; 714#define XGE_HAL_DEFAULT_BIOS_MMRB_COUNT -1 715#define XGE_HAL_MIN_MMRB_COUNT 0 /* 512b */ 716#define XGE_HAL_MAX_MMRB_COUNT 3 /* 4k */ 717 718 int shared_splits; 719#define XGE_HAL_MIN_SHARED_SPLITS 0 720#define XGE_HAL_MAX_SHARED_SPLITS 31 721 722 int stats_refresh_time_sec; 723#define XGE_HAL_STATS_REFRESH_DISABLE 0 724#define XGE_HAL_MIN_STATS_REFRESH_TIME 1 725#define XGE_HAL_MAX_STATS_REFRESH_TIME 300 726 727 int pci_freq_mherz; 728#define XGE_HAL_PCI_FREQ_MHERZ_33 33 729#define XGE_HAL_PCI_FREQ_MHERZ_66 66 730#define XGE_HAL_PCI_FREQ_MHERZ_100 100 731#define XGE_HAL_PCI_FREQ_MHERZ_133 133 732#define XGE_HAL_PCI_FREQ_MHERZ_266 266 733 734 int intr_mode; 735#define XGE_HAL_INTR_MODE_IRQLINE 0 736#define XGE_HAL_INTR_MODE_MSI 1 737#define XGE_HAL_INTR_MODE_MSIX 2 738 739 int sched_timer_us; 740#define XGE_HAL_SCHED_TIMER_DISABLED 0 741#define XGE_HAL_SCHED_TIMER_MIN 0 742#define XGE_HAL_SCHED_TIMER_MAX 0xFFFFF 743 744 int sched_timer_one_shot; 745#define XGE_HAL_SCHED_TIMER_ON_SHOT_DISABLE 0 746#define XGE_HAL_SCHED_TIMER_ON_SHOT_ENABLE 1 747 748 xge_hal_ring_config_t ring; 749 xge_hal_mac_config_t mac; 750 xge_hal_fifo_config_t fifo; 751 752 int dump_on_serr; 753#define XGE_HAL_DUMP_ON_SERR_DISABLE 0 754#define XGE_HAL_DUMP_ON_SERR_ENABLE 1 755 756 int dump_on_eccerr; 757#define XGE_HAL_DUMP_ON_ECCERR_DISABLE 0 758#define XGE_HAL_DUMP_ON_ECCERR_ENABLE 1 759 760 int dump_on_parityerr; 761#define XGE_HAL_DUMP_ON_PARITYERR_DISABLE 0 762#define XGE_HAL_DUMP_ON_PARITYERR_ENABLE 1 763 764 int rth_en; 765#define XGE_HAL_RTH_DISABLE 0 766#define XGE_HAL_RTH_ENABLE 1 767 768 int rth_bucket_size; 769#define XGE_HAL_MIN_RTH_BUCKET_SIZE 1 770#define XGE_HAL_MAX_RTH_BUCKET_SIZE 8 771 772 int rth_spdm_en; 773#define XGE_HAL_RTH_SPDM_DISABLE 0 774#define XGE_HAL_RTH_SPDM_ENABLE 1 775 776 int rth_spdm_use_l4; 777#define XGE_HAL_RTH_SPDM_USE_L4 1 778 779 int rxufca_intr_thres; 780#define XGE_HAL_RXUFCA_INTR_THRES_MIN 1 781#define XGE_HAL_RXUFCA_INTR_THRES_MAX 4096 782 783 int rxufca_lo_lim; 784#define XGE_HAL_RXUFCA_LO_LIM_MIN 1 785#define XGE_HAL_RXUFCA_LO_LIM_MAX 16 786 787 int rxufca_hi_lim; 788#define XGE_HAL_RXUFCA_HI_LIM_MIN 1 789#define XGE_HAL_RXUFCA_HI_LIM_MAX 256 790 791 int rxufca_lbolt_period; 792#define XGE_HAL_RXUFCA_LBOLT_PERIOD_MIN 1 793#define XGE_HAL_RXUFCA_LBOLT_PERIOD_MAX 1024 794 795 int link_valid_cnt; 796#define XGE_HAL_LINK_VALID_CNT_MIN 0 797#define XGE_HAL_LINK_VALID_CNT_MAX 127 798 799 int link_retry_cnt; 800#define XGE_HAL_LINK_RETRY_CNT_MIN 0 801#define XGE_HAL_LINK_RETRY_CNT_MAX 127 802 803 int link_stability_period; 804#define XGE_HAL_DEFAULT_LINK_STABILITY_PERIOD 2 /* 1ms */ 805#define XGE_HAL_MIN_LINK_STABILITY_PERIOD 0 /* instantaneous */ 806#define XGE_HAL_MAX_LINK_STABILITY_PERIOD 7 /* 2s */ 807 808 int device_poll_millis; 809#define XGE_HAL_DEFAULT_DEVICE_POLL_MILLIS 1000 810#define XGE_HAL_MIN_DEVICE_POLL_MILLIS 1 811#define XGE_HAL_MAX_DEVICE_POLL_MILLIS 100000 812 813 int no_isr_events; 814#define XGE_HAL_NO_ISR_EVENTS_MIN 0 815#define XGE_HAL_NO_ISR_EVENTS_MAX 1 816 817 int lro_sg_size; 818#define XGE_HAL_LRO_DEFAULT_SG_SIZE 10 819#define XGE_HAL_LRO_MIN_SG_SIZE 1 820#define XGE_HAL_LRO_MAX_SG_SIZE 64 821 822 int lro_frm_len; 823#define XGE_HAL_LRO_DEFAULT_FRM_LEN 65536 824#define XGE_HAL_LRO_MIN_FRM_LEN 4096 825#define XGE_HAL_LRO_MAX_FRM_LEN 65536 826 827 int bimodal_interrupts; 828#define XGE_HAL_BIMODAL_INTR_MIN -1 829#define XGE_HAL_BIMODAL_INTR_MAX 1 830 831 int bimodal_timer_lo_us; 832#define XGE_HAL_BIMODAL_TIMER_LO_US_MIN 1 833#define XGE_HAL_BIMODAL_TIMER_LO_US_MAX 127 834 835 int bimodal_timer_hi_us; 836#define XGE_HAL_BIMODAL_TIMER_HI_US_MIN 128 837#define XGE_HAL_BIMODAL_TIMER_HI_US_MAX 65535 838 839 int rts_mac_en; 840#define XGE_HAL_RTS_MAC_DISABLE 0 841#define XGE_HAL_RTS_MAC_ENABLE 1 842 843 int rts_qos_en; 844#define XGE_HAL_RTS_QOS_DISABLE 0 845#define XGE_HAL_RTS_QOS_ENABLE 1 846 847 int rts_port_en; 848#define XGE_HAL_RTS_PORT_DISABLE 0 849#define XGE_HAL_RTS_PORT_ENABLE 1 850 851} xge_hal_device_config_t; 852 853/** 854 * struct xge_hal_driver_config_t - HAL (layer) configuration. 855 * @periodic_poll_interval_millis: Interval, in milliseconds, which is used to 856 * periodically poll HAL, i.e, invoke 857 * xge_hal_device_poll(). 858 * Note that HAL does not maintain its own 859 * polling context. HAL relies on ULD to 860 * provide one. 861 * @queue_size_initial: Initial size of the HAL protected event queue. 862 * The queue is shared by HAL and upper-layer drivers. 863 * The queue is used to exchange and process slow-path 864 * events. See xge_hal_event_e. 865 * @queue_size_max: Maximum size of the HAL queue. Depending on the load, 866 * the queue may grow at run-time up to @queue_max_size. 867 * @tracebuf_size: Size of the trace buffer. Set it to '0' to disable. 868 * HAL configuration. (Note: do not confuse HAL layer with (possibly multiple) 869 * HAL devices.) 870 * Currently this structure contains just a few basic values. 871 * Note: Valid (min, max) range for each attribute is specified in the body of 872 * the structure. Please refer to the corresponding header file. 873 * See also: xge_hal_device_poll() 874 */ 875typedef struct xge_hal_driver_config_t { 876 int queue_size_initial; 877#define XGE_HAL_MIN_QUEUE_SIZE_INITIAL 1 878#define XGE_HAL_MAX_QUEUE_SIZE_INITIAL 16 879 880 int queue_size_max; 881#define XGE_HAL_MIN_QUEUE_SIZE_MAX 1 882#define XGE_HAL_MAX_QUEUE_SIZE_MAX 16 883 884#ifdef XGE_TRACE_INTO_CIRCULAR_ARR 885 int tracebuf_size; 886#define XGE_HAL_MIN_CIRCULAR_ARR 4096 887#define XGE_HAL_MAX_CIRCULAR_ARR 1048576 888#define XGE_HAL_DEF_CIRCULAR_ARR XGE_OS_HOST_PAGE_SIZE 889 890 int tracebuf_timestamp_en; 891#define XGE_HAL_MIN_TIMESTAMP_EN 0 892#define XGE_HAL_MAX_TIMESTAMP_EN 1 893#endif 894 895} xge_hal_driver_config_t; 896 897 898/* ========================== PRIVATE API ================================= */ 899 900xge_hal_status_e 901__hal_device_config_check_common (xge_hal_device_config_t *new_config); 902 903xge_hal_status_e 904__hal_device_config_check_xena (xge_hal_device_config_t *new_config); 905 906xge_hal_status_e 907__hal_device_config_check_herc (xge_hal_device_config_t *new_config); 908 909xge_hal_status_e 910__hal_driver_config_check (xge_hal_driver_config_t *new_config); 911 912__EXTERN_END_DECLS 913 914#endif /* XGE_HAL_CONFIG_H */ 915