board.c revision 330897
1/********************************************************************* 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * 5 * Copyright 2003-2006 Raza Microelectronics, Inc. (RMI). All rights 6 * reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY Raza Microelectronics, Inc. ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES, LOSS OF USE, DATA, OR PROFITS, OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * *****************************RMI_2**********************************/ 32#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 33__FBSDID("$FreeBSD: stable/11/sys/mips/rmi/board.c 330897 2018-03-14 03:19:51Z eadler $"); 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/bus.h> 37#include <sys/kernel.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40 41#include <machine/cpufunc.h> 42#include <mips/rmi/msgring.h> 43#include <mips/rmi/rmi_boot_info.h> 44#include <mips/rmi/board.h> 45#include <mips/rmi/pic.h> 46 47#define XLR_I2C_RTC_ADDR 0xd0 48#define XLR_I2C_EEPROM_ADDR 0xa0 49#define XLR_I2C_TEMPSENSOR_ADDR 0x98 50#define XLR_I2C_ATX8_TEMPSENSOR_ADDR 0x9a 51 52struct stn_cc *xlr_core_cc_configs[] = { &cc_table_cpu_0, &cc_table_cpu_1, 53 &cc_table_cpu_2, &cc_table_cpu_3, &cc_table_cpu_4, &cc_table_cpu_5, 54 &cc_table_cpu_6, &cc_table_cpu_7}; 55 56struct stn_cc *xls_core_cc_configs[] = { &xls_cc_table_cpu_0, &xls_cc_table_cpu_1, 57 &xls_cc_table_cpu_2, &xls_cc_table_cpu_3 }; 58 59struct xlr_board_info xlr_board_info; 60 61static int 62xlr_pcmcia_present(void) 63{ 64 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET); 65 uint32_t resetconf; 66 67 resetconf = xlr_read_reg(mmio, 21); 68 return ((resetconf & 0x4000) != 0); 69} 70 71static void 72xlr_chip_specific_overrides(struct xlr_board_info* board) 73{ 74 struct xlr_gmac_block_t *blk0, *blk1, *blk2; 75 uint32_t chipid; 76 uint32_t revision; 77 78 blk0 = &board->gmac_block[0]; 79 blk1 = &board->gmac_block[1]; 80 blk2 = &board->gmac_block[2]; 81 82 chipid = xlr_processor_id(); 83 revision = xlr_revision(); 84 85 if (revision == 0x04) { /* B2 */ 86 switch (chipid) { 87 case 0x07: /* XLR 508 */ 88 case 0x08: /* XLR 516 */ 89 case 0x09: /* XLR 532 */ 90 /* NA[12] not available */ 91 memset(blk1, 0, sizeof(*blk1)); 92 memset(blk2, 0, sizeof(*blk2)); 93 break; 94 case 0x06: /* XLR 308 */ 95 /* NA0 has 3 ports */ 96 blk0->gmac_port[3].valid = 0; 97 blk0->num_ports--; 98 /* NA[12] not available */ 99 memset(blk1, 0, sizeof(*blk1)); 100 memset(blk2, 0, sizeof(*blk2)); 101 break; 102 default: 103 break; 104 } 105 } else if (revision == 0x91) { /* C4 */ 106 switch (chipid) { 107 case 0x0B: /* XLR 508 */ 108 case 0x0A: /* XLR 516 */ 109 case 0x08: /* XLR 532 */ 110 /* NA[12] not available */ 111 memset(blk1, 0, sizeof(*blk1)); 112 memset(blk2, 0, sizeof(*blk2)); 113 break; 114 case 0x0F: /* XLR 308 */ 115 /* NA0 has 3 ports */ 116 blk0->gmac_port[3].valid = 0; 117 blk0->num_ports--; 118 /* NA[12] not available */ 119 memset(blk1, 0, sizeof(*blk1)); 120 memset(blk2, 0, sizeof(*blk2)); 121 break; 122 default: 123 break; 124 } 125 } else { /* other pre-production silicon */ 126 switch (chipid) { 127 /* XLR 5xx */ 128 case 0x0B: 129 case 0x0A: 130 case 0x07: 131 case 0x08: 132 case 0x09: 133 /* NA[12] not available */ 134 memset(blk1, 0, sizeof(*blk1)); 135 memset(blk2, 0, sizeof(*blk2)); 136 break; 137 /* XLR 3xx */ 138 case 0x0F: 139 case 0x06: 140 /* NA0 has 3 ports */ 141 blk0->gmac_port[3].valid = 0; 142 blk0->num_ports--; 143 /* NA[12] not available */ 144 memset(blk1, 0, sizeof(*blk1)); 145 memset(blk2, 0, sizeof(*blk2)); 146 break; 147 default: 148 break; 149 } 150 } 151} 152 153static void 154xlr_board_specific_overrides(struct xlr_board_info* board) 155{ 156 struct xlr_gmac_block_t *blk1, *blk2; 157 158 blk1 = &board->gmac_block[1]; 159 blk2 = &board->gmac_block[2]; 160 161 switch (xlr_boot1_info.board_major_version) { 162 case RMI_XLR_BOARD_ARIZONA_I: 163 /* ATX-I has SPI-4, not XGMAC */ 164 blk1->type = XLR_SPI4; 165 blk1->enabled = 0; /* nlge does not 166 support SPI-4 */ 167 blk2->type = XLR_SPI4; 168 blk2->enabled = 0; 169 break; 170 171 case RMI_XLR_BOARD_ARIZONA_II: 172 /* XGMII_A --> VSC7281, XGMII_B --> VSC7281 */ 173 blk1->enabled = 1; 174 blk1->num_ports = 1; 175 blk1->gmac_port[0].valid = 1; 176 177 blk2->enabled = 1; 178 blk2->num_ports = 1; 179 blk2->gmac_port[0].valid = 1; 180 default: 181 break; 182 } 183} 184 185static int 186quad0_xaui(void) 187{ 188 xlr_reg_t *gpio_mmio = 189 (unsigned int *)(DEFAULT_XLR_IO_BASE + XLR_IO_GPIO_OFFSET); 190 uint32_t bit24; 191 192 bit24 = (xlr_read_reg(gpio_mmio, 0x15) >> 24) & 0x1; 193 return (bit24); 194} 195 196static int 197quad1_xaui(void) 198{ 199 xlr_reg_t *gpio_mmio = 200 (unsigned int *)(DEFAULT_XLR_IO_BASE + XLR_IO_GPIO_OFFSET); 201 uint32_t bit25; 202 203 bit25 = (xlr_read_reg(gpio_mmio, 0x15) >> 25) & 0x1; 204 return (bit25); 205} 206 207static void 208xls_chip_specific_overrides(struct xlr_board_info* board) 209{ 210 struct xlr_gmac_block_t *blk0, *blk1; 211 uint32_t chipid; 212 213 blk0 = &board->gmac_block[0]; 214 blk1 = &board->gmac_block[1]; 215 chipid = xlr_processor_id(); 216 217 switch (chipid) { 218 case 0x8E: /* XLS208 */ 219 case 0x8F: /* XLS204 */ 220 /* NA1 is not available */ 221 memset(blk1, 0, sizeof(*blk1)); 222 break; 223 case 0xCE: /* XLS108 */ 224 case 0xCF: /* XLS104 */ 225 /* NA0 has 3 ports */ 226 blk0->gmac_port[3].valid = 0; 227 blk0->num_ports--; 228 /* NA1 is not available */ 229 memset(blk1, 0, sizeof(*blk1)); 230 break; 231 default: 232 break; 233 } 234} 235 236static void 237xls_board_specific_overrides(struct xlr_board_info* board) 238{ 239 struct xlr_gmac_block_t *blk0, *blk1; 240 int i; 241 struct xlr_i2c_dev_t* iic_blk; 242 243 blk0 = &board->gmac_block[0]; 244 blk1 = &board->gmac_block[1]; 245 246 switch (xlr_boot1_info.board_major_version) { 247 case RMI_XLR_BOARD_ARIZONA_VI: 248 blk0->mode = XLR_PORT0_RGMII; 249 blk0->gmac_port[0].type = XLR_RGMII; 250 blk0->gmac_port[0].phy_addr = 0; 251 blk0->gmac_port[0].mii_addr = XLR_IO_GMAC_4_OFFSET; 252 /* Because of the Octal PHY, SGMII Quad1 is MII is also bound 253 * to the PHY attached to SGMII0_MDC/MDIO/MDINT. */ 254 for (i = 0; i < 4; i++) { 255 blk1->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET; 256 blk1->gmac_port[i].serdes_addr = XLR_IO_GMAC_0_OFFSET; 257 } 258 blk1->gmac_port[1].mii_addr = XLR_IO_GMAC_0_OFFSET; 259 blk1->gmac_port[2].mii_addr = XLR_IO_GMAC_0_OFFSET; 260 blk1->gmac_port[3].mii_addr = XLR_IO_GMAC_0_OFFSET; 261 262 blk1->gmac_port[1].serdes_addr = XLR_IO_GMAC_0_OFFSET; 263 blk1->gmac_port[2].serdes_addr = XLR_IO_GMAC_0_OFFSET; 264 blk1->gmac_port[3].serdes_addr = XLR_IO_GMAC_0_OFFSET; 265 266 /* RGMII MDIO interrupt is thru NA1 and SGMII MDIO 267 * interrupts for ports in blk1 are from NA0 */ 268 blk0->gmac_port[0].mdint_id = 1; 269 270 blk1->gmac_port[0].mdint_id = 0; 271 blk1->gmac_port[1].mdint_id = 0; 272 blk1->gmac_port[2].mdint_id = 0; 273 blk1->gmac_port[3].mdint_id = 0; 274 275 /* If we have a 4xx lite chip, don't enable the 276 * GMACs which are disabled in hardware */ 277 if (xlr_is_xls4xx_lite()) { 278 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET); 279 uint32_t tmp; 280 281 /* Port 6 & 7 are not enabled on the condor 4xx, figure 282 * this out from the GPIO fuse bank */ 283 tmp = xlr_read_reg(mmio, 35); 284 if ((tmp & (3 << 28)) != 0) { 285 blk1->enabled = 0x3; 286 blk1->gmac_port[2].valid = 0; 287 blk1->gmac_port[3].valid = 0; 288 blk1->num_ports = 2; 289 } 290 } 291 break; 292 293 case RMI_XLR_BOARD_ARIZONA_VIII: 294 iic_blk = &xlr_board_info.xlr_i2c_device[I2C_THERMAL]; 295 if (iic_blk->enabled) { 296 iic_blk->addr = XLR_I2C_ATX8_TEMPSENSOR_ADDR; 297 } 298 if (blk1->enabled) { 299 /* There is just one Octal PHY on the board and it is 300 * connected to the MII interface for NA Quad 0. */ 301 for (i = 0; i < 4; i++) { 302 blk1->gmac_port[i].mii_addr = 303 XLR_IO_GMAC_0_OFFSET; 304 blk1->gmac_port[i].mdint_id = 0; 305 } 306 } 307 break; 308 309 case RMI_XLR_BOARD_ARIZONA_XI: 310 case RMI_XLR_BOARD_ARIZONA_XII: 311 if (quad0_xaui()) { /* GMAC ports 0-3 are set to XAUI */ 312 /* only GMAC0 is active i.e, the 0-th port on this quad. 313 * Disable all the other 7 possible ports. */ 314 for (i = 1; i < MAX_NA_PORTS; i++) { 315 memset(&blk0->gmac_port[i], 0, 316 sizeof(blk0->gmac_port[i])); 317 } 318 /* Setup for XAUI on N/w Acc0: gmac0 */ 319 blk0->type = XLR_XGMAC; 320 blk0->mode = XLR_XAUI; 321 blk0->num_ports = 1; 322 blk0->gmac_port[0].type = XLR_XAUI; 323 blk1->gmac_port[0].phy_addr = 16; 324 blk0->gmac_port[0].tx_bucket_id = blk0->station_txbase; 325 /* Other addresses etc need not be modified as XAUI_0 326 * shares its addresses with SGMII GMAC_0, which was 327 * set in the caller. */ 328 } 329 else { 330 blk0->num_ports = 1; /* only 1 RGMII port */ 331 blk0->mode = XLR_PORT0_RGMII; 332 blk0->gmac_port[0].type = XLR_RGMII; 333 blk0->gmac_port[0].phy_addr = 0; 334 blk0->gmac_port[0].mii_addr = XLR_IO_GMAC_0_OFFSET; 335 } 336 337 if (quad1_xaui()) { /* GMAC ports 4-7 are used for XAUI */ 338 /* only GMAC4 is active i.e, the 0-th port on this quad. 339 * Disable all the other 7 possible ports. */ 340 for (i = 1; i < MAX_NA_PORTS; i++) { 341 memset(&blk1->gmac_port[i], 0, 342 sizeof(blk1->gmac_port[i])); 343 } 344 /* Setup for XAUI on N/w Acc1: gmac4 */ 345 blk1->type = XLR_XGMAC; 346 blk1->mode = XLR_XAUI; 347 blk1->num_ports = 1; 348 /* XAUI and SGMII ports share FMN buckets on N/w Acc 1; 349 so, station_txbase, station_rfr need not be 350 patched up. */ 351 blk1->gmac_port[0].type = XLR_XAUI; 352 blk1->gmac_port[0].phy_addr = 16; 353 blk1->gmac_port[0].tx_bucket_id = blk1->station_txbase; 354 /* Other addresses etc need not be modified as XAUI_1 355 * shares its addresses with SGMII GMAC_4, which was 356 * set in the caller. */ 357 } 358 break; 359 360 default: 361 break; 362 } 363} 364 365/* 366 * All our knowledge of chip and board that cannot be detected by probing 367 * at run-time goes here 368 */ 369int 370xlr_board_info_setup() 371{ 372 struct xlr_gmac_block_t *blk0, *blk1, *blk2; 373 struct xlr_i2c_dev_t* iic_blk; 374 int i; 375 376 /* This setup code is long'ish because the same base driver 377 * (if_nlge.c) is used for different: 378 * - CPUs (XLR/XLS) 379 * - boards (for each CPU, multiple board configs are possible 380 * and available). 381 * 382 * At the time of writing, there are atleast 12 boards, 4 with XLR 383 * and 8 with XLS. This means that the base driver needs to work with 384 * 12 different configurations, with varying levels of differences. 385 * To accomodate the different configs, the xlr_board_info struct 386 * has various attributes for paramters that could be different. 387 * These attributes are setup here and can be used directly in the 388 * base driver. 389 * It was seen that the setup code is not entirely trivial and 390 * it is possible to organize it in different ways. In the following, 391 * we choose an approach that sacrifices code-compactness/speed for 392 * readability. This is because configuration code executes once 393 * per reboot and hence has a minimal performance impact. 394 * On the other hand, driver debugging/enhancements require 395 * that different engineers can quickly comprehend the setup 396 * sequence. Hence, readability is seen as the key requirement for 397 * this code. It is for the reader to decide how much of this 398 * requirement is met with the current code organization !! 399 * 400 * The initialization is organized thus: 401 * 402 * if (CPU is XLS) { 403 * // initialize per XLS architecture 404 * // default inits (per chip spec) 405 * // chip-specific overrides 406 * // board-specific overrides 407 * } else if (CPU is XLR) { 408 * // initialize per XLR architecture 409 * // default inits (per chip spec) 410 * // chip-specific overrides 411 * // board-specific overrides 412 * } 413 * 414 * For each CPU family, all the default initializations 415 * are done for a fully-loaded device of that family. 416 * This configuration is then adjusted for the actual 417 * chip id. This is followed up with board specific 418 * overrides. 419 */ 420 421 /* start with a clean slate */ 422 memset(&xlr_board_info, 0, sizeof(xlr_board_info)); 423 xlr_board_info.ata = xlr_pcmcia_present(); 424 425 blk0 = &xlr_board_info.gmac_block[0]; 426 blk1 = &xlr_board_info.gmac_block[1]; 427 blk2 = &xlr_board_info.gmac_block[2]; 428 429 iic_blk = xlr_board_info.xlr_i2c_device; 430 iic_blk[I2C_RTC].enabled = 1; 431 iic_blk[I2C_RTC].addr = XLR_I2C_RTC_ADDR; 432 iic_blk[I2C_THERMAL].enabled = 1; 433 iic_blk[I2C_THERMAL].addr = XLR_I2C_TEMPSENSOR_ADDR; 434 iic_blk[I2C_EEPROM].enabled = 1; 435 iic_blk[I2C_EEPROM].addr = XLR_I2C_EEPROM_ADDR; 436 437 if (xlr_is_xls()) { 438 xlr_board_info.is_xls = 1; 439 xlr_board_info.nr_cpus = 8; 440 xlr_board_info.usb = 1; 441 /* Board version 8 has NAND flash */ 442 xlr_board_info.cfi = 443 (xlr_boot1_info.board_major_version != RMI_XLR_BOARD_ARIZONA_VIII); 444 xlr_board_info.pci_irq = 0; 445 xlr_board_info.credit_configs = xls_core_cc_configs; 446 xlr_board_info.bucket_sizes = &xls_bucket_sizes; 447 xlr_board_info.gmacports = MAX_NA_PORTS; 448 449 /* ---------------- Network Acc 0 ---------------- */ 450 451 blk0->type = XLR_GMAC; 452 blk0->enabled = 0xf; 453 blk0->credit_config = &xls_cc_table_gmac0; 454 blk0->station_id = MSGRNG_STNID_GMAC; 455 blk0->station_txbase = MSGRNG_STNID_GMACTX0; 456 blk0->station_rfr = MSGRNG_STNID_GMACRFR_0; 457 blk0->mode = XLR_SGMII; 458 blk0->baseaddr = XLR_IO_GMAC_0_OFFSET; 459 blk0->baseirq = PIC_GMAC_0_IRQ; 460 blk0->baseinst = 0; 461 462 /* By default, assume SGMII is setup. But this can change based 463 on board-specific or setting-specific info. */ 464 for (i = 0; i < 4; i++) { 465 blk0->gmac_port[i].valid = 1; 466 blk0->gmac_port[i].instance = i + blk0->baseinst; 467 blk0->gmac_port[i].type = XLR_SGMII; 468 blk0->gmac_port[i].phy_addr = i + 16; 469 blk0->gmac_port[i].tx_bucket_id = 470 blk0->station_txbase + i; 471 blk0->gmac_port[i].mdint_id = 0; 472 blk0->num_ports++; 473 blk0->gmac_port[i].base_addr = XLR_IO_GMAC_0_OFFSET + i * 0x1000; 474 blk0->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET; 475 blk0->gmac_port[i].pcs_addr = XLR_IO_GMAC_0_OFFSET; 476 blk0->gmac_port[i].serdes_addr = XLR_IO_GMAC_0_OFFSET; 477 } 478 479 /* ---------------- Network Acc 1 ---------------- */ 480 blk1->type = XLR_GMAC; 481 blk1->enabled = 0xf; 482 blk1->credit_config = &xls_cc_table_gmac1; 483 blk1->station_id = MSGRNG_STNID_GMAC1; 484 blk1->station_txbase = MSGRNG_STNID_GMAC1_TX0; 485 blk1->station_rfr = MSGRNG_STNID_GMAC1_FR_0; 486 blk1->mode = XLR_SGMII; 487 blk1->baseaddr = XLR_IO_GMAC_4_OFFSET; 488 blk1->baseirq = PIC_XGS_0_IRQ; 489 blk1->baseinst = 4; 490 491 for (i = 0; i < 4; i++) { 492 blk1->gmac_port[i].valid = 1; 493 blk1->gmac_port[i].instance = i + blk1->baseinst; 494 blk1->gmac_port[i].type = XLR_SGMII; 495 blk1->gmac_port[i].phy_addr = i + 20; 496 blk1->gmac_port[i].tx_bucket_id = 497 blk1->station_txbase + i; 498 blk1->gmac_port[i].mdint_id = 1; 499 blk1->num_ports++; 500 blk1->gmac_port[i].base_addr = XLR_IO_GMAC_4_OFFSET + i * 0x1000; 501 blk1->gmac_port[i].mii_addr = XLR_IO_GMAC_4_OFFSET; 502 blk1->gmac_port[i].pcs_addr = XLR_IO_GMAC_4_OFFSET; 503 blk1->gmac_port[i].serdes_addr = XLR_IO_GMAC_0_OFFSET; 504 } 505 506 /* ---------------- Network Acc 2 ---------------- */ 507 xlr_board_info.gmac_block[2].enabled = 0; /* disabled on XLS */ 508 509 xls_chip_specific_overrides(&xlr_board_info); 510 xls_board_specific_overrides(&xlr_board_info); 511 512 } else { /* XLR */ 513 xlr_board_info.is_xls = 0; 514 xlr_board_info.nr_cpus = 32; 515 xlr_board_info.usb = 0; 516 xlr_board_info.cfi = 1; 517 xlr_board_info.pci_irq = 0; 518 xlr_board_info.credit_configs = xlr_core_cc_configs; 519 xlr_board_info.bucket_sizes = &bucket_sizes; 520 xlr_board_info.gmacports = 4; 521 522 /* ---------------- GMAC0 ---------------- */ 523 blk0->type = XLR_GMAC; 524 blk0->enabled = 0xf; 525 blk0->credit_config = &cc_table_gmac; 526 blk0->station_id = MSGRNG_STNID_GMAC; 527 blk0->station_txbase = MSGRNG_STNID_GMACTX0; 528 blk0->station_rfr = MSGRNG_STNID_GMACRFR_0; 529 blk0->mode = XLR_RGMII; 530 blk0->baseaddr = XLR_IO_GMAC_0_OFFSET; 531 blk0->baseirq = PIC_GMAC_0_IRQ; 532 blk0->baseinst = 0; 533 534 /* first, do the common/easy stuff for all the ports */ 535 for (i = 0; i < 4; i++) { 536 blk0->gmac_port[i].valid = 1; 537 blk0->gmac_port[i].instance = i + blk0->baseinst; 538 blk0->gmac_port[i].type = XLR_RGMII; 539 blk0->gmac_port[i].phy_addr = i; 540 blk0->gmac_port[i].tx_bucket_id = 541 blk0->station_txbase + i; 542 blk0->gmac_port[i].mdint_id = 0; 543 blk0->gmac_port[i].base_addr = XLR_IO_GMAC_0_OFFSET + i * 0x1000; 544 blk0->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET; 545 /* RGMII ports, no PCS/SERDES */ 546 blk0->num_ports++; 547 } 548 549 /* ---------------- XGMAC0 ---------------- */ 550 blk1->type = XLR_XGMAC; 551 blk1->mode = XLR_XGMII; 552 blk1->enabled = 0; 553 blk1->credit_config = &cc_table_xgs_0; 554 blk1->station_txbase = MSGRNG_STNID_XGS0_TX; 555 blk1->station_rfr = MSGRNG_STNID_XMAC0RFR; 556 blk1->station_id = MSGRNG_STNID_XGS0FR; 557 blk1->baseaddr = XLR_IO_XGMAC_0_OFFSET; 558 blk1->baseirq = PIC_XGS_0_IRQ; 559 blk1->baseinst = 4; 560 561 blk1->gmac_port[0].type = XLR_XGMII; 562 blk1->gmac_port[0].instance = 0; 563 blk1->gmac_port[0].phy_addr = 0; 564 blk1->gmac_port[0].base_addr = XLR_IO_XGMAC_0_OFFSET; 565 blk1->gmac_port[0].mii_addr = XLR_IO_XGMAC_0_OFFSET; 566 blk1->gmac_port[0].tx_bucket_id = blk1->station_txbase; 567 blk1->gmac_port[0].mdint_id = 1; 568 569 /* ---------------- XGMAC1 ---------------- */ 570 blk2->type = XLR_XGMAC; 571 blk2->mode = XLR_XGMII; 572 blk2->enabled = 0; 573 blk2->credit_config = &cc_table_xgs_1; 574 blk2->station_txbase = MSGRNG_STNID_XGS1_TX; 575 blk2->station_rfr = MSGRNG_STNID_XMAC1RFR; 576 blk2->station_id = MSGRNG_STNID_XGS1FR; 577 blk2->baseaddr = XLR_IO_XGMAC_1_OFFSET; 578 blk2->baseirq = PIC_XGS_1_IRQ; 579 blk2->baseinst = 5; 580 581 blk2->gmac_port[0].type = XLR_XGMII; 582 blk2->gmac_port[0].instance = 0; 583 blk2->gmac_port[0].phy_addr = 0; 584 blk2->gmac_port[0].base_addr = XLR_IO_XGMAC_1_OFFSET; 585 blk2->gmac_port[0].mii_addr = XLR_IO_XGMAC_1_OFFSET; 586 blk2->gmac_port[0].tx_bucket_id = blk2->station_txbase; 587 blk2->gmac_port[0].mdint_id = 2; 588 589 /* Done with default setup. Now handle chip and board-specific 590 variations. */ 591 xlr_chip_specific_overrides(&xlr_board_info); 592 xlr_board_specific_overrides(&xlr_board_info); 593 } 594 return 0; 595} 596