uart_dev_ns8250.c revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include "opt_platform.h" 30#include "opt_uart.h" 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: stable/11/sys/dev/uart/uart_dev_ns8250.c 330897 2018-03-14 03:19:51Z eadler $"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/conf.h> 39#include <sys/kernel.h> 40#include <sys/sysctl.h> 41#include <machine/bus.h> 42 43#ifdef FDT 44#include <dev/fdt/fdt_common.h> 45#include <dev/ofw/ofw_bus.h> 46#include <dev/ofw/ofw_bus_subr.h> 47#endif 48 49#include <dev/uart/uart.h> 50#include <dev/uart/uart_cpu.h> 51#ifdef FDT 52#include <dev/uart/uart_cpu_fdt.h> 53#endif 54#include <dev/uart/uart_bus.h> 55#include <dev/uart/uart_dev_ns8250.h> 56#include <dev/uart/uart_ppstypes.h> 57 58#include <dev/ic/ns16550.h> 59 60#include "uart_if.h" 61 62#define DEFAULT_RCLK 1843200 63 64/* 65 * Set the default baudrate tolerance to 3.0%. 66 * 67 * Some embedded boards have odd reference clocks (eg 25MHz) 68 * and we need to handle higher variances in the target baud rate. 69 */ 70#ifndef UART_DEV_TOLERANCE_PCT 71#define UART_DEV_TOLERANCE_PCT 30 72#endif /* UART_DEV_TOLERANCE_PCT */ 73 74static int broken_txfifo = 0; 75SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 76 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 77 78/* 79 * Clear pending interrupts. THRE is cleared by reading IIR. Data 80 * that may have been received gets lost here. 81 */ 82static void 83ns8250_clrint(struct uart_bas *bas) 84{ 85 uint8_t iir, lsr; 86 87 iir = uart_getreg(bas, REG_IIR); 88 while ((iir & IIR_NOPEND) == 0) { 89 iir &= IIR_IMASK; 90 if (iir == IIR_RLS) { 91 lsr = uart_getreg(bas, REG_LSR); 92 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 93 (void)uart_getreg(bas, REG_DATA); 94 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 95 (void)uart_getreg(bas, REG_DATA); 96 else if (iir == IIR_MLSC) 97 (void)uart_getreg(bas, REG_MSR); 98 uart_barrier(bas); 99 iir = uart_getreg(bas, REG_IIR); 100 } 101} 102 103static int 104ns8250_delay(struct uart_bas *bas) 105{ 106 int divisor; 107 u_char lcr; 108 109 lcr = uart_getreg(bas, REG_LCR); 110 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 111 uart_barrier(bas); 112 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 113 uart_barrier(bas); 114 uart_setreg(bas, REG_LCR, lcr); 115 uart_barrier(bas); 116 117 /* 1/10th the time to transmit 1 character (estimate). */ 118 if (divisor <= 134) 119 return (16000000 * divisor / bas->rclk); 120 return (16000 * divisor / (bas->rclk / 1000)); 121} 122 123static int 124ns8250_divisor(int rclk, int baudrate) 125{ 126 int actual_baud, divisor; 127 int error; 128 129 if (baudrate == 0) 130 return (0); 131 132 divisor = (rclk / (baudrate << 3) + 1) >> 1; 133 if (divisor == 0 || divisor >= 65536) 134 return (0); 135 actual_baud = rclk / (divisor << 4); 136 137 /* 10 times error in percent: */ 138 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 139 140 /* enforce maximum error tolerance: */ 141 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 142 return (0); 143 144 return (divisor); 145} 146 147static int 148ns8250_drain(struct uart_bas *bas, int what) 149{ 150 int delay, limit; 151 152 delay = ns8250_delay(bas); 153 154 if (what & UART_DRAIN_TRANSMITTER) { 155 /* 156 * Pick an arbitrary high limit to avoid getting stuck in 157 * an infinite loop when the hardware is broken. Make the 158 * limit high enough to handle large FIFOs. 159 */ 160 limit = 10*1024; 161 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 162 DELAY(delay); 163 if (limit == 0) { 164 /* printf("ns8250: transmitter appears stuck... "); */ 165 return (EIO); 166 } 167 } 168 169 if (what & UART_DRAIN_RECEIVER) { 170 /* 171 * Pick an arbitrary high limit to avoid getting stuck in 172 * an infinite loop when the hardware is broken. Make the 173 * limit high enough to handle large FIFOs and integrated 174 * UARTs. The HP rx2600 for example has 3 UARTs on the 175 * management board that tend to get a lot of data send 176 * to it when the UART is first activated. 177 */ 178 limit=10*4096; 179 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 180 (void)uart_getreg(bas, REG_DATA); 181 uart_barrier(bas); 182 DELAY(delay << 2); 183 } 184 if (limit == 0) { 185 /* printf("ns8250: receiver appears broken... "); */ 186 return (EIO); 187 } 188 } 189 190 return (0); 191} 192 193/* 194 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 195 * drained. WARNING: this function clobbers the FIFO setting! 196 */ 197static void 198ns8250_flush(struct uart_bas *bas, int what) 199{ 200 uint8_t fcr; 201 202 fcr = FCR_ENABLE; 203 if (what & UART_FLUSH_TRANSMITTER) 204 fcr |= FCR_XMT_RST; 205 if (what & UART_FLUSH_RECEIVER) 206 fcr |= FCR_RCV_RST; 207 uart_setreg(bas, REG_FCR, fcr); 208 uart_barrier(bas); 209} 210 211static int 212ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 213 int parity) 214{ 215 int divisor; 216 uint8_t lcr; 217 218 lcr = 0; 219 if (databits >= 8) 220 lcr |= LCR_8BITS; 221 else if (databits == 7) 222 lcr |= LCR_7BITS; 223 else if (databits == 6) 224 lcr |= LCR_6BITS; 225 else 226 lcr |= LCR_5BITS; 227 if (stopbits > 1) 228 lcr |= LCR_STOPB; 229 lcr |= parity << 3; 230 231 /* Set baudrate. */ 232 if (baudrate > 0) { 233 divisor = ns8250_divisor(bas->rclk, baudrate); 234 if (divisor == 0) 235 return (EINVAL); 236 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 237 uart_barrier(bas); 238 uart_setreg(bas, REG_DLL, divisor & 0xff); 239 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 240 uart_barrier(bas); 241 } 242 243 /* Set LCR and clear DLAB. */ 244 uart_setreg(bas, REG_LCR, lcr); 245 uart_barrier(bas); 246 return (0); 247} 248 249/* 250 * Low-level UART interface. 251 */ 252static int ns8250_probe(struct uart_bas *bas); 253static void ns8250_init(struct uart_bas *bas, int, int, int, int); 254static void ns8250_term(struct uart_bas *bas); 255static void ns8250_putc(struct uart_bas *bas, int); 256static int ns8250_rxready(struct uart_bas *bas); 257static int ns8250_getc(struct uart_bas *bas, struct mtx *); 258 259struct uart_ops uart_ns8250_ops = { 260 .probe = ns8250_probe, 261 .init = ns8250_init, 262 .term = ns8250_term, 263 .putc = ns8250_putc, 264 .rxready = ns8250_rxready, 265 .getc = ns8250_getc, 266}; 267 268static int 269ns8250_probe(struct uart_bas *bas) 270{ 271 u_char val; 272 273 /* Check known 0 bits that don't depend on DLAB. */ 274 val = uart_getreg(bas, REG_IIR); 275 if (val & 0x30) 276 return (ENXIO); 277 /* 278 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 279 * chip, but otherwise doesn't seem to have a function. In 280 * other words, uart(4) works regardless. Ignore that bit so 281 * the probe succeeds. 282 */ 283 val = uart_getreg(bas, REG_MCR); 284 if (val & 0xa0) 285 return (ENXIO); 286 287 return (0); 288} 289 290static void 291ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 292 int parity) 293{ 294 u_char ier; 295 296 if (bas->rclk == 0) 297 bas->rclk = DEFAULT_RCLK; 298 ns8250_param(bas, baudrate, databits, stopbits, parity); 299 300 /* Disable all interrupt sources. */ 301 /* 302 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 303 * UARTs split the receive time-out interrupt bit out separately as 304 * 0x10. This gets handled by ier_mask and ier_rxbits below. 305 */ 306 ier = uart_getreg(bas, REG_IER) & 0xe0; 307 uart_setreg(bas, REG_IER, ier); 308 uart_barrier(bas); 309 310 /* Disable the FIFO (if present). */ 311 uart_setreg(bas, REG_FCR, 0); 312 uart_barrier(bas); 313 314 /* Set RTS & DTR. */ 315 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 316 uart_barrier(bas); 317 318 ns8250_clrint(bas); 319} 320 321static void 322ns8250_term(struct uart_bas *bas) 323{ 324 325 /* Clear RTS & DTR. */ 326 uart_setreg(bas, REG_MCR, MCR_IE); 327 uart_barrier(bas); 328} 329 330static void 331ns8250_putc(struct uart_bas *bas, int c) 332{ 333 int limit; 334 335 limit = 250000; 336 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 337 DELAY(4); 338 uart_setreg(bas, REG_DATA, c); 339 uart_barrier(bas); 340} 341 342static int 343ns8250_rxready(struct uart_bas *bas) 344{ 345 346 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 347} 348 349static int 350ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 351{ 352 int c; 353 354 uart_lock(hwmtx); 355 356 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 357 uart_unlock(hwmtx); 358 DELAY(4); 359 uart_lock(hwmtx); 360 } 361 362 c = uart_getreg(bas, REG_DATA); 363 364 uart_unlock(hwmtx); 365 366 return (c); 367} 368 369static kobj_method_t ns8250_methods[] = { 370 KOBJMETHOD(uart_attach, ns8250_bus_attach), 371 KOBJMETHOD(uart_detach, ns8250_bus_detach), 372 KOBJMETHOD(uart_flush, ns8250_bus_flush), 373 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 374 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 375 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 376 KOBJMETHOD(uart_param, ns8250_bus_param), 377 KOBJMETHOD(uart_probe, ns8250_bus_probe), 378 KOBJMETHOD(uart_receive, ns8250_bus_receive), 379 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 380 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 381 KOBJMETHOD(uart_grab, ns8250_bus_grab), 382 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 383 { 0, 0 } 384}; 385 386struct uart_class uart_ns8250_class = { 387 "ns8250", 388 ns8250_methods, 389 sizeof(struct ns8250_softc), 390 .uc_ops = &uart_ns8250_ops, 391 .uc_range = 8, 392 .uc_rclk = DEFAULT_RCLK, 393 .uc_rshift = 0 394}; 395 396#ifdef FDT 397static struct ofw_compat_data compat_data[] = { 398 {"ns16550", (uintptr_t)&uart_ns8250_class}, 399 {"ns16550a", (uintptr_t)&uart_ns8250_class}, 400 {NULL, (uintptr_t)NULL}, 401}; 402UART_FDT_CLASS_AND_DEVICE(compat_data); 403#endif 404 405/* Use token-pasting to form SER_ and MSR_ named constants. */ 406#define SER(sig) SER_##sig 407#define SERD(sig) SER_D##sig 408#define MSR(sig) MSR_##sig 409#define MSRD(sig) MSR_D##sig 410 411/* 412 * Detect signal changes using software delta detection. The previous state of 413 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 414 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 415 * new state of both the signal and the delta bits. 416 */ 417#define SIGCHGSW(var, msr, sig) \ 418 if ((msr) & MSR(sig)) { \ 419 if ((var & SER(sig)) == 0) \ 420 var |= SERD(sig) | SER(sig); \ 421 } else { \ 422 if ((var & SER(sig)) != 0) \ 423 var = SERD(sig) | (var & ~SER(sig)); \ 424 } 425 426/* 427 * Detect signal changes using the hardware msr delta bits. This is currently 428 * used only when PPS timing information is being captured using the "narrow 429 * pulse" option. With a narrow PPS pulse the signal may not still be asserted 430 * by time the interrupt handler is invoked. The hardware will latch the fact 431 * that it changed in the delta bits. 432 */ 433#define SIGCHGHW(var, msr, sig) \ 434 if ((msr) & MSRD(sig)) { \ 435 if (((msr) & MSR(sig)) != 0) \ 436 var |= SERD(sig) | SER(sig); \ 437 else \ 438 var = SERD(sig) | (var & ~SER(sig)); \ 439 } 440 441int 442ns8250_bus_attach(struct uart_softc *sc) 443{ 444 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 445 struct uart_bas *bas; 446 unsigned int ivar; 447#ifdef FDT 448 phandle_t node; 449 pcell_t cell; 450#endif 451 452#ifdef FDT 453 /* Check whether uart has a broken txfifo. */ 454 node = ofw_bus_get_node(sc->sc_dev); 455 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 456 broken_txfifo = cell ? 1 : 0; 457#endif 458 459 bas = &sc->sc_bas; 460 461 ns8250->mcr = uart_getreg(bas, REG_MCR); 462 ns8250->fcr = FCR_ENABLE; 463 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 464 &ivar)) { 465 if (UART_FLAGS_FCR_RX_LOW(ivar)) 466 ns8250->fcr |= FCR_RX_LOW; 467 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 468 ns8250->fcr |= FCR_RX_MEDL; 469 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 470 ns8250->fcr |= FCR_RX_HIGH; 471 else 472 ns8250->fcr |= FCR_RX_MEDH; 473 } else 474 ns8250->fcr |= FCR_RX_MEDH; 475 476 /* Get IER mask */ 477 ivar = 0xf0; 478 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 479 &ivar); 480 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 481 482 /* Get IER RX interrupt bits */ 483 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 484 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 485 &ivar); 486 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 487 488 uart_setreg(bas, REG_FCR, ns8250->fcr); 489 uart_barrier(bas); 490 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 491 492 if (ns8250->mcr & MCR_DTR) 493 sc->sc_hwsig |= SER_DTR; 494 if (ns8250->mcr & MCR_RTS) 495 sc->sc_hwsig |= SER_RTS; 496 ns8250_bus_getsig(sc); 497 498 ns8250_clrint(bas); 499 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 500 ns8250->ier |= ns8250->ier_rxbits; 501 uart_setreg(bas, REG_IER, ns8250->ier); 502 uart_barrier(bas); 503 504 /* 505 * Timing of the H/W access was changed with r253161 of uart_core.c 506 * It has been observed that an ITE IT8513E would signal a break 507 * condition with pretty much every character it received, unless 508 * it had enough time to settle between ns8250_bus_attach() and 509 * ns8250_bus_ipend() -- which it accidentally had before r253161. 510 * It's not understood why the UART chip behaves this way and it 511 * could very well be that the DELAY make the H/W work in the same 512 * accidental manner as before. More analysis is warranted, but 513 * at least now we fixed a known regression. 514 */ 515 DELAY(200); 516 return (0); 517} 518 519int 520ns8250_bus_detach(struct uart_softc *sc) 521{ 522 struct ns8250_softc *ns8250; 523 struct uart_bas *bas; 524 u_char ier; 525 526 ns8250 = (struct ns8250_softc *)sc; 527 bas = &sc->sc_bas; 528 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 529 uart_setreg(bas, REG_IER, ier); 530 uart_barrier(bas); 531 ns8250_clrint(bas); 532 return (0); 533} 534 535int 536ns8250_bus_flush(struct uart_softc *sc, int what) 537{ 538 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 539 struct uart_bas *bas; 540 int error; 541 542 bas = &sc->sc_bas; 543 uart_lock(sc->sc_hwmtx); 544 if (sc->sc_rxfifosz > 1) { 545 ns8250_flush(bas, what); 546 uart_setreg(bas, REG_FCR, ns8250->fcr); 547 uart_barrier(bas); 548 error = 0; 549 } else 550 error = ns8250_drain(bas, what); 551 uart_unlock(sc->sc_hwmtx); 552 return (error); 553} 554 555int 556ns8250_bus_getsig(struct uart_softc *sc) 557{ 558 uint32_t old, sig; 559 uint8_t msr; 560 561 /* 562 * The delta bits are reputed to be broken on some hardware, so use 563 * software delta detection by default. Use the hardware delta bits 564 * when capturing PPS pulses which are too narrow for software detection 565 * to see the edges. Hardware delta for RI doesn't work like the 566 * others, so always use software for it. Other threads may be changing 567 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully 568 * update without other changes happening. Note that the SIGCHGxx() 569 * macros carefully preserve the delta bits when we have to loop several 570 * times and a signal transitions between iterations. 571 */ 572 do { 573 old = sc->sc_hwsig; 574 sig = old; 575 uart_lock(sc->sc_hwmtx); 576 msr = uart_getreg(&sc->sc_bas, REG_MSR); 577 uart_unlock(sc->sc_hwmtx); 578 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 579 SIGCHGHW(sig, msr, DSR); 580 SIGCHGHW(sig, msr, CTS); 581 SIGCHGHW(sig, msr, DCD); 582 } else { 583 SIGCHGSW(sig, msr, DSR); 584 SIGCHGSW(sig, msr, CTS); 585 SIGCHGSW(sig, msr, DCD); 586 } 587 SIGCHGSW(sig, msr, RI); 588 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 589 return (sig); 590} 591 592int 593ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 594{ 595 struct uart_bas *bas; 596 int baudrate, divisor, error; 597 uint8_t efr, lcr; 598 599 bas = &sc->sc_bas; 600 error = 0; 601 uart_lock(sc->sc_hwmtx); 602 switch (request) { 603 case UART_IOCTL_BREAK: 604 lcr = uart_getreg(bas, REG_LCR); 605 if (data) 606 lcr |= LCR_SBREAK; 607 else 608 lcr &= ~LCR_SBREAK; 609 uart_setreg(bas, REG_LCR, lcr); 610 uart_barrier(bas); 611 break; 612 case UART_IOCTL_IFLOW: 613 lcr = uart_getreg(bas, REG_LCR); 614 uart_barrier(bas); 615 uart_setreg(bas, REG_LCR, 0xbf); 616 uart_barrier(bas); 617 efr = uart_getreg(bas, REG_EFR); 618 if (data) 619 efr |= EFR_RTS; 620 else 621 efr &= ~EFR_RTS; 622 uart_setreg(bas, REG_EFR, efr); 623 uart_barrier(bas); 624 uart_setreg(bas, REG_LCR, lcr); 625 uart_barrier(bas); 626 break; 627 case UART_IOCTL_OFLOW: 628 lcr = uart_getreg(bas, REG_LCR); 629 uart_barrier(bas); 630 uart_setreg(bas, REG_LCR, 0xbf); 631 uart_barrier(bas); 632 efr = uart_getreg(bas, REG_EFR); 633 if (data) 634 efr |= EFR_CTS; 635 else 636 efr &= ~EFR_CTS; 637 uart_setreg(bas, REG_EFR, efr); 638 uart_barrier(bas); 639 uart_setreg(bas, REG_LCR, lcr); 640 uart_barrier(bas); 641 break; 642 case UART_IOCTL_BAUD: 643 lcr = uart_getreg(bas, REG_LCR); 644 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 645 uart_barrier(bas); 646 divisor = uart_getreg(bas, REG_DLL) | 647 (uart_getreg(bas, REG_DLH) << 8); 648 uart_barrier(bas); 649 uart_setreg(bas, REG_LCR, lcr); 650 uart_barrier(bas); 651 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 652 if (baudrate > 0) 653 *(int*)data = baudrate; 654 else 655 error = ENXIO; 656 break; 657 default: 658 error = EINVAL; 659 break; 660 } 661 uart_unlock(sc->sc_hwmtx); 662 return (error); 663} 664 665int 666ns8250_bus_ipend(struct uart_softc *sc) 667{ 668 struct uart_bas *bas; 669 struct ns8250_softc *ns8250; 670 int ipend; 671 uint8_t iir, lsr; 672 673 ns8250 = (struct ns8250_softc *)sc; 674 bas = &sc->sc_bas; 675 uart_lock(sc->sc_hwmtx); 676 iir = uart_getreg(bas, REG_IIR); 677 678 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 679 (void)uart_getreg(bas, DW_REG_USR); 680 uart_unlock(sc->sc_hwmtx); 681 return (0); 682 } 683 if (iir & IIR_NOPEND) { 684 uart_unlock(sc->sc_hwmtx); 685 return (0); 686 } 687 ipend = 0; 688 if (iir & IIR_RXRDY) { 689 lsr = uart_getreg(bas, REG_LSR); 690 if (lsr & LSR_OE) 691 ipend |= SER_INT_OVERRUN; 692 if (lsr & LSR_BI) 693 ipend |= SER_INT_BREAK; 694 if (lsr & LSR_RXRDY) 695 ipend |= SER_INT_RXREADY; 696 } else { 697 if (iir & IIR_TXRDY) { 698 ipend |= SER_INT_TXIDLE; 699 uart_setreg(bas, REG_IER, ns8250->ier); 700 uart_barrier(bas); 701 } else 702 ipend |= SER_INT_SIGCHG; 703 } 704 if (ipend == 0) 705 ns8250_clrint(bas); 706 uart_unlock(sc->sc_hwmtx); 707 return (ipend); 708} 709 710int 711ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 712 int stopbits, int parity) 713{ 714 struct ns8250_softc *ns8250; 715 struct uart_bas *bas; 716 int error, limit; 717 718 ns8250 = (struct ns8250_softc*)sc; 719 bas = &sc->sc_bas; 720 uart_lock(sc->sc_hwmtx); 721 /* 722 * When using DW UART with BUSY detection it is necessary to wait 723 * until all serial transfers are finished before manipulating the 724 * line control. LCR will not be affected when UART is busy. 725 */ 726 if (ns8250->busy_detect != 0) { 727 /* 728 * Pick an arbitrary high limit to avoid getting stuck in 729 * an infinite loop in case when the hardware is broken. 730 */ 731 limit = 10 * 1024; 732 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 733 --limit) 734 DELAY(4); 735 736 if (limit <= 0) { 737 /* UART appears to be stuck */ 738 uart_unlock(sc->sc_hwmtx); 739 return (EIO); 740 } 741 } 742 743 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 744 uart_unlock(sc->sc_hwmtx); 745 return (error); 746} 747 748int 749ns8250_bus_probe(struct uart_softc *sc) 750{ 751 struct ns8250_softc *ns8250; 752 struct uart_bas *bas; 753 int count, delay, error, limit; 754 uint8_t lsr, mcr, ier; 755 756 ns8250 = (struct ns8250_softc *)sc; 757 bas = &sc->sc_bas; 758 759 error = ns8250_probe(bas); 760 if (error) 761 return (error); 762 763 mcr = MCR_IE; 764 if (sc->sc_sysdev == NULL) { 765 /* By using ns8250_init() we also set DTR and RTS. */ 766 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 767 } else 768 mcr |= MCR_DTR | MCR_RTS; 769 770 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 771 if (error) 772 return (error); 773 774 /* 775 * Set loopback mode. This avoids having garbage on the wire and 776 * also allows us send and receive data. We set DTR and RTS to 777 * avoid the possibility that automatic flow-control prevents 778 * any data from being sent. 779 */ 780 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 781 uart_barrier(bas); 782 783 /* 784 * Enable FIFOs. And check that the UART has them. If not, we're 785 * done. Since this is the first time we enable the FIFOs, we reset 786 * them. 787 */ 788 uart_setreg(bas, REG_FCR, FCR_ENABLE); 789 uart_barrier(bas); 790 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 791 /* 792 * NS16450 or INS8250. We don't bother to differentiate 793 * between them. They're too old to be interesting. 794 */ 795 uart_setreg(bas, REG_MCR, mcr); 796 uart_barrier(bas); 797 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 798 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 799 return (0); 800 } 801 802 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 803 uart_barrier(bas); 804 805 count = 0; 806 delay = ns8250_delay(bas); 807 808 /* We have FIFOs. Drain the transmitter and receiver. */ 809 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 810 if (error) { 811 uart_setreg(bas, REG_MCR, mcr); 812 uart_setreg(bas, REG_FCR, 0); 813 uart_barrier(bas); 814 goto describe; 815 } 816 817 /* 818 * We should have a sufficiently clean "pipe" to determine the 819 * size of the FIFOs. We send as much characters as is reasonable 820 * and wait for the overflow bit in the LSR register to be 821 * asserted, counting the characters as we send them. Based on 822 * that count we know the FIFO size. 823 */ 824 do { 825 uart_setreg(bas, REG_DATA, 0); 826 uart_barrier(bas); 827 count++; 828 829 limit = 30; 830 lsr = 0; 831 /* 832 * LSR bits are cleared upon read, so we must accumulate 833 * them to be able to test LSR_OE below. 834 */ 835 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 836 --limit) 837 DELAY(delay); 838 if (limit == 0) { 839 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 840 uart_setreg(bas, REG_IER, ier); 841 uart_setreg(bas, REG_MCR, mcr); 842 uart_setreg(bas, REG_FCR, 0); 843 uart_barrier(bas); 844 count = 0; 845 goto describe; 846 } 847 } while ((lsr & LSR_OE) == 0 && count < 130); 848 count--; 849 850 uart_setreg(bas, REG_MCR, mcr); 851 852 /* Reset FIFOs. */ 853 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 854 855 describe: 856 if (count >= 14 && count <= 16) { 857 sc->sc_rxfifosz = 16; 858 device_set_desc(sc->sc_dev, "16550 or compatible"); 859 } else if (count >= 28 && count <= 32) { 860 sc->sc_rxfifosz = 32; 861 device_set_desc(sc->sc_dev, "16650 or compatible"); 862 } else if (count >= 56 && count <= 64) { 863 sc->sc_rxfifosz = 64; 864 device_set_desc(sc->sc_dev, "16750 or compatible"); 865 } else if (count >= 112 && count <= 128) { 866 sc->sc_rxfifosz = 128; 867 device_set_desc(sc->sc_dev, "16950 or compatible"); 868 } else { 869 sc->sc_rxfifosz = 16; 870 device_set_desc(sc->sc_dev, 871 "Non-standard ns8250 class UART with FIFOs"); 872 } 873 874 /* 875 * Force the Tx FIFO size to 16 bytes for now. We don't program the 876 * Tx trigger. Also, we assume that all data has been sent when the 877 * interrupt happens. 878 */ 879 sc->sc_txfifosz = 16; 880 881#if 0 882 /* 883 * XXX there are some issues related to hardware flow control and 884 * it's likely that uart(4) is the cause. This basically needs more 885 * investigation, but we avoid using for hardware flow control 886 * until then. 887 */ 888 /* 16650s or higher have automatic flow control. */ 889 if (sc->sc_rxfifosz > 16) { 890 sc->sc_hwiflow = 1; 891 sc->sc_hwoflow = 1; 892 } 893#endif 894 895 return (0); 896} 897 898int 899ns8250_bus_receive(struct uart_softc *sc) 900{ 901 struct uart_bas *bas; 902 int xc; 903 uint8_t lsr; 904 905 bas = &sc->sc_bas; 906 uart_lock(sc->sc_hwmtx); 907 lsr = uart_getreg(bas, REG_LSR); 908 while (lsr & LSR_RXRDY) { 909 if (uart_rx_full(sc)) { 910 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 911 break; 912 } 913 xc = uart_getreg(bas, REG_DATA); 914 if (lsr & LSR_FE) 915 xc |= UART_STAT_FRAMERR; 916 if (lsr & LSR_PE) 917 xc |= UART_STAT_PARERR; 918 uart_rx_put(sc, xc); 919 lsr = uart_getreg(bas, REG_LSR); 920 } 921 /* Discard everything left in the Rx FIFO. */ 922 while (lsr & LSR_RXRDY) { 923 (void)uart_getreg(bas, REG_DATA); 924 uart_barrier(bas); 925 lsr = uart_getreg(bas, REG_LSR); 926 } 927 uart_unlock(sc->sc_hwmtx); 928 return (0); 929} 930 931int 932ns8250_bus_setsig(struct uart_softc *sc, int sig) 933{ 934 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 935 struct uart_bas *bas; 936 uint32_t new, old; 937 938 bas = &sc->sc_bas; 939 do { 940 old = sc->sc_hwsig; 941 new = old; 942 if (sig & SER_DDTR) { 943 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 944 } 945 if (sig & SER_DRTS) { 946 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 947 } 948 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 949 uart_lock(sc->sc_hwmtx); 950 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 951 if (new & SER_DTR) 952 ns8250->mcr |= MCR_DTR; 953 if (new & SER_RTS) 954 ns8250->mcr |= MCR_RTS; 955 uart_setreg(bas, REG_MCR, ns8250->mcr); 956 uart_barrier(bas); 957 uart_unlock(sc->sc_hwmtx); 958 return (0); 959} 960 961int 962ns8250_bus_transmit(struct uart_softc *sc) 963{ 964 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 965 struct uart_bas *bas; 966 int i; 967 968 bas = &sc->sc_bas; 969 uart_lock(sc->sc_hwmtx); 970 if (sc->sc_txdatasz > 1) { 971 if ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0) 972 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 973 } else { 974 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 975 DELAY(4); 976 } 977 for (i = 0; i < sc->sc_txdatasz; i++) { 978 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 979 uart_barrier(bas); 980 } 981 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 982 uart_barrier(bas); 983 if (broken_txfifo) 984 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 985 else 986 sc->sc_txbusy = 1; 987 uart_unlock(sc->sc_hwmtx); 988 if (broken_txfifo) 989 uart_sched_softih(sc, SER_INT_TXIDLE); 990 return (0); 991} 992 993void 994ns8250_bus_grab(struct uart_softc *sc) 995{ 996 struct uart_bas *bas = &sc->sc_bas; 997 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 998 u_char ier; 999 1000 /* 1001 * turn off all interrupts to enter polling mode. Leave the 1002 * saved mask alone. We'll restore whatever it was in ungrab. 1003 * All pending interrupt signals are reset when IER is set to 0. 1004 */ 1005 uart_lock(sc->sc_hwmtx); 1006 ier = uart_getreg(bas, REG_IER); 1007 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1008 uart_barrier(bas); 1009 uart_unlock(sc->sc_hwmtx); 1010} 1011 1012void 1013ns8250_bus_ungrab(struct uart_softc *sc) 1014{ 1015 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1016 struct uart_bas *bas = &sc->sc_bas; 1017 1018 /* 1019 * Restore previous interrupt mask 1020 */ 1021 uart_lock(sc->sc_hwmtx); 1022 uart_setreg(bas, REG_IER, ns8250->ier); 1023 uart_barrier(bas); 1024 uart_unlock(sc->sc_hwmtx); 1025} 1026