sdhci_pci.c revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: stable/11/sys/dev/sdhci/sdhci_pci.c 330897 2018-03-14 03:19:51Z eadler $"); 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/bus.h> 34#include <sys/kernel.h> 35#include <sys/lock.h> 36#include <sys/module.h> 37#include <sys/mutex.h> 38#include <sys/resource.h> 39#include <sys/rman.h> 40#include <sys/sysctl.h> 41#include <sys/taskqueue.h> 42 43#include <dev/pci/pcireg.h> 44#include <dev/pci/pcivar.h> 45 46#include <machine/bus.h> 47#include <machine/resource.h> 48 49#include <dev/mmc/bridge.h> 50 51#include <dev/sdhci/sdhci.h> 52 53#include "mmcbr_if.h" 54#include "sdhci_if.h" 55 56/* 57 * PCI registers 58 */ 59#define PCI_SDHCI_IFPIO 0x00 60#define PCI_SDHCI_IFDMA 0x01 61#define PCI_SDHCI_IFVENDOR 0x02 62 63#define PCI_SLOT_INFO 0x40 /* 8 bits */ 64#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 65#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) 66 67/* 68 * RICOH specific PCI registers 69 */ 70#define SDHC_PCI_MODE_KEY 0xf9 71#define SDHC_PCI_MODE 0x150 72#define SDHC_PCI_MODE_SD20 0x10 73#define SDHC_PCI_BASE_FREQ_KEY 0xfc 74#define SDHC_PCI_BASE_FREQ 0xe1 75 76static const struct sdhci_device { 77 uint32_t model; 78 uint16_t subvendor; 79 const char *desc; 80 u_int quirks; 81} sdhci_devices[] = { 82 { 0x08221180, 0xffff, "RICOH R5C822 SD", 83 SDHCI_QUIRK_FORCE_DMA }, 84 { 0xe8221180, 0xffff, "RICOH R5CE822 SD", 85 SDHCI_QUIRK_FORCE_DMA | 86 SDHCI_QUIRK_LOWER_FREQUENCY }, 87 { 0xe8231180, 0xffff, "RICOH R5CE823 SD", 88 SDHCI_QUIRK_LOWER_FREQUENCY }, 89 { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 90 SDHCI_QUIRK_FORCE_DMA }, 91 { 0x05501524, 0xffff, "ENE CB712 SD", 92 SDHCI_QUIRK_BROKEN_TIMINGS }, 93 { 0x05511524, 0xffff, "ENE CB712 SD 2", 94 SDHCI_QUIRK_BROKEN_TIMINGS }, 95 { 0x07501524, 0xffff, "ENE CB714 SD", 96 SDHCI_QUIRK_RESET_ON_IOS | 97 SDHCI_QUIRK_BROKEN_TIMINGS }, 98 { 0x07511524, 0xffff, "ENE CB714 SD 2", 99 SDHCI_QUIRK_RESET_ON_IOS | 100 SDHCI_QUIRK_BROKEN_TIMINGS }, 101 { 0x410111ab, 0xffff, "Marvell CaFe SD", 102 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 103 { 0x2381197B, 0xffff, "JMicron JMB38X SD", 104 SDHCI_QUIRK_32BIT_DMA_SIZE | 105 SDHCI_QUIRK_RESET_AFTER_REQUEST }, 106 { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader", 107 SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC }, 108 { 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 109 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 110 SDHCI_QUIRK_WAIT_WHILE_BUSY | 111 SDHCI_QUIRK_MMC_DDR52 | 112 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 113 SDHCI_QUIRK_PRESET_VALUE_BROKEN}, 114 { 0x0f158086, 0xffff, "Intel Bay Trail SDXC Controller", 115 SDHCI_QUIRK_WAIT_WHILE_BUSY | 116 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 117 { 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 118 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 119 SDHCI_QUIRK_WAIT_WHILE_BUSY | 120 SDHCI_QUIRK_MMC_DDR52 | 121 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 122 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 123 { 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller", 124 SDHCI_QUIRK_DATA_TIMEOUT_1MHZ | 125 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 126 SDHCI_QUIRK_WAIT_WHILE_BUSY | 127 SDHCI_QUIRK_MMC_DDR52 | 128 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 129 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 130 { 0x22968086, 0xffff, "Intel Braswell SDXC Controller", 131 SDHCI_QUIRK_WAIT_WHILE_BUSY | 132 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 133 { 0x5aca8086, 0xffff, "Intel Apollo Lake SDXC Controller", 134 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */ 135 SDHCI_QUIRK_WAIT_WHILE_BUSY | 136 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 137 { 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller", 138 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */ 139 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 140 SDHCI_QUIRK_WAIT_WHILE_BUSY | 141 SDHCI_QUIRK_MMC_DDR52 | 142 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 143 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 144 { 0, 0xffff, NULL, 145 0 } 146}; 147 148struct sdhci_pci_softc { 149 u_int quirks; /* Chip specific quirks */ 150 struct resource *irq_res; /* IRQ resource */ 151 void *intrhand; /* Interrupt handle */ 152 153 int num_slots; /* Number of slots on this controller */ 154 struct sdhci_slot slots[6]; 155 struct resource *mem_res[6]; /* Memory resource */ 156 uint8_t cfg_freq; /* Saved frequency */ 157 uint8_t cfg_mode; /* Saved mode */ 158}; 159 160static int sdhci_enable_msi = 1; 161SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi, 162 0, "Enable MSI interrupts"); 163 164static uint8_t 165sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 166{ 167 struct sdhci_pci_softc *sc = device_get_softc(dev); 168 169 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 170 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 171 return bus_read_1(sc->mem_res[slot->num], off); 172} 173 174static void 175sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot __unused, 176 bus_size_t off, uint8_t val) 177{ 178 struct sdhci_pci_softc *sc = device_get_softc(dev); 179 180 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 181 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 182 bus_write_1(sc->mem_res[slot->num], off, val); 183} 184 185static uint16_t 186sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 187{ 188 struct sdhci_pci_softc *sc = device_get_softc(dev); 189 190 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 191 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 192 return bus_read_2(sc->mem_res[slot->num], off); 193} 194 195static void 196sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot __unused, 197 bus_size_t off, uint16_t val) 198{ 199 struct sdhci_pci_softc *sc = device_get_softc(dev); 200 201 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 202 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 203 bus_write_2(sc->mem_res[slot->num], off, val); 204} 205 206static uint32_t 207sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 208{ 209 struct sdhci_pci_softc *sc = device_get_softc(dev); 210 211 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 212 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 213 return bus_read_4(sc->mem_res[slot->num], off); 214} 215 216static void 217sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot __unused, 218 bus_size_t off, uint32_t val) 219{ 220 struct sdhci_pci_softc *sc = device_get_softc(dev); 221 222 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 223 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 224 bus_write_4(sc->mem_res[slot->num], off, val); 225} 226 227static void 228sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot __unused, 229 bus_size_t off, uint32_t *data, bus_size_t count) 230{ 231 struct sdhci_pci_softc *sc = device_get_softc(dev); 232 233 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); 234} 235 236static void 237sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot __unused, 238 bus_size_t off, uint32_t *data, bus_size_t count) 239{ 240 struct sdhci_pci_softc *sc = device_get_softc(dev); 241 242 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); 243} 244 245static void sdhci_pci_intr(void *arg); 246 247static void 248sdhci_lower_frequency(device_t dev) 249{ 250 struct sdhci_pci_softc *sc = device_get_softc(dev); 251 252 /* 253 * Enable SD2.0 mode. 254 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822. 255 */ 256 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 257 sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1); 258 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); 259 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 260 261 /* 262 * Some SD/MMC cards don't work with the default base 263 * clock frequency of 200 MHz. Lower it to 50 MHz. 264 */ 265 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 266 sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1); 267 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); 268 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 269} 270 271static void 272sdhci_restore_frequency(device_t dev) 273{ 274 struct sdhci_pci_softc *sc = device_get_softc(dev); 275 276 /* Restore mode. */ 277 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 278 pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1); 279 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 280 281 /* Restore frequency. */ 282 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 283 pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1); 284 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 285} 286 287static int 288sdhci_pci_probe(device_t dev) 289{ 290 uint32_t model; 291 uint16_t subvendor; 292 uint8_t class, subclass; 293 int i, result; 294 295 model = (uint32_t)pci_get_device(dev) << 16; 296 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 297 subvendor = pci_get_subvendor(dev); 298 class = pci_get_class(dev); 299 subclass = pci_get_subclass(dev); 300 301 result = ENXIO; 302 for (i = 0; sdhci_devices[i].model != 0; i++) { 303 if (sdhci_devices[i].model == model && 304 (sdhci_devices[i].subvendor == 0xffff || 305 sdhci_devices[i].subvendor == subvendor)) { 306 device_set_desc(dev, sdhci_devices[i].desc); 307 result = BUS_PROBE_DEFAULT; 308 break; 309 } 310 } 311 if (result == ENXIO && class == PCIC_BASEPERIPH && 312 subclass == PCIS_BASEPERIPH_SDHC) { 313 device_set_desc(dev, "Generic SD HCI"); 314 result = BUS_PROBE_GENERIC; 315 } 316 317 return (result); 318} 319 320static int 321sdhci_pci_attach(device_t dev) 322{ 323 struct sdhci_pci_softc *sc = device_get_softc(dev); 324 struct sdhci_slot *slot; 325 uint32_t model; 326 uint16_t subvendor; 327 int bar, err, rid, slots, i; 328 329 model = (uint32_t)pci_get_device(dev) << 16; 330 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 331 subvendor = pci_get_subvendor(dev); 332 /* Apply chip specific quirks. */ 333 for (i = 0; sdhci_devices[i].model != 0; i++) { 334 if (sdhci_devices[i].model == model && 335 (sdhci_devices[i].subvendor == 0xffff || 336 sdhci_devices[i].subvendor == subvendor)) { 337 sc->quirks = sdhci_devices[i].quirks; 338 break; 339 } 340 } 341 sc->quirks &= ~sdhci_quirk_clear; 342 sc->quirks |= sdhci_quirk_set; 343 344 /* Some controllers need to be bumped into the right mode. */ 345 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 346 sdhci_lower_frequency(dev); 347 /* Read slots info from PCI registers. */ 348 slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 349 bar = PCI_SLOT_INFO_FIRST_BAR(slots); 350 slots = PCI_SLOT_INFO_SLOTS(slots); 351 if (slots > 6 || bar > 5) { 352 device_printf(dev, "Incorrect slots information (%d, %d).\n", 353 slots, bar); 354 return (EINVAL); 355 } 356 /* Allocate IRQ. */ 357 i = 1; 358 rid = 0; 359 if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0) 360 rid = 1; 361 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 362 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 363 if (sc->irq_res == NULL) { 364 device_printf(dev, "Can't allocate IRQ\n"); 365 pci_release_msi(dev); 366 return (ENOMEM); 367 } 368 /* Scan all slots. */ 369 for (i = 0; i < slots; i++) { 370 slot = &sc->slots[sc->num_slots]; 371 372 /* Allocate memory. */ 373 rid = PCIR_BAR(bar + i); 374 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 375 &rid, RF_ACTIVE); 376 if (sc->mem_res[i] == NULL) { 377 device_printf(dev, 378 "Can't allocate memory for slot %d\n", i); 379 continue; 380 } 381 382 slot->quirks = sc->quirks; 383 384 if (sdhci_init_slot(dev, slot, i) != 0) 385 continue; 386 387 sc->num_slots++; 388 } 389 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 390 /* Activate the interrupt */ 391 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 392 NULL, sdhci_pci_intr, sc, &sc->intrhand); 393 if (err) 394 device_printf(dev, "Can't setup IRQ\n"); 395 pci_enable_busmaster(dev); 396 /* Process cards detection. */ 397 for (i = 0; i < sc->num_slots; i++) 398 sdhci_start_slot(&sc->slots[i]); 399 400 return (0); 401} 402 403static int 404sdhci_pci_detach(device_t dev) 405{ 406 struct sdhci_pci_softc *sc = device_get_softc(dev); 407 int i; 408 409 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 410 bus_release_resource(dev, SYS_RES_IRQ, 411 rman_get_rid(sc->irq_res), sc->irq_res); 412 pci_release_msi(dev); 413 414 for (i = 0; i < sc->num_slots; i++) { 415 sdhci_cleanup_slot(&sc->slots[i]); 416 bus_release_resource(dev, SYS_RES_MEMORY, 417 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 418 } 419 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 420 sdhci_restore_frequency(dev); 421 return (0); 422} 423 424static int 425sdhci_pci_shutdown(device_t dev) 426{ 427 struct sdhci_pci_softc *sc = device_get_softc(dev); 428 429 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 430 sdhci_restore_frequency(dev); 431 return (0); 432} 433 434static int 435sdhci_pci_suspend(device_t dev) 436{ 437 struct sdhci_pci_softc *sc = device_get_softc(dev); 438 int i, err; 439 440 err = bus_generic_suspend(dev); 441 if (err) 442 return (err); 443 for (i = 0; i < sc->num_slots; i++) 444 sdhci_generic_suspend(&sc->slots[i]); 445 return (0); 446} 447 448static int 449sdhci_pci_resume(device_t dev) 450{ 451 struct sdhci_pci_softc *sc = device_get_softc(dev); 452 int i, err; 453 454 for (i = 0; i < sc->num_slots; i++) 455 sdhci_generic_resume(&sc->slots[i]); 456 err = bus_generic_resume(dev); 457 if (err) 458 return (err); 459 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 460 sdhci_lower_frequency(dev); 461 return (0); 462} 463 464static void 465sdhci_pci_intr(void *arg) 466{ 467 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; 468 int i; 469 470 for (i = 0; i < sc->num_slots; i++) 471 sdhci_generic_intr(&sc->slots[i]); 472} 473 474static device_method_t sdhci_methods[] = { 475 /* device_if */ 476 DEVMETHOD(device_probe, sdhci_pci_probe), 477 DEVMETHOD(device_attach, sdhci_pci_attach), 478 DEVMETHOD(device_detach, sdhci_pci_detach), 479 DEVMETHOD(device_shutdown, sdhci_pci_shutdown), 480 DEVMETHOD(device_suspend, sdhci_pci_suspend), 481 DEVMETHOD(device_resume, sdhci_pci_resume), 482 483 /* Bus interface */ 484 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 485 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 486 487 /* mmcbr_if */ 488 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 489 DEVMETHOD(mmcbr_switch_vccq, sdhci_generic_switch_vccq), 490 DEVMETHOD(mmcbr_tune, sdhci_generic_tune), 491 DEVMETHOD(mmcbr_retune, sdhci_generic_retune), 492 DEVMETHOD(mmcbr_request, sdhci_generic_request), 493 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 494 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 495 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 496 497 /* SDHCI accessors */ 498 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), 499 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), 500 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), 501 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), 502 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), 503 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), 504 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), 505 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), 506 DEVMETHOD(sdhci_set_uhs_timing, sdhci_generic_set_uhs_timing), 507 508 DEVMETHOD_END 509}; 510 511static driver_t sdhci_pci_driver = { 512 "sdhci_pci", 513 sdhci_methods, 514 sizeof(struct sdhci_pci_softc), 515}; 516static devclass_t sdhci_pci_devclass; 517 518DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL, 519 NULL); 520MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1); 521MMC_DECLARE_BRIDGE(sdhci_pci); 522