if_vxreg.h revision 331722
1/*- 2 * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: 1. Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 2. The name 8 * of the author may not be used to endorse or promote products derived from 9 * this software without specific prior written permission 10 * 11 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 14 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 15 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 16 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 17 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 18 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 19 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 20 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 21 * 22 * $FreeBSD: stable/11/sys/dev/vx/if_vxreg.h 331722 2018-03-29 02:50:57Z eadler $ 23 */ 24 25/* 26 * Created from if_epreg.h by Fred Gray (fgray@rice.edu) to support the 27 * 3c590 family. 28 */ 29 30/* 31 * Some global constants 32 */ 33 34#define TX_INIT_RATE 16 35#define TX_INIT_MAX_RATE 64 36#define RX_INIT_LATENCY 64 37#define RX_INIT_EARLY_THRESH 64 38#define MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */ 39#define MIN_RX_EARLY_THRESHL 4 40 41#define EEPROMSIZE 0x40 42#define MAX_EEPROMBUSY 1000 43#define VX_LAST_TAG 0xd7 44#define VX_MAX_BOARDS 16 45 46/* 47 * Commands to read/write EEPROM trough EEPROM command register (Window 0, 48 * Offset 0xa) 49 */ 50#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */ 51#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */ 52#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */ 53#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */ 54 55#define EEPROM_BUSY (1<<15) 56#define EEPROM_TST_MODE (1<<14) 57 58/* 59 * Some short functions, worth to let them be a macro 60 */ 61#define GO_WINDOW(x) CSR_WRITE_2(sc, VX_COMMAND, WINDOW_SELECT|(x)) 62 63/************************************************************************** 64 * * 65 * These define the EEPROM data structure. They are used in the probe 66 * function to verify the existence of the adapter after having sent 67 * the ID_Sequence. 68 * 69 **************************************************************************/ 70 71#define EEPROM_NODE_ADDR_0 0x0 /* Word */ 72#define EEPROM_NODE_ADDR_1 0x1 /* Word */ 73#define EEPROM_NODE_ADDR_2 0x2 /* Word */ 74#define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ 75#define EEPROM_MFG_DATE 0x4 /* Manufacturing date */ 76#define EEPROM_MFG_DIVSION 0x5 /* Manufacturing division */ 77#define EEPROM_MFG_PRODUCT 0x6 /* Product code */ 78#define EEPROM_MFG_ID 0x7 /* 0x6d50 */ 79#define EEPROM_ADDR_CFG 0x8 /* Base addr */ 80#define ADDR_CFG_EISA 0x1f 81#define ADDR_CFG_MASK 0x1f 82#define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ 83#define EEPROM_OEM_ADDR0 0xa 84#define EEPROM_OEM_ADDR1 0xb 85#define EEPROM_OEM_ADDR2 0xc 86#define EEPROM_SOFTINFO 0xd 87#define EEPROM_COMPAT 0xe 88#define EEPROM_SOFTINFO2 0xf 89#define EEPROM_CAP 0x10 90#define CAP_ISA 0x2083 91#define CAP_PCMCIA 0x2082 92#define EEPROM_INT_CONFIG_0 0x12 93#define EEPROM_INT_CONFIG_1 0x13 94/* RAM Partition TX FIFO/RX FIFO */ 95#define ICW1_RAM_PART_MASK 0x03 96#define ICW1_RAM_PART_35 0x00 /* 2:5 (only legal if RAM size == 000b 97 * default power-up/reset */ 98#define ICW1_RAM_PART_13 0x01 /* 1:3 (only legal if RAM size == 99 * 000b) */ 100#define ICW1_RAM_PART_11 0x10 /* 1:1 */ 101#define ICW1_RAM_PART_RESV 0x11 /* Reserved */ 102/* ISA Adapter Selection */ 103#define ICW1_IAS_MASK 0x0c 104#define ICW1_IAS_DIS 0x00 /* Both mechanisms disabled (default) */ 105#define ICW1_IAS_ISA 0x04 /* ISA contention only */ 106#define ICW1_IAS_PNP 0x08 /* ISA Plug and Play only */ 107#define ICW1_IAS_BOTH 0x0c /* Both mechanisms enabled */ 108 109#define EEPROM_CHECKSUM_EL3 0x17 110 111#define NO_RX_OVN_ANOMALY (1<<5) 112 113/************************************************************************** 114 * These are the registers for the 3Com 3c509 and their bit patterns when * 115 * applicable. They have been taken out the "EtherLink III Parallel * 116 * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual * 117 * from 3com. * 118 **************************************************************************/ 119#define VX_COMMAND 0x0e /* Write. BASE+0x0e is always a 120 * command reg. */ 121#define VX_STATUS 0x0e /* Read. BASE+0x0e is always status 122 * reg. */ 123#define VX_WINDOW 0x0f /* Read. BASE+0x0f is always window 124 * reg. */ 125/* 126 * Window 0 registers. Setup. 127 */ 128/* Write */ 129#define VX_W0_EEPROM_DATA 0x0c 130#define VX_W0_EEPROM_COMMAND 0x0a 131#define VX_W0_RESOURCE_CFG 0x08 132#define VX_W0_ADDRESS_CFG 0x06 133#define VX_W0_CONFIG_CTRL 0x04 134 /* Read */ 135#define VX_W0_PRODUCT_ID 0x02 136#define VX_W0_MFG_ID 0x00 137 138/* 139 * Window 1 registers. Operating Set. 140 */ 141/* Write */ 142#define VX_W1_TX_PIO_WR_2 0x02 143#define VX_W1_TX_PIO_WR_1 0x00 144/* Read */ 145#define VX_W1_FREE_TX 0x0c 146#define VX_W1_TX_STATUS 0x0b /* byte */ 147#define VX_W1_TIMER 0x0a /* byte */ 148#define VX_W1_RX_STATUS 0x08 149#define VX_W1_RX_PIO_RD_2 0x02 150#define VX_W1_RX_PIO_RD_1 0x00 151 152/* 153 * Window 2 registers. Station Address Setup/Read 154 */ 155/* Read/Write */ 156#define VX_W2_ADDR_5 0x05 157#define VX_W2_ADDR_4 0x04 158#define VX_W2_ADDR_3 0x03 159#define VX_W2_ADDR_2 0x02 160#define VX_W2_ADDR_1 0x01 161#define VX_W2_ADDR_0 0x00 162 163/* 164 * Window 3 registers. FIFO Management. 165 */ 166/* Read */ 167#define VX_W3_INTERNAL_CFG 0x00 168#define VX_W3_RESET_OPT 0x08 169#define VX_W3_FREE_TX 0x0c 170#define VX_W3_FREE_RX 0x0a 171 172/* 173 * Window 4 registers. Diagnostics. 174 */ 175/* Read/Write */ 176#define VX_W4_MEDIA_TYPE 0x0a 177#define VX_W4_CTRLR_STATUS 0x08 178#define VX_W4_NET_DIAG 0x06 179#define VX_W4_FIFO_DIAG 0x04 180#define VX_W4_HOST_DIAG 0x02 181#define VX_W4_TX_DIAG 0x00 182 183/* 184 * Window 5 Registers. Results and Internal status. 185 */ 186/* Read */ 187#define VX_W5_READ_0_MASK 0x0c 188#define VX_W5_INTR_MASK 0x0a 189#define VX_W5_RX_FILTER 0x08 190#define VX_W5_RX_EARLY_THRESH 0x06 191#define VX_W5_TX_AVAIL_THRESH 0x02 192#define VX_W5_TX_START_THRESH 0x00 193 194/* 195 * Window 6 registers. Statistics. 196 */ 197/* Read/Write */ 198#define TX_TOTAL_OK 0x0c 199#define RX_TOTAL_OK 0x0a 200#define TX_DEFERRALS 0x08 201#define RX_FRAMES_OK 0x07 202#define TX_FRAMES_OK 0x06 203#define RX_OVERRUNS 0x05 204#define TX_COLLISIONS 0x04 205#define TX_AFTER_1_COLLISION 0x03 206#define TX_AFTER_X_COLLISIONS 0x02 207#define TX_NO_SQE 0x01 208#define TX_CD_LOST 0x00 209 210/**************************************** 211 * 212 * Register definitions. 213 * 214 ****************************************/ 215 216/* 217 * Command register. All windows. 218 * 219 * 16 bit register. 220 * 15-11: 5-bit code for command to be executed. 221 * 10-0: 11-bit arg if any. For commands with no args; 222 * this can be set to anything. 223 */ 224#define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms 225 * after issuing */ 226#define WINDOW_SELECT (u_short) (0x1<<11) 227#define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to 228 * determine whether 229 * this is needed. If 230 * so; wait 800 uSec 231 * before using trans- 232 * ceiver. */ 233#define RX_DISABLE (u_short) (0x3<<11) /* state disabled on 234 * power-up */ 235#define RX_ENABLE (u_short) (0x4<<11) 236#define RX_RESET (u_short) (0x5<<11) 237#define RX_DISCARD_TOP_PACK (u_short) (0x8<<11) 238#define TX_ENABLE (u_short) (0x9<<11) 239#define TX_DISABLE (u_short) (0xa<<11) 240#define TX_RESET (u_short) (0xb<<11) 241#define REQ_INTR (u_short) (0xc<<11) 242/* 243 * The following C_* acknowledge the various interrupts. 244 * Some of them don't do anything. See the manual. 245 */ 246#define ACK_INTR (u_short) (0x6800) 247#define C_INTR_LATCH (u_short) (ACK_INTR|0x1) 248#define C_CARD_FAILURE (u_short) (ACK_INTR|0x2) 249#define C_TX_COMPLETE (u_short) (ACK_INTR|0x4) 250#define C_TX_AVAIL (u_short) (ACK_INTR|0x8) 251#define C_RX_COMPLETE (u_short) (ACK_INTR|0x10) 252#define C_RX_EARLY (u_short) (ACK_INTR|0x20) 253#define C_INT_RQD (u_short) (ACK_INTR|0x40) 254#define C_UPD_STATS (u_short) (ACK_INTR|0x80) 255#define SET_INTR_MASK (u_short) (0xe<<11) 256#define SET_RD_0_MASK (u_short) (0xf<<11) 257#define SET_RX_FILTER (u_short) (0x10<<11) 258#define FIL_INDIVIDUAL (u_short) (0x1) 259#define FIL_MULTICAST (u_short) (0x02) 260#define FIL_BRDCST (u_short) (0x04) 261#define FIL_PROMISC (u_short) (0x08) 262#define SET_RX_EARLY_THRESH (u_short) (0x11<<11) 263#define SET_TX_AVAIL_THRESH (u_short) (0x12<<11) 264#define SET_TX_START_THRESH (u_short) (0x13<<11) 265#define STATS_ENABLE (u_short) (0x15<<11) 266#define STATS_DISABLE (u_short) (0x16<<11) 267#define STOP_TRANSCEIVER (u_short) (0x17<<11) 268 269/* 270 * Status register. All windows. 271 * 272 * 15-13: Window number(0-7). 273 * 12: Command_in_progress. 274 * 11: reserved. 275 * 10: reserved. 276 * 9: reserved. 277 * 8: reserved. 278 * 7: Update Statistics. 279 * 6: Interrupt Requested. 280 * 5: RX Early. 281 * 4: RX Complete. 282 * 3: TX Available. 283 * 2: TX Complete. 284 * 1: Adapter Failure. 285 * 0: Interrupt Latch. 286 */ 287#define S_INTR_LATCH (u_short) (0x1) 288#define S_CARD_FAILURE (u_short) (0x2) 289#define S_TX_COMPLETE (u_short) (0x4) 290#define S_TX_AVAIL (u_short) (0x8) 291#define S_RX_COMPLETE (u_short) (0x10) 292#define S_RX_EARLY (u_short) (0x20) 293#define S_INT_RQD (u_short) (0x40) 294#define S_UPD_STATS (u_short) (0x80) 295#define S_COMMAND_IN_PROGRESS (u_short) (0x1000) 296 297#define VX_BUSY_WAIT while (CSR_READ_2(sc, VX_STATUS) & S_COMMAND_IN_PROGRESS) 298 299/* Address Config. Register. 300 * Window 0/Port 06 301 */ 302 303#define ACF_CONNECTOR_BITS 14 304#define ACF_CONNECTOR_UTP 0 305#define ACF_CONNECTOR_AUI 1 306#define ACF_CONNECTOR_BNC 3 307 308#define INTERNAL_CONNECTOR_BITS 20 309#define INTERNAL_CONNECTOR_MASK 0x01700000 310 311/* 312 * FIFO Registers. RX Status. 313 * 314 * 15: Incomplete or FIFO empty. 315 * 14: 1: Error in RX Packet 0: Incomplete or no error. 316 * 13-11: Type of error. 317 * 1000 = Overrun. 318 * 1011 = Run Packet Error. 319 * 1100 = Alignment Error. 320 * 1101 = CRC Error. 321 * 1001 = Oversize Packet Error (>1514 bytes) 322 * 0010 = Dribble Bits. 323 * (all other error codes, no errors.) 324 * 325 * 10-0: RX Bytes (0-1514) 326 */ 327#define ERR_INCOMPLETE (u_short) (0x8000) 328#define ERR_RX (u_short) (0x4000) 329#define ERR_MASK (u_short) (0x7800) 330#define ERR_OVERRUN (u_short) (0x4000) 331#define ERR_RUNT (u_short) (0x5800) 332#define ERR_ALIGNMENT (u_short) (0x6000) 333#define ERR_CRC (u_short) (0x6800) 334#define ERR_OVERSIZE (u_short) (0x4800) 335#define ERR_DRIBBLE (u_short) (0x1000) 336 337/* 338 * TX Status. 339 * 340 * Reports the transmit status of a completed transmission. Writing this 341 * register pops the transmit completion stack. 342 * 343 * Window 1/Port 0x0b. 344 * 345 * 7: Complete 346 * 6: Interrupt on successful transmission requested. 347 * 5: Jabber Error (TP Only, TX Reset required. ) 348 * 4: Underrun (TX Reset required. ) 349 * 3: Maximum Collisions. 350 * 2: TX Status Overflow. 351 * 1-0: Undefined. 352 * 353 */ 354#define TXS_COMPLETE 0x80 355#define TXS_INTR_REQ 0x40 356#define TXS_JABBER 0x20 357#define TXS_UNDERRUN 0x10 358#define TXS_MAX_COLLISION 0x8 359#define TXS_STATUS_OVERFLOW 0x4 360 361#define RS_AUI (1<<5) 362#define RS_BNC (1<<4) 363#define RS_UTP (1<<3) 364#define RS_T4 (1<<0) 365#define RS_TX (1<<1) 366#define RS_FX (1<<2) 367#define RS_MII (1<<6) 368 369 370/* 371 * FIFO Status (Window 4) 372 * 373 * Supports FIFO diagnostics 374 * 375 * Window 4/Port 0x04.1 376 * 377 * 15: 1=RX receiving (RO). Set when a packet is being received 378 * into the RX FIFO. 379 * 14: Reserved 380 * 13: 1=RX underrun (RO). Generates Adapter Failure interrupt. 381 * Requires RX Reset or Global Reset command to recover. 382 * It is generated when you read past the end of a packet - 383 * reading past what has been received so far will give bad 384 * data. 385 * 12: 1=RX status overrun (RO). Set when there are already 8 386 * packets in the RX FIFO. While this bit is set, no additional 387 * packets are received. Requires no action on the part of 388 * the host. The condition is cleared once a packet has been 389 * read out of the RX FIFO. 390 * 11: 1=RX overrun (RO). Set when the RX FIFO is full (there 391 * may not be an overrun packet yet). While this bit is set, 392 * no additional packets will be received (some additional 393 * bytes can still be pending between the wire and the RX 394 * FIFO). Requires no action on the part of the host. The 395 * condition is cleared once a few bytes have been read out 396 * from the RX FIFO. 397 * 10: 1=TX overrun (RO). Generates adapter failure interrupt. 398 * Requires TX Reset or Global Reset command to recover. 399 * Disables Transmitter. 400 * 9-8: Unassigned. 401 * 7-0: Built in self test bits for the RX and TX FIFO's. 402 */ 403#define FIFOS_RX_RECEIVING (u_short) 0x8000 404#define FIFOS_RX_UNDERRUN (u_short) 0x2000 405#define FIFOS_RX_STATUS_OVERRUN (u_short) 0x1000 406#define FIFOS_RX_OVERRUN (u_short) 0x0800 407#define FIFOS_TX_OVERRUN (u_short) 0x0400 408 409/* 410 * Misc defines for various things. 411 */ 412#define TAG_ADAPTER 0xd0 413#define ACTIVATE_ADAPTER_TO_CONFIG 0xff 414#define ENABLE_DRQ_IRQ 0x0001 415#define MFG_ID 0x506d /* `TCM' */ 416#define PROD_ID 0x5090 417#define JABBER_GUARD_ENABLE 0x40 418#define LINKBEAT_ENABLE 0x80 419#define ENABLE_UTP (JABBER_GUARD_ENABLE | LINKBEAT_ENABLE) 420#define DISABLE_UTP 0x0 421#define RX_BYTES_MASK (u_short) (0x07ff) 422#define TX_INDICATE (1<<15) 423 424#define VX_IOSIZE 0x20 425 426#define VX_CONNECTORS 8 427