if_stgereg.h revision 330897
1323129Sdes/* $NetBSD: if_stgereg.h,v 1.3 2003/02/10 21:10:07 christos Exp $ */ 276259Sgreen 376259Sgreen/*- 492555Sdes * SPDX-License-Identifier: BSD-2-Clause-NetBSD 576259Sgreen * 676259Sgreen * Copyright (c) 2001 The NetBSD Foundation, Inc. 776259Sgreen * All rights reserved. 876259Sgreen * 976259Sgreen * This code is derived from software contributed to The NetBSD Foundation 1076259Sgreen * by Jason R. Thorpe. 1176259Sgreen * 1276259Sgreen * Redistribution and use in source and binary forms, with or without 1376259Sgreen * modification, are permitted provided that the following conditions 1476259Sgreen * are met: 1576259Sgreen * 1. Redistributions of source code must retain the above copyright 1676259Sgreen * notice, this list of conditions and the following disclaimer. 1776259Sgreen * 2. Redistributions in binary form must reproduce the above copyright 1876259Sgreen * notice, this list of conditions and the following disclaimer in the 1976259Sgreen * documentation and/or other materials provided with the distribution. 2076259Sgreen * 2176259Sgreen * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 2276259Sgreen * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 2376259Sgreen * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 2476259Sgreen * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 2576259Sgreen * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26162856Sdes * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2776259Sgreen * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2876259Sgreen * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29162856Sdes * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30162856Sdes * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31162856Sdes * POSSIBILITY OF SUCH DAMAGE. 32162856Sdes */ 33162856Sdes 34162856Sdes/* $FreeBSD: stable/11/sys/dev/stge/if_stgereg.h 330897 2018-03-14 03:19:51Z eadler $ */ 35162856Sdes 3676259Sgreen/* 37162856Sdes * Sundance Technology PCI vendor ID 38162856Sdes */ 3976259Sgreen#define VENDOR_SUNDANCETI 0x13f0 4092555Sdes 4176259Sgreen/* 4276259Sgreen * Tamarack Microelectronics PCI vendor ID 4376259Sgreen */ 44294328Sdes#define VENDOR_TAMARACK 0x143d 45147005Sdes 4676259Sgreen/* 47147005Sdes * D-Link Systems PCI vendor ID 48147005Sdes */ 49147005Sdes#define VENDOR_DLINK 0x1186 5092555Sdes 5192555Sdes/* 52294332Sdes * Antares Microsystems PCI vendor ID 5376259Sgreen */ 5492555Sdes#define VENDOR_ANTARES 0x1754 5592555Sdes 5698941Sdes/* 5799052Sdes * Sundance Technology device ID 58124211Sdes */ 5999052Sdes#define DEVICEID_SUNDANCETI_ST1023 0x1023 6098941Sdes#define DEVICEID_SUNDANCETI_ST2021 0x2021 6192555Sdes#define DEVICEID_TAMARACK_TC9021 0x1021 6292555Sdes#define DEVICEID_TAMARACK_TC9021_ALT 0x9021 6398941Sdes 6492555Sdes/* 6592555Sdes * D-Link Systems device ID 6692555Sdes */ 6792555Sdes#define DEVICEID_DLINK_DL4000 0x4000 6898941Sdes 6999052Sdes/* 70124211Sdes * Antares Microsystems device ID 7199052Sdes */ 7298941Sdes#define DEVICEID_ANTARES_TC9021 0x1021 7392555Sdes 7492555Sdes/* 7598941Sdes * Register description for the Sundance Tech. TC9021 10/100/1000 7692555Sdes * Ethernet controller. 7792555Sdes * 7892555Sdes * Note that while DMA addresses are all in 64-bit fields, only 7992555Sdes * the lower 40 bits of a DMA address are valid. 8092555Sdes */ 8192555Sdes#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 8292555Sdes#define STGE_DMA_MAXADDR BUS_SPACE_MAXADDR 8392555Sdes#else 8492555Sdes#define STGE_DMA_MAXADDR 0xFFFFFFFFFF 8599063Sdes#endif 86285975Sdelphij 8792555Sdes/* 8892555Sdes * Register access macros 89147005Sdes */ 90147005Sdes#define CSR_WRITE_4(_sc, reg, val) \ 91147005Sdes bus_write_4((_sc)->sc_res[0], (reg), (val)) 92147005Sdes#define CSR_WRITE_2(_sc, reg, val) \ 93147005Sdes bus_write_2((_sc)->sc_res[0], (reg), (val)) 94147005Sdes#define CSR_WRITE_1(_sc, reg, val) \ 95147005Sdes bus_write_1((_sc)->sc_res[0], (reg), (val)) 96147005Sdes 97147005Sdes#define CSR_READ_4(_sc, reg) \ 98147005Sdes bus_read_4((_sc)->sc_res[0], (reg)) 99147005Sdes#define CSR_READ_2(_sc, reg) \ 100147005Sdes bus_read_2((_sc)->sc_res[0], (reg)) 101147005Sdes#define CSR_READ_1(_sc, reg) \ 102147005Sdes bus_read_1((_sc)->sc_res[0], (reg)) 103147005Sdes 10492555Sdes#define CSR_BARRIER(_sc, reg, length, flags) \ 10592555Sdes bus_barrier((_sc)->sc_res[0], reg, length, flags) 10692555Sdes 10792555Sdes/* 10892555Sdes * TC9021 buffer fragment descriptor. 10992555Sdes */ 11092555Sdesstruct stge_frag { 111147005Sdes uint64_t frag_word0; /* address, length */ 112147005Sdes}; 113147005Sdes 114147005Sdes#define FRAG_ADDR(x) (((uint64_t)(x)) << 0) 115147005Sdes#define FRAG_ADDR_MASK FRAG_ADDR(0xfffffffffULL) 116257954Sdelphij#define FRAG_LEN(x) (((uint64_t)(x)) << 48) 11792555Sdes#define FRAG_LEN_MASK FRAG_LEN(0xffffULL) 11892555Sdes 11992555Sdes/* 12092555Sdes * TC9021 Transmit Frame Descriptor. Note the number of fragments 12192555Sdes * here is arbitrary, but we can't have any more than 15. 12292555Sdes */ 12392555Sdes#define STGE_NTXFRAGS 15 12492555Sdesstruct stge_tfd { 125323129Sdes uint64_t tfd_next; /* next TFD in list */ 126323129Sdes uint64_t tfd_control; /* control bits */ 12792555Sdes /* the buffer fragments */ 12892555Sdes struct stge_frag tfd_frags[STGE_NTXFRAGS]; 12992555Sdes}; 13092555Sdes 13192555Sdes#define TFD_FrameId(x) ((x) << 0) 13292555Sdes#define TFD_FrameId_MAX 0xffff 13392555Sdes#define TFD_WordAlign(x) ((x) << 16) 13499063Sdes#define TFD_WordAlign_dword 0 /* align to dword in TxFIFO */ 13592555Sdes#define TFD_WordAlign_word 2 /* align to word in TxFIFO */ 13692555Sdes#define TFD_WordAlign_disable 1 /* disable alignment */ 13792555Sdes#define TFD_TCPChecksumEnable (1ULL << 18) 13892555Sdes#define TFD_UDPChecksumEnable (1ULL << 19) 13992555Sdes#define TFD_IPChecksumEnable (1ULL << 20) 14092555Sdes#define TFD_FcsAppendDisable (1ULL << 21) 14192555Sdes#define TFD_TxIndicate (1ULL << 22) 14292555Sdes#define TFD_TxDMAIndicate (1ULL << 23) 14392555Sdes#define TFD_FragCount(x) ((x) << 24) 14492555Sdes#define TFD_VLANTagInsert (1ULL << 28) 14592555Sdes#define TFD_TFDDone (1ULL << 31) 14692555Sdes#define TFD_VID(x) (((uint64_t)(x)) << 32) 14792555Sdes#define TFD_CFI (1ULL << 44) 14892555Sdes#define TFD_UserPriority(x) (((uint64_t)(x)) << 45) 14992555Sdes 15092555Sdes/* 15192555Sdes * TC9021 Receive Frame Descriptor. Each RFD has a single fragment 152255767Sdes * in it, and the chip tells us the beginning and end of the frame. 153263712Sdes */ 154255767Sdesstruct stge_rfd { 15592555Sdes uint64_t rfd_next; /* next RFD in list */ 15692555Sdes uint64_t rfd_status; /* status bits */ 15792555Sdes struct stge_frag rfd_frag; /* the buffer */ 158255767Sdes}; 15992555Sdes 16092555Sdes/* Low word of rfd_status */ 16192555Sdes#define RFD_RxStatus(x) ((x) & 0xffffffff) 16292555Sdes#define RFD_RxDMAFrameLen(x) ((x) & 0xffff) 16392555Sdes#define RFD_RxFIFOOverrun 0x00010000 16492555Sdes#define RFD_RxRuntFrame 0x00020000 16592555Sdes#define RFD_RxAlignmentError 0x00040000 16692555Sdes#define RFD_RxFCSError 0x00080000 16792555Sdes#define RFD_RxOversizedFrame 0x00100000 16892555Sdes#define RFD_RxLengthError 0x00200000 16992555Sdes#define RFD_VLANDetected 0x00400000 17092555Sdes#define RFD_TCPDetected 0x00800000 17192555Sdes#define RFD_TCPError 0x01000000 172255767Sdes#define RFD_UDPDetected 0x02000000 173285975Sdelphij#define RFD_UDPError 0x04000000 174285975Sdelphij#define RFD_IPDetected 0x08000000 175255767Sdes#define RFD_IPError 0x10000000 176255767Sdes#define RFD_FrameStart 0x20000000 177285975Sdelphij#define RFD_FrameEnd 0x40000000 178285975Sdelphij#define RFD_RFDDone 0x80000000 17992555Sdes/* High word of rfd_status */ 180285975Sdelphij#define RFD_TCI(x) ((((uint64_t)(x)) >> 32) & 0xffff) 181285975Sdelphij 182255767Sdes/* 18392555Sdes * EEPROM offsets. 18492555Sdes */ 185255767Sdes#define STGE_EEPROM_ConfigParam 0x00 18692555Sdes#define STGE_EEPROM_AsicCtrl 0x01 187149753Sdes#define STGE_EEPROM_SubSystemVendorId 0x02 18892555Sdes#define STGE_EEPROM_SubSystemId 0x03 18992555Sdes#define STGE_EEPROM_LEDMode 0x06 19092555Sdes#define STGE_EEPROM_StationAddress0 0x10 19192555Sdes#define STGE_EEPROM_StationAddress1 0x11 19292555Sdes#define STGE_EEPROM_StationAddress2 0x12 19376259Sgreen 19492555Sdes/* 19576259Sgreen * The TC9021 register space. 19676259Sgreen */ 19776259Sgreen 19876259Sgreen#define STGE_DMACtrl 0x00 19976259Sgreen#define DMAC_RxDMAComplete (1U << 3) 20092555Sdes#define DMAC_RxDMAPollNow (1U << 4) 20192555Sdes#define DMAC_TxDMAComplete (1U << 11) 20292555Sdes#define DMAC_TxDMAPollNow (1U << 12) 20376259Sgreen#define DMAC_TxDMAInProg (1U << 15) 20492555Sdes#define DMAC_RxEarlyDisable (1U << 16) 20576259Sgreen#define DMAC_MWIDisable (1U << 18) 20692555Sdes#define DMAC_TxWriteBackDisable (1U << 19) 20792555Sdes#define DMAC_TxBurstLimit(x) ((x) << 20) 20892555Sdes#define DMAC_TargetAbort (1U << 30) 20992555Sdes#define DMAC_MasterAbort (1U << 31) 21092555Sdes 21192555Sdes#define STGE_RxDMAStatus 0x08 21292555Sdes 21392555Sdes#define STGE_TFDListPtrLo 0x10 21492555Sdes 21592555Sdes#define STGE_TFDListPtrHi 0x14 21692555Sdes 217181111Sdes#define STGE_TxDMABurstThresh 0x18 /* 8-bit */ 21892555Sdes 21992555Sdes#define STGE_TxDMAUrgentThresh 0x19 /* 8-bit */ 22092555Sdes 22192555Sdes#define STGE_TxDMAPollPeriod 0x1a /* 8-bit, 320ns increments */ 22292555Sdes 22392555Sdes#define STGE_RFDListPtrLo 0x1c 22492555Sdes 22592555Sdes#define STGE_RFDListPtrHi 0x20 22692555Sdes 22792555Sdes#define STGE_RxDMABurstThresh 0x24 /* 8-bit */ 22892555Sdes 22992555Sdes#define STGE_RxDMAUrgentThresh 0x25 /* 8-bit */ 23092555Sdes 23192555Sdes#define STGE_RxDMAPollPeriod 0x26 /* 8-bit, 320ns increments */ 232255767Sdes 23392555Sdes#define STGE_RxDMAIntCtrl 0x28 23476259Sgreen#define RDIC_RxFrameCount(x) ((x) & 0xff) 23592555Sdes#define RDIC_PriorityThresh(x) ((x) << 10) 23692555Sdes#define RDIC_RxDMAWaitTime(x) ((x) << 16) 23792555Sdes/* 23892555Sdes * Number of receive frames transferred via DMA before a Rx interrupt is issued. 23992555Sdes */ 24092555Sdes#define STGE_RXINT_NFRAME_DEFAULT 8 24192555Sdes#define STGE_RXINT_NFRAME_MIN 1 24292555Sdes#define STGE_RXINT_NFRAME_MAX 255 24392555Sdes/* 24492555Sdes * Maximum amount of time (in 64ns increments) to wait before issuing a Rx 24592555Sdes * interrupt if number of frames recevied is less than STGE_RXINT_NFRAME 24692555Sdes * (STGE_RXINT_NFRAME_MIN <= STGE_RXINT_NFRAME <= STGE_RXINT_NFRAME_MAX) 24776259Sgreen */ 24876259Sgreen#define STGE_RXINT_DMAWAIT_DEFAULT 30 /* 30us */ 24992555Sdes#define STGE_RXINT_DMAWAIT_MIN 0 25076259Sgreen#define STGE_RXINT_DMAWAIT_MAX 4194 25176259Sgreen#define STGE_RXINT_USECS2TICK(x) (((x) * 1000)/64) 25276259Sgreen 25376259Sgreen#define STGE_DebugCtrl 0x2c /* 16-bit */ 25492555Sdes#define DC_GPIO0Ctrl (1U << 0) 25592555Sdes#define DC_GPIO1Ctrl (1U << 1) 25676259Sgreen#define DC_GPIO0 (1U << 2) 25792555Sdes#define DC_GPIO1 (1U << 3) 25892555Sdes 259149753Sdes#define STGE_AsicCtrl 0x30 26076259Sgreen#define AC_ExpRomDisable (1U << 0) 26192555Sdes#define AC_ExpRomSize (1U << 1) 26292555Sdes#define AC_PhySpeed10 (1U << 4) 26399063Sdes#define AC_PhySpeed100 (1U << 5) 26492555Sdes#define AC_PhySpeed1000 (1U << 6) 26592555Sdes#define AC_PhyMedia (1U << 7) 26676259Sgreen#define AC_ForcedConfig(x) ((x) << 8) 26792555Sdes#define AC_ForcedConfig_MASK AC_ForcedConfig(7) 26892555Sdes#define AC_D3ResetDisable (1U << 11) 26998684Sdes#define AC_SpeedupMode (1U << 13) 27099063Sdes#define AC_LEDMode (1U << 14) 27199063Sdes#define AC_RstOutPolarity (1U << 15) 27292555Sdes#define AC_GlobalReset (1U << 16) 27392555Sdes#define AC_RxReset (1U << 17) 27492555Sdes#define AC_TxReset (1U << 18) 27576259Sgreen#define AC_DMA (1U << 19) 27676259Sgreen#define AC_FIFO (1U << 20) 27792555Sdes#define AC_Network (1U << 21) 27899063Sdes#define AC_Host (1U << 22) 279255767Sdes#define AC_AutoInit (1U << 23) 280255767Sdes#define AC_RstOut (1U << 24) 281255767Sdes#define AC_InterruptRequest (1U << 25) 282255767Sdes#define AC_ResetBusy (1U << 26) 283255767Sdes#define AC_LEDSpeed (1U << 27) 28492555Sdes#define AC_LEDModeBit1 (1U << 29) 28576259Sgreen 28676259Sgreen#define STGE_FIFOCtrl 0x38 /* 16-bit */ 287294332Sdes#define FC_RAMTestMode (1U << 0) 28892555Sdes#define FC_Transmitting (1U << 14) 28976259Sgreen#define FC_Receiving (1U << 15) 29076259Sgreen 29192555Sdes#define STGE_RxEarlyThresh 0x3a /* 16-bit */ 292192595Sdes 293149753Sdes#define STGE_FlowOffThresh 0x3c /* 16-bit */ 294248619Sdes 295248619Sdes#define STGE_FlowOnTresh 0x3e /* 16-bit */ 29676259Sgreen 29776259Sgreen#define STGE_TxStartThresh 0x44 /* 16-bit */ 29876259Sgreen 29992555Sdes#define STGE_EepromData 0x48 /* 16-bit */ 30092555Sdes 30192555Sdes#define STGE_EepromCtrl 0x4a /* 16-bit */ 30292555Sdes#define EC_EepromAddress(x) ((x) & 0xff) 30392555Sdes#define EC_EepromOpcode(x) ((x) << 8) 30476259Sgreen#define EC_OP_WE 0 30576259Sgreen#define EC_OP_WR 1 30676259Sgreen#define EC_OP_RR 2 30799063Sdes#define EC_OP_ER 3 30899063Sdes#define EC_EepromBusy (1U << 15) 30999063Sdes 31099063Sdes#define STGE_ExpRomAddr 0x4c 31192555Sdes 312162856Sdes#define STGE_ExpRomData 0x50 /* 8-bit */ 31392555Sdes 31492555Sdes#define STGE_WakeEvent 0x51 /* 8-bit */ 31592555Sdes#define WE_WakePktEnable (1U << 0) 31692555Sdes#define WE_MagicPktEnable (1U << 1) 31792555Sdes#define WE_LinkEventEnable (1U << 2) 318147005Sdes#define WE_WakePolarity (1U << 3) 31992555Sdes#define WE_WakePktEvent (1U << 4) 32092555Sdes#define WE_MagicPktEvent (1U << 5) 321263712Sdes#define WE_LinkEvent (1U << 6) 322255767Sdes#define WE_WakeOnLanEnable (1U << 7) 32392555Sdes 324255767Sdes#define STGE_Countdown 0x54 32592555Sdes#define CD_Count(x) ((x) & 0xffff) 32692555Sdes#define CD_CountdownSpeed (1U << 24) 32792555Sdes#define CD_CountdownMode (1U << 25) 32892555Sdes#define CD_CountdownIntEnabled (1U << 26) 329147005Sdes 33092555Sdes#define STGE_IntStatusAck 0x5a /* 16-bit */ 33192555Sdes 33292555Sdes#define STGE_IntEnable 0x5c /* 16-bit */ 33392555Sdes 33492555Sdes#define STGE_IntStatus 0x5e /* 16-bit */ 33592555Sdes 33692555Sdes#define IS_InterruptStatus (1U << 0) 33792555Sdes#define IS_HostError (1U << 1) 33892555Sdes#define IS_TxComplete (1U << 2) 33976259Sgreen#define IS_MACControlFrame (1U << 3) 340248619Sdes#define IS_RxComplete (1U << 4) 34192555Sdes#define IS_RxEarly (1U << 5) 34292555Sdes#define IS_InRequested (1U << 6) 34392555Sdes#define IS_UpdateStats (1U << 7) 34492555Sdes#define IS_LinkEvent (1U << 8) 34592555Sdes#define IS_TxDMAComplete (1U << 9) 34692555Sdes#define IS_RxDMAComplete (1U << 10) 34792555Sdes#define IS_RFDListEnd (1U << 11) 34892555Sdes#define IS_RxDMAPriority (1U << 12) 34992555Sdes 350248619Sdes#define STGE_TxStatus 0x60 351248619Sdes#define TS_TxError (1U << 0) 352294332Sdes#define TS_LateCollision (1U << 2) 35376259Sgreen#define TS_MaxCollisions (1U << 3) 35498684Sdes#define TS_TxUnderrun (1U << 4) 35598684Sdes#define TS_TxIndicateReqd (1U << 6) 35698684Sdes#define TS_TxComplete (1U << 7) 35798684Sdes#define TS_TxFrameId_get(x) ((x) >> 16) 358124211Sdes 359124211Sdes#define STGE_MACCtrl 0x6c 360124211Sdes#define MC_IFSSelect(x) ((x) & 3) 36198684Sdes#define MC_IFS96bit 0 36298684Sdes#define MC_IFS1024bit 1 36398684Sdes#define MC_IFS1792bit 2 36499052Sdes#define MC_IFS4352bit 3 365124211Sdes 36699052Sdes#define MC_DuplexSelect (1U << 5) 36798684Sdes#define MC_RcvLargeFrames (1U << 6) 36898684Sdes#define MC_TxFlowControlEnable (1U << 7) 36998684Sdes#define MC_RxFlowControlEnable (1U << 8) 37099052Sdes#define MC_RcvFCS (1U << 9) 37198684Sdes#define MC_FIFOLoopback (1U << 10) 37299052Sdes#define MC_MACLoopback (1U << 11) 37398684Sdes#define MC_AutoVLANtagging (1U << 12) 37499052Sdes#define MC_AutoVLANuntagging (1U << 13) 375124211Sdes#define MC_CollisionDetect (1U << 16) 37699052Sdes#define MC_CarrierSense (1U << 17) 37798684Sdes#define MC_StatisticsEnable (1U << 21) 37899052Sdes#define MC_StatisticsDisable (1U << 22) 37998684Sdes#define MC_StatisticsEnabled (1U << 23) 38098684Sdes#define MC_TxEnable (1U << 24) 38198684Sdes#define MC_TxDisable (1U << 25) 382#define MC_TxEnabled (1U << 26) 383#define MC_RxEnable (1U << 27) 384#define MC_RxDisable (1U << 28) 385#define MC_RxEnabled (1U << 29) 386#define MC_Paused (1U << 30) 387#define MC_MASK 0x7fe33fa3 388 389#define STGE_VLANTag 0x70 390 391#define STGE_PhySet 0x75 /* 8-bit */ 392#define PS_MemLenb9b (1U << 0) 393#define PS_MemLen (1U << 1) 394#define PS_NonCompdet (1U << 2) 395 396#define STGE_PhyCtrl 0x76 /* 8-bit */ 397#define PC_MgmtClk (1U << 0) 398#define PC_MgmtData (1U << 1) 399#define PC_MgmtDir (1U << 2) /* MAC->PHY */ 400#define PC_PhyDuplexPolarity (1U << 3) 401#define PC_PhyDuplexStatus (1U << 4) 402#define PC_PhyLnkPolarity (1U << 5) 403#define PC_LinkSpeed(x) (((x) >> 6) & 3) 404#define PC_LinkSpeed_Down 0 405#define PC_LinkSpeed_10 1 406#define PC_LinkSpeed_100 2 407#define PC_LinkSpeed_1000 3 408 409#define STGE_StationAddress0 0x78 /* 16-bit */ 410 411#define STGE_StationAddress1 0x7a /* 16-bit */ 412 413#define STGE_StationAddress2 0x7c /* 16-bit */ 414 415#define STGE_VLANHashTable 0x7e /* 16-bit */ 416 417#define STGE_VLANId 0x80 418 419#define STGE_MaxFrameSize 0x86 420 421#define STGE_ReceiveMode 0x88 /* 16-bit */ 422#define RM_ReceiveUnicast (1U << 0) 423#define RM_ReceiveMulticast (1U << 1) 424#define RM_ReceiveBroadcast (1U << 2) 425#define RM_ReceiveAllFrames (1U << 3) 426#define RM_ReceiveMulticastHash (1U << 4) 427#define RM_ReceiveIPMulticast (1U << 5) 428#define RM_ReceiveVLANMatch (1U << 8) 429#define RM_ReceiveVLANHash (1U << 9) 430 431#define STGE_HashTable0 0x8c 432 433#define STGE_HashTable1 0x90 434 435#define STGE_RMONStatisticsMask 0x98 /* set to disable */ 436 437#define STGE_StatisticsMask 0x9c /* set to disable */ 438 439#define STGE_RxJumboFrames 0xbc /* 16-bit */ 440 441#define STGE_TCPCheckSumErrors 0xc0 /* 16-bit */ 442 443#define STGE_IPCheckSumErrors 0xc2 /* 16-bit */ 444 445#define STGE_UDPCheckSumErrors 0xc4 /* 16-bit */ 446 447#define STGE_TxJumboFrames 0xf4 /* 16-bit */ 448 449/* 450 * TC9021 statistics. Available memory and I/O mapped. 451 */ 452 453#define STGE_OctetRcvOk 0xa8 454 455#define STGE_McstOctetRcvdOk 0xac 456 457#define STGE_BcstOctetRcvdOk 0xb0 458 459#define STGE_FramesRcvdOk 0xb4 460 461#define STGE_McstFramesRcvdOk 0xb8 462 463#define STGE_BcstFramesRcvdOk 0xbe /* 16-bit */ 464 465#define STGE_MacControlFramesRcvd 0xc6 /* 16-bit */ 466 467#define STGE_FrameTooLongErrors 0xc8 /* 16-bit */ 468 469#define STGE_InRangeLengthErrors 0xca /* 16-bit */ 470 471#define STGE_FramesCheckSeqErrors 0xcc /* 16-bit */ 472 473#define STGE_FramesLostRxErrors 0xce /* 16-bit */ 474 475#define STGE_OctetXmtdOk 0xd0 476 477#define STGE_McstOctetXmtdOk 0xd4 478 479#define STGE_BcstOctetXmtdOk 0xd8 480 481#define STGE_FramesXmtdOk 0xdc 482 483#define STGE_McstFramesXmtdOk 0xe0 484 485#define STGE_FramesWDeferredXmt 0xe4 486 487#define STGE_LateCollisions 0xe8 488 489#define STGE_MultiColFrames 0xec 490 491#define STGE_SingleColFrames 0xf0 492 493#define STGE_BcstFramesXmtdOk 0xf6 /* 16-bit */ 494 495#define STGE_CarrierSenseErrors 0xf8 /* 16-bit */ 496 497#define STGE_MacControlFramesXmtd 0xfa /* 16-bit */ 498 499#define STGE_FramesAbortXSColls 0xfc /* 16-bit */ 500 501#define STGE_FramesWEXDeferal 0xfe /* 16-bit */ 502 503/* 504 * RMON-compatible statistics. Only accessible if memory-mapped. 505 */ 506 507#define STGE_EtherStatsCollisions 0x100 508 509#define STGE_EtherStatsOctetsTransmit 0x104 510 511#define STGE_EtherStatsPktsTransmit 0x108 512 513#define STGE_EtherStatsPkts64OctetsTransmit 0x10c 514 515#define STGE_EtherStatsPkts64to127OctetsTransmit 0x110 516 517#define STGE_EtherStatsPkts128to255OctetsTransmit 0x114 518 519#define STGE_EtherStatsPkts256to511OctetsTransmit 0x118 520 521#define STGE_EtherStatsPkts512to1023OctetsTransmit 0x11c 522 523#define STGE_EtherStatsPkts1024to1518OctetsTransmit 0x120 524 525#define STGE_EtherStatsCRCAlignErrors 0x124 526 527#define STGE_EtherStatsUndersizePkts 0x128 528 529#define STGE_EtherStatsFragments 0x12c 530 531#define STGE_EtherStatsJabbers 0x130 532 533#define STGE_EtherStatsOctets 0x134 534 535#define STGE_EtherStatsPkts 0x138 536 537#define STGE_EtherStatsPkts64Octets 0x13c 538 539#define STGE_EtherStatsPkts65to127Octets 0x140 540 541#define STGE_EtherStatsPkts128to255Octets 0x144 542 543#define STGE_EtherStatsPkts256to511Octets 0x148 544 545#define STGE_EtherStatsPkts512to1023Octets 0x14c 546 547#define STGE_EtherStatsPkts1024to1518Octets 0x150 548 549/* 550 * Transmit descriptor list size. 551 */ 552#define STGE_TX_RING_CNT 256 553#define STGE_TX_LOWAT (STGE_TX_RING_CNT/32) 554#define STGE_TX_HIWAT (STGE_TX_RING_CNT - STGE_TX_LOWAT) 555 556/* 557 * Receive descriptor list size. 558 */ 559#define STGE_RX_RING_CNT 256 560 561#define STGE_MAXTXSEGS STGE_NTXFRAGS 562 563#define STGE_JUMBO_FRAMELEN 9022 564#define STGE_JUMBO_MTU \ 565 (STGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 566 567struct stge_txdesc { 568 struct mbuf *tx_m; /* head of our mbuf chain */ 569 bus_dmamap_t tx_dmamap; /* our DMA map */ 570 STAILQ_ENTRY(stge_txdesc) tx_q; 571}; 572 573STAILQ_HEAD(stge_txdq, stge_txdesc); 574 575struct stge_rxdesc { 576 struct mbuf *rx_m; 577 bus_dmamap_t rx_dmamap; 578}; 579 580#define STGE_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff) 581#define STGE_ADDR_HI(x) ((u_int64_t) (x) >> 32) 582 583#define STGE_RING_ALIGN 8 584 585struct stge_chain_data{ 586 bus_dma_tag_t stge_parent_tag; 587 bus_dma_tag_t stge_tx_tag; 588 struct stge_txdesc stge_txdesc[STGE_TX_RING_CNT]; 589 struct stge_txdq stge_txfreeq; 590 struct stge_txdq stge_txbusyq; 591 bus_dma_tag_t stge_rx_tag; 592 struct stge_rxdesc stge_rxdesc[STGE_RX_RING_CNT]; 593 bus_dma_tag_t stge_tx_ring_tag; 594 bus_dmamap_t stge_tx_ring_map; 595 bus_dma_tag_t stge_rx_ring_tag; 596 bus_dmamap_t stge_rx_ring_map; 597 bus_dmamap_t stge_rx_sparemap; 598 599 int stge_tx_prod; 600 int stge_tx_cons; 601 int stge_tx_cnt; 602 int stge_rx_cons; 603#ifdef DEVICE_POLLING 604 int stge_rxcycles; 605#endif 606 int stge_rxlen; 607 struct mbuf *stge_rxhead; 608 struct mbuf *stge_rxtail; 609}; 610 611struct stge_ring_data { 612 struct stge_tfd *stge_tx_ring; 613 bus_addr_t stge_tx_ring_paddr; 614 struct stge_rfd *stge_rx_ring; 615 bus_addr_t stge_rx_ring_paddr; 616}; 617 618#define STGE_TX_RING_ADDR(sc, i) \ 619 ((sc)->sc_rdata.stge_tx_ring_paddr + sizeof(struct stge_tfd) * (i)) 620#define STGE_RX_RING_ADDR(sc, i) \ 621 ((sc)->sc_rdata.stge_rx_ring_paddr + sizeof(struct stge_rfd) * (i)) 622 623#define STGE_TX_RING_SZ \ 624 (sizeof(struct stge_tfd) * STGE_TX_RING_CNT) 625#define STGE_RX_RING_SZ \ 626 (sizeof(struct stge_rfd) * STGE_RX_RING_CNT) 627 628/* 629 * Software state per device. 630 */ 631struct stge_softc { 632 struct ifnet *sc_ifp; /* interface info */ 633 device_t sc_dev; 634 device_t sc_miibus; 635 struct resource *sc_res[2]; 636 struct resource_spec *sc_spec; 637 void *sc_ih; /* interrupt cookie */ 638 int sc_rev; /* silicon revision */ 639 640 struct callout sc_tick_ch; /* tick callout */ 641 642 struct stge_chain_data sc_cdata; 643 struct stge_ring_data sc_rdata; 644 int sc_if_flags; 645 int sc_if_framesize; 646 int sc_txthresh; /* Tx threshold */ 647 uint32_t sc_usefiber:1; /* if we're fiber */ 648 uint32_t sc_stge1023:1; /* are we a 1023 */ 649 uint32_t sc_DMACtrl; /* prototype DMACtrl reg. */ 650 uint32_t sc_MACCtrl; /* prototype MacCtrl reg. */ 651 uint16_t sc_IntEnable; /* prototype IntEnable reg. */ 652 uint16_t sc_led; /* LED conf. from EEPROM */ 653 uint8_t sc_PhyCtrl; /* prototype PhyCtrl reg. */ 654 int sc_suspended; 655 int sc_detach; 656 657 int sc_rxint_nframe; 658 int sc_rxint_dmawait; 659 int sc_nerr; 660 int sc_watchdog_timer; 661 int sc_link; 662 663 struct task sc_link_task; 664 struct mtx sc_mii_mtx; /* MII mutex */ 665 struct mtx sc_mtx; 666}; 667 668#define STGE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 669#define STGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 670#define STGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 671#define STGE_MII_LOCK(_sc) mtx_lock(&(_sc)->sc_mii_mtx) 672#define STGE_MII_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mii_mtx) 673 674#define STGE_MAXERR 5 675 676#define STGE_RXCHAIN_RESET(_sc) \ 677do { \ 678 (_sc)->sc_cdata.stge_rxhead = NULL; \ 679 (_sc)->sc_cdata.stge_rxtail = NULL; \ 680 (_sc)->sc_cdata.stge_rxlen = 0; \ 681} while (/*CONSTCOND*/0) 682 683#define STGE_TIMEOUT 1000 684 685#define STGE_RESET_NONE 0x00 686#define STGE_RESET_TX 0x01 687#define STGE_RESET_RX 0x02 688#define STGE_RESET_FULL 0x04 689