| 360659 |
05-May-2020 |
dim |
Fix-up for arm, armeb and armv6 builds erroring after r360658, with:
In file included from /usr/src/contrib/compiler-rt/lib/builtins/clear_cache.c:26:
/usr/obj/arm.armv6/usr/src/tmp/usr/include/machine/sysarch.h:95:22: error: unknown type name 'u_int'
int arm_sync_icache (u_int addr, int len);
^
MFC r349887 (by ian):
De-pollute arm's sysarch.h.
Instead of including stdint.h for uintptr_t, include sys/_types.h and use
__types for everything that isn't a native C keyword type.
Remove the #include of cdefs.h. It appears after the include of armreg.h
which has a precondition of cdefs.h being included before it, so everyone
including sysarch.h is already including cdefs.h. (When armv5 support
goes away, there will be no need include armreg.h here either.)
Unfortunately, the unprefixed struct member names "addr" and "len" cannot
be changed, because 3rd-party software is relying on them (libcompiler_rt
is one known consumer). |
| 342078 |
14-Dec-2018 |
mmel |
MFC r341679:
Fix cut&paste typo in atomic_fetchadd_64(). |
| 340556 |
18-Nov-2018 |
kib |
MFC r340136:
Move the fixed base for PIE loading on arm. |
| 340270 |
08-Nov-2018 |
jhb |
MFC 340164,340168,340170: Add custom cpu_lock_delay() for x86.
340164:
Add a KPI for the delay while spinning on a spin lock.
Replace a call to DELAY(1) with a new cpu_lock_delay() KPI. Currently
cpu_lock_delay() is defined to DELAY(1) on all platforms. However,
platforms with a DELAY() implementation that uses spin locks should
implement a custom cpu_lock_delay() doesn't use locks.
340168:
Add a delay_tsc() static function for when DELAY() uses the TSC.
This uses slightly simpler logic than the existing code by using the
full 64-bit counter and thus not having to worry about counter
overflow.
340170:
Add a custom implementation of cpu_lock_delay() for x86.
Avoid using DELAY() since it can try to use spin locks on CPUs without
a P-state invariant TSC. For cpu_lock_delay(), always use the TSC if
it exists (even if it is not P-state invariant) to delay for a
microsecond. If the TSC does not exist, read from I/O port 0x84 to
delay instead.
PR: 228768 |
| 338514 |
06-Sep-2018 |
jhb |
MFC 332906,332907,332976,333679,336053: Expand testing of breakpoints.
332906:
Extend support for ptrace() tests using breakpoints.
- Use a single list of platforms to define HAVE_BREAKPOINT for platforms
that expose a functional breakpoint() inline to userland. Replace
existing lists of platform tests with HAVE_BREAKPOINT instead.
- Add support for advancing PC past a breakpoint inserted via breakpoint()
to support the existing ptrace__PT_CONTINUE_different_thread test on
non-x86 platforms (x86 advances the PC past the breakpoint instruction,
but other platforms do not). This is implemented by defining a new
SKIP_BREAK macro which accepts a pointer to a 'struct reg' as its sole
argument and modifies the contents to advance the PC. The intention is
to use it in between PT_GETREGS and PT_SETREGS.
332907:
Expose breakpoint() to userland from <machine/cpufunc.h> on MIPS.
Enable ptrace() tests using breakpoint on MIPS as well.
332976:
Shorten some recently-added lines that are an extra indent over 80 columns.
333679:
Export a breakpoint() function to userland for riscv.
As a result, enable tests using breakpoint() on riscv.
336053:
Export a breakpoint() function to userland for arm and arm64.
Enable ptrace() tests using breakpoint() on these architectures. |
| 333687 |
16-May-2018 |
jhb |
MFC 332891,332892: Fixes for atomic_*cmpset() on arm.
332891:
Fix some harmless type mismatches in the ARM atomic_cmpset implementations.
The return value of atomic_cmpset() and atomic_fcmpset() is an int (which
is really a bool) that has the values 0 or 1. Some of the inlines were
using the type being operated on (e.g. uint32_t) as either the return type
of the function, or the type of a local 'ret' variable used to hold the
return value. Fix all of these to just use plain 'int'. Due to C promotion
rules and the fact that the value can only be 0 or 1, these should all be
harmless.
332892:
Implement 32-bit atomic_fcmpset() in userland for armv4/v5.
- Add an implementation of atomic_fcmpset_32() using RAS for armv4/v5.
This fixes recent world breakage due to use of atomic_fcmpset() in
userland.
- While here, be more careful to not expose wrapper macros for 64-bit
atomic_*cmpset to userland for armv4/v5 as only 32-bit cmpset is
implemented.
This has been reviewed, but not runtime-tested, but should fix the arm.arm
and arm.armeb worlds that have been broken for a while.
Approved by: re (kib) |
| 332135 |
06-Apr-2018 |
kevans |
MFC r329859,r329860: Float protection in stand
r329859: Do not include float interfaces when using libsa.
We don't support float in the boot loaders, so don't include
interfaces for float or double in systems headers. In addition, take
the unusual step of spiking double and float to prevent any more
accidental seepage.
r329860: Floaty McFloatface is funnier... |
| 331988 |
04-Apr-2018 |
mmel |
MFC r328467:
Implement mitigation for Spectre version 2 attacks on ARMv7. |
| 331971 |
04-Apr-2018 |
mmel |
MFC r309531,r309553,r309604:
r309531:
Implement fake pmap_mapdev_attr() for ARMv6. This function is referenced,
but never called from DRM2 code. Also, real behavior of pmap_mapdev_attr()
in ARM world is unclear as we don't have any additional attribute for a
device memory type.
r309553:
Fix build breakage caused by r309531.
r309604:
Fix the armv6 build after r309553. |
| 331968 |
04-Apr-2018 |
mmel |
MFC r319896,r320054:
r319896:
Implement tunable CPU quirks. These quirks are intended for optimizing CPU
performance, not for applying errata workarounds. Nobody can expect that
CPU with unfixed errata is stable enough to execute the kernel until quirks
are applied.
r320054:
Manually load tunable CPU quirks. These are needed too early, far before
SYSINIT is processed. |
| 331907 |
03-Apr-2018 |
gonzo |
MFC r307943-r307944, r308698
r307943 by andrew:
Remove the need for the delay to be zero when MULTIDELAY is undefined,
it may be useful to only enable this in some configs.
Sponsored by: ABT Systems Ltd
r307944 by andrew:
Add MULTIDELAY support to the am335x dmtimer. This will be useful for
testing Cortex-A8 support in GENERIC.
Sponsored by: ABT Systems Ltd
r308698 by loos:
After r308533, the platform compatible string must be an exact match.
Use "ti,am33xx" instead of "ti,am335x", which gives an exact match in every
DTS we support.
This fixes the boot on TI SoCs after r308533.
Suggested by: gonzo
Sponsored by: Rubicon Communications, LLC (Netgate) |
| 331722 |
29-Mar-2018 |
eadler |
Revert r330897:
This was intended to be a non-functional change. It wasn't. The commit
message was thus wrong. In addition it broke arm, and merged crypto
related code.
Revert with prejudice.
This revert skips files touched in r316370 since that commit was since
MFCed. This revert also skips files that require $FreeBSD$ property
changes.
Thank you to those who helped me get out of this mess including but not
limited to gonzo, kevans, rgrimes.
Requested by: gjb (re) |
| 331643 |
27-Mar-2018 |
dim |
MFC r314568 (by emaste):
kern_sig.c: ANSIfy and remove archaic register keyword
Sponsored by: The FreeBSD Foundation
MFC r318389 (by emaste):
Remove register keyword from sys/ and ANSIfy prototypes
A long long time ago the register keyword told the compiler to store
the corresponding variable in a CPU register, but it is not relevant
for any compiler used in the FreeBSD world today.
ANSIfy related prototypes while here.
Reviewed by: cem, jhb
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D10193 |
| 330897 |
14-Mar-2018 |
eadler |
Partial merge of the SPDX changes
These changes are incomplete but are making it difficult
to determine what other changes can/should be merged.
No objections from: pfg |
| 329140 |
11-Feb-2018 |
kevans |
MFC Loader Fixes 2017q4p6: r324649,r324650,r324651,r324652,r324653,r324654,
r324700,r324702,r324709,r324717,r324719,r324841,r324842,r324843,r324845,
r324850,r324876,r324877,r324878,r324879,r324880,r324881,r324883,r324980,
r324981,r324982,r324995,r325014,r325093,r325094,r325114,r325170,r325171,
r325172,r325173,r325174,r325175,r325176,r325248,r325286,r325310,r325332,
r325338,r325339,r325376,r325377,r325379,r325380,r325382,r325478,r325479,
r325480,r325482,r325483,r325484,r325485,r325556,r325641,r325681,r325685,
r325686,r325687,r325688,r325689,r325690,r325691,r325692,r325693,r325694,
r325743,r325744,r325748,r325775,r325779,r325780
r324649: Move common/Makefile.inc to sys/boot/loader.mk.
r324650: tweak style
r324651: create defs.mk for common definitions
r324652: Move all the ficl common code into ficl.mk
r324653: LOADER_foo_SUPPORTED
r324654: Explicitly inlcude SYSDIR in the include path
r324700: loader: initialize dv_cleanup in md.c to eliminate clang warning
r324702: We need to include disk.o in libuboot.a when we're building with
support for disk access.
r324709: Revert "Unify boot1 with loader" change r324646
r324717: libsa/ip.c: misplaced comment, ip_v is half char, not ip_p
r324719: libsa/ip: stop read loop on bad fragments
r324841: Use BOOTDIR more consistently in defs.mk rather than repeat
sys/boot.
r324842: Introduce BOOTOBJ: The top level object directory for the boot tree
r324843: Stopgap fix to the mistmatch between LOADER_GELI_SUPPORT and
LOADER_NO_GELI_SUPPORT.
r324845: Use BOOTOBJ and BOOTDIR to find geli includes and libraries.
r324850: Define LIBSA32 to LIBSA on i386 to fix build.
r324876: Move fdt and uboot defines into common uboot.mk.
r324877: End source directories with SRC rather than a hodgepodge of names
r324878: Make at91 boot loader compile again.
r324879: Prefer SRCTOP paths for bits we're grabbing from libc.
r324880: Use BOOTSRC here.
r324881: Use SYSDIR instead of ${.CURDIR}/../..<etc>/sys.
r324883: Use preferred defined paths, rather than relative paths in fdt.
r324980: Use BOOTDIR consistently.
r324981: Move BINDIR definition to defs.mk, and override where it isn't
/boot
r324982: Remove sys/boot/arm/at91 and ixp425
r324995: loader.efi: Make framebuffer commands available for arm64
r325014: Add a 'place holder' arm struct efi_fb until a real one comes
r325093: Define new EFI variables
r325094: Cleanup non-arch Makefiles
r325114: Use defs.mk defins in most MD code
r325170: Use defs.mk values for userboot
r325171: Use defs.mk name and prefer bsd.init.mk
r325172: Remove the -nostdlib stuff I added. Instead, fix LDFLAGS to be
honored correctly with the new Makefile.inc include order.
r325173: We don't need to build a special ficl for userboot.
r325174: Minor cleanup
r325175: For amd64, compile both zfs and zfs32 libraries.
r325176: Actually add zfs32/Makefile
r325248: loader ptblread() is broken with >512B sectors
r325286: efipart_strategy is using wrong offset with >512B sectors
r325310: zfs.c:vdev_read() needs to be careful about large sectors
r325332: loader: re-enable gzip support for x86
r325338: loader: fix BOOTSRC -> BOOTOBJ in a library path
r325339: This used to have bzip2 support too.
r325376: WIP: centralize machine links
r325377: mostly libsa
r325379: Revert "mostly libsa"
r325380: Revert "WIP: centralize machine links"
r325382: Cleanup stray libstand names to be libsa names.
r325478: Powerpc is a 32-bit boot loader.
r325479: Define LIBFICL32 to be libficl.a on i386 and libficl32.a on amd64.
r325480: Use DO32 for all the places that we need to flag we're building a
32-bit version of a library.
r325482: Move machine and other link creation to defs.mk
r325483: MACHINE can never be powerpc64, so cleanup code that thinks it can.
r325484: Prefer bsd.init.mk to src.opts.mk
r325485: Centralize all 32-bit builds on 64-bit platform stuff.
r325556: loader: set options before including bsd.init.mk
r325641: loader.efi: efi_devpath_is_prefix should return bool
r325681: boot1: avoid using NULL device path
r325685: libsa32 isn't needed for i386. It's already a 32-bit platform.
r325686: Simplify this if to a direct assignment.
r325687: Remove all the empty help files from the powerpc build.
r325688: FDT support doesn't make sense for ps3, remove it.
r325689: Remove LOADER_FDT_SUPPORT as a Makefile variable.
r325690: Remove LOADER_ZFS_SUPPORT as a Makefile variable
r325691: Remove useless PNP define here.
r325692: Replace LOADER_FIREWIRE_SUPPORT variable
r325693: Move LOADER_{NO,}_GELI_SUPPORT to MK_LOADER_GELI
r325694: Install the 4th files in sys/boot/forth instead of each loader
r325743: Make sure the proper loader.rc gets installed.
r325744: boot1: also check for NULL device
r325748: Use proper include file.
r325775: Add loader.conf to the list of files that are MD.
r325779: Add /boot/dts to the list of default modules.
r325780: Don't add /boot/dt*s* but /boot/dt*b*. Stupid think-o. |
| 328966 |
07-Feb-2018 |
mmel |
MFC r325438:
All CP15 registers are bit fields or counters, don't use signed type when
accessing them. |
| 328386 |
25-Jan-2018 |
pkelsey |
MFC r316648:
Corrected misspelled versions of rendezvous.
The MFC maintains smp_no_rendevous_barrier() as a symbol alias of
smp_no_rendezvous_barrier().
__FreeBSD_version bumped to indicate presence of the new name
smp_no_rendezvous_barrier().
Reviewed by: gnn, jhb (email), kib
Differential Revision: https://reviews.freebsd.org/D10313 |
| 327658 |
07-Jan-2018 |
ian |
MFC r327367:
Make kernel option KERNVIRTADDR optional, remove it from std.<platform>
files that can use the default value.
It used to be required that the low-order bits of KERNVIRTADDR matched
the low-order bits of the physical load address for all arm platforms.
That hasn't been a requirement for armv6 platforms since FreeBSD 10.
There is no longer any relationship between load addr and KERNVIRTADDR
except that both must be aligned to a 2 MiB boundary.
This change makes the default KERNVIRTADDR value 0xc0000000, and removes the
options from all the platforms that can use the default value. The default
is now defined in vmparam.h, and that file is now included in a few new
places that reference KERNVIRTADDR, since it may not come in via the
forced-include of opt_global.h on the compile command line. |
| 327195 |
26-Dec-2017 |
kib |
MFC r326971, r327047 (by ian), r327053 (by marius), r327074, r327097:
Add atomic_load(9) and atomic_store(9) operations. |
| 325831 |
14-Nov-2017 |
jhb |
MFC 323581,323582,323583: Add ptrace operations for VFP registers.
323581:
Only mess with VFP state on the CPU for curthread for get/set_vfpcontext.
Future changes will use these functions to fetch and store VFP state for
threads other than curthread.
323582:
Add ptrace operations to fetch and store VFP registers.
323583:
Export get/set_vfpcontext from machdep.c.
Should have been part of the previous commit to add ptrace operations
for VFP registers. |
| 325810 |
14-Nov-2017 |
jhb |
MFC 323580,323933,323934,324814,324817: Enable AT_HWCAP on arm.
I reused the SV_HWCAP stub to cover the sv_hwcap2 field as well.
323580:
Add AT_HWCAP flags for VFP settings for FreeBSD/arm.
These flags match the meaning and value of flags in Linux, though
Linux has many more flags.
323933:
Correct HWCAP_VFP3* values to match Linux.
323934:
Detect NEON and set HWCAP_NEON if present.
324814:
Add AT_HWCAP2 ELF auxiliary vector.
- allocate value for new AT_HWCAP2 auxiliary vector on all platforms.
- expand 'struct sysentvec' by new 'u_long *sv_hwcap2', in exactly
same way as for AT_HWCAP.
324817:
Fullify implementation of AT_HWCAP and AT_HWCAP2 for ARMv6,7.
This makes elf_aux_info(3) useable for ARM ports.
Tested by: mmel |
| 325307 |
02-Nov-2017 |
mmel |
MFC r324660:
Save VFP state in getcontext(3) on ARM. This is a last followup of r315974,
which fixes userland part of VFP save/restore problems described in PR
217611. |
| 324687 |
17-Oct-2017 |
jhb |
MFC 323579,323585: Add AT_HWCAP and AT_EHDRFLAGS on all platforms.
To preserve KBI on stable/11, a new SV_HWCAP flag is added which
indicates if the sv_hwcap field is present and valid to avoid examining
the field in old modules. Only sysentvec's which wish to use sv_hwcap
need to set the flag in stable/11.
323579:
Add AT_HWCAP and AT_EHDRFLAGS on all platforms.
A new 'u_long *sv_hwcap' field is added to 'struct sysentvec'. A
process ABI can set this field to point to a value holding a mask of
architecture-specific CPU feature flags. If an ABI does not wish to
supply AT_HWCAP to processes the field can be left as NULL.
The support code for AT_EHDRFLAGS was already present on all systems,
just the #define was not present. This is a step towards unifying the
AT_* constants across platforms.
323585:
Add AT_EHDRFLAGS and AT_HWCAP on amd64.
x86 has two separate (but identical) list of AT_* constants and the
earlier commit to add AT_HWCAP only updated the i386 list. |
| 323423 |
11-Sep-2017 |
ian |
MFC r321489:
Use the MD __size_t to avoid a dependency on/include of non-MD header files.
This should fix the compilation of the lua 5.3.4 port, among others. |
| 321039 |
16-Jul-2017 |
markj |
MFC r311204:
Add some missing atomic_*_ptr #defines for arm. |
| 318742 |
23-May-2017 |
mmel |
MFC r318021,r318251:
r318021:
Introduce pmap_remap_vm_attr(), it allows to remap one VM memattr class to
another.
r318251:
Clarify usage rules for pmap_remap_vm_attr(). Not a functional change. |
| 318637 |
22-May-2017 |
mmel |
MFC r318530:
Increase maximum text segment size. LLVM binaries are huge... |
| 318576 |
20-May-2017 |
kib |
MFC efivar(8) (by imp):
List of revisions merged:
r307070
r307071
r307072
r307074
r307189
r307224
r307339
r307390
r307391
r309776
r314231
r314232
r314615
r314616
r314617
r314618
r314619
r314620
r314621
r314623
r314890
r314925
r314926
r314927
r314928
r315770
r315771
Discussed with: gjb (re), imp
Sponsored by: The FreeBSD Foundation |
| 317005 |
16-Apr-2017 |
mmel |
MFC r315900,r315973,r315974:
r315900:
Cleanup structures related to VFP and/or mcontext_t. - in mcontext_t,
rename newer used 'union __vfp' to equaly sized 'mc_spare'.
Space allocated by 'union __vfp' is too small and cannot hold full VFP
context.
- move structures defined in fp.h to more appropriate headers. - remove
all unused VFP structures.
r315973:
Save VFP state on fork(). Update the copy of VFP state in PCB before it is
cloned for new process.
r315974:
Preserve VFP state across signal delivery. |
| 317004 |
16-Apr-2017 |
mmel |
MFC r303261,r315059:
r303261:
Add more UEFI/e820 memory types from latest specifications.
r315059:
Split overbloated machep.c to multiple files and do basic cleanup of these
fragments. |
| 317003 |
16-Apr-2017 |
mmel |
MFC r306704,r308406:
r306704:
ARM: Remove next bunch of unused cpu_functions from ARMv6.
r308406:
Only include sys/boot.h if LINUX_BOOT_ABI is defined |
| 317002 |
16-Apr-2017 |
mmel |
MFC r306631,r306640,r306641,r306650,r306656:
r306631:
Use C99 designated initializers to create the armv6 cpu_functions structs.
This will help with a later cleanup of what functions we implement.
r306640:
Only define the CF_* macros on ARMv4/v5. They are unused on armv6.
r306641:
Remove the parts of cpu_functions from armv6 that are unused on that
architecture.
r306650:
Add the Cortex-A{53,57,72} ID register values. These can all run 32-bit
code so could run a 32-bit kernel.
r306656:
Use the cortex functions when booting on one of the Cortex-A ARMv8 CPUs.
This list is incomplete, however we don't have the ID values for the
missing Cortex-A32 or A35. |
| 315874 |
23-Mar-2017 |
mjg |
MFC r312932,r312933,r312949,r313141
(by cognet)
Use strexeq instead of needlessly branch.
==
(by cognet)
Remove useless labels.
==
(by cognet)
Correct the IT instruction in atomic_fcmpset_64().
==
(by andrew)
Only define atomic_fcmpset_long in the kernel. We may include
machine/atomic.h in userspace, however atomic_fcmpset_32 is unimplemented
there. |
| 315371 |
16-Mar-2017 |
mjg |
MFC r311169,r311898,r312925,r312973,r312975,r313007,r313040,r313080,
r313254,r313341
amd64: add atomic_fcmpset
==
sparc64: add atomic_fcmpset
==
Implement atomic_fcmpset_* for arm and arm64.
==
Add atomic_fcmpset_*() inlines for powerpc
Summary:
atomic_fcmpset_*() is analogous to atomic_cmpset(), but saves off the read value
from the target memory location into the 'old' pointer in the case of failure.
==
i386: add atomic_fcmpset
==
Don't retry a lost reservation in atomic_fcmpset()
The desired behavior of atomic_fcmpset_() is to always exit on error. Instead
of retrying on lost reservation, leave the retry to the caller, and return
==
Add atomic_fcmpset_*() inlines for MIPS
atomic_fcmpset_*() is analogous to atomic_cmpset(), but saves off the
read value from the target memory location into the 'old' pointer.
==
i386: fixup fcmpset
An incorrect output specifier was used which worked with clang by accident,
but breaks with the in-tree gcc version.
While here plug a whitespace nit.
==
Implement atomic_fcmpset_*() for RISC-V.
==
Use 64bit store instruction in atomic_fcmpset_64. |
| 314530 |
02-Mar-2017 |
ian |
MFC r312292, r313573:
Stop including sys/types.h from arm's machine/atomic.h, fix the places
where atomic.h was being included without ensuring that types.h (via
param.h) was included first, as required by atomic(9).
Remove arm's cpuconf.h, and references to it, after moving a few lines from
it into pmap-v4.h where they are used. Other than those few lines of
support for different MMU types, nothing in cpuconf.h has been used in our
code for quite a while.
The file existed to set up a variety of symbols to describe the
architecture. Over the past few years we have converted all of our source
to use the new architecture symbols standardized by ARM Inc, and predefined
by both clang and gcc. |
| 314525 |
01-Mar-2017 |
ian |
MFC r306901:
ARM: Split identify_arm_cpu() into ARMv4 and ARMv6 variant.
On ARMv6, be more verbose about supported CPU features and/or
optional instructions. |
| 314506 |
01-Mar-2017 |
ian |
MFC r306262, r306267, r310021: (needed to avoid conflicts on later merges)
Remove bus_dma_get_range and bus_dma_get_range_nb on armv6. We only need
this on a few earlier arm SoCs.
Restrict where we need to define fdt_fixup_table to just PowerPC and
Marvell.
Add the missing void to function signatures in much of the arm code. |
| 313989 |
20-Feb-2017 |
kib |
MFC r313345:
Update arm and arm64 counters MD bits.
MFC r313394 (by manu):
subr_sfbus.c need sys/proc.h for struct thread definition. |
| 313766 |
15-Feb-2017 |
jah |
MFC r312610, r312792
r312610:
Like r310481 for i386, move the objects used to create temporary
mappings for armv6 pmap zero and copy operations to the MD PCPU region.
Change sysmap initialization to only allocate KVA pages for CPUs that
are actually present.
While here, collapse CMAP3 into CMAP2 (their use was mutually exclusive
anyway) and "recover" some space in PCPU padding that has always been
available due to 64-byte cacheline padding.
r312792:
Further cleanup of per-CPU armv6 pmap data:
- Replace pcpu_find(curcpu) with get_pcpu(), which is much more direct.
- Remove armv4 pcpu fields which I added in r286296 but never needed
to use.
- armv6 pc_qmap_addr was leftover from the old armv6 pmap
implementation. Rename it and put it to use in the new one. |
| 313574 |
11-Feb-2017 |
kib |
MFC r313194:
Define the vm_ooffset_t and vm_pindex_t types as machine-independend. |
| 308327 |
05-Nov-2016 |
mmel |
MFC r306667,r306668:
r306667:
ARM: Add atomic_swap_64(). It's need by linuxkpi and drm-next-4.7.
r306668:
ARM: Add mising early clobber modifier in atomic_swap_32(). |
| 307344 |
15-Oct-2016 |
mmel |
MFC r306756:
ARM: SEV/WFE instructions are implemented starting from ARMv6K, use it
directly. |
| 307342 |
15-Oct-2016 |
mmel |
MFC r306755:
ARM: Add identifiers for ARM Cortex v8 and Marvell Sheeva v7 cores. Not a
functional change. |
| 307136 |
12-Oct-2016 |
ed |
MFC r306162:
Make it possible to safely use TPIDRURW from userspace.
On amd64, arm64 and i386, we have the possibility to switch between TLS
areas in userspace. The nice thing about this is that it makes it easier
to do light-weight threading, if we ever feel like doing that. On armv6,
let's go into the same direction by making it possible to safely use the
TPIDRURW register, which is intended for this purpose.
Clean up the ARMv6 code to remove md_tp entirely. Simply add a dedicated
field to the PCB to hold the value of TPIDRURW across context switches,
like we do for any other register. As userspace currently uses the
read-only TPIDRURO register, simply ensure that we keep both values in
sync where possible. The system calls for modifying the read-only
register will simply write the intended value into both registers, so
that it lazily ends up in the PCB during the next context switch.
Approved by: andrew
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D7951 |
| 306404 |
28-Sep-2016 |
kib |
MFC r306091:
Add a way for the architecture to specify the calling ABI for methods
in the EFI Runtime Services Table. On amd64, the calling conventions
are MS. |
| 305866 |
16-Sep-2016 |
kib |
MFC r304285:
Implement userspace gettimeofday(2) with HPET timecounter. |
| 305848 |
15-Sep-2016 |
emaste |
MFC r303677: Move/add ARM ELF PHDR types to elf_common.h |
| 302408 |
08-Jul-2016 |
gjb |
Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, as nothing has been merged
here.
Additional commits post-branch will follow.
Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation |
| 302064 |
21-Jun-2016 |
ian |
Revert the recent armv6 changes to ALIGNED_POINTER(), restoring the
fully-pessimized implementation that requires a type to be aligned to
its natural size.
On armv6+ the compiler might generate load-/store-multiple instructions
which require 4-byte alignment even though the source code is only
accessing individual uint32_t values in a way that doesn't require any
particular alignment at all. The compiler apparently feels free to
combine multiple accesses into a single instruction that requires a
more-strict alignment, and no set of compiler flags seems to disable
this behavior (at least in clang 3.8).
This fixes alignment faults on arm systems using wifi adapters. The
wifi code uses ALIGNED_POINTER(p, uint32_t) to decide whether it needs
to copy-align tcp headers. Because clang is combining several uint32_t
accesses into a single ldm instruction, we need to say that accessing a
uint32_t requires 4-byte alignment.
Approved by: re(gjb)
|
| 301872 |
13-Jun-2016 |
ian |
Do not define __NO_STRICT_ALIGNMENT for armv6. While the requirements
are no longer natural-alignment strict, there are still some restrictions.
FreeBSD network code assumes data is naturally-aligned or is running
on a platform with no restrictions; pointers are not annotated to
indicate the data pointed to may be packed or unaligned. The clang
optimizer can sometimes combine the load or store of a pair of adjacent
32-bit values into a single doubleword load/store, and that operation
requires at least 4-byte alignment. __NO_STRICT_ALIGNMENT can lead
to tcp headers being only 2-byte aligned.
Note that alignment faults remain disabled on armv6, this change reverts
only the defining of the symbol which leads to some overly-agressive code
shortcuts when building common/shared drivers and network code for arm.
Approved by: re(kib)
|
| 301700 |
08-Jun-2016 |
andrew |
Remove the ARMv4/ARMv5 userland atomic support from struct proc on armv6.
Nothing should use this on armv6 as we use the atomic instructions added in
ARMv6k.
Sponsored by: ABT Systems Ltd
|
| 301561 |
07-Jun-2016 |
andrew |
Start to clean MIDR values using the CPUID scheme. We don't need to know
the exact CPU we are running on to set the cpu functions. Relax the check
to ignore the CPU revision. Even so this may still be too specific.
Reviewed by: mmel
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D6504
|
| 300969 |
29-May-2016 |
zbb |
Improve ARM debug_monitor for SMP machines
- Reset debug architecture and enable monitor for secondary
CPUs in init_secondary() rather than when configuring watchpoint, etc.
- Disable HW debugging capabilities when one of the CPU cores fails
to set up.
- Use dbg_capable() in a more atomic manner to avoid any mismatch
between CPUs.
Differential Revision: https://reviews.freebsd.org/D6009
|
| 300701 |
26-May-2016 |
ian |
Disable alignment faults on armv6, adjust various alignment-related macros
to match the new state of affairs. The hardware we support has always been
able to do unaligned accesses, we've just never enabled it until now.
This brings FreeBSD into line with all the other major OSes, and should help
with the growing volume of 3rd-party software that assumes unaligned access
will just work on armv6 and armv7.
|
| 300694 |
25-May-2016 |
ian |
Include machine/acle-compat.h in cdefs.h on arm if the compiler doesn't
have ACLE support built in. The ACLE (ARM C Language Extensions) defines
a set of standardized symbols which indicate the architecture version and
features available. ACLE support is built in to modern compilers (both
clang and gcc), but absent from gcc prior to 4.4.
ARM (the company) provides the acle-compat.h header file to define the
right symbols for older versions of gcc. Basically, acle-compat.h does
for arm about the same thing cdefs.h does for freebsd: defines
standardized macros that work no matter which compiler you use. If ARM
hadn't provided this file we would have ended up with a big #ifdef __arm__
section in cdefs.h with our own compatibility shims.
Remove #include <machine/acle-compat.h> from the zillion other places (an
ever-growing list) that it appears. Since style(9) requires sys/types.h
or sys/param.h early in the include list, and both of those lead to
including cdefs.h, only a couple special cases still need to include
acle-compat.h directly.
Loves it: imp
|
| 300533 |
23-May-2016 |
ian |
Use the new(-ish) CP15_SCTLR macro to generate system control reg accesses
where possible. In the places that doesn't work (multi-line inline asm,
and places where the old armv4 cpufuncs mechanism is used), annotate the
accesses with a comment that includes SCTLR. Now a grep -i sctlr can find
all the system control register manipulations.
No functional changes.
|
| 300375 |
21-May-2016 |
ian |
Adjust _ALIGNBYTES to the proper value for arm and armv6 arches. Modern
compilers can emit arm instructions that require 8-byte alignment. The
alignment-sensitive instructions were added in armv5, which has to be
supported by our combined v4/v5 kernels, so the value is set uncoditionally
for all arm architecture versions.
Also adjust the comment to explain in more detail why the macros have the
form and values they do.
Per advice from bde@, maintain the unsignedness of the value of _ALIGNBYTES
(but do so using his second choice of allowing sizeof() to supply the
unsignedness, rather than just hardcoding '8U', which in my mind would
require an even more verbose comment to explain why it's right). Also
explain in the comment that the resulting type of _ALIGN() is equivelent
to uinptr_t on arm (32-bit unsigned int), but it's purposely spelled as
"unsigned" to avoid problems with including other header files. Even
including machine/_types.h to allow use of __uintptr_t causes compilation
failures because of this header being included (indirectly) in asm code.
The discussion that led to this change (albeit at a glacial pace) is at
https://lists.freebsd.org/pipermail/svn-src-head/2014-November/064593.html
|
| 300324 |
20-May-2016 |
imp |
Remove hf appending code from param.h for machine arch name.
Submitted by: ian@ andyt@
|
| 300144 |
18-May-2016 |
andrew |
Implement atomic_cmpset_acq_64 and atomic_cmpset_rel_64 on arm and armeb.
This should allow r300113 to build there.
Sponsored by: ABT Systems Ltd
|
| 300050 |
17-May-2016 |
eadler |
Don't repeat the the word 'the'
(one manual change to fix grammar)
Confirmed With: db
Approved by: secteam (not really, but this is a comment typo fix)
|
| 298854 |
30-Apr-2016 |
andrew |
Add a MULTIDELAY option to allow the ARM kernel to have multiple DELAY
implementations. Early in the boot the kernel will use an approximate,
however after the timer has been probed it will switch to a more accurate
implementation.
Reviewed by: manu
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D5762
|
| 298627 |
26-Apr-2016 |
br |
Move arm's devmap to some generic place, so it can be used
by other architectures.
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D6091
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
|
| 298457 |
22-Apr-2016 |
skra |
Don't use atomic operations for page table entries and handle access
and R/W emulation aborts under pmap lock.
There were two reasons for using of atomic operations:
(1) the pmap code is based on i386 one where they are used,
(2) there was an idea that access and R/W emulation aborts should be
handled as quick as possible, without pmap locking.
However, the atomic operations in i386 pmap code are used only because
page table entries may be modified by hardware. At the beginning, we
were not sure that it's the only reason. So even if arm hardware does
not modify them, we did not risk to not use them at that time. Further,
it turns out after some testing that using of pmap lock for access and
R/W emulation aborts does not bring any extra cost and there was no
measurable difference. Thus, we have decided finally to use pmap lock
for all operations on page table entries and so, there is no reason for
atomic operations on them. This makes the code cleaner and safer.
This decision introduce a question if it's safe to use pmap lock for
access and R/W emulation aborts. Anyhow, there may happen two cases in
general:
(A) Aborts while the pmap lock is locked already - this should not
happen as pmap lock is not recursive. However, under pmap lock only
internal kernel data should be accessed and such data should be mapped
with A bit set and NM bit cleared. If double abort happens, then
a mapping of data which has caused it must be fixed.
(B) Aborts while another lock(s) is/are locked - this already can
happen. There is no difference here if it's either access or R/W
emulation abort, or if it's some other abort.
Reviewed by: kib
|
| 298455 |
22-Apr-2016 |
skra |
Add four functions which check a virtual address for stage 1 privileged
(PL1) and unprivileged (PL0) read/write access. As cp15 virtual to
physical address translation operations are used, interrupts must be
disabled to get consistent result when they are called.
These functions should be used only in very specific occasions like
during abort handling or kernel debugging. One of them is going to be
used in pmap_fault(). However, complete function set is added. It cost
nothing, as they are inlined.
While here, fix comment of #endif.
Reviewed by: kib
|
| 298068 |
15-Apr-2016 |
andrew |
Rename ARM_INTRNG and MIPS_INTRNG to INTRNG. This will help with machine
independent code that needs to know about INTRNG such as PCI drivers.
Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
|
| 297539 |
04-Apr-2016 |
skra |
Remove FDT specific parts from INTRNG. Change its interface to make it
universal.
(1) New struct intr_map_data is defined as a container for arbitrary
description of an interrupt used by a device. Typically, an interrupt
number and configuration relevant to an interrupt controller is encoded
in such description. However, any additional information may be encoded
too like a set of cpus on which an interrupt should be enabled or vendor
specific data needed for setup of an interrupt in controller. The struct
intr_map_data itself is meant to be opaque for INTRNG.
(2) An intr_map_irq() function is created which takes an interrupt
controller identification and struct intr_map_data as arguments and
returns global interrupt number which identifies an interrupt.
(3) A set of functions to be used by bus drivers is created as well as
a corresponding set of methods for interrupt controller drivers. These
sets take both struct resource and struct intr_map_data as one of the
arguments. There is a goal to keep struct intr_map_data in struct
resource, however, this way a final solution is not limited to that.
(4) Other small changes are done to reflect new situation.
This is only first step aiming to create stable interface for interrupt
controller drivers. Thus, some temporary solution is taken. Interrupt
descriptions for devices are stored in INTRNG and two specific mapping
function are created to be temporary used by bus drivers. That's why
the struct intr_map_data is not opaque for INTRNG now. This temporary
solution will be replaced by final one in next step.
Differential Revision: https://reviews.freebsd.org/D5730
|
| 297285 |
26-Mar-2016 |
mmel |
ARM: Fix ATAG handling in LINUX_BOOT_API:
- Don't convert atags address passed from U-Boot. It's real physical
address (and we have 1:1 mapping).
- Size of tags is encoded in words, not in bytes
|
| 297284 |
26-Mar-2016 |
mmel |
ARM: Teach LINUX_BOOT_ABI to recognize DT blob.
This allow us to boot FreeBSD kernel (using uImage encapsulation) directly
from U-boot using 'bootm' command or by Android fastboot loader.
For now, kernel uImage must be marked as Linux, but we can add support for
FreeBSD into U-Boot later.
|
| 297230 |
24-Mar-2016 |
skra |
Generalize IPI support for ARM intrng and use it for interrupt
controller IPI provider.
New struct intr_ipi is defined which keeps all info about an IPI:
its name, counter, send and dispatch methods. Generic intr_ipi_setup(),
intr_ipi_send() and intr_ipi_dispatch() functions are implemented.
An IPI provider must implement two functions:
(1) an intr_ipi_send_t function which is able to send an IPI,
(2) a setup function which initializes itself for an IPI and
calls intr_ipi_setup() with appropriate arguments.
Differential Revision: https://reviews.freebsd.org/D5700
|
| 296138 |
27-Feb-2016 |
skra |
Move IPI related parts back to (ARM) machine specific file now, when
the interrupt framework is also going to be used by another (MIPS)
architecture. IPI implementations may vary much across different
architectures.
An IPI implementation should still define INTR_IPI_COUNT and use
intr_ipi_setup_counters() to setup IPI counters which are inside of
intrcnt[] and intrnames[] arrays. Those are used for sysctl and ddb.
Then, intr_ipi_increment_count() should be used to increment obtained
counter.
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D5459
|
| 296100 |
26-Feb-2016 |
andrew |
Almost all copies of platform_mp_init_secondary just called
intr_pic_init_secondary. Replace them with a direct call. On BCM2836
and ARMADA XP we need to add this function, but it can be empty.
Reviewed by: ian, imp
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D5460
|
| 296098 |
26-Feb-2016 |
andrew |
Remove platform_mp_probe as it's almost identical on most ARM SoCs, and
slightly wrong on the others. We should just check if mp_ncpus is set to
more than one CPU as we may wish to run on a single core even when SMP is
available.
Reviewed by: ian
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D5458
|
| 296066 |
25-Feb-2016 |
andrew |
Remove platform_ipi_send, it's an unneeded as all implementations are
identical.
Sponsored by: ABT Systems Ltd
|
| 295920 |
23-Feb-2016 |
skra |
Remove redundant __ARM_ARCH >= 6 check in armv6 specific files.
|
| 295803 |
19-Feb-2016 |
skra |
Remove not used definitions and fix some style nits.
No functional changes.
|
| 295802 |
19-Feb-2016 |
skra |
Remove AP_KRW definition not needed after r295801.
|
| 295801 |
19-Feb-2016 |
skra |
Rename pte.h to pte-v4.h and start including directly either pte-v4.h
or pte-v6.h in files which needs it.
There are quite internal definitions in pte-v4.h and pte-v6.h headers
specific for corresponding pmap implementation. These headers should be
included only in very few files and an intention is to not hide for
which implementation such files are.
Further, sys/arm/arm/elf_trampoline.c is an example of file which
uses armv4 like pmap implementation for both armv4 and armv6 platforms.
This is another reason why pte.h which includes specific header
according to __ARM_ARCH is not created.
|
| 295799 |
19-Feb-2016 |
skra |
Move common definitions from both pmap-v4.h and pmap-v6.h into pmap.h.
(1) MI interface needed for vm subsystem.
(2) MD interface created for ARM architecture to be used in files
shared by armv4 and armv6 platforms.
|
| 295798 |
19-Feb-2016 |
skra |
Rename pmap.h to pmap-v4.h and remove pmap-v6.h include from it.
Create new pmap.h which includes specific header according to
__ARM_ARCH.
Note that <machine/pmap.h> is included from <vm/pmap.h> so one common
<machine/pmap.h> must exist.
|
| 295752 |
18-Feb-2016 |
skra |
Remove redundant ARM_L2_ADDR_BITS and L2_ADDR_BITS definitions and
replace them by primary ones where needed.
|
| 295751 |
18-Feb-2016 |
skra |
Remove redundant L2_ADDR_MASK definition and replace it by primary one.
|
| 295750 |
18-Feb-2016 |
skra |
Remove unneeded definitions after r291406. Also remove redundant and
not used L1_ADDR_BITS definition.
|
| 295703 |
17-Feb-2016 |
skra |
Do not use PMAP_DOMAIN_KERNEL definition for __ARM_ARCH >= 6 as domains
are not utilized there. Only domain #0 is used and there is no reference
to it in the whole pmap-v6.c. Thus initialize domain access register in
locore-v6.c without reference too.
|
| 295696 |
17-Feb-2016 |
skra |
Remove unneeded vector_page_setprot() for __ARM_ARCH >= 6. A vector
page is always mapped in KVA space and so it's always writeable.
|
| 295695 |
17-Feb-2016 |
skra |
Include pte-v6.h only where needed.
|
| 295694 |
17-Feb-2016 |
skra |
Remove pd_prot and pd_cache members from struct arm_devmap_entry.
The struct is used for definition of static device mappings which
should always have same protection and attributes.
|
| 295459 |
10-Feb-2016 |
adrian |
Break out the shared bits of the arm intrng definitions into sys/intr.h;
leave the machine dependent bits in sys/arm/.
This is in preparation for MIPS INTRNG work.
Submitted by: Stanislav Galabov <sgalabov@gmail.com>
|
| 295319 |
05-Feb-2016 |
mmel |
ARM: Use new ARMv6 naming conventions for cache and TLB functions
in all but ARMv4 specific files.
Expand ARMv6 compatibility stubs in cpu-v4.h. Use physical address
in L2 cache functions if ARM_L2_PIPT is defined.
|
| 295315 |
05-Feb-2016 |
mmel |
ARM: Introduce new cpu-v4.h header and move all ARMv4 specific code
from cpu-v6.h to it.
Remove unneeded cpu-v6.h includes.
|
| 295257 |
04-Feb-2016 |
skra |
Make VM_MEMATTR_xxx definitions independent on pmap internals
for __ARM_ARCH >= 6.
It's TEX class number now, so it still has some meaning.
|
| 295252 |
04-Feb-2016 |
mmel |
ARM: Don't use ugly (and hidden) global variable, control register is
readable at any time.
|
| 295213 |
03-Feb-2016 |
mmel |
ARM: Consistently use cpu_setttb() instead of setttb().
Remove unused #define for drain_writebuf.
|
| 295207 |
03-Feb-2016 |
mmel |
ARM: Replace only once used cpu_icache_sync_all() by ranged equivalent.
Remove it from cpu_functions table.
|
| 295206 |
03-Feb-2016 |
skra |
Partly revert r295168 and define PTE_DEVICE in pmap-v6.h header again.
It turned out that devmap.c is not only file in which PTE_DEVICE
is used and simultaneously, built for both armv4 and armv6 platforms.
When I tried to build all arm kernels before r295168 commit, it was
hid by some other local changes in my tree. I hope that this is just
temporary workaround before VM_MEMATTR_DEVICE could be used instead of
PTE_DEVICE outside of pmap code for __ARM_ARCH < 6.
|
| 295200 |
03-Feb-2016 |
mmel |
ARM: Remove support for xscale i80219 and i80321 CPUs. We haven't single
supported config/board with these CPUs.
|
| 295168 |
02-Feb-2016 |
skra |
Use pmap_preboot_map_attr() directly in arm_devmap_bootstrap()
instead of hiding behind pmap_map_chunk(). It's not longer needed
after old pmap-v6 code was removed.
For compatibility with __ARM_ARCH < 6, define PTE_DEVICE in devmap.c
file. Certainly, it would be nice if VM_MEMATTR_DEVICE could be used
even for __ARM_ARCH < 6.
|
| 295166 |
02-Feb-2016 |
skra |
Make pmap_preboot_map_attr() vm subsystem compliant, so its arguments
do not depend on pmap internals. This is a preparation for hiding
internal pmap definitions as much as possible from the rest of system.
Simultaneously, the protection argument evaluation is fixed. Happily,
it did not effect the mappings. And it's the reason why it was not fixed
earlier.
|
| 295149 |
02-Feb-2016 |
mmel |
ARM: All remaining functions in cpufunc_asm_arm10.S are identical with
functions in cpufunc_asm_arm9.S. Use arm9 variants and remove
cpufunc_asm_arm10.S completly.
|
| 295145 |
02-Feb-2016 |
mmel |
ARM: Remove last unused function, cpu_flush_prefetchbuf(),
from cpu_functions table.
|
| 295143 |
02-Feb-2016 |
skra |
Remove all remaining references to old and not more used struct
pmap_devmap, pmap_devmap_bootstrap() and pmap_devmap[]. It was
replaced in r257660.
|
| 295129 |
01-Feb-2016 |
skra |
Remove all stuff related to __ARM_ARCH >= 6 from pmap.h header except
for <machine/pmap-v6.h> include. It was used by old pmap-v6 code.
|
| 295122 |
01-Feb-2016 |
mmel |
ARM: Remove never used cpu_tlb_flushI and cpu_tlb_flushI_SE() functions
and their implementations.
|
| 295096 |
31-Jan-2016 |
mmel |
ARM: cpufunc_domains, cpufunc_faultstatus and cpufunc_faultaddress
functions are equal for all ARM variants. Remove them from cpu_functions
table.
|
| 295095 |
31-Jan-2016 |
mmel |
ARM: Next round of cpufunc.* cleaning. Nobody uses flush_brnchtgt* functions,
delete them.
|
| 295092 |
31-Jan-2016 |
mmel |
ARM: First round of cpufunc.* cleaning. All abort_fixup functions are
not currently used or defined. Delete them.
|
| 295091 |
31-Jan-2016 |
mmel |
ARM: Rename ARM specific VM_MEMATTR_WT memory attribute to standard one.
|
| 295073 |
30-Jan-2016 |
mmel |
ARM: Remove TLB IPI.
We don't support SMP on ARMv6. All ARMv7 multicore cpus already uses
hardware broadcast for TLB and cache operations.
|
| 295049 |
29-Jan-2016 |
skra |
Retire pmap_pte_init_mmu_v6() which was used by old pmap-v6.
|
| 295043 |
29-Jan-2016 |
skra |
Remove NPTEPG definition which is not used anywhere now after
introduction of new pmap dump interface (r294722). And do not
expose pt_entry_t type.
|
| 295042 |
29-Jan-2016 |
skra |
Use kernel_pmap directly instead of pmap_kernel(). The kernel_pmap is
already used for __ARM_ARCH >= 6 and so even for __ARM_ARCH < 6 on some
common places.
|
| 295036 |
29-Jan-2016 |
mmel |
ARM: remove old pmap-v6 code. The new pmap-v6 is mature enough, and
dual implementation is showstopper for major cleanup.
This patch only removes old code from tree. Cleanups will follow asap.
|
| 294987 |
28-Jan-2016 |
zbb |
SMP support for ARMv6/v7 HW watchpoints
Use per-CPU structure to store HW watchpoints registers state
for each CPU present in the system. Those registers will be restored
upon wake up from the STOP state if requested by the debug_monitor
code. The method is similar to the one introduced to AMD64.
We store all possible 16 registers for HW watchpoints
(maximum allowed by the architecture).
HW breakpoints are not maintained since they are used for single
stepping only.
Pointed out by: kib
Reviewed by: wma
No strong objections from: kib
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Obtained from: Semihalf
Sponsored by: Juniper Networks Inc.
Differential Revision: https://reviews.freebsd.org/D4338
|
| 294754 |
25-Jan-2016 |
andrew |
Allow us to be told about memory past the first 4GB point, but ignore it.
This allows, for example, UEFI pass a memory map with some ram in this
region, but for us to ignore it. This is the case when running under the
qemu virt machine type.
Sponsored by: ABT Systems Ltd
|
| 294740 |
25-Jan-2016 |
zbb |
Introduce support for HW watchpoints and single stepping for ARMv6/v7
Allows for using hardware watchpoints for 1, 2, 4, 8 byte long addresses.
The default configuration of watchpoint is RW but code allows to select
RO or WO and X.
Since debugging registers are per-CPU (CP14) the watchpoint is set on
the CPU that was lucky (or not) to enter DDB.
HW breakpoints are used to perform single step in KDB.
When HW breakpoint is enabled all watchpoints are temporary disabled
to avoid recursive abort on both watchpoint and breakpoint.
In case of branch, the breakpoint is set to both - next instruction
and possible branch address. This requires at least 2 breakpoints
supported in the CPU however this is a must for ARMv6/v7 CPUs.
Reviewed by: imp
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Obtained from: Semihalf
Sponsored by: Juniper Networks Inc.
Differential Revision: https://reviews.freebsd.org/D4037
|
| 294722 |
25-Jan-2016 |
skra |
Create new pmap dump interface for minidump and use it for existing
pmap implementations on ARM. This way minidump code can be used without
any platform specific modification.
Also, this is the last piece missing for ARM_NEW_PMAP.
Differential Revision: https://reviews.freebsd.org/D5023
|
| 294138 |
16-Jan-2016 |
andrew |
Use __ARM_ARCH to decide when ARM_TP_ADDRESS needs to be set. This fixes
an issue with clang 3.8.0 where none of the __ARM_ARCH_*__ macros were
defined on some ARMv6 kernel configs.
Sponsored by: ABT Systems Ltd
|
| 294098 |
15-Jan-2016 |
skra |
Add mmu format info into ARM vmcore.
Fix kvatop translation for 64K pages.
Reviewed by: jhb
Approved by: kib (mentor)
Differential Revision: https://reviews.freebsd.org/D4942
|
| 292555 |
21-Dec-2015 |
ian |
Implement OF_decode_addr() for arm. Move most of powerpc's implementation
into a new function that other platforms can share.
This creates a new ofw_reg_to_paddr() function (in a new ofw_subr.c file)
that contains most of the existing ppc implementation, mostly unchanged.
The ppc code now calls the new MI code from the MD code, then creates a
ppc-specific bus_space mapping from the results. The new arm implementation
does the same in an arm-specific way.
This also moves the declaration of OF_decode_addr() from ofw_machdep.h to
openfirm.h, except on sparc64 which uses a different function signature.
This will help all FDT platforms to set up early console access using
OF_decode_addr().
|
| 292426 |
18-Dec-2015 |
adrian |
[intrng] Migrate the intrng code from sys/arm/arm to sys/kern/subr_intr.c.
The ci20 port (by kan@) is going to reuse almost all of the intrng code
since the SoC in question looks suspiciously like someone took an ARM
SoC design and replaced the ARM core with a MIPS core.
* migrate out the code;
* rename ARM_ -> INTR_;
* rename arm_ -> intr_;
* move the interrupt flush routine from intr.c / intrng.c into
arm/machdep_intr.c - removing the code duplication and removing
the ARM specific bits from here.
Thanks to the Star Wars: The Force Awakens premiere line for allowing
me a couple hours of quiet time to finish the universe builds.
Tested:
* make universe
TODO:
* The structure definitions in subr_intr.c still includes machine/intr.h
which requires one duplicates all of the intrng definitions in
the platform code (which kan has done, and I think we don't have to.)
Instead I should break out the generic things (function declarations,
common intr structures, etc) into a separate header.
* Kan has requested I make the PIC based IPI stuff optional.
|
| 292276 |
15-Dec-2015 |
skra |
Local TLB flush is sufficient in pmap_remove_pages().
(1) The pmap argument passed to the function must be current pmap only.
(2) The process must be single threaded as the function is called either
when a process is exiting or from exec_new_vmspace().
Remove pmap_tlb_flush_ng() which is not used anywhere now.
Approved by: kib (mentor)
|
| 292260 |
15-Dec-2015 |
mmel |
ARM: Remove outdated katelib.h.
Approved by: kib (mentor)
|
| 291937 |
07-Dec-2015 |
kib |
Add support for usermode (vdso-like) gettimeofday(2) and
clock_gettime(2) on ARMv7 and ARMv8 systems which have architectural
generic timer hardware. It is similar how the RDTSC timer is used in
userspace on x86.
Fix a permission problem where generic timer access from EL0 (or
userspace on v7) was not properly initialized on APs.
For ARMv7, mark the stack non-executable. The shared page is added for
all arms (including ARMv8 64bit), and the signal trampoline code is
moved to the page.
Reviewed by: andrew
Discussed with: emaste, mmel
Sponsored by: The FreeBSD Foundation
Differential revision: https://reviews.freebsd.org/D4209
|
| 291852 |
05-Dec-2015 |
andrew |
Move the check to see if we are tracing a function with the DTrace Function
Boundary Trace to assembly to reduce the overhead of these checks.
Submitted by: Howard Su <howard0su@gmail.com>
Relnotes: Yes
Differential Revision: https://reviews.freebsd.org/D4266
|
| 291650 |
02-Dec-2015 |
mmel |
ARM: Define PCI_RES_BUS resource for platforms having NEW_PCIB enabled.
Approved by: kib (mentor)
|
| 291492 |
30-Nov-2015 |
mmel |
ARM: create new memory attribute for writethrough cacheable memory.
- add new TEX class for WT cacheable memory
- export new TEX class to kernel as VM_MEMATTR_WT attribute
- add new aliases VM_MEMATTR_WRITE_COMBINING and
VM_MEMATTR_WRITE_BACK, it's used in DRM code
Note:
Only Cortex A8 supports WT caching in HW. On rest of Cortex CPUs,
WT requests is treated as uncacheable.
Approved by: kib (mentor)
|
| 291426 |
28-Nov-2015 |
mmel |
ARM: Implement atomic_swap_int(9). It's used in DRM2 code.
Approved by: kib (mentor)
|
| 291425 |
28-Nov-2015 |
mmel |
ARM: Add support for new KRAIT 300 CPU revision.
Approved by: kib (mentor)
|
| 291258 |
24-Nov-2015 |
skra |
Flush all kernel mappings from TLB(s) in time when they are cleared.
Replace tlb_flush_local() by tlb_flush() as even not global mappings
could be fetched to TLB(s) on other cores by speculative table walk.
From OS point of view, it was not a problem as either such mappings
were not used anymore or they were flushed from TLB(s) when reused.
However, from hardware point of view, it was a problem. Not flushed
mappings could be a target for speculative reads or prefetches (which
might be quite aggresive on ARM cores). As speculative read can fill
cacheline, it can cause a real problem, when physical page is reused,
but mapped with different memory attributes.
Anyhow, it's good to have only valid mappings in TLB(s).
Approved by: kib (mentor)
|
| 291131 |
21-Nov-2015 |
andrew |
Limit arm_base_bs_tag to ARMv4 and ARMv5, we only used it in one place in
armv6 and that can use fdtbus_bs_tag.
|
| 290979 |
17-Nov-2015 |
zbb |
Make PCB structure binary compatible for old and new PMAP on ARM
This structure must be binary compatible regardless of PMAP
version being used. Create reserved section for NEW_PMAP to
make other variables be placed exactly in the same memory
addresses. This fixes kgdb/gdb behavoiur, which uses pcb.h stuctures.
The NEW_PMAP is kernel flag, so it does not propagate to the buildworld,
what makes the tools using pcb.h unable to parse PCB data.
Reviewed by: mmel, kib
Submitted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf
Sponsored by: Juniper Networks Inc.
Differential Revision: https://reviews.freebsd.org/D4011
|
| 290974 |
17-Nov-2015 |
andrew |
Make pl310_print_config static, it's not called out of pl310.c
Sponsored by: ABT Systems Ltd
|
| 290661 |
10-Nov-2015 |
mmel |
ARM: Refactor interrupt_enable/disable/restore.
Allow manipulation with PSR_A bit on ARMv6+.
Remove declaration of unused functions.
This effectively enables asynchronous aborts on early bootstrap stage,
which previously was not enabled due to an error in enable_interrupts().
PR: 201434
Reported by: Gregory Soutade <soutade at gmail.com>
Approved by: kib (mentor)
|
| 290656 |
10-Nov-2015 |
skra |
Fix cp15 PAR definition and function. While here, add cp15 ATS1CPW
function which checks an address for privileged (PL1) write access.
The function is inlined so it does not bring any cost, but makes
function set for checking privileged access complete.
Approved by: kib (mentor)
|
| 290649 |
10-Nov-2015 |
kib |
Implement atomic_testandset_{32,int,long,64} for ARMv6. Only
little-endian configuration for 64-bit variant is supported.
Reviewed by: mmel
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D4113
|
| 290648 |
10-Nov-2015 |
mmel |
ARM: Remove trailing whitespace from sys/arm/include
No functional changes.
Approved by: kib (mentor)
|
| 290614 |
09-Nov-2015 |
bz |
Now that the PMU implementation is independent of HWPMC
as of r288992 use it to manage the CCNT.
Use the CNNT for get_cyclecount() instead of binuptime() when device pmu
is compiled in; if it fails to attach, fall back to the former method.
Enable by default for the BeagleBoneBlack configuration.
Optained from: Cambridge/L41
Sponsored by: DARPA/AFRL
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D3837
|
| 290541 |
08-Nov-2015 |
skra |
Make usermode variable the bool type. It's already used that way.
Suggested by: kib
Approved by: kib (mentor)
|
| 290369 |
04-Nov-2015 |
skra |
Fix comment about unpriviledged instructions. Now, it matches with
current state after r289372.
While here, do some style and comment cleanups. No functional changes.
Approved by: kib (mentor)
|
| 290309 |
02-Nov-2015 |
ian |
Eliminate the last dregs of the old global arm_root_dma_tag.
In the old days, device drivers passed NULL for the parent tag when creating
a new tag, and on arm platforms that resulted in a global tag representing
overall platform constraints being substituted in the busdma code. Now all
drivers use bus_get_dma_tag() and if there is a need to represent overall
platform constraints they will be inherited from a tag supplied by nexus or
some bus driver in the hierarchy.
The only arm platforms still relying on the old global-tag scheme were some
xscale boards with special PCI-bus constraints. This change provides those
constraints through a tag supplied by the xscale PCI bus driver, and
eliminates the few remaining references to the old global var.
Reviewed by: cognet
|
| 290273 |
02-Nov-2015 |
zbb |
Add support for branch instruction on armv7 with ptrace single step
Previous code supported only "continuous" code without any kind of
branch instructions. To change that, new function was implemented
which parses current instruction and returns an addres where
the jump might happen (alternative addr).
mdthread structure was extended to support two breakpoints
(one directly below current instruction and the second placed
at the alternative location).
One of them must trigger regardless the instruction has or has not been
executed due to condition field.
Upon cleanup, both software breakpoints are removed.
This implementation parses only the most common instructions
that are present in the code (like 99.99% of all), but there
is a chance there are some left, not covered by the parsing routine.
Parsing is done only for 32-bit instruction, no Thumb nor Thumb-2
support is provided.
Reviewed by: kib
Submitted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf
Sponsored by: Juniper Networks Inc.
Differential Revision: https://reviews.freebsd.org/D4021
|
| 290243 |
01-Nov-2015 |
gonzo |
Treat synchronous VFP exception just like aynchronous: as an FP exception,
not as illegal instruction
|
| 290120 |
28-Oct-2015 |
jah |
Retire pmap_dmap_iscurrent(). It is only a wrapper around pmap_is_current(), and is no longer called.
|
| 289892 |
24-Oct-2015 |
ian |
Provide armv4/v5 implementations of several of the armv6 cache maintenance
functions. This will make it possible to use the same busdma code for all
arm platforms v4 thru v7.
|
| 289887 |
24-Oct-2015 |
ian |
Rename dcache_dma_preread() to dcache_inv_poc_dma() to make it clear that it
is a dcache invalidate to point of coherency just like dcache_inv_poc(), but
a slightly different version specific to dma operations. Elaborate the
comment about how and why it's different.
|
| 289759 |
22-Oct-2015 |
jah |
Use pmap_quick* functions in armv6 busdma, for bounce buffers and cache maintenance. This makes it safe to sync buffers that have no VA mapping associated with the busdma map, but may have other mappings, possibly on different CPUs. This also makes it safe to sync unmapped bounce buffers in non-sleepable thread contexts.
Similar to r286787 for x86, this treats userspace buffers the same as unmapped buffers and no longer borrows the UVA for sync operations.
Submitted by: Svatopluk Kraus <onwahe@gmail.com> (earlier revision)
Tested by: Svatopluk Kraus
Differential Revision: https://reviews.freebsd.org/D3869
|
| 289602 |
19-Oct-2015 |
ian |
Set the correct values in the arm aux control register, based on chip type.
The bits in the aux control register vary based on the processor type. In
the past we've always just set the 'smp' and "broadcast tlb/cache ops' bits,
which worked fine for the first few SoCs we supported. Now that we support
most of the cortex-a series processors, it's important to get the right bits
set based on the processor type.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>
|
| 289548 |
18-Oct-2015 |
ian |
Only decode fdt data which belongs to the GIC controller.
The interrupts-extended property is a list of controller-specific
interrupt tuples for more than one controller. The decode routine of
every PIC gets called in the pre-INTRNG code (nexus doesn't know which
device instance belongs to which fdt node), so the GIC code has to
check each FDT node it is asked to decode to ensure it is the owner.
Because in the pre-INTRNG world there can only be one instance of a GIC,
it's safe to cache the results of a positive lookup in a static variable
to avoid the expensive lookups on subsequent calls.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>
Differential Revision: https://reviews.freebsd.org/D2345
|
| 289529 |
18-Oct-2015 |
ian |
Import ARM_INTRNG, the "next generation" interrupt architecture for arm
and armv6 architecures. The primary enhancement over the old design is
support for hierarchical interrupt controllers (such as a gpio driver
which can receive interrupts from a root PIC and act as a PIC itself for
clients interested in handling a change of gpio pin state as an
interrupt). The new code also provides an infrastructure for mapping
interrupts described in metadata in the form of a "controller reference
plus interrupt number" tuple into the simple "0-n" flat numeric space
understood by rman and the bus resource mechanisms.
Use of the new code is enabled by setting the ARM_INTRNG option, and by
making a few simple changes to the platform's support code. In addition
each existing PIC driver needs changes to be ready for INTRNG; this commit
contains the changes for the arm/gic driver, which most armv6 SoCs use, but
it does not enable the new code yet on any platform.
This project has been many years in the making, starting as a GSoC project
by Jakub Klama (jceel@) in 2012. That didn't get committed right away and
the source base evolved out from under it to some degree. In 2014 I rebased
the diffs to then -current and did some enhancements in the area of mapping
interrupt numbers and storing associated fdt data, then the project went
cold again for a while. Eventually Svata Kraus took that work in progress
and did another big round of work on it, removing most of the remaining
rough edges. Finally I took that and made one more pass through it, mostly
disabling the "INTR_SOLO" feature for now, pending further design
discussions on how to most efficiently dispatch a pending interrupt through
more than one layer of PIC. The current code with the INTR_SOLO feature
disabled uses approximate 100 extra cpu cycles for each cascaded PIC the
interrupt has to be passed to, so what's left to do is about efficiency, not
correct operation.
Differential Revision: https://reviews.freebsd.org/D2047
|
| 289522 |
18-Oct-2015 |
ian |
Rename arm_init_secondary_ic() -> arm_pic_init_secondary(). The latter is
the name the function will have when the new ARM_INTRNG code is integrated,
and doing this rename first will make it easier to toggle the new interrupt
handling code on/off with a config option for debugging.
|
| 289372 |
15-Oct-2015 |
kib |
ARM userspace accessors, e.g. {s,f}uword(9), copy{in,out}(9),
casuword(9) and others, use LDRT and STRT instructions to access
memory with the privileges of userspace. If the *RT instruction
faults on the kernel address, then additional checks must be done to
not confuse the VM system with invalid kernel-mode faults.
Put ARM on line with other FreeBSD architectures and disallow usermode
buffers which intersect with the kernel address space in advance,
before any accesses are performed. In other words, vm_fault(9) is no
longer called when e.g. suword(9) stores to invalid (i.e. not
userspace) address.
Also, switch ARM to use fueword(9) and casueword(9).
Note: there is a pending patch in D3617, which adds the special
processing for faults from LDRT and STRT. The addition of the
processing is useful for potential other uses of the instructions and
for completeness, but standard userspace accessors are better served
by not allowing such faults beforehand.
Reviewed by: andrew
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D3816
MFC after: 2 weeks
|
| 288983 |
07-Oct-2015 |
kib |
A follow-up to r288492. In fact, revert the mentioned commit for
pre-VFPv3 processors, since they do require software support code to
handle denormals. For VFPv3 and later, enable flush-to-zero if
hardware does not claim full denormals arithmetic support by VMVFR1_FZ
field in mvfr1 register.
The end result is that we do use correct fpu environment on Cortexes
with VFPv3, while ARM11 (e.g. rpi) is in non-compliant flush-to-zero
mode. At least CPUs without complete hardware implementation of
IEEE 754 do not cause unhandled floating point exception on underflow,
as it was before r288492.
Noted by: ian
Tested by: gjb
Sponsored by: The FreeBSD Foundation
MFC after: 1 week
|
| 288662 |
04-Oct-2015 |
rwatson |
Add missing stack unwind information to several assembly functions on
ARMv6/7:
- Define _SAVE() macro to allow unwind data to be conditionally defined for
ARM assembly code in the kernel.
- Use _SAVE() to provide unwind information for bcopy_page(), and two (of
many) instances of copyin() and copyout().
Reviewed by: andrew, imp
MFC after: 3 days
Sponsored by: University of Cambridge
|
| 288491 |
02-Oct-2015 |
kib |
FreeBSD does not support SMP on ARMv5. Since processor is always
self-consistent, there is no need in anything but compiler barrier in
the implementation of atomic_thread_fence_*() on ARMv5. Split
implementation of fences for ARMv4/5 and ARMv6; the former use
compiler barriers, the later also perform hardware barriers.
An issue which is fixed by the change is the faults from the CP15
coprocessor accesses in the user mode. This was uncovered by the
pthread_once() changes in r287556.
Reported by: Mattia Rossi <mattia.rossi.mailinglists@gmail.com>
Discussed with: alc, cognet, jhb
Sponsored by: The FreeBSD Foundation
MFC after: 1 week
|
| 286960 |
20-Aug-2015 |
kib |
Typo.
|
| 286725 |
13-Aug-2015 |
marcel |
The Broadcom BCM56060 chip has a Cortex-A9R4 core.
Submitted by: Steve Kiernan <stevek@juniper.net>
Reviewed by: imp@
Differential Revision: https://reviews.freebsd.org/D3357
|
| 286584 |
10-Aug-2015 |
kib |
Make kstack_pages a tunable on arm, x86, and powepc. On i386, the
initial thread stack is not adjusted by the tunable, the stack is
allocated too early to get access to the kernel environment. See
TD0_KSTACK_PAGES for the thread0 stack sizing on i386.
The tunable was tested on x86 only. From the visual inspection, it
seems that it might work on arm and powerpc. The arm
USPACE_SVC_STACK_TOP and powerpc USPACE macros seems to be already
incorrect for the threads with non-default kstack size. I only
changed the macros to use variable instead of constant, since I cannot
test.
On arm64, mips and sparc64, some static data structures are sized by
KSTACK_PAGES, so the tunable is disabled.
Sponsored by: The FreeBSD Foundation
MFC after: 2 week
|
| 286327 |
05-Aug-2015 |
emaste |
Rationalize BSD license on sys/*/include/float.h
Remove the advertising clause from the Regents of the University of
California's license, per the letter dated July 22, 1999.
Update clause numbering.
|
| 286296 |
04-Aug-2015 |
jah |
Add two new pmap functions:
vm_offset_t pmap_quick_enter_page(vm_page_t m)
void pmap_quick_remove_page(vm_offset_t kva)
These will create and destroy a temporary, CPU-local KVA mapping of a specified page.
Guarantees:
--Will not sleep and will not fail.
--Safe to call under a non-sleepable lock or from an ithread
Restrictions:
--Not guaranteed to be safe to call from an interrupt filter or under a spin mutex on all platforms
--Current implementation does not guarantee more than one page of mapping space across all platforms. MI code should not make nested calls to pmap_quick_enter_page.
--MI code should not perform locking while holding onto a mapping created by pmap_quick_enter_page
The idea is to use this in busdma, for bounce buffer copies as well as virtually-indexed cache maintenance on mips and arm.
NOTE: the non-i386, non-amd64 implementations of these functions still need review and testing.
Reviewed by: kib
Approved by: kib (mentor)
Differential Revision: http://reviews.freebsd.org/D3013
|
| 285694 |
19-Jul-2015 |
andrew |
Fix atomic_store_64, it should write the value passed in, not the value
read by the load.
Pointy Hat: andrew
|
| 285689 |
19-Jul-2015 |
andrew |
Clean up the style of the armv6 atomic code.
Sponsored by: ABT Systems Ltd
|
| 285687 |
19-Jul-2015 |
andrew |
Sort the ARM atomic functions to be in alphabetical order.
Sponsored by: ABT Systems Ltd
|
| 285631 |
16-Jul-2015 |
andrew |
Split out the arm and armv6 parts of atomic.h to new files. While here use
__ARM_ARCH to determine which revision of the architecture is applicable.
Sponsored by: ABT Systems Ltd
|
| 285283 |
08-Jul-2015 |
kib |
Add the atomic_thread_fence() family of functions with intent to
provide a semantic defined by the C11 fences with corresponding
memory_order.
atomic_thread_fence_acq() gives r | r, w, where r and w are read and
write accesses, and | denotes the fence itself.
atomic_thread_fence_rel() is r, w | w.
atomic_thread_fence_acq_rel() is the combination of the acquire and
release in single operation. Note that reads after the acq+rel fence
could be made visible before writes preceeding the fence.
atomic_thread_fence_seq_cst() orders all accesses before/after the
fence, and the fence itself is globally ordered against other
sequentially consistent atomic operations.
Reviewed by: alc
Discussed with: bde
Sponsored by: The FreeBSD Foundation
MFC after: 3 weeks
|
| 284265 |
11-Jun-2015 |
andrew |
Stop using VFP in pcpu.h when we mean ARMv6 and later.
|
| 284147 |
08-Jun-2015 |
alc |
Retire VM_FREEPOOL_CACHE as the next step in eliminating PG_CACHE pages.
Differential Revision: https://reviews.freebsd.org/D2712
Reviewed by: kib
Sponsored by: EMC / Isilon Storage Division
|
| 284109 |
07-Jun-2015 |
andrew |
Remove pc_cpu, it was duplicating pc_cpuid so was unneeded.
|
| 283812 |
31-May-2015 |
andrew |
We only support the ARM EABI in head, remove the check on __ARM_EABI__.
|
| 283365 |
24-May-2015 |
andrew |
Add more cp15_ functions, and use them in cpufunc.c where possible.
|
| 283297 |
22-May-2015 |
imp |
Export the eflags field from the elf header. This allows better
discrimination between different subarch binaries, at least for mips
and arm. Arm is implemented, mips is still tbd, so not currently
exported. aarch64 does not export this because aarch64 binaries use
different tags and flags than arm.
Differential Revision: https://reviews.freebsd.org/D2611
|
| 283034 |
17-May-2015 |
andrew |
Clean up struct syscall_args:
1. Align to a 64-bit address so 64-bit data will be correctly aligned.
2. Add a comment explaining why.
3. Remove an unneeded value from the struct.
This fixes an issue where the struct may not be correctly aligned on the
stack in the syscall function. This may lead to accesing a 64-bit value
at a non 64-bit. This will raise an exception and panic the kernel.
We have been lucky where on arm and armv6 both clang and gcc correctly
align the data, even without us asking to, however, on armeb with clang to
not be the case. This tells the compiler we really do need this to be
aligned.
Reported and tested by: jmg (on armeb with clang)
MFC after: 1 Week [1, 2]
|
| 282984 |
15-May-2015 |
ian |
Add assertions that the addresses passed to tlb maintenance are page-aligned.
Perform cache writebacks and invalidations in the correct (inner to outer
or vice versa) order, and add comments that explain that.
Consistantly use 'va' as the variable name for virtual addresses.
Submitted by: Michal Meloun <meloun@miracle.cz>
|
| 282934 |
15-May-2015 |
ganbold |
It appears to be armv7_sleep is a duplication of armv7_cpu_sleep.
For consistency with the naming conventions used by the other
implementations kill armv7_sleep and keep armv7_cpu_sleep.
Differential Revision: https://reviews.freebsd.org/D2537
Submitted by: John Wehle
Reviewed by: ian@, andrew@
|
| 282780 |
11-May-2015 |
alc |
Retire pmap_lazyfix(). This function only existed in the new armv6 pmap
because the i386 pmap on which the new armv6 pmap is based had it, and in
r281707 pmap_lazyfix() was removed from the i386 pmap.
Discussed with: kib
Submitted by: Michal Meloun (via Svatopluk Kraus)
|
| 282778 |
11-May-2015 |
andrew |
Mark thumb entry points as such when building for thumb, otherwise mark
them as arm.
|
| 282777 |
11-May-2015 |
andrew |
Use the Thumb compliant version of the add instruction. We can only use
"add Rd, Rn, Rm" from within an IT (if-then) block.
|
| 282776 |
11-May-2015 |
andrew |
List both registers to use in the 64-bit atomic instructions. We will need
these to build for Thumb-2.
|
| 282767 |
11-May-2015 |
andrew |
cpu-v6.h should only be used in the kernel, add an error to enforce this.
|
| 282586 |
07-May-2015 |
emaste |
Correct PL310_POWER_CTRL offset
Offet for the power control register was specified incorrectly (it had
the same value as the prefetch control register.) This change corrects
the offset value to 0xF80, per the ARM PL310 documentation.
Submitted by: Steve Kiernan <stevek@juniper.net>
Obtained from: Juniper Networks, Inc.
|
| 282547 |
06-May-2015 |
zbb |
Add new CP15 operations and DB_SHOW_COMMAND to print CP15 registers
Submitted by: Wojciech Macek <wma@semihalf.com>
Reviewed by: imp, Michal Meloun <meloun@miracle.cz>
Obtained from: Semihalf
|
| 281369 |
10-Apr-2015 |
ian |
Add a pmap_kremove_device() to undo mappings made with pmap_kenter_device().
Previously we used pmap_kremove(), but with ARM_NEW_PMAP it does the remove
in a way that isn't SMP-coherent (which is appropriate in some circumstances
such as mapping/unmapping sf buffers). With matching enter/remove routines
for device mappings, each low-level implementation can do the right thing.
Reviewed by: Svatopluk Kraus <onwahe@gmail.com>
|
| 281156 |
06-Apr-2015 |
andrew |
Add support to the efi boot1 and loader for 32-bit ARM. This will be used
by the future qemu virt support.
Differential Revision: https://reviews.freebsd.org/D2238
Reviewed by: emaste
|
| 281106 |
05-Apr-2015 |
andrew |
dev/ofw/openfirm.h is not needed in the arm machine/fdt.h
|
| 281093 |
04-Apr-2015 |
andrew |
Re-add machine/bus.h to machine/fdt.h on arm, it's still needed.
|
| 281089 |
04-Apr-2015 |
andrew |
Don't include unneeded files in the arm machine/fdt.h. While here, remove
it from more files.
|
| 281087 |
04-Apr-2015 |
andrew |
Move the definition of fdt_localbus_devmap to a Marvell specific file as
it's only used there.
|
| 280985 |
02-Apr-2015 |
andrew |
Add the generic timer registers to sysreg.h and cpu-v6.h, and use the
access functions in the generic timer driver.
Differential Revision: https://reviews.freebsd.org/D2198
Sponsored by: The FreeBSD Foundation
|
| 280847 |
30-Mar-2015 |
andrew |
Remove support for CPU_XSCALE_80200. None of our configs support it, and
there wasn;t an option to enable it.
While here remove a check for CPU_ARM10 being defined as it has also been
removed.
|
| 280842 |
30-Mar-2015 |
andrew |
Remove support for CPU_FA626TE. It's unused by any of our kernel configs.
|
| 280832 |
29-Mar-2015 |
andrew |
pj4b_config and pj4bv7_setup are only used when CPU_MV_PJ4B is defined.
|
| 280824 |
29-Mar-2015 |
andrew |
Remove arm1136 support. We don't have any configs that use it, and I don't
expect us to add support for any more arm11 SoCs.
|
| 280823 |
29-Mar-2015 |
andrew |
Remove the bootconfig parsing. We never used it and always passed either an
empty string or NULL to the setup functions that called into it.
|
| 280817 |
29-Mar-2015 |
andrew |
Remove ARM9_CACHE_WRITE_THROUGH, none of our configs define it.
|
| 280813 |
29-Mar-2015 |
andrew |
Remove unused cpufunc arm11 and armv6 code. While here only define the
remaining functions in the context we use them in.
|
| 280811 |
29-Mar-2015 |
andrew |
Remove unused arm10_* functions. The remaining functions are only used in
mv configs.
|
| 280809 |
29-Mar-2015 |
andrew |
Remove support for CPU_ARM10. No kernel configs could possibly use this as
it's not an available option. Along with this we will never support this
cpu type as very few arm10 chips were made.
|
| 280737 |
27-Mar-2015 |
bz |
Rather than defining our own magic checks here use INKERNEL() for
the PMC_IN_KERNEL() macro definition.
Add missing macros to extract the return address (LR) from the trapframe.
Discussed with: andrew
Obtained from: Cambridge/L41
Sponsored by: DARPA, AFRL
MFC after: 2 weeks
|
| 280712 |
26-Mar-2015 |
ian |
New pmap code for armv6. Disabled by default, option ARM_NEW_PMAP enables it.
This is pretty much a complete rewrite based on the existing i386 code. The
patches have been circulating for a couple years and have been looked at by
plenty of people, but I'm not putting anybody on the hook as having reviewed
this in any formal sense except myself.
After this has gotten wider testing from the user community, ARM_NEW_PMAP
will become the default and various dregs of the old pmap code will be
removed.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz>
|
| 280278 |
20-Mar-2015 |
zbb |
Allow to override default kernel virtual address assignment on ARM
Each plaform performs virtual memory split between kernel and user space
and assigns kernel certain amount of memory space. However, is is sometimes
reasonable to change the default values. Such situation may happen on
systems where the demand for kernel buffers is high, many devices occupying
memory etc. This of course comes with the cost of decreasing user space
memory range so shall be used with care. Most embedded systems will not
suffer from this limtation but rather take advantage of this potential
since default behavior is left unchanged.
Submitted by: Wojciech Macek <wma@semihalf.com>
Reviewed by: imp
Obtained from: Semihalf
|
| 279944 |
13-Mar-2015 |
emaste |
Delete stray clause 3 and renumber.
|
| 279811 |
09-Mar-2015 |
ian |
Add minimum cache line sizes to struct cpuinfo, use them in the new cache
maintenance routines. Also add a routine to invalidate the branch cache.
Submitted by: Michal Meloun
|
| 279543 |
02-Mar-2015 |
ian |
Revert r279338. The casts are apparently bogus, despite the fact that
they've been working in i386 (where this change came from).
|
| 279338 |
26-Feb-2015 |
ian |
Add casting to make atomic ops work for pointers. (Apparently nobody has
ever done atomic ops on pointers before now on arm).
Submitted by: Svatopluk Kraus <onwahe@gmail.com>
|
| 279114 |
21-Feb-2015 |
ian |
Correct a comment which was exactly backwards from reality.
|
| 278996 |
19-Feb-2015 |
andrew |
Allow the ARM unwinder to work through modules. This will be used to add
support for unwinding from dtrace.
Tested by: gnn (with dtrace)
Sponsored by: ABT Systems Ltd
|
| 278895 |
17-Feb-2015 |
andrew |
Pull the ARM ddb unwind code out to a new file. This will allow it to be
used by other places that expect to unwind the stack, e.g. dtrace and
stack(9).
As I have written most of this code I'm changing the license to the
standard FreeBSD license. I have received approval from the other
developers who have changed any of the affected code.
Approved by: ian, imp, rpaulo, eadler (all license change)
|
| 278529 |
10-Feb-2015 |
gnn |
Initial version of DTrace on ARM32.
Submitted by: Howard Su based on work by Oleksandr Tymoshenko
Reviewed by: ian, andrew, rpaulo, markj
|
| 278518 |
10-Feb-2015 |
zbb |
Resolve cache line size from CP15
Switch the cache line size during invalidations/flushes
to be read from CP15 cache type register.
Submitted by: Wojciech Macek <wma@semihalf.com>
Reviewed by: ian, imp
Obtained from: Semihalf
|
| 277998 |
31-Jan-2015 |
andrew |
Stop using load-multiple with lr and pc. This has been deprecated in ARMv7
and clang 3.6 warns about it. As this is used in libc and we build it with
-Werror this warning becomes an error stopping the build.
|
| 277835 |
28-Jan-2015 |
br |
Add ARMv7 performance monitoring counters.
Differential Revision: https://reviews.freebsd.org/D1687
Reviewed by: rpaulo
Sponsored by: DARPA, AFRL
|
| 277533 |
22-Jan-2015 |
ian |
Declare Maxmem on arm. This should have been part of r277532.
|
| 277512 |
21-Jan-2015 |
ian |
Micro-optimize the new arm inline bus_space implementation by grouping all
the data the inline functions access together at the start of the bus_space
struct. The start-of part isn't so important, it's the grouping-together
that's the point: now all the most-accessed data should be in one cache line.
Suggested by: cognet
|
| 277473 |
21-Jan-2015 |
ian |
The versatile platform had two copies of a bus_space that are essentially
duplicates of the standard arm base bus_space, so just use it.
|
| 277470 |
21-Jan-2015 |
ian |
Move bs_unimplemented() to bus_space_generic.c so it can be shared.
|
| 277460 |
21-Jan-2015 |
ian |
Revise the arm bus_space implementation to avoid dereferencing the tag on
every operation to retrieve the bs_cookie value almost nothing actually uses.
The bus_space struct contains a private data pointer (poorly named bs_cookie,
now renamed to bs_privdata) which is used only by a few old armv4 xscale
implementations. The bus_space functions were all defined to take this
value as the first parameter instead of the bus_space_tag_t, requiring all
the inline macro and function expansions to dereference the tag to pass it
to another function, which never uses it. Now all the functions take the tag
as the first parameter and retrieve the privdata if they need it.
Also fix a couple bus_space_unmap() implementations that were calling
kva_free() instead of pmap_unmapdev().
Discussed with: cognet
|
| 277454 |
20-Jan-2015 |
ian |
Add inline implementations of arm bus_space_read/write_N().
Reviewed by: cognet
|
| 277415 |
20-Jan-2015 |
andrew |
Add the User and PL1 read only and reqd write thread ID registers.
Sponsored by: The FreeBSD Foundation
|
| 277156 |
14-Jan-2015 |
ganbold |
Correct cpu type, it was rather Cortex A12 R0.
Approved by: stas (mentor)
|
| 277116 |
13-Jan-2015 |
ganbold |
Add CPU ID for ARM Cortex A17.
Approved by: stas (mentor)
|
| 276984 |
11-Jan-2015 |
andrew |
Rename gic_init_secondary to arm_init_secondary_ic to help with the merge
of the arm_intrng project branch.
|
| 276808 |
08-Jan-2015 |
ian |
Move the inclusion of cpu-v6.h inside the #ifdef _KERNEL block, so that
userland programs (which probably don't actually need machine/cpu.h) compile.
|
| 276803 |
08-Jan-2015 |
ian |
Add accessors for the ARM CP15 performance monitor registers. Also ensure
that some #ifdef SMP code is also conditional on __ARM_ARCH >= 7; we don't
support SMP on armv6, but some drivers and modules are compiled with it
forced on via the compiler command line.
|
| 276772 |
07-Jan-2015 |
markj |
Factor out duplicated code from dumpsys() on each architecture into generic
code in sys/kern/kern_dump.c. Most dumpsys() implementations are nearly
identical and simply redefine a number of constants and helper subroutines;
a generic implementation will make it easier to implement features around
kernel core dumps. This change does not alter any minidump code and should
have no functional impact.
PR: 193873
Differential Revision: https://reviews.freebsd.org/D904
Submitted by: Conrad Meyer <conrad.meyer@isilon.com>
Reviewed by: jhibbits (earlier version)
Sponsored by: EMC / Isilon Storage Division
|
| 276638 |
03-Jan-2015 |
ian |
Add a new trap-v6.c which has support for all armv7 exceptions. This
mostly paves the way for the new pmap code, and shouldn't result in any
noticible behavior differences.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz
|
| 276596 |
02-Jan-2015 |
ian |
Fix alignment directives in arm asm code after clang 3.5 import.
The ancient gas we've been using interprets .align 0 as align to the
minimum required alignment for the current section. Clang's integrated
assembler interprets it as align to a byte boundary. Fortunately both
assemblers interpret a non-zero value as align to 2^N so just make sure
we have appropriate non-zero values everywhere.
|
| 276539 |
02-Jan-2015 |
emaste |
Update ELF headers to include additional defines
The elftoolchain project includes these additional defines for various
userland programs. Given that arch-specific defines are still interesting
in the context of userland programs reading or writing ELF metadata, they
should be included in top-level ELF headers.
Remove duplicate defines from ARM and MIPS elf headers.
Submitted by: will (initial version)
Reviewed by: imp, will
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D844
|
| 276519 |
01-Jan-2015 |
ian |
Define a WFI macro that expands to the right form of wait-for-interrupt
depending on the architecture.
|
| 276340 |
28-Dec-2014 |
ian |
Fix a "decl is not a prototype" error noticed by gcc (but not clang).
|
| 276335 |
28-Dec-2014 |
ian |
Eliminate an unused macro whose name clashes now with a function in the
new cpu-v6.h. This should have been part of r276334.
|
| 276334 |
28-Dec-2014 |
ian |
Add new TLB and cache maintainence functions for armv6 and armv7. These
are inline functions that handle all the routine maintenance operations
except the flush-all and invalidate-all routines which are required only
during early kernel init.
These inline functions should be very much faster than the old mechanism
that involved jumping through the big cpufuncs table, especially for
common operations such as invalidating a single TLB entry. Note that
nothing is calling these yet, this just is just required infrastructure
for upcoming changes to the pmap-v6 code.
|
| 276333 |
28-Dec-2014 |
ian |
Add new code to read and parse cpu identification data using the new CPUID
mechanism defined for armv7 (and also present on some armv6 chips including
the arm1176 used on rpi). The information is parsed into a global cpuinfo
structure, which will be used by (upcoming) new cache and tlb maintenance
code to handle cpu-specific variations of the maintence sequences.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz
|
| 276247 |
26-Dec-2014 |
ian |
Include acle-compat.h directly (we use its symbols) rather than getting
it via sysreg.h.
|
| 276213 |
25-Dec-2014 |
ian |
Define only the CP15 register operations that are valid for the architecture.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz
|
| 276212 |
25-Dec-2014 |
ian |
Add macros for asm barrier instructions with arch-specific implementations.
|
| 276206 |
25-Dec-2014 |
ian |
For data and instruction prefetch aborts, call the same handler in the C
code, passing a 0/1 flag that indicates which type of abort it was. This
sets the stage for unifying the handling of page faults in a single routine.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz
|
| 276204 |
25-Dec-2014 |
ian |
Create 'L' variants of all the ENTRY macros for file-static/local symbols.
If it seems like this is getting out of hand, I quite agree. I wonder if
it's safe, here in the 21st century, to lose the distinction between C and
ASM symbols?
|
| 276203 |
25-Dec-2014 |
ian |
Fix the GLOBAL macro so it works (upper vs lowercase X), use it in _EENTRY.
|
| 276202 |
25-Dec-2014 |
ian |
Stylish changes... put tabs where they need to be in macros, move lines
around so that related things are more grouped together, rewrite comments.
No functional changes, this is all so that the functional changes in the
next commit will stand out.
|
| 276198 |
25-Dec-2014 |
ian |
Remove _PROF_PROLOGUE from the EENTRY() macros. These macros define
'extra' entry points which are nested within or provide a synonym name
for another function. It's most likely not safe to be messing with the
IP and LR registers at anything other than the primary entry point to a
function. Anywhere beyond initial function entry, those registers may
be in use as scratch or variable registers.
|
| 276190 |
24-Dec-2014 |
ian |
Cleanup up ARM *frame structures...
- Eliminate unused irqframe
- Eliminate unused saframe
- Instead of splitting r4-sp storage between the stack and switchframe,
just put all the registers in switchframe and eliminate the un_32 struct.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz>
|
| 276180 |
24-Dec-2014 |
andrew |
Rename pic_ipi_get to pic_ipi_read for intrng.
|
| 276166 |
24-Dec-2014 |
ian |
Revert a glitched mismerge that got caught up in the prior commit.
The PJ4B family is still armv7, not armv6.
|
| 276165 |
24-Dec-2014 |
ian |
Define the old-school arm arch constants we still use internally based on
the somewhat newer constants predefined by the compiler. This will allow
userland apps to use various machine/foo.h headers without CPUTYPE defined.
|
| 276032 |
21-Dec-2014 |
andrew |
Pull out the fdt mapping code into intr.c. The arm_intrng branch also
defines this function allowing the mapping method to change when we move
to it.
|
| 275378 |
01-Dec-2014 |
andrew |
Pull in the NetBSD global offset table handling code. Clang 3.5 creates
relocations the linker complains about.
Obtained from: NetBSD
MFC after: 1 Week
|
| 275264 |
29-Nov-2014 |
andrew |
Update _ENTRY to use _EENTRY to reduce the common code.
|
| 275004 |
25-Nov-2014 |
emaste |
Revert r274772: it is not valid on MIPS
Reported by: sbruno
|
| 274941 |
24-Nov-2014 |
ian |
The arm PJ4B cpu is armv7 architecture, not v6.
If this feels like deja vu... the last time this was fixed in this file
only ARM_MMU_V6 was fixed, this time it's ARM_ARCH_V6 (and this time I
searched for other occurrances of pj4b in here).
|
| 274772 |
21-Nov-2014 |
emaste |
Use canonical __PIC__ flag
It is automatically set when -fPIC is passed to the compiler.
Reviewed by: dim, kib
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D1179
|
| 274668 |
18-Nov-2014 |
imp |
opt_global.h is included automatically in the build. No need to
explicitly include it in these places.
Sponsored by: Netflix
|
| 273783 |
28-Oct-2014 |
kib |
Add fueword(9) and casueword(9) functions. They are like fuword(9)
and casuword(9), but do not mix value read and indication of fault.
I know (or remember) enough assembly to handle x86 and powerpc. For
arm, mips and sparc64, implement fueword() and casueword() as wrappers
around fuword() and casuword(), which means that the functions cannot
distinguish between -1 and fault.
On architectures where fueword() and casueword() are native, implement
fuword() and casuword() using fueword() and casuword(), to reduce
assembly code duplication.
Sponsored by: The FreeBSD Foundation
Tested by: pho
MFC after: 2 weeks (ia64 needs treating)
|
| 273251 |
18-Oct-2014 |
andrew |
Add an elf not so kgdb detects the kernel as a FreeBSD elf file. The
ELFNOTE macro is based on one from the FreeBSD/ARM Xen tree [1].
Obtained from: Julien Grall <julien.grall AT linaro.org> [1]
|
| 272766 |
08-Oct-2014 |
markj |
Pass up the error status of minidumpsys() to its callers.
PR: 193761
Submitted by: Conrad Meyer <conrad.meyer@isilon.com>
Sponsored by: EMC / Isilon Storage Division
|
| 272300 |
30-Sep-2014 |
andrew |
Make sure __ARM_ARCH is defined in sysreg.h by including acle-compat.h
|
| 272209 |
27-Sep-2014 |
andrew |
Add machine/sysreg.h to simplify accessing the system control coprocessor
registers and use it in the ARMv7 CPU functions.
The sysreg.h file has been checked by hand, however it may contain errors
with the comments on when a register was first introduced. The ARMv7 cpu
functions have been checked by compiling both the previous and this version
and comparing the md5 of the object files.
Submitted by: Svatopluk Kraus <onwahe at gmail.com>
Submitted by: Michal Meloun <meloun at miracle.cz>
Reviewed by: ian, rpaulo
Differential Revision: https://reviews.freebsd.org/D795
|
| 271601 |
14-Sep-2014 |
ian |
Add a common routine for parsing FDT data describing an ARM GIC interrupt.
In the fdt data we've written for ourselves, the interrupt properties
for GIC interrupts have just been a bare interrupt number. In standard
data that conforms to the published bindings, GIC interrupt properties
contain 3-tuples that describe the interrupt as shared vs private, the
interrupt number within the shared/private address space, and configuration
info such as level vs edge triggered.
The new gic_decode_fdt() function parses both types of data, based on the
#interrupt-cells property. Previously, each platform implemented a decode
routine and put a pointer to it into fdt_pic_table. Now they can just
list this function in their table instead if they use arm/gic.c.
|
| 271422 |
11-Sep-2014 |
andrew |
Rename pmap_kenter_temp to pmap_kenter_temporary to be consistent with the
other architectures with this function.
Submitted by: Svatopluk Kraus <onwahe at gmail.com>
Submitted by: Michal Meloun <meloun at miracle.cz>
|
| 271398 |
10-Sep-2014 |
andrew |
Unify interrupts bit definition and usage. While here remove PSR_C_bit.
Submitted by: Svatopluk Kraus <onwahe at gmail.com>,
Michal Meloun <meloun at miracle.cz>
Differential Revision: https://reviews.freebsd.org/D754
|
| 271394 |
10-Sep-2014 |
andrew |
Add more register values to armreg.h and remove CPU_CONTROL_32BP_ENABLE
from asm.h as they were already defined in armreg.h.
Submitted by: Michal Meloun <meloun at miracle.cz>
|
| 271310 |
09-Sep-2014 |
ian |
Rename new to newval in inline asm code, to avoid clashes with C++ new.
Also rename cmp to cmpval just to keep the asm variable names similar to
the C variable names.
|
| 270930 |
01-Sep-2014 |
ian |
Do not generate unwind info in asm functions if _STANDALONE is defined.
The .fnend op causes the assembler to emit RELOC references to unwind
support functions that don't exist in libstand.
|
| 270884 |
31-Aug-2014 |
br |
GIC (Cortex A's interrupt controller) supports up to 1020 IRQs.
|
| 270878 |
31-Aug-2014 |
ian |
The Marvell PJ4B cpu family is armv7, not armv6.
|
| 270123 |
18-Aug-2014 |
imp |
Expand the elf brandelf infrastructure to give access to the whole ELF
header (Elf_Ehdr) to determine if a particular interpretor wants to
accept it or not. Use this mechanism to filter EABI arm on OABI arm
kernels, and vice versa. This method could also be used to implement
OABI on EABI arm kernels, if desired, or to allow a single mips kernel
to run o32, n32 and n64 binaries.
Differential Revision: https://reviews.freebsd.org/D609
|
| 270081 |
17-Aug-2014 |
ian |
When the initarm_* routines were renamed to platform_* and moved to their
own header file, the lovely block of comments explaining what the generic
init code expects of the soc implementations got lost, restore it.
|
| 269956 |
14-Aug-2014 |
imp |
From https://sourceware.org/ml/newlib/2014/msg00113.html
By Richard Earnshaw at ARM
>
>GCC has for a number of years provides a set of pre-defined macros for
>use with determining the ISA and features of the target during
>pre-processing. However, the design was always somewhat cumbersome in
>that each new architecture revision created a new define and then
>removed the previous one. This meant that it was necessary to keep
>updating the support code simply to recognise a new architecture being
>added.
>
>The ACLE specification (ARM C Language Extentions)
>(http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.swdev/index.html)
>provides a much more suitable interface and GCC has supported this
>since gcc-4.8.
>
>This patch makes use of the ACLE pre-defines to map to the internal
>feature definitions. To support older versions of GCC a compatibility
>header is provided that maps the traditional pre-defines onto the new
>ACLE ones.
Stop using __FreeBSD_ARCH_armv6__ and switch to __ARM_ARCH >= 6 in the
couple of places in tree. clang already implements ACLE. Add a define
that says we implement version 1.1, even though the implementation
isn't quite complete.
|
| 269598 |
05-Aug-2014 |
ian |
Set the pl310 L2 cache driver to attach during the middle of BUS_PASS_CPU.
Because that's earlier than interrupts are available, set up deferred
configuration of interrupts (which are used only for debugging).
|
| 269577 |
05-Aug-2014 |
glebius |
Merge all MD sf_buf allocators into one MI, residing in kern/subr_sfbuf.c
The MD allocators were very common, however there were some minor
differencies. These differencies were all consolidated in the MI allocator,
under ifdefs. The defines from machine/vmparam.h turn on features required
for a particular machine. For details look in the comment in sys/sf_buf.h.
As result no MD code left in sys/*/*/vm_machdep.c. Some arches still have
machine/sf_buf.h, which is usually quite small.
Tested by: glebius (i386), tuexen (arm32), kevlo (arm32)
Reviewed by: kib
Sponsored by: Netflix
Sponsored by: Nginx, Inc.
|
| 269414 |
02-Aug-2014 |
ian |
When arm 64-bit atomic ops are available, define ARM_HAVE_ATOMIC64. Use
that symbol (which will be correct in both kernel and userland contexts)
rather than just __arm__ to decide whether to use a local implementation.
|
| 269406 |
01-Aug-2014 |
ian |
Use atomic_load/store_64() in the arm implementation of counter(9), and
remove the XXX comments about non-atomic access to the counters.
|
| 269405 |
01-Aug-2014 |
ian |
Add 64-bit atomic ops for armv4, only for kernel code, mostly so that we
don't need any #ifdef stuff to use atomic_load/store_64() elsewhere in
the kernel. For armv4 the atomics are trivial to implement for kernel
code (just disable interrupts), less so for user mode, so this only has
the kernel mode implementations for now.
|
| 269403 |
01-Aug-2014 |
ian |
Add 64-bit atomic ops for armv6. The only safe way to access a 64-bit
value shared across multiple cores is with atomic_load_64() and
atomic_store_64(), because the normal 64-bit load/store instructions
are not atomic on 32-bit arm. Luckily the ldrexd/strexd instructions
that are atomic are fairly cheap on armv6. Because it's fairly simple
to do, this implements all the ops for 64-bit, not just load/store.
Reviewed by: andrew, cognet
|
| 269390 |
01-Aug-2014 |
ian |
Fix unwind-info errors in our hand-written arm assembler code.
We have functions nested within functions, and places where we start a
function then never end it, we just jump to the middle of something else.
We tried to express this with nested ENTRY()/END() macros (which result
in .fnstart and .fnend directives), but it turns out there's no way to
express that nesting in ARM EHABI unwind info, and newer tools treat
multiple .fnstart directives without an intervening .fnend as an error.
These changes introduce two new macros, EENTRY() and EEND(). EENTRY()
creates a global label you can call/jump to just like ENTRY(), but it
doesn't emit a .fnstart. EEND() is a no-op that just documents the
conceptual endpoint that matches up with the same-named EENTRY().
This is based on patches submitted by Stepan Dyatkovskiy, but I made some
changes and added the EEND() stuff, so blame any problems on me.
Submitted by: Stepan Dyatkovskiy <stpworld@narod.ru>
|
| 268893 |
19-Jul-2014 |
ian |
Add dl_unwind_find_exidx() for ARM EABI, required for C++ exception
handling. For statically linked apps this uses the __exidx_start/end
symbols set up by the linker. For dynamically linked apps it finds the
shared object that contains the given address and returns the location and
size of the exidx section in that shared object.
The dl_unwind_find_exidx() name is used by other BSD projects and Android,
and is mentioned in clang 3.5 comments as "the BSD interface" for finding
exidx data. GCC (in libgcc_s) expects the exact same API and functionality
to be provided by a function named __gnu_Unwind_Find_exidx(), so we provide
that with an alias ("strong reference").
Reviewed by: kib@
MFC after: 1 week
|
| 267597 |
17-Jun-2014 |
tuexen |
Different versions of the ARM processor use different registers.
Fix the code used on a Raspberry Pi.
Reviewed by: markm@
|
| 266673 |
25-May-2014 |
zbb |
Delete obsolete and unused PJ4B CPU functions
Since PJ4Bv7 uses armv7_ CPU functions only pj4b_config
function is necessary. Remove obsolete routines.
|
| 266621 |
24-May-2014 |
ian |
Eliminate one of the causes of spurious interrupts on armv6. The arm weak
memory ordering model allows writes to different devices to complete out
of order, leading to a situation where the write that clears an interrupt
source at a device can complete after a write that unmasks and EOIs the
interrupt at the interrupt controller, leading to a spurious re-interrupt.
This adds a generic barrier function specific to the needs of interrupt
controllers, and calls that function from the GIC and TI AINTC controllers.
There may still be other soc-specific controllers that need to make the call.
Reviewed by: cognet, Svatopluk Kraus <onwahe@gmail.com>
MFC after: 3 days
|
| 266570 |
23-May-2014 |
imp |
Remove NetBSD implementation details not relevant to FreeBSD.
|
| 266333 |
17-May-2014 |
andrew |
Add FDT_PLATFORM_DEF2 for when there are multiple platforms needing to use
the same platform methods.
|
| 266303 |
17-May-2014 |
andrew |
Fix a comment s/initarm_/platform_/
|
| 266301 |
17-May-2014 |
andrew |
Add the start of the ARM platform code. This is based on the PowerPC
platform code, it is expected these will be merged in the future when the
ARM code is more complete.
Until more boards can be tested only use this with the Raspberry Pi and
rrename the functions on the other SoCs.
Reviewed by: ian@
|
| 266083 |
14-May-2014 |
markm |
Give suitably-endowed ARMs a register similar to the x86 TSC register.
Here, "suitably endowed" means that the System Control Coprocessor
(#15) has Performance Monitoring Registers, including a CCNT (Cycle
Count) register.
The CCNT register is used in a way similar to the TSC register in
x86 processors by the get_cyclecount(9) function. The entropy-harvesting
thread is a heavy user of this function, and will benefit from not
having to call binuptime(9) instead.
One problem with the CCNT register is that it is 32-bit only, so
the upper 32-bits of the returned number are always 0. The entropy
harvester does not care, but in case any one else does, follow-up
work may include an interrup trap to increment an upper-32-bit
counter on CCNT overflow.
Another problem is that the CCNT register is not readable in user-mode
code; in can be made readable by userland, but then it is also
writable, and so is a good chunk of the PMU system. For that reason,
the CCNT is not enabled for user-mode access in this commit.
Like the x86, there is one CCNT per core, so they don't all run in
perfect sync.
Reviewed by: ian@ (an earlier version)
Tested by: ian@ (same earlier version)
Committed from: WANDBOARD-QUAD
|
| 265870 |
11-May-2014 |
ian |
Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().
On modern ARM SoCs the L2 cache controller sits between the CPU and the
AXI bus, and most on-chip memory-mapped devices are on the AXI bus. We
map the device registers using the 'Device' memory attribute, which means
the memory is not cached, but writes to it are buffered. Ensuring that a
write has made it all the way to a device may require that the L2
controller take some action.
There is currently only one implementation of the new function, for the
PL310 cache controller. It invokes a function that the controller
manual calls "cache sync" but it actually has nothing to do with cache at
all, it triggers a drain of all pending store buffer writes and it blocks
until they complete.
The sheeva and xscale L2 controllers (which predate the concept of Device
memory) don't seem to have a corresponding function. It appears that the
standard armv5 drain_writebuf function includes draining all the way
through the L2 controller.
|
| 265861 |
11-May-2014 |
ian |
Make the hardware memory and instruction barrier functions work on armv4
and armv5 as well.
|
| 265446 |
06-May-2014 |
ian |
Add a public routine to set the L2 cache ram latencies. This can be
called by platform init routines to fine-tune cache performance.
|
| 265445 |
06-May-2014 |
ian |
Add defines for the bits in the PL310 debug control register.
This should have been part of r265444.
|
| 265111 |
29-Apr-2014 |
ian |
Make this declaration into a proper function prototype.
|
| 265035 |
27-Apr-2014 |
ian |
Move duplicated code to print l2 cache config into the common code.
|
| 265023 |
27-Apr-2014 |
ian |
There is no difference between IPI_STOP and IPI_STOP_HARD on ARM, so
map them both to the same interrupt number like other arches do.
|
| 265020 |
27-Apr-2014 |
ian |
Remove cpu_idcache_wbinv_all() from kdb_cpu_trap(), it's no longer needed.
This was added ca. 2004 for the purpose of ensuring the caches were in the
right state after the debugger set a breakpoint. kdb_cpu_sync_icache()
was added in 2007 to handle that situation, and now the wbinv_all is
actually harmful because the operation isn't broadcast to other cores.
|
| 264994 |
27-Apr-2014 |
ian |
Provide a proper armv7 implementation of icache_sync_all rather than
using armv7_idcache_wbinv_all, because wbinv_all doesn't broadcast the
operation to other cores. In elf_cpu_load_file() use icache_sync_all()
and explain why it's needed (and why other sync operations aren't).
As part of doing this, all callers of cpu_icache_sync_all() were
inspected to ensure they weren't relying on the old side effect of
doing a wbinv_all along with the icache work.
|
| 264990 |
26-Apr-2014 |
ian |
Call cpu_icache_sync_range() rather than sync_all since we know the range
and flushing the entire icache is needlessly expensive.
|
| 264203 |
06-Apr-2014 |
ian |
Tell VM we now have ARM platforms with physically discontiguous memory.
|
| 264135 |
04-Apr-2014 |
ian |
We don't support any ARM systems with an ISA bus and don't need a freelist
of memory to support ISA addressing limitations.
|
| 263998 |
01-Apr-2014 |
tijl |
Rename __wchar_t so it no longer conflicts with __wchar_t from clang 3.4
-fms-extensions.
MFC after: 2 weeks
|
| 263982 |
01-Apr-2014 |
br |
Add Cortex-A15 cpu id revisions.
|
| 263914 |
29-Mar-2014 |
andrew |
VFP fixes/cleanups for ARM11:
* Save the required VFP registers on context switch. If the exception bit
is set we need to save and restore the FPINST register, and if the fp2v
bit is also set we need to save and restore FPINST2.
* Move saving and restoring the floating point control registers to C.
* Clear the fpexc exception and fp2v flags on a floating-point exception.
* Signal a SIGFPE if the fpexc exception flag is set on an undefined
instruction. This is how the ARM core signals to software there is a
floating-point exception.
|
| 263910 |
29-Mar-2014 |
andrew |
Add more flags for the fpexc register from the ARM1176JZF-S Manual
|
| 263679 |
24-Mar-2014 |
andrew |
Move an else case that was missed in r263676
|
| 263676 |
23-Mar-2014 |
andrew |
Reorder the pmap macros so "ARM_MMU_V6 + ARM_MMU_V7" is first. As they are
identical this allows us to build for both v6 and v7 together.
|
| 263637 |
22-Mar-2014 |
andrew |
Simplify how we build MACHINE_ARCH. There are 3 options that may be set
however only arm, armeb, armv6, and soon armv6hf will be used.
|
| 263057 |
11-Mar-2014 |
ian |
Remove #include <machine/asmacros.h> from files that don't need it.
|
| 263056 |
11-Mar-2014 |
ian |
Remove the unreferenced DATA() macro. That leaves only GET_CURTHREAD_PTR()
which was added by cognet in 2012, so remove the no-longer-applicable
license stuff that referred to all the old contents, and put in a
standard 2-clause BSD license (to cover the 6 lines of useful code left
in here).
|
| 262987 |
10-Mar-2014 |
ian |
Arrange for arm fork_trampoline() to return to userland via the standard
swi_exit code in exception.S instead of having its own inline expansion
of the DO_AST and PULLFRAME macros. That means that now all references
to the PUSH/PULLFRAME and DO_AST macros are localized to exception.S,
so move the macros themselves into there and remove them from asmacros.h
|
| 262986 |
10-Mar-2014 |
ian |
Change the way the asm GET_CURTHREAD_PTR() macro is defined so that code
using it doesn't have to have an "AST_LOCALS" macro somewhere in the file.
|
| 262958 |
09-Mar-2014 |
ian |
Remove all traces of support for ARM chips prior to the arm9 series. We
never actually ran on these chips (other than using SA1 support in an
emulator to do the early porting to FreeBSD long long ago). The clutter
and complexity of some of this code keeps getting in the way of other
maintenance, so it's time to go.
|
| 262948 |
09-Mar-2014 |
ian |
Always call vfp_discard() on thread death, not just when the VFP is
enabled. In vfp_discard(), if the state in the VFP hardware belongs to
the thread which is dying, NULL out pcpu fpcurthread to indicate the
state currently in the hardware belongs to nobody.
Submitted by: Juergen Weiss
Pointy hat to: me
|
| 262942 |
09-Mar-2014 |
ian |
Remove all dregs of a per-thread undefined-exception-mode stack. This is
a leftover from the days when a low-level debugger had hooks in the
undefined exception vector and needed stack space to function. These days
it effectively isn't used because we switch immediately to the svc32 mode
stack on exception entry. For that, the single undef mode stack per core
that gets set up at init time works fine.
The stack wasn't necessary but it was harmful, because the space for it
was carved out of the normal per-thread svc32 stack, in effect cutting
that 8K stack in half. If svc32 mode used more than 4k of stack space it
wandered down into the undef mode stack, and then an undef exception would
overwrite a couple words on the stack while switching to svc32 mode,
corrupting the scv32 stack. Having another stack abut the bottom of the
svc32 stack also effectively mooted the guard page below the stack.
This work is based on analysis and patches submitted by Juergen Weiss.
|
| 262941 |
09-Mar-2014 |
ian |
Rework the VFP code that handles demand-based save and restore of state.
The old code was full of complexity that would only matter if the
kernel itself used the VFP hardware. Now that's reduced to either killing
the userland process or panicking the kernel on an illegal VFP instruction.
This removes most of the complexity from the assembler code, reducing it
to just calling the save code if the outgoing thread used the VFP.
The routine that stores the VFP state now takes a flag that indicates
whether the hardware should be disabled after saving state. Right now it
always is, but this makes the code ready to be used by get/set_mcontext()
(doing so will be addressed in a future commit).
Remove the arm-specific pc_vfpcthread from struct pcpu and use the MI
field pc_fpcurthread instead.
Reviewed by: cognet
|
| 262587 |
28-Feb-2014 |
ian |
Add an armv7 implementation of cpu_sleep(). The arm11/armv6 implementation
we've been using was actually just spinning due to ARM having redefined
the old 'wait for interrupt' operation via the system coprocessor as a nop
and replacing it with a WFI instruction.
|
| 262534 |
26-Feb-2014 |
ian |
Replace many pasted identical definitions of cpu_initclocks() with a common
implementation in arm/machdep.c. Most arm platforms either don't need to
do anything, or just need to call the standard eventtimer init routines.
A generic implementation that does that is now provided via weak linkage.
Any platform that needs to do something different can provide a its own
implementation to override the generic one.
|
| 262420 |
24-Feb-2014 |
ian |
Add a new cache maintenance function, idcache_inv_all, to the table, and
implementations for each of the chips we support. Most chips up through
armv6 can use the armv4 implementation which has a single coprocessor
opcode for this operation. The rather more complex armv7 implementation
comes from netbsd.
|
| 262409 |
23-Feb-2014 |
ian |
Move the declaration for mpentry() into a header file instead of pasting
it into a bunch of different .c files. Remove declarations for the unused
mptramp() function from everywhere except AramadaXP (and I think it's
really not used there either, because the code that references it appears
to be insanely does-nothing in nature).
|
| 262123 |
17-Feb-2014 |
ian |
Give the fdt helper routines static linkage since no global definition
of them is provided anywhere. (gcc was nice enough to warn about this,
clang didn't for some reason.)
|
| 261917 |
15-Feb-2014 |
zbb |
Always clear L1 PTE descriptor when removing superpage on ARM
Invalidate L1 PTE regardles of existance of the corresponding
l2_bucket. This is relevant when superpage is entered via
pmap_enter_object() and will fix crash on entering page
in place of not properly removed superpage.
|
| 261808 |
12-Feb-2014 |
ian |
Use the right symbols for determining arm architecture. Include the
necessary header file which has the new FAULT_WNR symbol defined in it.
|
| 261663 |
09-Feb-2014 |
andrew |
Pass the pagetable used from locore.S to initarm to allow it to map data
in as required.
|
| 261656 |
09-Feb-2014 |
ian |
Use vm_paddr_t, not vm_offset_t, when dealing with physical addresses.
Pointed out by: alc
|
| 261649 |
09-Feb-2014 |
ian |
It turns out a global variable is the only straightforward way to
communicate the kernel's physical load address from where it's known in
initarm() into cpu_mp_start() which is called from non-arm code and
takes no parameters.
This adds the global variable and ensures that all the various copies
of initarm() set it. It uses the variable in cpu_mp_start(), eliminating
the last uses of KERNPHYSADDR outside of locore.S (where we can now
calculate it instead of relying on the constant).
|
| 261643 |
09-Feb-2014 |
ian |
Consolidate code related to setting up physical memory configuration into
a new physmem.c file. The new code provides helper routines that can be
used by legacy SoCs and newer FDT-based systems. There are routines to
add one or more regions of physically contiguous ram, and exclude one or
more physically contiguous regions of ram. Ram can be excluded from crash
dumps, from being given over to the vm system for allocation management,
or both. After all the included and excluded regions have been added,
arm_physmem_init_kernel_globals() processes the regions into the global
dump_avail and phys_avail arrays and realmem and physmem variables that
communicate memory configuration to the rest of the kernel.
Convert all existing SoCs to use the new helper code.
|
| 261642 |
08-Feb-2014 |
ian |
Remove the ARM_USE_SMALL_ALLOC option and code related to it.
This was an optimization used only by a few xscale platforms. Part of
the optimization was to create a direct map for all physical pages, and
that resulted in making multiple mappings of pages in a way that bypassed
the logic in pmap.c to handle VIVT cache aliasing. It also just generally
made the code more complex and hard to maintain for all SoCs.
Reviewed by: cognet
|
| 261565 |
06-Feb-2014 |
andrew |
Use abp_physaddr for the physical address over KERNPHYSADDR. This helps us
remove the need to load the kernel at a fixed address.
|
| 261562 |
06-Feb-2014 |
andrew |
Pass the kernel physical address to initarm through the boot param struct.
|
| 261419 |
02-Feb-2014 |
cognet |
Only use the CPU ID register if SMP is defined. Some non-MPCore armv6 cpu,
such as the one found in the RPi, don't have it, and just hang when we try
to access it.
|
| 261417 |
02-Feb-2014 |
ian |
Add missing semicolon.
|
| 261415 |
02-Feb-2014 |
cognet |
Change the way pcpu and curthread are stored per-core:
the old way was to store pcpu in a register, and get curthread from pcpu,
which is not very atomic, and led to issues if the thread was migrated
to another core between the time we got the pcpu address and the time we
got curthread.
Instead, we now store curthread where pcpu used to be store, and we
calculate the pcpu address based on the cpu id.
|
| 261393 |
02-Feb-2014 |
ian |
Update all arm code that manipulates the PSR registers to use modern syntax.
It turns out the version of gas we're using interprets the old '_all' mask
as 'fc' instead of 'fsxc'. That is, "all" doesn't really mean "all".
This was the cause of the "wrong-endian register restore" bug that's
been causing problems with some cortex-a9 chips. The 'endian' bit in the
spsr register would never get changed (it falls into the 'x' mask group)
and the first return-from-exception would fail if the chip had powered on
with garbage in the spsr register that included the big-endian bit. It's
unknown why this affected only certain cortex-a9 chips.
|
| 261137 |
24-Jan-2014 |
andrew |
Correct the alignment of sp through functions that use UNWINDSVCFRAME. We
were incorrectly adding the trap frame padding to the stack pointer after
reading it's value and unaligning it.
|
| 260493 |
09-Jan-2014 |
ian |
Add a prototype for the new arm_devmap_print_table(). This should have
been part of r260490.
|
| 260375 |
06-Jan-2014 |
andreast |
Fix arm build.
Reviewed by: ian, zbb
|
| 260340 |
05-Jan-2014 |
ian |
Remove dev/fdt/fdt_pci.c, which was code specific to Marvell ARM SoCs,
related to setting up static device mappings. Since it was only used by
arm/mv/mv_pci.c, it's now just static functions within that file, plus
one public function that gets called only from arm/mv/mv_machdep.c.
|
| 260327 |
05-Jan-2014 |
nwhitehorn |
Retire machine/fdt.h as a header used by MI code, as its function is now
obsolete. This involves the following pieces:
- Remove it entirely on PowerPC, where it is not used by MD code either
- Remove all references to machine/fdt.h in non-architecture-specific code
(aside from uart_cpu_fdt.c, shared by ARM and MIPS, and so is somewhat
non-arch-specific).
- Fix code relying on header pollution from machine/fdt.h includes
- Legacy fdtbus.c (still used on x86 FDT systems) now passes resource
requests to its parent (nexus). This allows x86 FDT devices to allocate
both memory and IO requests and removes the last notionally MI use of
fdtbus_bs_tag.
- On those architectures that retain a machine/fdt.h, unused bits like
FDT_MAP_IRQ and FDT_INTR_MAX have been removed.
|
| 260161 |
01-Jan-2014 |
zbb |
Add polarity and level support to ARM GIC
Add suport for setting triggering level and polarity in GIC.
New function pointer was added to nexus which corresponds
to the function which sets level/sense in the hardware (GIC).
Submitted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf
|
| 259640 |
20-Dec-2013 |
ganbold |
Add identification and necessary type checks for Krait CPU cores. Krait CPU is used in
Qualcomm Snapdragon S4 and Snapdragon 400/600/800 SoCs and has architectural
similarities to ARM Cortex-A15. As for development boards IFC6400 series embedded
boards from Inforce Computing uses Snapdragon S4 Pro/APQ8064.
Approved by: stas (mentor)
|
| 258780 |
30-Nov-2013 |
eadler |
Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this
shifts into the sign bit. Instead use (1U << 31) which gets the
expected result.
This fix is not ideal as it assumes a 32 bit int, but does fix the issue
for most cases.
A similar change was made in OpenBSD.
Discussed with: -arch, rdivacky
Reviewed by: cperciva
|
| 258531 |
24-Nov-2013 |
gavin |
platform_devmap_init() was renamed initarm_devmap_init() in r257669, update
comments to match.
|
| 257854 |
08-Nov-2013 |
alc |
As of r257209, all architectures have defined VM_KMEM_SIZE_SCALE. In other
words, every architecture is now auto-sizing the kmem arena. This revision
changes kmeminit() so that the definition of VM_KMEM_SIZE_SCALE becomes
mandatory and the definition of VM_KMEM_SIZE becomes optional.
Replace or eliminate all existing definitions of VM_KMEM_SIZE. With
auto-sizing enabled, VM_KMEM_SIZE effectively became an alternate spelling
for VM_KMEM_SIZE_MIN on most architectures. Use VM_KMEM_SIZE_MIN for
clarity.
Change kmeminit() so that the effect of defining VM_KMEM_SIZE is similar to
that of setting the tunable vm.kmem_size. Whereas the macros
VM_KMEM_SIZE_{MAX,MIN,SCALE} have had the same effect as the tunables
vm.kmem_size_{max,min,scale}, the effects of VM_KMEM_SIZE and vm.kmem_size
have been distinct. In particular, whereas VM_KMEM_SIZE was overridden by
VM_KMEM_SIZE_{MAX,MIN,SCALE} and vm.kmem_size_{max,min,scale}, vm.kmem_size
was not. Remedy this inconsistency. Now, VM_KMEM_SIZE can be used to set
the size of the kmem arena at compile-time without that value being
overridden by auto-sizing.
Update the nearby comments to reflect the kmem submap being replaced by the
kmem arena. Stop duplicating the auto-sizing formula in every machine-
dependent vmparam.h and place it in kmeminit() where auto-sizing takes
place.
Reviewed by: kib (an earlier version)
Sponsored by: EMC / Isilon Storage Division
|
| 257676 |
05-Nov-2013 |
ian |
Style and comment tweaks, no functional changes.
|
| 257673 |
05-Nov-2013 |
ian |
Add new helper routines for arm static device mapping. The new code
allocates kva space from the top down for the device mappings and builds
entries in an internal table which is automatically used later by
arm_devmap_bootstrap(). The platform code just calls the new
arm_devmap_add_entry() function as many times as it needs to (up to 32
entries allowed; most platforms use 2 or 3 at most).
There is also a new arm_devmap_lastaddr() function that returns the lowest
kva address allocated; this can be used to implement initarm_lastaddr()
which is used to initialize vm_max_kernel_address.
The new code is based on a similar concept developed for the imx family
SoCs recently. They will soon be converted to use this new common code.
|
| 257672 |
05-Nov-2013 |
ian |
Make PTE_DEVICE a synonym for PTE_NOCACHE on armv4, to make it easier to
share the same code on both architectures.
|
| 257669 |
05-Nov-2013 |
ian |
Call initarm_lastaddr() later in the init sequence, after establishing
static device mappings, rather than as the first of the initializations
that a platform can hook into. This allows a platform to allocate KVA
from the top of the address space downwards for things like static device
mapping, and return the final "last usable address" result after that and
other early init work is done.
Because some platforms were doing work in initarm_lastaddr() that needs to
be done early, add a new initarm_early_init() routine and move the early
init code to that routine on those platforms.
Rename platform_devmap_init() to initarm_devmap_init() to match all the
other init routines called from initarm() that are designed to be
implemented by platform code.
Add a comment block that explains when these routines are called and the
type of work expected to be done in each of them.
|
| 257660 |
04-Nov-2013 |
ian |
Move remaining code and data related to static device mapping into the
new devmap.[ch] files. Emphasize the MD nature of these things by using
the prefix arm_devmap_ on the function and type names (already a few of
these things found their way into MI code, hopefully it will be harder to
do by accident in the future).
|
| 257648 |
04-Nov-2013 |
ian |
Begin reducing code duplication in arm pmap.c and pmap-v6.c by factoring
out common code related to mapping device memory into a new devmap.c file.
Remove the growing duplication of code that used pmap_devmap_find_pa() and
then did some math with the returned results to generate a virtual address,
and likewise in reverse to get a physical address. Now there are a pair
of functions, arm_devmap_vtop() and arm_devmap_ptov(), to do that. The
bus_space_map() implementations are rewritten in terms of these.
|
| 257549 |
02-Nov-2013 |
alc |
Don't create a distinct free page pool for segregating allocations that are
accessed through the direct map unless the kernel configuration actually
includes a direct map. Only a few configurations do, and for the rest the
unnecessary free page pool is a small pessimization.
Tested by: zbb
MFC after: 6 weeks
|
| 257291 |
28-Oct-2013 |
zbb |
Fix condition that determines PMAP_NEEDS_PTE_SYNC value for ARM
Use values of the correct defines to determine statement's result.
ARM_ARCH_ symbols are always defined, hence only values are relevant.
Reviewed by: cognet
|
| 257282 |
28-Oct-2013 |
zbb |
Switch off explicit broadcasting of the TLB flush operations for PJ4B CPU
Since CPU_MV_PJ4B describes ARMv7 compliant CPU there is no need for
sending an IPI each time when TLB is flushed in any way.
Tested by: kevlo
|
| 257281 |
28-Oct-2013 |
zbb |
Remove not working and deprecated PJ4Bv6 support
Sheeva PJ4Bv6 - based chips were only prototypes for V7 class Armada
SoC family. Current in-tree support for PJ4Bv6 will not work and also
there should be no platforms in active use that would incorporate that
CPU revision.
|
| 257231 |
27-Oct-2013 |
cognet |
Make sure the PCB is aligned on 8 bytes, we may use ldrd/strd to access it,
which may have strong alignment requirements.
|
| 257217 |
27-Oct-2013 |
ian |
Remove the last dregs of trapframe_t. It turns out only arm was using
this type, so remove it to make arm code more consistant with other
platforms. Thanks to bde@ for pointing out only arm used trapframe_t.
|
| 257201 |
27-Oct-2013 |
ian |
Retire arm_remap_nocache() and the data and constants associated with it.
The only remaining user was the code that allocates bounce pages for armv4
busdma. It's not clear why bounce pages would need uncached memory, but
if that ever changes, kmem_alloc_attr() would be the way to get it.
|
| 257200 |
27-Oct-2013 |
ian |
Remove #include <machine/frame.h> from all the arm code that doesn't
really need it. That would be almost everywhere it was included. Add
it in a couple files that really do need it and were previously getting
it by accident via another header.
|
| 257199 |
27-Oct-2013 |
ian |
Remove all #include <machine/pmap.h> from arm code. It's already
included by vm/pmap.h, which is a prerequisite for arm/machine/pmap.h
so there's no reason to ever include it directly.
Thanks to alc@ for pointing this out.
|
| 257189 |
26-Oct-2013 |
andrew |
Fix an itt instruction. We need to execute both the mov and b instructions
when building for Thumb.
|
| 256708 |
17-Oct-2013 |
cognet |
Spell cpu_l2cache_wb_range correctly.
|
| 256707 |
17-Oct-2013 |
cognet |
- Switch to use WBWA mappings for page tables on armv6, this is needed for SMP.
- Fix PTE_SYNC() for PIPT L2 caches, using the virtual address wasn't so useful.
- Use PTE_SYNC() for >= armv6
|
| 256629 |
16-Oct-2013 |
br |
Add CPU ID for ARM Cortex A5.
Approved by: cognet (mentor)
|
| 255361 |
07-Sep-2013 |
andrew |
On ARM EABI double precision floating point values are stored in the
endian the CPU is in, i.e. little-endian on most ARM cores.
This allows ARMv4 and ARMv5 boards to boot with the ARM EABI.
|
| 255352 |
07-Sep-2013 |
glebius |
Fix of r255318: move sf_buf_alloc()/sf_buf_free() out of #ifdef
ARM_USE_SMALL_ALLOC.
|
| 255318 |
06-Sep-2013 |
glebius |
Fix build with gcc. Move sf_buf_alloc()/sf_buf_free() declarations
to MD headers.
|
| 254918 |
26-Aug-2013 |
raj |
Introduce superpages support for ARMv6/v7.
Promoting base pages to superpages can increase TLB coverage and allow for
efficient use of page table entries. This development provides FreeBSD/ARM
with superpages management mechanism roughly equivalent to what we have for
i386 and amd64 architectures.
1. Add mechanism for automatic promotion of 4KB page mappings to 1MB section
mappings (and demotion when not needed, respectively).
2. Managed and non-kernel mappings are now superpages-aware.
3. The functionality can be enabled by setting "vm.pmap.sp_enabled" tunable to
a non-zero value (either in loader.conf or by modifying "sp_enabled"
variable in pmap-v6.c file). By default, automatic promotion is currently
disabled.
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Reviewed by: alc
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 254915 |
26-Aug-2013 |
raj |
Provide settings for superpage reservation system on ARM.
This allows for enabling and configuring superpages reservation mechanism in
order to allocate and populate 256 4KB base pages (for the purpose of
promotion to a 1MB superpage).
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Reviewed by: alc
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 254536 |
19-Aug-2013 |
raj |
Do not use pv_kva on ARMv6/v7 and save some space on each vm_page. It's only
relevant for older ARM variants (with virtual cache).
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Reviewed by: gber
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 254532 |
19-Aug-2013 |
raj |
Clear all L2 PTE protection bits before their configuration.
Revise L2_S_PROT_MASK to include all of the protection bits. Notice that
clearing these bits does not always take away the corresponding permissions
(for example, permission is granted when the bit is cleared). The bits are
cleared but are to be set or left cleared accordingly in pmap_set_prot(),
pmap_enter_locked(), etc.
Clear L2_XN along with L2_S_PROT_MASK in pmap_set_prot() so that all
permissions related bits are cleared before actual configuration.
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Reviewed by: gber
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 254461 |
17-Aug-2013 |
andrew |
Rename device vfp to option VFP and retire the ARM_VFP_SUPPORT option. This
simplifies enabling as previously both options were required to be enabled,
now we only need a single option.
While here enable VFP on the PandaBoard.
|
| 254452 |
17-Aug-2013 |
andrew |
Remove fpe_sp_state as we don't support fpe.
|
| 254166 |
09-Aug-2013 |
cognet |
Instead of just trying to do it for arm, make sure vm_kmem_size is properly
aligned in kmeminit(), where it'll work for any arch.
Suggested by: alc
|
| 254164 |
09-Aug-2013 |
cognet |
Make sure vm_kmem_size is aligned on a page boundary, since that's what vmem
expects.
|
| 253968 |
05-Aug-2013 |
andrew |
When entering exception handlers we may not have an aligned stack. This is
because an exception may happen at any time. The stack alignment rules on
ARM EABI state the only place the stack must be 8-byte aligned is on a
function boundary.
If an exception happens while a function is setting up or tearing down it's
stack frame it may not be correctly aligned. There is also no requirement
for it to be when the function is a leaf node.
The fix is to align the stack after we have stored a backup of the old stack
pointer, but before we have stored anything in the trapframe. Along with
this we need to adjust the size of the trapframe by 4 bytes to ensure the
stack below it is also correctly aligned.
|
| 253857 |
01-Aug-2013 |
ganbold |
Add identification for Cortex-A7 (R0) cores.
Reviewed by: cognet@
|
| 253768 |
29-Jul-2013 |
cognet |
Explicitely include <machine/pcb.h>, so that we get the definition of
struct pcb.
Submitted by: Zbyszek Bodek <zbb@semihalf.com>
Pointy hat to: cognet
|
| 253762 |
29-Jul-2013 |
cognet |
Define KDB_STOPPEDPCB, so that we can access the backtraces of threads running
on other cores.
|
| 253750 |
28-Jul-2013 |
avg |
Revert r253748,253749
This WIP should not have been committed yet.
Pointyhat to: avg
|
| 253748 |
28-Jul-2013 |
avg |
put contents of cpu.h under _KERNEL
no userland-serviceable parts inside
MFC after: 20 days
|
| 253489 |
20-Jul-2013 |
andrew |
Start adding support to build bits of our code using the Thumb-2
instruction set. Thumb-2 requires an if-then instruction to implement
conditional codes.
When building for ARM mode the it-then instructions do not generate any
assembled instruction as per the ARMv7-A Architecture Reference Manual, and
are safe to use.
While this allows the atomic instructions to be built, it doesn't mean we
fully support Thumb code. It works in small tests, but is still known to
fail in a large number of places.
While here add a check for the armv6t2 architecture.
|
| 252434 |
01-Jul-2013 |
kib |
Fix issues with zeroing and fetching the counters, on x86 and ppc64.
Issues were noted by Bruce Evans and are present on all architectures.
On i386, a counter fetch should use atomic read of 64bit value,
otherwise carry from the increment on other CPU could be lost for the
given fetch, making error of 2^32. If 64bit read (cmpxchg8b) is not
available on the machine, it cannot be SMP and it is enough to disable
preemption around read to avoid the split read.
On x86 the counter increment is not atomic on purpose, which makes it
possible for the store of the incremented result to override just
zeroed per-cpu slot. The effect would be a counter going off by
arbitrary value after zeroing. Perform the counter zeroing on the
same processor which does the increments, making the operations
mutually exclusive. On i386, same as for the fetching, if the
cmpxchg8b is not available, machine is not SMP and we disable
preemption for zeroing.
PowerPC64 is treated the same as amd64.
For other architectures, the changes made to allow the compilation to
succeed, without fixing the issues with zeroing or fetching. It
should be possible to handle them by using the 64bit loads and stores
atomic WRT preemption (assuming the architectures also converted from
using critical sections to proper asm). If architecture does not
provide the facility, using global (spin) mutex would be non-optimal
but working solution.
Noted by: bde
Sponsored by: The FreeBSD Foundation
|
| 252362 |
28-Jun-2013 |
ray |
Bump max number of IRQs for Cortex-Ax family to cover Exynos5 requirement.
Submitted by: Ruslan Bukin <br@bsdpad.com>
|
| 252361 |
28-Jun-2013 |
ray |
Add identification for Cortex-A15 (R0) cores.
Submitted by: Ruslan Bukin <br@bsdpad.com>
|
| 252311 |
27-Jun-2013 |
andrew |
Add UNWINDSVCFRAME to provide the unwind pseudo ops to allow us to unwind
past a trapframe.
Use this macro in exception_exit as it is the function the unwinder enters
as the functions that store the frame setting lr to point to it.
|
| 251712 |
13-Jun-2013 |
andrew |
Fix the vfp code to work with the 16 register variants of the VFP unit. We
check which variant we are on, and if it is a VFPv3 or v4, and has 32
double registers we save these. This fixes VFP support on Raspberry Pi.
While here clean fmrx and fmxr up to use the register names from vfp.h
as opposed to the raw register names.
|
| 251517 |
08-Jun-2013 |
andrew |
Merge in changes from NetBSD:
* Remove support for non-elf files.
* Add the VFP setjmp magic numbers.
* Add the offsets for the VFP registers within the buffer.
|
| 251510 |
07-Jun-2013 |
andrew |
Reduce the difference to NetBSD.
* Stop pretending we support anything other than ELF by removing code
surrounded by #ifdef __ELF__ ... #endif.
* Remove _JB_MAGIC_SETJMP and _JB_MAGIC__SETJMP, they are defined in
setjmp.h, which is able to be included from asm.
* Fix the spelling of dependent.
* Rename END _END and add END and ASEND to complement ENTRY and ASENTRY
respectively
* Add macros to simplify accessing the Global Offset Table, some of these
will be used in the upcoming update to the setjmp functions.
|
| 250930 |
23-May-2013 |
gber |
Stop using PVF_MOD, PVF_REF & PVF_EXEC flags in pv_entry, use PTE.
Using PVF_MOD, PVF_REF and PVF_EXEC is redundant as we can get the proper
info from PTE bits.
When the mapping is marked as executable and has been referenced we assume
that it has been executed. Similarly, when the mapping is set to be writable
and is referenced, it must have been due to write access to it.
PVF_MOD and PVF_REF flags are kept just for pmap_clearbit() usage,
to pass the information on which bit should be cleared.
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 250929 |
23-May-2013 |
gber |
Improve, optimize and clean-up ARMv6/v7 memory management related code.
Use pmap_find_pv if needed instead of multiplying its code throughout
pmap-v6.
Avoid possible NULL pointer dereference in pmap_enter_locked()
When trying to get m->md.pv_memattr, make sure that m != NULL,
in particular that vector_page is set to be NULL.
Do not set PGA_REFERENCED flag in pmap_enter_pv().
On ARM any new page reference will result in either entering the new
mapping by calling pmap_enter, etc. or fixing-up the existing mapping in
pmap_fault_fixup().
Therefore we set PGA_REFERENCED flag in the earlier mentioned cases and
setting it later in pmap_enter_pv() is just waste of cycles.
Delete unused pm_pdir pointer from the pmap structure.
Rearrange brackets in the fault cause detection in trap.c
Place the brackets correctly in order to see course of the conditions
instantaneously.
Unify naming in pmap-v6.c and improve style
Use naming common for whole pmap and compatible with other pmaps,
improve style where possible:
pm -> pmap
pg -> m
opg -> om
*pt -> *ptep
*pte -> *ptep
*pde -> *pdep
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 250928 |
23-May-2013 |
gber |
Switch to AP[2:1] access permissions model. Store "referenced"
bit in PTE.
Enable Access Flag in CPU control. With AF enabled each valid mapping
needs to have referenced bit in PTE set in order to be able to cache
it in the TLB.
AP[0] bit is to be used as reference flag.
All access permissions are encoded by AP[2:1] wherein AP[1] is in fact
"user enable" and AP[2](APX) is "write disable".
All mappings are always set to be valid. Reference emulation is performed
by setting/clearing reference flag in PTE.
md.pvh_attrs are no longer necessary however pv_flags are still being used
for now.
Marking vm_page as "dirty" or "referenced" is being performed on:
- page or flag fault servicing in pmap_fault_fixup(), basing on the fault
type
- vm_fault servicing in pmap_enter() according to the desired protections
and faulty access type
Redundant page marking has been removed as on ARM we know exactly when the
particular page is referenced or is going to be written.
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 250634 |
14-May-2013 |
gber |
Port the new PV entry allocator from amd64/i386/mips to armv6/v7.
PV entries are now roughly half the size.
Instead of using a shared UMA zone for 28 byte pv entries
(two 8-byte tailq nodes, a 4 byte pointer, a 4 byte address and 4 byte
flags), we allocate a page at a time per process.
This provides 252 pv entries per process (actually, per pmap address space)
and eliminates one of the 8-byte tailq entries since we now can track
per-process pv entries implicitly.
The pointer to the pmap can be eliminated by doing address arithmetic to
find the metadata on the page headers to find a single pointer shared by
all 252 entries. There is an 8-int bitmap for the freelist of those 252
entries.
When in serious low memory condition, allocation of another pv_chunk is
possible by freeing some pages in pmap_pv_reclaim().
Added pv_entry/pv_chunk related statistics to pmap.
pv_entry/pv_chunk statistics can be accessed via sysctl vm.pmap.
Ported PTE freelist of KVA allocation and maintenance from i386.
Using an idea from Stephan Uphoff, use the empty pte's that correspond
to the unused kva in the pv memory block to thread a freelist through.
This allows us to free pages that used to be used for pv entry chunks
since we can now track holes in the kva memory block.
As both ARM pmap.c and pmap-v6.c use the same header and pv_entry, pmap and
md_page structures are different, it was needed to separate code designed
for ARMv6/7 from the one for other ARMs.
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Reviewed by: alc
Sponsored by: The FreeBSD Foundation, Semihalf
|
| 250338 |
07-May-2013 |
attilio |
Rename VM_NDOMAIN into MAXMEMDOM and move it into machine/param.h in
order to match the MAXCPU concept. The change should also be useful
for consolidation and consistency.
Sponsored by: EMC / Isilon storage division
Obtained from: jeff
Reviewed by: alc
|
| 250297 |
06-May-2013 |
gber |
Fix L2 PTE access permissions management.
Keep following access permissions:
APX AP Kernel User
1 01 R N
1 10 R R
0 01 R/W N
0 11 R/W R/W
Avoid using reserved in ARMv6 APX|AP settings:
- In case of unprivileged (user) access without permission to write,
the access permission bits were being set to reserved for ARMv6
(but valid for ARMv7) value of APX|AP = 111.
Fix-up faulting userland accesses properly:
- Wrong condition statement in pmap_fault_fixup() caused that
any genuine, unprivileged access was being fixed-up instead of
just skip doing anything and return. Staring from now we ensure
proper reaction for illicit user accesses.
L2_S_PROT_R and L2_S_PROT_U names might be misleading as they do not
reflect real permission levels. It will be clarified in following
patches (switch to AP[2:1] permissions model).
Obtained from: Semihalf
|
| 249999 |
27-Apr-2013 |
wkoszek |
Add Xilinx Zynq ARM/FPGA SoC support to FreeBSD/arm port.
Submitted by: Thomas Skibo <ThomasSkibo (at) sbcglobal.net>
Tested by: wkoszek (ZedBoard)
Reviewed by: wkoszek, freebsd-arm@ (no objections raised)
|
| 249582 |
17-Apr-2013 |
gabor |
- Correct mispellings of the word occurrence
Submitted by: Christoph Mallon <christoph.mallon@gmx.de> (via private mail)
|
| 249268 |
08-Apr-2013 |
glebius |
Merge from projects/counters: counter(9).
Introduce counter(9) API, that implements fast and raceless counters,
provided (but not limited to) for gathering of statistical data.
See http://lists.freebsd.org/pipermail/freebsd-arch/2013-April/014204.html
for more details.
In collaboration with: kib
Reviewed by: luigi
Tested by: ae, ray
Sponsored by: Nginx, Inc.
|
| 249265 |
08-Apr-2013 |
glebius |
Merge from projects/counters:
Pad struct pcpu so that its size is denominator of PAGE_SIZE. This
is done to reduce memory waste in UMA_PCPU_ZONE zones.
Sponsored by: Nginx, Inc.
|
| 249180 |
06-Apr-2013 |
andrew |
Hide non-assembler bits behind #ifndef __ASSEMBLER__
|
| 248911 |
29-Mar-2013 |
ian |
Add userland access to at91 gpio functionality via ioctl calls. Also,
add the ability for userland to be notified of changes on gpio pins via
a select(2)/read(2) interface.
Change the interrupt handler from filtered to threaded.
Because of the uiomove() calls in the new interface, change locking from
standard mutex to sx.
Add / restore the at91_gpio_high_z() function.
Reviewed by: imp (long ago)
|
| 248907 |
29-Mar-2013 |
ian |
Add a couple forward declarations, so that board support routines don't have
to pre-include a bunch of header files they don't need just to use this one.
|
| 248467 |
18-Mar-2013 |
ray |
o Switch to use physical addresses in rman for FDT.
o Remove vtophys used to translate virtual address to physical in case rman carry virtual.
Sponsored by: The FreeBSD Foundation
|
| 248407 |
17-Mar-2013 |
ian |
Add a macro that gets the physical address of a memory mapped device
register from a bus space resource.
Note that this macro is just for ARM, and is intended to have a short
lifespan. The DMA engines in some SoCs need the physical address of a
memory-mapped device register as one of the arguments for the transfer.
Several scattered ad-hoc solutions have been converted to use this macro,
which now also serves to mark the places where a more complete fix needs
to be applied (after that fix has been designed).
|
| 248361 |
16-Mar-2013 |
andrew |
Add an END macro to ARM. This is mostly used to tell gas where the bounds
of the functions are when creating the EABI unwind tables.
|
| 248280 |
14-Mar-2013 |
kib |
Add pmap function pmap_copy_pages(), which copies the content of the
pages around, taking array of vm_page_t both for source and
destination. Starting offsets and total transfer size are specified.
The function implements optimal algorithm for copying using the
platform-specific optimizations. For instance, on the architectures
were the direct map is available, no transient mappings are created,
for i386 the per-cpu ephemeral page frame is used. The code was
typically borrowed from the pmap_copy_page() for the same
architecture.
Only i386/amd64, powerpc aim and arm/arm-v6 implementations were
tested at the time of commit. High-level code, not committed yet to
the tree, ensures that the use of the function is only allowed after
explicit enablement.
For sparc64, the existing code has known issues and a stab is added
instead, to allow the kernel linking.
Sponsored by: The FreeBSD Foundation
Tested by: pho (i386, amd64), scottl (amd64), ian (arm and arm-v6)
MFC after: 2 weeks
|
| 248153 |
11-Mar-2013 |
cognet |
Don't use an empty struct.
|
| 248119 |
10-Mar-2013 |
andrew |
__FreeBSD_ARCH_armv6__ is undefined on clang. We can use __ARM_ARCH in
it's place. This makes 'uname -p' correctly output 'armv6' on a kernel
built with clang.
|
| 247864 |
06-Mar-2013 |
andrew |
Fix stack alignment in the kernel to be on an 8 byte boundary as required
by AAPCS.
|
| 247610 |
02-Mar-2013 |
andrew |
Move some virtual memory constants to the top of the file where they are on
other architectures [1].
While here:
- Remove an unused and commented out include.
- Add a comment describing the file that other copies have.
- Fix the style of the defines and add a comment on what each one is.
Suggested by: [1] alc
|
| 247587 |
01-Mar-2013 |
andrew |
Increase the maximum text size on ARM to 64MiB. Without this clang would be
sent a SIGABRT when it is loaded as it is too large. This is the smallest
power of two MiB value that allows us to execute clang.
While here wrap it in an #ifndef to be consistent with the other
architectures.
Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp>
|
| 247535 |
01-Mar-2013 |
alc |
Copy the definition of VM_MAX_AUTOTUNE_MAXUSERS from i386. (See r242847.)
Tested by: andrew
|
| 247341 |
26-Feb-2013 |
cognet |
Export vfp_init() prototype, for use in the MP code.
|
| 247314 |
26-Feb-2013 |
alc |
Be more conservative in auto-sizing and capping the kmem submap. In
fact, use the same values here that we use on 32-bit x86 and MIPS. Some
machines were reported to have problems with the more aggressive values.
Reported and tested by: andrew
|
| 247046 |
20-Feb-2013 |
alc |
Initialize vm_max_kernel_address on non-FDT platforms. (This should have
been included in r246926.)
The second parameter to pmap_bootstrap() is redundant. Eliminate it.
Reviewed by: andrew
|
| 246929 |
18-Feb-2013 |
alc |
Place a cap on the size of the kernel's heap, also known as the kmem
submap. Otherwise, after r246204, the auto-scaling logic in kern_malloc.c
tries to create a kmem submap that consumes the entire kernel map on a
Pandaboard with 1 GB of RAM.
Tested by: gonzo
|
| 246926 |
18-Feb-2013 |
alc |
On arm, like sparc64, the end of the kernel map varies from one type of
machine to another. Therefore, VM_MAX_KERNEL_ADDRESS can't be a constant.
Instead, #define it to be a variable, vm_max_kernel_address, just like we
do on sparc64.
Reviewed by: kib
Tested by: ian
|
| 246204 |
01-Feb-2013 |
andre |
Add VM_KMEM_SIZE_SCALE parameter set to 2 (50%) for all ARM platforms.
VM_KMEM_SIZE_SCALE specifies which fraction of the available physical
memory, after deduction of the kernel itself and other early statically
allocated memory, can be used for the kmem_map. The kmem_map provides
for all UMA/malloc allocations in KVM space.
Previously ARM was using a fixed kmem_map size of (12*1024*1024) = 12MB
without regard to effectively available memory. This is too small for
recent ARM SoC with more than 128MB of RAM.
For reference a description of others related kmem_map parameters:
VM_KMEM_SIZE default start size of kmem_map if SCALE is
not defined
VM_KMEM_SIZE_MIN hard floor on the kmem_map size
VM_KMEM_SIZE_MAX hard ceiling on the kmem_map size
VM_KMEM_SIZE_SCALE fraction of the available real memory to
be used for the kmem_map, limited by the
MIN and MAX parameters.
Tested by: ian
MFC after: 1 week
|
| 245637 |
19-Jan-2013 |
ian |
Eliminate the need for an intermediate array of indices into the arrays of
interrupt counts and names, by making the names into an array of fixed-length
strings that can be directly indexed. This eliminates extra memory accesses
on every interrupt to increment the counts.
As a side effect, it also fixes a bug that would corrupt the names data
if a name was longer than MAXCOMLEN, which led to incorrect vmstat -i output.
Approved by: cognet (mentor)
|
| 245551 |
17-Jan-2013 |
andrew |
* Correct KINFO_PROC_SIZE for ARM EABI.
* Update the syscall interface to pass in the syscall value in register r7.
|
| 245475 |
15-Jan-2013 |
cognet |
Don't define rel/acq variants of some atomic operations as the regular
version for armv6.
|
| 245202 |
09-Jan-2013 |
cognet |
Use get_pcpu() instead of using pcpup, as it's wrong for SMP.
Submitted by: Lukasz Plachno <luk@semihalf.com>
|
| 245147 |
08-Jan-2013 |
gonzo |
Switch default cache type for ARMv6/ARMv7 from write-through to
writeback-writeallocate
|
| 245135 |
07-Jan-2013 |
gonzo |
Implement barriers for AMRv6 and ARMv7
Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp>
Reviewed by: ian, cognet
|
| 245083 |
06-Jan-2013 |
andrew |
Only work around errata when we are on a part where the erratum applies.
Reviewed by: gonzo
|
| 245079 |
05-Jan-2013 |
gonzo |
Add hw.board.serial and hw.board.revision for exporting board-specific info
|
| 244919 |
01-Jan-2013 |
andrew |
Document the known values of the RTL release field in the cache is register
|
| 244914 |
31-Dec-2012 |
gonzo |
PL310 driver update:
- Add pl310.disable tunable to disable L2 cache altogether. In
order to make sure that it's 100% disabled we use cache event
counters for cache line eviction and read allocate events
and panic if any of these counters increased. This is purely
for debugging purpose
- Direct access DEBUG_CTRL and CTRL might be unavailable in
unsecure mode, so use platform-specific functions for
these registers
- Replace #if 1 with proper erratum numbers
- Add erratum 753970 workaround
- Remove wait function for atomic operations
- Protect cache operations with spin mutex in order to prevent race condition
- Disable instruction cache prefetch and make sure data cache
prefetch is enabled in OMAP4-specific intialization
|
| 244480 |
20-Dec-2012 |
gonzo |
Replace generic ARM11 option with more specific
support for ARM1136 and ARM1176
Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp>
Obtained from: NetBSD
|
| 244476 |
20-Dec-2012 |
gonzo |
Fix misleading comment
|
| 244414 |
19-Dec-2012 |
cognet |
Properly implement pmap_[get|set]_memattr
Submitted by: Ian Lepore <freebsd@damnhippie.dyndns.org>
|
| 243576 |
27-Nov-2012 |
marcel |
Don't define intr_disable and intr_restore as macros. The macros
interfere with structure fields of the same name in drivers, like
the intr_disable function pointer in struct cphy_ops in cxgb(4).
Instead define intr_disable and intr_restore as inline functions.
With intr_disable() an inline function, the I32_bit and F32_bit
macros now need to be visible in MI code and given the rather
poor names, this is not at all good. Define ARM_CPSR_F32 and
ARM_CPSR_I32 and use that instead of F32_bit and I32_bit (resp)
for now.
|
| 242531 |
03-Nov-2012 |
andrew |
Merge the FDT versions of initarm.
The copies of initarm used on platforms with FDT support were almost
identical. The differences were pulled out into separate functions that
were called by initarm.
This change merges the, now identical, copies of initarm and a few of it's
support functions. This is a step towards a common kernel on ARMv6.
|
| 241080 |
01-Oct-2012 |
andrew |
Fix the clobber list on the atomic operators that do comparisons. Without
this some compilers will place a cmp instruction before the atomic operation
and expect to be able to use the result afterwards. By adding "cc" to the
list of used registers we tell the compiler to not do this.
|
| 241058 |
29-Sep-2012 |
alc |
Eliminate an unused declaration.
|
| 240983 |
27-Sep-2012 |
alc |
Implementing pmap_kextract(va) as pmap_extract(kernel_pmap, va) is
problematic because some callers to pmap_kextract() expect its
implementation to be lock-less. In particular, uma_dbg_alloc() implicitly
requires this. Otherwise, lock-order reversals occur between pmap locks and
UMA zone locks. So, this change introduces a lock-less implementation of
pmap_kextract().
Disable recursion on the pvh global lock in the new armv6 pmap. While
recursion on this locks occurs in the old arm pmap, it thankfully doesn't
occur in the armv6 pmap.
Tested by: jmg
|
| 240846 |
23-Sep-2012 |
andrew |
Pull out the SoC specific parts of initarm into separate functions
|
| 240802 |
22-Sep-2012 |
andrew |
Create a common set_stackptrs in sys/arm/machdep.c.
On single core devices set_stackptrs is only ever called with cpu = 0 in
initarm and will be identical to the existing function. On SMP this needs
to be implemented for sys/arm/mp_machdep.c, but the implementations are
identical for each SoC.
|
| 240492 |
14-Sep-2012 |
gber |
Add support for MSI in interrupt controlller.
MSI are implemented via software interrupt. PCIe cards will write
into software interrupt register which will cause inbound shared
interrupt which will be interpreted as a MSI.
Obtained from: Marvell, Semihalf
|
| 240488 |
14-Sep-2012 |
gber |
Add support for Armada XP A0.
- Add functions to calculate clocks instead using hardcoded values
- Update reset and timers functions
- Update number of interrupts
- Change name of platform from db88f78100 to db78460
- Correct DRAM size and PCI IRQ routing in dts file.
Obtained from: Semihalf
|
| 240486 |
14-Sep-2012 |
gber |
Support identification of new PJ4B cores.
Obtained from: Semihalf
|
| 240181 |
07-Sep-2012 |
alc |
Eliminate an unused macro.
|
| 239701 |
26-Aug-2012 |
gonzo |
Add support for ARM11 cpufunc
Obtained from: NetBSD (partially)
|
| 239696 |
26-Aug-2012 |
gonzo |
Piggyback MIPS changes and add ARM syscons support for devices with
framebuffer
While here - sort #if defined() order alphabetically
|
| 239688 |
25-Aug-2012 |
gonzo |
ARM11 might have more then 32 interrupts, e.g. BCM2835: 72 interrupts
|
| 239268 |
15-Aug-2012 |
gonzo |
Merging projects/armv6, part 1
Cummulative patch of changes that are not vendor-specific:
- ARMv6 and ARMv7 architecture support
- ARM SMP support
- VFP/Neon support
- ARM Generic Interrupt Controller driver
- Simplification of startup code for all platforms
|
| 238347 |
10-Jul-2012 |
imp |
Revert committal of local change accidentally swept up in r238329.
|
| 238329 |
10-Jul-2012 |
imp |
Remove some unused variables/externs that have been copied too many times...
|
| 238189 |
07-Jul-2012 |
imp |
Create a generic way to support multiple boards within an
arm platform. Add all the atmel boards to the ATMEL kernel for
testing purposes. Until boot loader arg parsing of baord type
is done, this won't actually be able to do the runtime selection.
|
| 237517 |
24-Jun-2012 |
andrew |
Make the wchar_t type machine dependent.
This is required for ARM EABI. Section 7.1.1 of the Procedure Call for the
ARM Architecture (AAPCS) defines wchar_t as either an unsigned int or an
unsigned short with the former preferred.
Because of this requirement we need to move the definition of __wchar_t to
a machine dependent header. It also cleans up the macros defining the limits
of wchar_t by defining __WCHAR_MIN and __WCHAR_MAX in the same machine
dependent header then using them to define WCHAR_MIN and WCHAR_MAX
respectively.
Discussed with: bde
|
| 237433 |
22-Jun-2012 |
kib |
Implement mechanism to export some kernel timekeeping data to
usermode, using shared page. The structures and functions have vdso
prefix, to indicate the intended location of the code in some future.
The versioned per-algorithm data is exported in the format of struct
vdso_timehands, which mostly repeats the content of in-kernel struct
timehands. Usermode reading of the structure can be lockless.
Compatibility export for 32bit processes on 64bit host is also
provided. Kernel also provides usermode with indication about
currently used timecounter, so that libc can fall back to syscall if
configured timecounter is unknown to usermode code.
The shared data updates are initiated both from the tc_windup(), where
a fast task is queued to do the update, and from sysctl handlers which
change timecounter. A manual override switch
kern.timecounter.fast_gettime allows to turn off the mechanism.
Only x86 architectures export the real algorithm data, and there, only
for tsc timecounter. HPET counters page could be exported as well, but
I prefer to not further glue the kernel and libc ABI there until
proper vdso-based solution is developed.
Minimal stubs neccessary for non-x86 architectures to still compile
are provided.
Discussed with: bde
Reviewed by: jhb
Tested by: flo
MFC after: 1 month
|
| 237430 |
22-Jun-2012 |
kib |
Reserve AT_TIMEKEEP auxv entry for providing usermode the pointer to
timekeeping information.
MFC after: 1 week
|
| 237168 |
16-Jun-2012 |
alc |
The page flag PGA_WRITEABLE is set and cleared exclusively by the pmap
layer, but it is read directly by the MI VM layer. This change introduces
pmap_page_is_write_mapped() in order to completely encapsulate all direct
access to PGA_WRITEABLE in the pmap layer.
Aesthetics aside, I am making this change because amd64 will likely begin
using an alternative method to track write mappings, and having
pmap_page_is_write_mapped() in place allows me to make such a change
without further modification to the MI VM layer.
As an added bonus, tidy up some nearby comments concerning page flags.
Reviewed by: kib
MFC after: 6 weeks
|
| 237069 |
14-Jun-2012 |
imp |
Defines for parsing linux ATAGs lists.
|
| 237045 |
14-Jun-2012 |
imp |
More Linux boot support. Create arm_dump_avail_init() to initialize
this array either from Linux boot data, when enabled, or in the
typical way that most ports do it. arm_pyhs_avail_init is coming
soon since it must be a separate function.
|
| 237044 |
14-Jun-2012 |
imp |
Add support for parsing Linux ATAGs such as you'd see from uboot or
redboot. Support is very preiminary and likely needs some work. Also,
do some minor code shuffling of the FreeBSD /boot/loader metadata
parsing code. This code is preliminary and should be used with
caution.
|
| 237042 |
14-Jun-2012 |
imp |
Create default_parse_boot_param which, if FreeBSD /boot/loader support
is enabled, sets values based on the metadata passed in. Otherwise
fake_preload_metadata is called. Change the default parse_boot_param
to default_parse_boot_param. Enable this functionality only on the mv
platform, which is where most of the code is from.
Reviewed by: cognet, Ian Lapore
|
| 237040 |
14-Jun-2012 |
imp |
Modify all the arm platform files to call parse_boot_param passing in
the boot parameters from initarm first thing. parse_boot_param parses
the boot arguments and converts them to the /boot/loader metadata the
rest of the kernel uses. parse_boot_param is a weak alias to
fake_preload_metadata, which all the platforms use now, but may become
more extensive in the future.
Since it is a weak symbol, specific boards may define their own
parse_boot_param to interface to custom boot loaders.
Reviewed by: cognet@, Ian Lapore
|
| 236997 |
13-Jun-2012 |
fabient |
Add ARM callchain support for hwpmc.
Sponsored by: NETASQ
MFC after: 3 days
|
| 236992 |
13-Jun-2012 |
imp |
trim trailing whitespace
|
| 236828 |
10-Jun-2012 |
andrew |
Pull out the common code to initialise proc0 & thread0 from initarm to a
common function.
Reviewed by: imp
|
| 236524 |
03-Jun-2012 |
imp |
Minor rearrangement of the locore <-> initarm interface. Pass in a
structure with the first 4 registers to allow a wider range of boot
loaders to work. Future commits will make use of this to centralize
support for the different loaders.
|
| 236307 |
30-May-2012 |
gber |
Flush D and I caches after setting a breakpoint.
Reviewed by: imp
Obtained from: Semihalf
|
| 235941 |
24-May-2012 |
bz |
MFp4 bz_ipv6_fast:
in_cksum.h required ip.h to be included for struct ip. To be
able to use some general checksum functions like in_addword()
in a non-IPv4 context, limit the (also exported to user space)
IPv4 specific functions to the times, when the ip.h header is
present and IPVERSION is defined (to 4).
We should consider more general checksum (updating) functions
to also allow easier incremental checksum updates in the L3/4
stack and firewalls, as well as ponder further requirements by
certain NIC drivers needing slightly different pseudo values
in offloading cases. Thinking in terms of a better "library".
Sponsored by: The FreeBSD Foundation
Sponsored by: iXsystems
Reviewed by: gnn (as part of the whole)
MFC After: 3 days
|
| 235831 |
23-May-2012 |
fabient |
Soft PMC support for ARM.
Callgraph is not captured, only current location.
Sample system wide profiling: "pmcstat -Sclock.hard -T"
|
| 235609 |
18-May-2012 |
gber |
Add architecture dependent code to support NAND Framework on Marvell SoCs.
Obtained from: Semihalf
Supported by: FreeBSD Foundation, Juniper Networks
|
| 235072 |
06-May-2012 |
imp |
Fix the MACHINE_ARCH for big endian arm to be armeb.
|
| 234785 |
29-Apr-2012 |
dim |
Add a convenience macro for the returns_twice attribute, and apply it to
the prototypes of the appropriate functions (getcontext, savectx,
setjmp, sigsetjmp and vfork).
MFC after: 2 weeks
|
| 234337 |
16-Apr-2012 |
andrew |
Replace the C implementation of __aeabi_read_tp with an assembly version.
This ensures we follow the ABI by preserving registers r1-r3.
Reviewed by: jmallett, imp
|
| 234006 |
07-Apr-2012 |
stas |
- Revert part of r234005, which I did not intend to commit.
Sorry! :(
|
| 234005 |
07-Apr-2012 |
stas |
- Add kernel config file for QEMU-emulated gumstix board.
|
| 233628 |
28-Mar-2012 |
fabient |
Add software PMC support.
New kernel events can be added at various location for sampling or counting.
This will for example allow easy system profiling whatever the processor is
with known tools like pmcstat(8).
Simultaneous usage of software PMC and hardware PMC is possible, for example
looking at the lock acquire failure, page fault while sampling on
instructions.
Sponsored by: NETASQ
MFC after: 1 month
|
| 230475 |
23-Jan-2012 |
das |
Add C11 macros describing subnormal numbers to float.h.
Reviewed by: bde
|
| 230366 |
20-Jan-2012 |
das |
Add parentheses where required. Without them, `sizeof LDBL_MAX'
is a syntax error and shouldn't be, while `1 FLT_ROUNDS' isn't a
syntax error and should be. Thanks to bde for the examples.
|
| 230229 |
16-Jan-2012 |
das |
Fix the value of float_t to match what is implied by FLT_EVAL_METHOD.
|
| 230198 |
16-Jan-2012 |
das |
Fix the definition of FLT_EVAL_METHOD and some minor bugs.
|
| 230191 |
16-Jan-2012 |
das |
Implement FLT_ROUNDS for arm. Some (all?) arm FPUs lack support for
dynamic rounding modes, but FPUless chips that use softfloat can support it
because everything is emulated anyway. (We presently have incomplete
support for hardware FPUs.)
Submitted by: Ian Lepore
|
| 228530 |
15-Dec-2011 |
raj |
ARM pmap fixes:
- Write Buffers have to be drained after write to Page Table even if caches
are in write-through mode.
- Make sure to sync PTE in pmap_zero_page_generic().
Submitted by: Michal Mazur
Reviewed by: cognet
Obtained from: Semihalf
MFC after: 1 month
|
| 228469 |
13-Dec-2011 |
ed |
Replace __signed by signed.
The signed keyword is an integral part of the C syntax. There's no need
to use __signed.
|
| 226607 |
21-Oct-2011 |
das |
People porting FreeBSD to new architectures ought not have to
implement a deprecated FPU control interface in addition to the
standard one. To make this clearer, further deprecate ieeefp.h
by not declaring the function prototypes except on architectures
that implement them already.
Currently i386 and amd64 implement the ieeefp.h interface for
compatibility, and for fp[gs]etprec(), which doesn't exist on
most other hardware. Powerpc, sparc64, and ia64 partially implement
it and probably shouldn't, and other architectures don't implement it
at all.
|
| 226443 |
16-Oct-2011 |
cognet |
Fix 2 bugs :
- A race condition could happen if two threads were using RAS at the same time
as the code didn't reset RAS_END, the RAS code could believe we were not in
a RAS, when we were in fact.
- Using signed value logic to compare addresses wasn't such a good idea.
Many thanks to Ian to investigate on these issues.
Pointy hat to: cognet
PR: arm/161498
Submitted by: Ian Lepore <freebsd At damnhippie DOT dyndns dot org
MFC after: 1 week
|
| 226112 |
07-Oct-2011 |
kib |
Remove unused define.
MFC after: 1 month
|
| 225995 |
04-Oct-2011 |
marcel |
Properly guard definitions of DFLDSIZ, MAXDSIZ, DFLSSIZ, MAXSSIZ and
SGROWSIZ. They can be set in the kernel configuration file.
|
| 225973 |
04-Oct-2011 |
kib |
Convert ARM to the syscallenter/syscallret system call sequence handlers.
Tested by: gber
MFC after: 1 month
|
| 224207 |
19-Jul-2011 |
attilio |
Add the possibility to specify from kernel configs MAXCPU value.
This patch is going to help in cases like mips flavours where you
want a more granular support on MAXCPU.
No MFC is previewed for this patch.
Tested by: pluknet
Approved by: re (kib)
|
| 222813 |
07-Jun-2011 |
attilio |
etire the cpumask_t type and replace it with cpuset_t usage.
This is intended to fix the bug where cpu mask objects are
capped to 32. MAXCPU, then, can now arbitrarely bumped to whatever
value. Anyway, as long as several structures in the kernel are
statically allocated and sized as MAXCPU, it is suggested to keep it
as low as possible for the time being.
Technical notes on this commit itself:
- More functions to handle with cpuset_t objects are introduced.
The most notable are cpusetobj_ffs() (which calculates a ffs(3)
for a cpuset_t object), cpusetobj_strprint() (which prepares a string
representing a cpuset_t object) and cpusetobj_strscan() (which
creates a valid cpuset_t starting from a string representation).
- pc_cpumask and pc_other_cpus are target to be removed soon.
With the moving from cpumask_t to cpuset_t they are now inefficient
and not really useful. Anyway, for the time being, please note that
access to pcpu datas is protected by sched_pin() in order to avoid
migrating the CPU while reading more than one (possible) word
- Please note that size of cpuset_t objects may differ between kernel
and userland. While this is not directly related to the patch itself,
it is good to understand that concept and possibly use the patch
as a reference on how to deal with cpuset_t objects in userland, when
accessing kernland members.
- KTR_CPUMASK is changed and now is represented through a string, to be
set as the example reported in NOTES.
Please additively note that no MAXCPU is bumped in this patch, but
private testing has been done until to MAXCPU=128 on a real 8x8x2(htt)
machine (amd64).
Please note that the FreeBSD version is not yet bumped because of
the upcoming pcpu changes. However, note that this patch is not
targeted for MFC.
People to thank for the time spent on this patch:
- sbruno, pluknet and Nicholas Esborn (nick AT desert DOT net) tested
several revision of the patches and really helped in improving
stability of this work.
- marius fixed several bugs in the sparc64 implementation and reviewed
patches related to ktr.
- jeff and jhb discussed the basic approach followed.
- kib and marcel made targeted review on some specific part of the
patch.
- marius, art, nwhitehorn and andreast reviewed MD specific part of
the patch.
- marius, andreast, gonzo, nwhitehorn and jceel tested MD specific
implementations of the patch.
- Other people have made contributions on other patches that have been
already committed and have been listed separately.
Companies that should be mentioned for having participated at several
degrees:
- Yahoo! for having offered the machines used for testing on big
count of CPUs.
- The FreeBSD Foundation for having sponsored my devsummit attendance,
which has been instrumental.
- Sandvine for having offered offices and infrastructure during
development.
(I really hope I didn't forget anyone, if it happened I apologize in
advance).
|
| 221855 |
13-May-2011 |
mdf |
Move the ZERO_REGION_SIZE to a machine-dependent file, as on many
architectures (i386, for example) the virtual memory space may be
constrained enough that 2MB is a large chunk. Use 64K for arches
other than amd64 and ia64, with special handling for sparc64 due to
differing hardware.
Also commit the comment changes to kmem_init_zero_region() that I
missed due to not saving the file. (Darn the unfamiliar development
environment).
Arch maintainers, please feel free to adjust ZERO_REGION_SIZE as you
see fit.
Requested by: alc
MFC after: 1 week
MFC with: r221853
|
| 219653 |
14-Mar-2011 |
jkim |
Make get_cyclecount(9) little bit more useful where binuptime(9) is used.
|
| 218773 |
17-Feb-2011 |
alc |
Remove pmap fields that are either unused or not fully implemented.
Discussed with: kib
|
| 218482 |
09-Feb-2011 |
jhb |
Whitespace tweak.
|
| 218311 |
05-Feb-2011 |
imp |
phys_addr is a PA not a VA so declare it as a vm_paddr_t not a vm_offset_t.
|
| 218310 |
05-Feb-2011 |
imp |
Make md_tp a register_t not a void *. This will keep us from
accidentally dereferencng it and might be one fewer things to change
if arm64 happens...
Submitted by: rwatson's question on irc...
|
| 218073 |
29-Jan-2011 |
marcel |
Introduce macro FDT_MAP_IRQ to map from an interrupt controller and
interrupt pin pair to a global IRQ number. When multiple PICs exist
on a board, the interrupt pin alone is not unique.
|
| 217515 |
17-Jan-2011 |
jkim |
Add reader/writer lock around mem_range_attr_get() and mem_range_attr_set().
Compile sys/dev/mem/memutil.c for all supported platforms and remove now
unnecessary dev_mem_md_init(). Consistently define mem_range_softc from
mem.c for all platforms. Add missing #include guards for machine/memdev.h
and sys/memrange.h. Clean up some nearby style(9) nits.
MFC after: 1 month
|
| 217290 |
11-Jan-2011 |
marcel |
Don't re-use MODINFOMD_BOOTINFO as MODINFOMD_DTBP. It breaks
compatibility without any means for the kernel to work with
an older loader.
|
| 217192 |
09-Jan-2011 |
kib |
Move repeated MAXSLP definition from machine/vmparam.h to sys/vmmeter.h.
Update the outdated comments describing MAXSLP and the process
selection algorithm for swap out.
Comments wording and reviewed by: alc
|
| 217147 |
08-Jan-2011 |
tijl |
On mixed 32/64 bit architectures (mips, powerpc) use __LP64__ rather than
architecture macros (__mips_n64, __powerpc64__) when 64 bit types (and
corresponding macros) are different from 32 bit. [1]
Correct the type of INT64_MIN, INT64_MAX and UINT64_MAX.
Define (U)INTMAX_C as an alias for (U)INT64_C matching the type definition
for (u)intmax_t. Do this on all architectures for consistency.
Suggested by: bde [1]
Approved by: kib (mentor)
|
| 217146 |
08-Jan-2011 |
tijl |
On 32 bit architectures define (u)int64_t as (unsigned) long long instead
of (unsigned) int __attribute__((__mode__(__DI__))). This aligns better
with macros such as (U)INT64_C, (U)INT64_MAX, etc. which assume (u)int64_t
has type (unsigned) long long.
The mode attribute was used because long long wasn't standardised until
C99. Nowadays compilers should support long long and use of the mode
attribute is discouraged according to GCC Internals documentation.
The type definition has to be marked with __extension__ to support
compilation with "-std=c89 -pedantic".
Discussed with: bde
Approved by: kib (mentor)
|
| 217145 |
08-Jan-2011 |
tijl |
Fix types of some values in machine/_limits.h.
On some architectures UCHAR_MAX and USHRT_MAX had type unsigned int.
However, lacking integer suffixes for types smaller than int, their type
should correspond to that of an object of type unsigned char (or short)
when used in an expression with objects of type int. In that case unsigned
char (short) are promoted to int (i.e. signed) so the type of UCHAR_MAX and
USHRT_MAX should also be int.
Where MIN/MAX constants implicitly have the correct type the suffix has
been removed.
While here, correct some comments.
Reviewed by: bde
Approved by: kib (mentor)
|
| 217128 |
07-Jan-2011 |
tijl |
Remove unused support for 64 bit long on 32 bit architectures.
It was used mainly to discover and fix some 64-bit portability problems
before 64-bit arches were widely available.
Discussed with: bde
Approved by: kib (mentor)
|
| 217097 |
07-Jan-2011 |
kib |
Add AT_STACKPROT elf aux vector. Will be used to inform rtld about the
initial stack protection set by the kernel image activator.
|
| 217032 |
05-Jan-2011 |
imp |
Remove ancient simulation code. Skyeye simulation never really worked
quite right and hasn't been used in ages and is likely broken. QEMU
with GUMSTIX is a more promising road to FreeBSD/arm in emulation
anyway.
Reviewed by: cognet@
|
| 216143 |
03-Dec-2010 |
brucec |
Revert r216134. This checkin broke platforms where bus_space are macros:
they need to be a single statement, and do { } while (0) doesn't work in this
situation so revert until a solution can be devised.
|
| 216134 |
02-Dec-2010 |
brucec |
Disallow passing in a count of zero bytes to the bus_space(9) functions.
Passing a count of zero on i386 and amd64 for [I386|AMD64]_BUS_SPACE_MEM
causes a crash/hang since the 'loop' instruction decrements the counter
before checking if it's zero.
PR: kern/80980
Discussed with: jhb
|
| 215054 |
09-Nov-2010 |
jhb |
- Remove <machine/mutex.h>. Most of the headers were empty, and the
contents of the ones that were not empty were stale and unused.
- Now that <machine/mutex.h> no longer exists, there is no need to allow it
to override various helper macros in <sys/mutex.h>.
- Rename various helper macros for low-level operations on mutexes to live
in the _mtx_* or __mtx_* namespaces. While here, change the names to more
closely match the real API functions they are backing.
- Drop support for including <sys/mutex.h> in assembly source files.
Suggested by: bde (1, 2)
|
| 215031 |
09-Nov-2010 |
kevlo |
Minor cosmetic changes
|
| 214972 |
08-Nov-2010 |
kevlo |
Intel IXP425 SoC is based on the ARMv5TE architecture
MFC after: 3 days
|
| 212825 |
18-Sep-2010 |
mav |
Add basic cpu_sleep() support for Marvell SoCs. This drops my SheevaPlug's
heatsink termperature in open air from 49C to 43C when idle.
|
| 211412 |
17-Aug-2010 |
kib |
Supply some useful information to the started image using ELF aux vectors.
In particular, provide pagesize and pagesizes array, the canary value
for SSP use, number of host CPUs and osreldate.
Tested by: marius (sparc64)
MFC after: 1 month
|
| 211197 |
11-Aug-2010 |
jhb |
Update various places that store or manipulate CPU masks to use cpumask_t
instead of int or u_int. Since cpumask_t is currently u_int on all
platforms this should just be a cosmetic change.
|
| 210550 |
27-Jul-2010 |
jhb |
Very rough first cut at NUMA support for the physical page allocator. For
now it uses a very dumb first-touch allocation policy. This will change in
the future.
- Each architecture indicates the maximum number of supported memory domains
via a new VM_NDOMAIN parameter in <machine/vmparam.h>.
- Each cpu now has a PCPU_GET(domain) member to indicate the memory domain
a CPU belongs to. Domain values are dense and numbered from 0.
- When a platform supports multiple domains, the default freelist
(VM_FREELIST_DEFAULT) is split up into N freelists, one for each domain.
The MD code is required to populate an array of mem_affinity structures.
Each entry in the array defines a range of memory (start and end) and a
domain for the range. Multiple entries may be present for a single
domain. The list is terminated by an entry where all fields are zero.
This array of structures is used to split up phys_avail[] regions that
fall in VM_FREELIST_DEFAULT into per-domain freelists.
- Each memory domain has a separate lookup-array of freelists that is
used when fulfulling a physical memory allocation. Right now the
per-domain freelists are listed in a round-robin order for each domain.
In the future a table such as the ACPI SLIT table may be used to order
the per-domain lookup lists based on the penalty for each memory domain
relative to a specific domain. The lookup lists may be examined via a
new vm.phys.lookup_lists sysctl.
- The first-touch policy is implemented by using PCPU_GET(domain) to
pick a lookup list when allocating memory.
Reviewed by: alc
|
| 210247 |
19-Jul-2010 |
raj |
Eliminate FDT_IMMR_VA define.
This removes platform dependencies from <machine>/fdt.h for the benfit of
portability.
|
| 209909 |
11-Jul-2010 |
raj |
Get rid of bootinfo for good in loader (U-Boot-based) and ARM.
For FDT-enabled platforms the device tree is a modern replacement for bootinfo
config data.
|
| 209161 |
14-Jun-2010 |
raj |
Temporarily bring back the ARM bootinfo (and make tinderbox happy).
BI will be eliminated for good when powerpc transition to FDT is complete.
|
| 209131 |
13-Jun-2010 |
raj |
Convert Marvell ARM platforms to FDT convention.
The following systems are involved:
- DB-88F5182
- DB-88F5281
- DB-88F6281
- DB-78100
- SheevaPlug
This overhaul covers the following major changes:
- All integrated peripherals drivers for Marvell ARM SoC, which are
currently in the FreeBSD source tree are reworked and adjusted so they
derive config data out of the device tree blob (instead of hard coded /
tabelarized values).
- Since the common FDT infrastrucutre (fdtbus, simplebus) is used we say
good by to obio / mbus drivers and numerous hard-coded config data.
Note that world needs to be built WITH_FDT for the affected platforms.
Reviewed by: imp
Sponsored by: The FreeBSD Foundation.
|
| 209130 |
13-Jun-2010 |
raj |
Initial FDT infrastructure elements for ARM.
Reviewed by: imp
Sponsored by: The FreeBSD Foundation
|
| 208538 |
25-May-2010 |
raj |
Initial loader(8) support for Flattened Device Tree.
o This is disabled by default for now, and can be enabled using WITH_FDT at
build time.
o Tested with ARM and PowerPC.
Reviewed by: imp
Sponsored by: The FreeBSD Foundation
|
| 208052 |
14-May-2010 |
cognet |
Catchup with new prototype for db_printf().
|
| 207954 |
12-May-2010 |
kevlo |
The FA526 belongs to the ARM9TDMI family
|
| 207611 |
04-May-2010 |
kevlo |
Add support for FA626TE.
Tested on GM8181 development board.
|
| 207410 |
30-Apr-2010 |
kmacy |
On Alan's advice, rather than do a wholesale conversion on a single
architecture from page queue lock to a hashed array of page locks
(based on a patch by Jeff Roberson), I've implemented page lock
support in the MI code and have only moved vm_page's hold_count
out from under page queue mutex to page lock. This changes
pmap_extract_and_hold on all pmaps.
Supported by: Bitgravity Inc.
Discussed with: alc, jeffr, and kib
|
| 207269 |
27-Apr-2010 |
kib |
Style: use #define<TAB> instead of #define<SPACE>.
Noted by: bde, pluknet gmail com
MFC after: 11 days
|
| 207152 |
24-Apr-2010 |
kib |
Move the constants specifying the size of struct kinfo_proc into
machine-specific header files. Add KINFO_PROC32_SIZE for struct
kinfo_proc32 for architectures providing COMPAT_FREEBSD32. Add
CTASSERT for the size of struct kinfo_proc32.
Submitted by: pluknet
Reviewed by: imp, jhb, nwhitehorn
MFC after: 2 weeks
|
| 206404 |
08-Apr-2010 |
imp |
Add BUS_SPACE_UNRESTRICTED and define it to be ~0, just like all the
other platforms.
|
| 204122 |
20-Feb-2010 |
kevlo |
Show the cpu info for fa526
Submitted by: Yohanes Nugroho <yohanes at gmail dot com>
|
| 204121 |
20-Feb-2010 |
kevlo |
Correct both FA526/FA626TE cpu ids since the cpu id is always
masked with 0xfffffff0
|
| 203974 |
16-Feb-2010 |
imp |
The NetBSD Foundation has granted permission to remove clauses 3 and 4.
Obtained from: NetBSD
|
| 203852 |
14-Feb-2010 |
kevlo |
Correct cpu id for FA526.
While I'm here, add cpu id for FA626TE.
|
| 201468 |
04-Jan-2010 |
rpaulo |
Add support for Cavium Econa CNS11XX ARM boards. These boards were
previously know by StarSemi STR9104.
Tested by the submitter on an Emprex NSD-100 board.
Submitted by: Yohanes Nugroho <yohanes at gmail.com>
Reviewed by: freebsd-arm, stas
Obtained from: //depot/projects/str91xx/...
|
| 200928 |
23-Dec-2009 |
rpaulo |
Intel XScale hwpmc(4) support.
This brings hwpmc(4) support for 2nd and 3rd generation XScale cores.
Right now it's enabled by default to make sure we test this a bit.
When the time comes it can be disabled by default.
Tested on Gateworks boards.
A man page is coming.
Obtained from: //depot/user/rpaulo/xscalepmc/...
|
| 197933 |
10-Oct-2009 |
kib |
Define architectural load bases for PIE binaries. Addresses were selected
by looking at the bases used for non-relocatable executables by gnu ld(1),
and adjusting it slightly.
Discussed with: bz
Reviewed by: kan
Tested by: bz (i386, amd64), bsam (linux)
MFC after: some time
|
| 197523 |
26-Sep-2009 |
rpaulo |
Promote the cpu_class local variable to global and expose it in md_var.h
Reviewed by: freebsd-arm
|
| 197316 |
18-Sep-2009 |
alc |
Add a new sysctl for reporting all of the supported page sizes.
Reviewed by: jhb
MFC after: 3 weeks
|
| 196994 |
08-Sep-2009 |
phk |
Get rid of the _NO_NAMESPACE_POLLUTION kludge by creating an
architecture specific include file containing the _ALIGN*
stuff which <sys/socket.h> needs.
|
| 195649 |
12-Jul-2009 |
alc |
Add support to the virtual memory system for configuring machine-
dependent memory attributes:
Rename vm_cache_mode_t to vm_memattr_t. The new name reflects the
fact that there are machine-dependent memory attributes that have
nothing to do with controlling the cache's behavior.
Introduce vm_object_set_memattr() for setting the default memory
attributes that will be given to an object's pages.
Introduce and use pmap_page_{get,set}_memattr() for getting and
setting a page's machine-dependent memory attributes. Add full
support for these functions on amd64 and i386 and stubs for them on
the other architectures. The function pmap_page_set_memattr() is also
responsible for any other machine-dependent aspects of changing a
page's memory attributes, such as flushing the cache or updating the
direct map. The uses include kmem_alloc_contig(), vm_page_alloc(),
and the device pager:
kmem_alloc_contig() can now be used to allocate kernel memory with
non-default memory attributes on amd64 and i386.
vm_page_alloc() and the device pager will set the memory attributes
for the real or fictitious page according to the object's default
memory attributes.
Update the various pmap functions on amd64 and i386 that map pages to
incorporate each page's memory attributes in the mapping.
Notes: (1) Inherent to this design are safety features that prevent
the specification of inconsistent memory attributes by different
mappings on amd64 and i386. In addition, the device pager provides a
warning when a device driver creates a fictitious page with memory
attributes that are inconsistent with the real page that the
fictitious page is an alias for. (2) Storing the machine-dependent
memory attributes for amd64 and i386 as a dedicated "int" in "struct
md_page" represents a compromise between space efficiency and the ease
of MFCing these changes to RELENG_7.
In collaboration with: jhb
Approved by: re (kib)
|
| 195376 |
05-Jul-2009 |
sam |
Cleanup ALIGNED_POINTER:
o add to platforms where it was missing (arm, i386, powerpc, sparc64, sun4v)
o define as "1" on amd64 and i386 where there is no restriction
o make the type returned consistent with ALIGN
o remove _ALIGNED_POINTER
o make associated comments consistent
Reviewed by: bde, imp, marcel
Approved by: re (kensmith)
|
| 195060 |
26-Jun-2009 |
alc |
Correct the #endif comment.
Noticed by: jmallett
Approved by: re (kib)
|
| 195033 |
26-Jun-2009 |
alc |
This change is the next step in implementing the cache control functionality
required by video card drivers. Specifically, this change introduces
vm_cache_mode_t with an appropriate VM_CACHE_DEFAULT definition on all
architectures. In addition, this changes adds a vm_cache_mode_t parameter
to kmem_alloc_contig() and vm_phys_alloc_contig(). These will be the
interfaces for allocating mapped kernel memory and physical memory,
respectively, with non-default cache modes.
In collaboration with: jhb
|
| 194459 |
18-Jun-2009 |
thompsa |
Track the kernel mapping of a physical page by a new entry in vm_page
structure. When the page is shared, the kernel mapping becomes a special
type of managed page to force the cache off the page mappings. This is
needed to avoid stale entries on all ARM VIVT caches, and VIPT caches
with cache color issue.
Submitted by: Mark Tinguely
Reviewed by: alc
Tested by: Grzegorz Bernacki, thompsa
|
| 193847 |
09-Jun-2009 |
marcel |
Pass the previously returned IRQ back to arm_get_next_irq() so that
the implementation can guarantee forward progress in the event of
a stuck interrupt or interrupt storm. This is especially critical
for fast interrupt handlers, as they can cause a hard hang in that
case. When first called, arm_get_next_irq() is passed -1.
Obtained from: Juniper Networks, Inc.
|
| 191873 |
07-May-2009 |
alc |
Define the kernel pmap in the same way on arm as on every other
architecture.
Eliminate an unused definition.
Tested by: cognet
|
| 191309 |
20-Apr-2009 |
rwatson |
Don't conditionally define CACHE_LINE_SHIFT, as we anticipate sizing
a fair number of static data structures, making this an unlikely
option to try to change without also changing source code. [1]
Change default cache line size on ia64, sparc64, and sun4v to 128
bytes, as this was what rtld-elf was already using on those
platforms. [2]
Suggested by: bde [1], jhb [2]
MFC after: 2 weeks
|
| 191278 |
19-Apr-2009 |
rwatson |
Add description and cautionary note regarding CACHE_LINE_SIZE.
MFC after: 2 weeks
Suggested by: alc
|
| 191276 |
19-Apr-2009 |
rwatson |
For each architecture, define CACHE_LINE_SHIFT and a derived
CACHE_LINE_SIZE constant. These constants are intended to
over-estimate the cache line size, and be used at compile-time
when a run-time tuning alternative isn't appropriate or
available.
Defaults for all architectures are 64 bytes, except powerpc
where it is 128 bytes (used on G5 systems).
MFC after: 2 weeks
Discussed on: arch@
|
| 190705 |
04-Apr-2009 |
alc |
Retire VM_PROT_READ_IS_EXEC. It was intended to be a micro-optimization,
but I see no benefit from it today.
VM_PROT_READ_IS_EXEC was only intended for use on processors that do not
distinguish between read and execute permission. On an mmap(2) or
mprotect(2), it automatically added execute permission if the caller
specified permissions included read permission. The hope was that this
would reduce the number of vm map entries needed to implement an address
space because there would be fewer neighboring vm map entries that differed
only in the presence or absence of VM_PROT_EXECUTE. (See vm/vm_mmap.c
revision 1.56.)
Today, I don't see any real applications that benefit from
VM_PROT_READ_IS_EXEC. In any case, vm map entries are now organized
as a self-adjusting binary search tree instead of an ordered list. So,
the need for coalescing vm map entries is not as great as it once was.
|
| 190603 |
31-Mar-2009 |
cognet |
Fix the userland, RAS, version of atomic_fetchadd_32 :
return the correct value, and do not store the wrong one in the supplied
pointer.
Submitted by: Mark Tinguely <tinguely casselton net>
|
| 189926 |
17-Mar-2009 |
kib |
Add AT_EXECPATH ELF auxinfo entry type. The value's a_ptr is a pointer
to the full path of the image that is being executed.
Increase AT_COUNT.
Remove no longer true comment about types used in Linux ELF binaries,
listed types contain FreeBSD-specific entries.
Reviewed by: kan
|
| 188540 |
12-Feb-2009 |
cognet |
To prevent various race conditions in the RAS code, store and restore the
values in ARM_RAS_START and ARM_RAS_END at context switch time.
MFC after: 1 week
|
| 188085 |
03-Feb-2009 |
sam |
force atomic_cmpset_ptr types to match atomic_cmpset_32;
this matches what powerpc does
Submitted by: stass
MFC after: 2 weeks
|
| 187592 |
22-Jan-2009 |
cognet |
Add a comment explaining what ARM_KERN_DIRECTMAP is all about.
Suggested by: raj
|
| 186933 |
09-Jan-2009 |
raj |
Fix confusing naming of Marvell ARM CPU specific routines.
- The contents of 'feroceon_cpufuncs' dispatch table was really dedicated for the
new Sheeva CPU (in 88F6xxx and MV-78xxx SOCs), and NOT Feroceon.
- Feroceon CPU (in 88F5xxx SOCs) appears as a regular ARM926EJ-S core and does
not require dedicated routines.
This will be accompanied by a file rename commit.
|
| 186461 |
23-Dec-2008 |
marcel |
Add support for the FPA floating-point format on ARM. The
FPA floating-point format is identical to the VFP format,
but is always stored in big-endian.
Introduce _IEEE_WORD_ORDER to describe the byte-order of
the FP representation.
Obtained from: Juniper Networks, Inc
|
| 186417 |
23-Dec-2008 |
sam |
add IXP465 and generic IXP425 definition
|
| 186352 |
20-Dec-2008 |
sam |
Merge support for Gateworks Cambria boards:
o add support for IXP435 cpu's (e.g. 64 irq's)
o add support for Cambria-specific devices: npe, led's (front panel and
octal latch), ehci, mcu, ide cf
o redo memory mapping for xscale/ixp4xx boards: previously memory
was assumed aliased to 0x10000000 but this appears to be true only
for ixp425 systems and breaks operation on others; rework so memory
is assumed to start at 0
o rework NPE configuration support to use NPE id's instead of port #'s;
these changes also rename the associated MAC's to follow the NPE's
they are attached to
o update npe firmware to latest rev (same license) and update default fw
imageid's to match; in particular this adds NPE-A and crypto support
o re-style NPE fw handling code and add a console msg identifying the
attributes of the loaded fw
o fix numerous problems with handling failures during npe setup
o fix npe rx q setup; need to spin waiting for mailbox responses during
early boot stages as qmgr interrupts are not delivered; this fixes
the problem where all 8 traffic classifications were not tied to the
rx q (and eliminates the console msg "remember to fix rx q setup")
o add DELAY to npe MII wait logic for IXP435
o strip down builtin phys->virt address translation table in resource
handling to just those resources that require it and add a console msg
to alert people when this (kludge) table needs to be extended
o purge a bunch of dead netbsd-ism's
o cleanup avila led driver
o add Cambria support to boot2 and rework code for better multi-board support
Notes:
1. NPE-A doesn't work and causes NPE-C to stop working; it is disabled
in the hints
2. USB isn't working yet; controller communicates ok but device
discovery fails
3. Cambria support must be configured separately from IXP425 boards;
multi-board support is TBD
Sponsored by: Hobnob, Gateworks (board donation)
Reviewed by: imp
|
| 186212 |
17-Dec-2008 |
imp |
AT_DEBUG and AT_BRK were OBE like 10 years ago, so retire them.
Reviewed by: peter
|
| 185162 |
22-Nov-2008 |
kmacy |
- bump __FreeBSD version to reflect added buf_ring, memory barriers,
and ifnet functions
- add memory barriers to <machine/atomic.h>
- update drivers to only conditionally define their own
- add lockless producer / consumer ring buffer
- remove ring buffer implementation from cxgb and update its callers
- add if_transmit(struct ifnet *ifp, struct mbuf *m) to ifnet to
allow drivers to efficiently manage multiple hardware queues
(i.e. not serialize all packets through one ifq)
- expose if_qflush to allow drivers to flush any driver managed queues
This work was supported by Bitgravity Inc. and Chelsio Inc.
|
| 184728 |
06-Nov-2008 |
raj |
Support kernel crash mini dumps on ARM architecture.
Obtained from: Juniper Networks, Semihalf
|
| 183878 |
14-Oct-2008 |
raj |
Initial support of loader(8) for ARM machines running U-Boot.
This uses the common U-Boot support lib (sys/boot/uboot, already used on
FreeBSD/powerpc), and assumes the underlying firmware has the modern API for
stand-alone apps enabled in the config (CONFIG_API).
Only netbooting is supported at the moment.
Obtained from: Marvell, Semihalf
|
| 183840 |
13-Oct-2008 |
raj |
Introduce basic support for Marvell families of system-on-chip ARM devices:
* Orion
- 88F5181
- 88F5182
- 88F5281
* Kirkwood
- 88F6281
* Discovery
- MV78100
The above families of SOCs are built around CPU cores compliant with ARMv5TE
instruction set architecture definition. They share a number of integrated
peripherals. This commit brings support for the following basic elements:
* GPIO
* Interrupt controller
* L1, L2 cache
* Timers, watchdog, RTC
* TWSI (I2C)
* UART
Other peripherals drivers will be introduced separately.
Reviewed by: imp, marcel, stass (Thanks guys!)
Obtained from: Marvell, Semihalf
|
| 183835 |
13-Oct-2008 |
raj |
Introduce low-level support for new Marvell core CPUs: 88FR131, 88FR571.
They are compliant with ARMv5TE and integrated on 88F6281 (Kirkwood) and
MV78100 (Discovery) system-on-chip families.
Obtained from: Marvell, Semihalf
|
| 182945 |
11-Sep-2008 |
cognet |
Remove the unused field "pc_prvspace" from the MD fields for the struct
pcpu. There's not even a thing such as a "struct pcup".
While I'm there, remove a comment that makes no sense for arm.
Spotted out by: Mark Tinguely
|
| 182933 |
11-Sep-2008 |
raj |
ARM interrupts improvements.
- Fix nexus_setup_intr() abuse of setting up multiple IRQs in one go. Calling
arm_setup_irqhandler() in loop is bogus, as there's just one cookie given
from the caller and it is overwritten in each iteration so that only the
last handler's cookie value prevails.
- Proper intr masking/unmasking handling: the IRQ source is masked at PIC level
only after the last handler has been removed from the list.
Reviewed by: cognet, imp, sam, stass
Obtained from: Grzegorz Bernacki gjb ! semihalf dot com
|
| 182086 |
23-Aug-2008 |
imp |
Whitespace nit.
|
| 181875 |
19-Aug-2008 |
jhb |
Export 'struct pcpu' to userland w/o requiring _KERNEL. A few ports
already define _KERNEL to get to this and I'm about to add hooks to
libkvm to access per-CPU data.
MFC after: 1 week
|
| 181253 |
03-Aug-2008 |
cognet |
Add "add pc, whatever" as a branch instruction, we use it in memcpy().
MFC after: 3 days
|
| 181222 |
03-Aug-2008 |
cognet |
Add blx as a branch instruction.
MFC after: 3 days
|
| 181174 |
02-Aug-2008 |
cognet |
Add yet another branch instruction.
Obtained from: NetBSD
MFC after: 3 days
|
| 179990 |
25-Jun-2008 |
ed |
Remove the unused major/minor numbers from iodev and memdev.
Now that st_rdev is being automatically generated by the kernel, there
is no need to define static major/minor numbers for the iodev and
memdev. We still need the minor numbers for the memdev, however, to
distinguish between /dev/mem and /dev/kmem.
Approved by: philip (mentor)
|
| 179595 |
06-Jun-2008 |
benno |
Support for the XScale PXA255 SoC as found on the Gumstix Basix and Connex
boards. This is enough to net-boot to multiuser.
Also supported is the SMSC LAN91C111 parts used on the netCF, netDUO and netMMC
add-on boards.
I'll be putting some instructions on how to boot this on the Gumstix boards
online soon.
This is still fairly rough and will be refined over time but I felt it was
better to get this out there where other people can help out.
|
| 178366 |
20-Apr-2008 |
cognet |
On the AT91, we need to write on the EOI register after we handle an
interrupt. So, add a new function pointer, arm_post_filter, which defaults
to NULL, and which will be used as the post_filter arg for
intr_event_create(). Set it properly for the AT91, so that it boots again.
Reported by: hps
|
| 177883 |
03-Apr-2008 |
imp |
Take the first baby step towards unifying and cleaning up arminit():
- Pull all the code to deal with the trampoline stuff into one
centeralized place and use it from everywhere.
- Some minor style tidiness
Reviewed by: tinguely
|
| 177661 |
27-Mar-2008 |
jb |
When building a kernel module, define MAXCPU the same as SMP so
that modules work with and without SMP.
|
| 176885 |
06-Mar-2008 |
cognet |
Remove unused pv_list_count from the vm_page, and pm_count from the struct
pmap.
Submitted by: Mark Tinguely
|
| 176589 |
26-Feb-2008 |
rwatson |
Remove errant % in license comment.
MFC after: 3 days
|
| 175982 |
05-Feb-2008 |
raj |
Improve ARM_TP_ADDRESS and RAS area.
De-hardcode usage of ARM_TP_ADDRESS and RAS local storage, and move this
special purpose page to a more convenient place i.e. after the vectors high
page, more towards the end of address space. Previous location (0xe000_0000)
caused grief if KVA was to go beyond the default limit.
Note that ARM world rebuilding is required after this change since the
location of ARM_TP_ADDRESS is shared between kernel and userland.
Submitted by: Grzegorz Bernacki (gjb AT semihalf dot com)
Reviewed by: imp
Approved by: cognet (mentor)
|
| 175840 |
31-Jan-2008 |
cognet |
Bring in the nice work from Mark Tinguely on arm pmap.
The only downside is that it renames pmap_vac_me_harder() to pmap_fix_cache().
From Mark's email on -arm :
pmap_get_vac_flags(), pmap_vac_me_harder(), pmap_vac_me_kpmap(), and
pmap_vac_me_user() has been rewritten as pmap_fix_cache() to be more
efficient in the kernel map case. I also removed the reference to
the md.kro_mappings, md.krw_mappings, md.uro_mappings, and md.urw_mappings
counts.
In pmap_clearbit(), we can also skip over tests and writeback/invalidations
in the PVF_MOD and PVF_REF cases if those bits are not set in the pv_flag.
PVF_WRITE will turn caching back on and remove the PV_MOD bit.
In pmap_nuke_pv(), the vm_page_flag_clear(pg, PG_WRITEABLE) has been moved
to the pmap_fix_cache().
We can be more agressive in attempting to turn caching back on by calling
pmap_fix_cache() at times that may be appropriate to turn cache on
(a kernel mapping has been removed, a write has been removed or a read
has been removed and we know the mapping does not have multiple write
mappings to a page).
In pmap_remove_pages() the cpu_idcache_wbinv_all() is moved to happen
before the page tables are NULLed because the caches are virtually
indexed and virtually tagged.
In pmap_remove_all(), the pmap_remove_write(m) is added before the
page tables are NULLed because the caches are virtually indexed and
virtually tagged. This also removes the need for the caches fixing routine
(whichever is being used pmap_vac_me_harder() or pmap_fix_cache()) to be
called on any of these mappings.
In pmap_remove(), I simplified the cache cleaning process and removed
extra TLB removals. Basically if more than PMAP_REMOVE_CLEAN_LIST_SIZE
are removed, then just flush the entire cache.
|
| 174938 |
27-Dec-2007 |
alc |
Add configuration knobs for the superpage reservation system. Initially,
the reservation will only be enabled on amd64.
|
| 174405 |
07-Dec-2007 |
jkoshy |
Add stubs to unbreak LINT.
|
| 174195 |
02-Dec-2007 |
rwatson |
Break out stack(9) from ddb(4):
- Introduce per-architecture stack_machdep.c to hold stack_save(9).
- Introduce per-architecture machine/stack.h to capture any common
definitions required between db_trace.c and stack_machdep.c.
- Add new kernel option "options STACK"; we will build in stack(9) if it is
defined, or also if "options DDB" is defined to provide compatibility
with existing users of stack(9).
Add new stack_save_td(9) function, which allows the capture of a stacktrace
of another thread rather than the current thread, which the existing
stack_save(9) was limited to. It requires that the thread be neither
swapped out nor running, which is the responsibility of the consumer to
enforce.
Update stack(9) man page.
Build tested: amd64, arm, i386, ia64, powerpc, sparc64, sun4v
Runtime tested: amd64 (rwatson), arm (cognet), i386 (rwatson)
|
| 174170 |
02-Dec-2007 |
cognet |
Close a race.
The RAS implementation would set the end address, then the start
address. These were used by the kernel to restart a RAS sequence if
it was interrupted. When the thread switching code ran, it would
check these values and adjust the PC and clear them if it did.
However, there's a small flaw in this scheme. Thread T1, sets the end
address and gets preempted. Thread T2 runs and also does a RAS
operation. This resets end to zero. Thread T1 now runs again and
sets start and then begins the RAS sequence, but is preempted before
the RAS sequence executes its last instruction. The kernel code that
would ordinarily restart the RAS sequence doesn't because the PC isn't
between start and 0, so the PC isn't set to the start of the sequence.
So when T1 is resumed again, it is at the wrong location for RAS to
produce the correct results. This causes the wrong results for the
atomic sequence.
The window for the first race is 3 instructions. The window for the
second race is 5-10 instructions depending on the atomic operation.
This makes this failure fairly rare and hard to reproduce.
Mutexs are implemented in libthr using atomic operations. When the
above race would occur, a lock could get stuck locked, causing many
downstream problems, as you might expect.
Also, make sure to reset the start and end address when doing a syscall, or
a malicious process could set them before doing a syscall.
Reviewed by: imp, ups (thanks guys)
Pointy hat to: cognet
MFC After: 3 days
|
| 173999 |
27-Nov-2007 |
cognet |
In atomic_fetchadd_32(), do not blindly increase the value of %3.
It should just contain the value we want to add, as if we're interrupted
between the add and the str, we will restart from the beginning. Just use
a register we can scratch instead.
MFC After: 1 week
|
| 173249 |
01-Nov-2007 |
kevlo |
__CPU_XSCALE_PXA2XX -> CPU_XSCALE_PXA2X0
|
| 172738 |
18-Oct-2007 |
imp |
Merge support from p4 (from NetBSD) for arm9e and arm10, arm11 cores. Not
yet connected to the build, but reduces diffs to p4 repo.
Obtained from: NetBSD
|
| 172734 |
18-Oct-2007 |
imp |
Merge definitions for ARM9E, ARM10 and ARM11 processors from p4 (which
got them from NetBSD).
|
| 172613 |
13-Oct-2007 |
cognet |
Define _ARM_ARCH_5E too, so that we know if pld/strd/ldrd are available.
MFC After: 3 days
|
| 172317 |
25-Sep-2007 |
alc |
Change the management of cached pages (PQ_CACHE) in two fundamental
ways:
(1) Cached pages are no longer kept in the object's resident page
splay tree and memq. Instead, they are kept in a separate per-object
splay tree of cached pages. However, access to this new per-object
splay tree is synchronized by the _free_ page queues lock, not to be
confused with the heavily contended page queues lock. Consequently, a
cached page can be reclaimed by vm_page_alloc(9) without acquiring the
object's lock or the page queues lock.
This solves a problem independently reported by tegge@ and Isilon.
Specifically, they observed the page daemon consuming a great deal of
CPU time because of pages bouncing back and forth between the cache
queue (PQ_CACHE) and the inactive queue (PQ_INACTIVE). The source of
this problem turned out to be a deadlock avoidance strategy employed
when selecting a cached page to reclaim in vm_page_select_cache().
However, the root cause was really that reclaiming a cached page
required the acquisition of an object lock while the page queues lock
was already held. Thus, this change addresses the problem at its
root, by eliminating the need to acquire the object's lock.
Moreover, keeping cached pages in the object's primary splay tree and
memq was, in effect, optimizing for the uncommon case. Cached pages
are reclaimed far, far more often than they are reactivated. Instead,
this change makes reclamation cheaper, especially in terms of
synchronization overhead, and reactivation more expensive, because
reactivated pages will have to be reentered into the object's primary
splay tree and memq.
(2) Cached pages are now stored alongside free pages in the physical
memory allocator's buddy queues, increasing the likelihood that large
allocations of contiguous physical memory (i.e., superpages) will
succeed.
Finally, as a result of this change long-standing restrictions on when
and where a cached page can be reclaimed and returned by
vm_page_alloc(9) are eliminated. Specifically, calls to
vm_page_alloc(9) specifying VM_ALLOC_INTERRUPT can now reclaim and
return a formerly cached page. Consequently, a call to malloc(9)
specifying M_NOWAIT is less likely to fail.
Discussed with: many over the course of the summer, including jeff@,
Justin Husted @ Isilon, peter@, tegge@
Tested by: an earlier version by kris@
Approved by: re (kensmith)
|
| 172296 |
22-Sep-2007 |
cognet |
Twist the RAS logic a bit to avoid branching.
MFC After: 1 week
Approved by: re (blanket)
|
| 172104 |
09-Sep-2007 |
cognet |
In __bswap16_var(), make sure the 16 upper bits are cleared; while
optimizing, gcc4 doesn't always do so.
Reported by: Nathan Whitehorn
Approved by: re (blanket)
|
| 171630 |
27-Jul-2007 |
cognet |
XScale core 3 definitions.
Approved by: re (blanket)
|
| 171621 |
27-Jul-2007 |
cognet |
Fix the cache mode description.
Approved by: re (blanket)
|
| 171620 |
27-Jul-2007 |
cognet |
Properly handle supersections.
Make sure we cache entries in the L2 cache.
Approved by: re (blanket)
|
| 171618 |
27-Jul-2007 |
cognet |
Add a new set of functions to handle L2 cache. Make them no-op for every
CPU except Xscale core 3.
Approved by: re (blanket)
|
| 170827 |
16-Jun-2007 |
cognet |
The iop34x has 128 interrupts.
|
| 170582 |
11-Jun-2007 |
cognet |
Introduce pmap_kenter_supersection(), which maps 16MB super-sections into
the kernel pmap.
Document a bit more the behavior of the xscale core 3.
|
| 170473 |
09-Jun-2007 |
marcel |
Add kdb_cpu_sync_icache(), intended to synchronize instruction
caches with data caches after writing to memory. This typically
is required to make breakpoints work on ia64 and powerpc. For
those architectures the function is implemented.
|
| 170388 |
06-Jun-2007 |
jeff |
- PCPU_ADD is no longer spelled with LAZY_ in the middle.
Submitted by: attilio
|
| 170291 |
04-Jun-2007 |
attilio |
Rework the PCPU_* (MD) interface:
- Rename PCPU_LAZY_INC into PCPU_INC
- Add the PCPU_ADD interface which just does an add on the pcpu member
given a specific value.
Note that for most architectures PCPU_INC and PCPU_ADD are not safe.
This is a point that needs some discussions/work in the next days.
Reviewed by: alc, bde
Approved by: jeff (mentor)
|
| 170277 |
04-Jun-2007 |
alc |
Add the machine-specific definitions for configuring the new physical
memory allocator.
Approved by: re
|
| 170072 |
28-May-2007 |
alc |
Eliminate some unused definitions that came from NetBSD.
|
| 169768 |
19-May-2007 |
cognet |
Use __mcount() instead of _mcount() to reduce diffs with NetBSD.
|
| 169756 |
19-May-2007 |
cognet |
Switch the kernel's pmap domain from 15 to 0.
This should be a no-op, and this is needed for xscale core 3 supersections
support, as they are always part of the domain 0
|
| 169291 |
05-May-2007 |
alc |
Define every architecture as either VM_PHYSSEG_DENSE or
VM_PHYSSEG_SPARSE depending on whether the physical address space is
densely or sparsely populated with memory. The effect of this
definition is to determine which of two implementations of
vm_page_array and PHYS_TO_VM_PAGE() is used. The legacy
implementation is obtained by defining VM_PHYSSEG_DENSE, and a new
implementation that trades off time for space is obtained by defining
VM_PHYSSEG_SPARSE. For now, all architectures except for ia64 and
sparc64 define VM_PHYSSEG_DENSE. Defining VM_PHYSSEG_SPARSE on ia64
allows the entirety of my Itanium 2's memory to be used. Previously,
only the first 1 GB could be used. Defining VM_PHYSSEG_SPARSE on
sparc64 allows USIIIi-based systems to boot without crashing.
This change is a combination of Nathan Whitehorn's patch and my own
work in perforce.
Discussed with: kmacy, marius, Nathan Whitehorn
PR: 112194
|
| 167752 |
21-Mar-2007 |
kevlo |
Remove __P
|
| 167429 |
11-Mar-2007 |
alc |
Push down the implementation of PCPU_LAZY_INC() into the machine-dependent
header file. Reimplement PCPU_LAZY_INC() on amd64 and i386 making it
atomic with respect to interrupts.
Reviewed by: bde, jhb
|
| 166901 |
23-Feb-2007 |
piso |
o break newbus api: add a new argument of type driver_filter_t to
bus_setup_intr()
o add an int return code to all fast handlers
o retire INTR_FAST/IH_FAST
For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current
Reviewed by: many
Approved by: re@
|
| 166063 |
17-Jan-2007 |
cognet |
- Add bounce pages for arm, largely based on the i386 implementation.
- Add a default parent dma tag, similar to what has been done for sparc64.
- Before invalidating the dcache in POSTREAD, save the bits which are in the
same cachelines than our buffers, but not part of it, and restore them after
the invalidation.
|
| 165786 |
05-Jan-2007 |
ticso |
MFp4: Add missing atomic functions
Based on a patch by: des
|
| 164777 |
30-Nov-2006 |
cognet |
Introduce CPU_XSCALE_CORE3, as XScale Core 3 is significally different than
regular Xscale (it has no mini data cache, has armv6-style 16MB
supersections, and can address 36bits).
Define it for i81342.
|
| 164424 |
19-Nov-2006 |
sam |
correct bus space unmap prototype
Reviewed by: cognet, imp
MFC after: 1 month
|
| 164250 |
13-Nov-2006 |
ru |
Fix a comment.
|
| 164198 |
11-Nov-2006 |
alc |
Eliminate unused global variables.
|
| 164080 |
07-Nov-2006 |
cognet |
Identify the xscale 81342.
|
| 164059 |
07-Nov-2006 |
cognet |
Add atomic_cmpset_acq_32.
|
| 163016 |
04-Oct-2006 |
jb |
PR:
Submitted by:
Reviewed by:
Approved by:
Obtained from:
MFC after:
Security:
Move the relocation definitions to the common elf header so that DTrace
can use them on one architecture targeted to a different one.
Add the additional ELF types defines in Sun's "Linker and Libraries"
manual.
|
| 162954 |
02-Oct-2006 |
phk |
First part of a little cleanup in the calendar/timezone/RTC handling.
Move relevant variables to <sys/clock.h> and fix #includes as necessary.
Use libkern's much more time- & spamce-efficient BCD routines.
|
| 162487 |
21-Sep-2006 |
kan |
Use __builtin_va_start instead of __builtin_stdarg_start. GCC4 obsoletes
the former and __builtin_va_start was present in all GCC version 3.1 and
later.
|
| 161735 |
30-Aug-2006 |
cognet |
Remove dead code, already defined in sys/cdef.h
Spotted out by: bde
|
| 161628 |
25-Aug-2006 |
alc |
Eliminate unused definitions. (They came from NetBSD.)
Discussed with: cognet, grehan, marcel
|
| 161592 |
24-Aug-2006 |
cognet |
Finally bring it support for the i80219 XScale processor.
Submitted by: Max M. Boyarov <m.boyarov bsd by>
|
| 161591 |
24-Aug-2006 |
cognet |
Use ELFDATA2MSB if we're building big endian.
Noticed by: Oleksandr Tymoshenko <gonzo freebsd org>
|
| 161105 |
08-Aug-2006 |
cognet |
Rewrite ARM_USE_SMALL_ALLOC so that instead of the current behavior, it maps
whole the physical memory, cached, using 1MB section mappings. This reduces
the address space available for user processes a bit, but given the amount of
memory a typical arm machine has, it is not (yet) a big issue.
It then provides a uma_small_alloc() that works as it does for architectures
which have a direct mapping.
|
| 160740 |
27-Jul-2006 |
cognet |
Define BYTE_MSF if we're compiling a big endian kernel, so that DDB can
correctly disassemble instructions on big endian.
|
| 160332 |
14-Jul-2006 |
cognet |
Add remote GDB bits for arm.
|
| 159325 |
06-Jun-2006 |
alc |
Add partial pmap locking.
Eliminate the unused allpmaps list.
Tested by: cognet@
|
| 159167 |
02-Jun-2006 |
cognet |
Don't #error if no CPU is defined but we're not compiling the kernel.
|
| 159145 |
01-Jun-2006 |
cognet |
Don't enable the FIQ in enable_interrupts() if F32_bit is not specified.
This has been committed by mistake.
Reported by: ssouhlal
|
| 159101 |
31-May-2006 |
cognet |
Ooops arm10 is armv5, not armv4.
Submitted by: kevlo
|
| 159100 |
31-May-2006 |
cognet |
Include machine/cpuconf.h in pmap.h in order to get ARM_NMMUS defined,
to appease -Wundef.
|
| 158593 |
15-May-2006 |
cognet |
Add definitions for atomic_subtract_rel_32, atomic_add_rel_32 and
atomic_load_acq_32, needed for hwpmc.
|
| 158581 |
15-May-2006 |
cognet |
Switch to a 64bit time_t, while it's not a big problem to do so.
Suggested by: imp
|
| 158531 |
13-May-2006 |
cognet |
Resurrect Skyeye support :
Add a new option, SKYEYE_WORKAROUNDS, which as the name suggests adds
workarounds for things skyeye doesn't simulate. Specifically :
- Use USART0 instead of DBGU as the console, make it not use DMA, and manually provoke an interrupt when we're done in the transmit function.
- Skyeye maintains an internal counter for clock, but apparently there's
no way to access it, so hack the timecounter code to return a value which
is increased at every clock interrupts. This is gross, but I didn't find a
better way to implement timecounters without hacking Skyeye to get the
counter value.
- Force the write-back of PTEs once we're done writing them, even if they
are supposed to be write-through. I don't know why I have to do that.
|
| 158445 |
11-May-2006 |
phk |
Clean out sysctl machdep.* related defines.
The cmos clock related stuff should really be in MI code.
|
| 157725 |
13-Apr-2006 |
cognet |
Disable/enable fiqs as well as irqs.
|
| 157615 |
09-Apr-2006 |
cognet |
MFp4: Don't write-back the PTEs if they are mapped write-through, this was
apparently only needed because skyeye has bugs in its cache emulation.
|
| 156520 |
09-Mar-2006 |
cognet |
MFp4: Forget the asm inlined version of in_cksum_hdr(). It doesn't work if
the pointer is unaligned, and it just doesn't worth it.
|
| 156191 |
01-Mar-2006 |
cognet |
Try to honor BUS_DMA_COHERENT : if the flag is set, normally allocate memory
with malloc() or contigmalloc() as usual, but try to re-map the allocated
memory into a VA outside the KVA, non-cached, thus making the calls to
bus_dmamap_sync() for these buffers useless.
|
| 155391 |
06-Feb-2006 |
cognet |
Use memory clobbers, to be on the safe side.
Suggested by: jhb
|
| 155355 |
05-Feb-2006 |
cognet |
Backout rev 1.12. It would have been a good thing, if gcc was smart enough
not to generate bad code.
|
| 154128 |
09-Jan-2006 |
imp |
By popular demand, move __HAVE_ACPI and __PCI_REROUTE_INTERRUPT into
param.h. Per request, I've placed these just after the
_NO_NAMESPACE_POLLUTION ifndef. I've not renamed anything yet, but
may since we don't need the __.
Submitted by: bde, jhb, scottl, many others.
|
| 153955 |
01-Jan-2006 |
imp |
Define __HAVE_ACPI and/or __PCI_REROUTE_INTERRUPT, as appropriate for
each platform. These will be used in the pci code in preference to
the complicated #ifdefs we have there now.
|
| 153666 |
22-Dec-2005 |
jhb |
Tweak how the MD code calls the fooclock() methods some. Instead of
passing a pointer to an opaque clockframe structure and requiring the
MD code to supply CLKF_FOO() macros to extract needed values out of the
opaque structure, just pass the needed values directly. In practice this
means passing the pair (usermode, pc) to hardclock() and profclock() and
passing the boolean (usermode) to hardclock_cpu() and hardclock_process().
Other details:
- Axe clockframe and CLKF_FOO() macros on all architectures. Basically,
all the archs were taking a trapframe and converting it into a clockframe
one way or another. Now they can just extract the PC and usermode values
directly out of the trapframe and pass it to fooclock().
- Renamed hardclock_process() to hardclock_cpu() as the latter is more
accurate.
- On Alpha, we now run profclock() at hz (profhz == hz) rather than at
the slower stathz.
- On Alpha, for the TurboLaser machines that don't have an 8254
timecounter, call hardclock() directly. This removes an extra
conditional check from every clock interrupt on Alpha on the BSP.
There is probably room for even further pruning here by changing Alpha
to use the simplified timecounter we use on x86 with the lapic timer
since we don't get interrupts from the 8254 on Alpha anyway.
- On x86, clkintr() shouldn't ever be called now unless using_lapic_timer
is false, so add a KASSERT() to that affect and remove a condition
to slightly optimize the non-lapic case.
- Change prototypeof arm_handler_execute() so that it's first arg is a
trapframe pointer rather than a void pointer for clarity.
- Use KCOUNT macro in profclock() to lookup the kernel profiling bucket.
Tested on: alpha, amd64, arm, i386, ia64, sparc64
Reviewed by: bde (mostly)
|
| 153276 |
09-Dec-2005 |
cognet |
A #define is not enough, we need to cast from u_long * to uint32_t *.
|
| 153275 |
09-Dec-2005 |
cognet |
Define atomic_whatever_long
|
| 153168 |
06-Dec-2005 |
ru |
Drop _MACHINE_ARCH and _MACHINE defines (not to be confused with
MACHINE_ARCH and MACHINE). Their purpose was to be able to test
in cpp(1), but cpp(1) only understands integer type expressions.
Using such unsupported expressions introduced a number of subtle
bugs, which were discovered by compiling with -Wundef.
|
| 152743 |
24-Nov-2005 |
cognet |
Use a magic number to know we were started from the elf wrapper.
Add a dummy _start function to make the non-elf version of the wrapper work.
|
| 152654 |
21-Nov-2005 |
cognet |
Force pmap to write-back the pte cacheline after each pte modification,
even if the pte is supposed to be cached in write through mode (might be a
skyeye bug, I'll have to check).
|
| 152653 |
21-Nov-2005 |
cognet |
Add an alternate ID for the arm920t (the real solution is to have
per-cpu class masks, but oh well).
|
| 152189 |
08-Nov-2005 |
cognet |
There's no need to include <machine/asmacros.h> here.
|
| 152128 |
06-Nov-2005 |
cognet |
MFi386 rev 1.536 (sort of)
Move what can be moved (UMA zones creation, pv_entry_* initialization) from
pmap_init2() to pmap_init().
Create a new function, pmap_postinit(), called from cpu_startup(), to do the
L1 tables allocation.
pmap_init2() is now empty for arm as well.
|
| 151340 |
14-Oct-2005 |
jhb |
Whitespace.
|
| 151334 |
14-Oct-2005 |
jhb |
Change the userland atomic operations on arm to use memory operands for
the modified memory rather than using register operands that held a pointer
to the memory. The biggest effect is that we now correctly tell the
compiler that these functions change the memory that these functions
modify.
Reviewed by: cognet
|
| 150936 |
04-Oct-2005 |
cognet |
dump_avail has nothing to do with ARM_USE_SMALL_ALLOC, so move its
declaration out of the #ifdef.
|
| 150867 |
03-Oct-2005 |
cognet |
Provide a dump_avail[] variable, which contains the page ranges to be
dumped.
For iq31244_machdep.c, attempt to recognize hints provided by the elf
trampoline.
|
| 150864 |
03-Oct-2005 |
cognet |
Add a new API to let platform-specific ports provide functions for big
copy/zeroing.
|
| 150858 |
03-Oct-2005 |
cognet |
asm versions of in_cksum_hdr() and in_pseudo().
|
| 150627 |
27-Sep-2005 |
jhb |
Add a new atomic_fetchadd() primitive that atomically adds a value to a
variable and returns the previous value of the variable.
Tested on: i386, alpha, sparc64, arm (cognet)
Reviewed by: arch@
Submitted by: cognet (arm)
MFC after: 1 week
|
| 149337 |
20-Aug-2005 |
stefanf |
Move MINSIGSTKSZ from <machine/signal.h> to <machine/_limits.h> and rename
it to __MINSIGSTKSZ. Define MINSIGSTKSZ in <sys/signal.h>.
This is done in order to use MINSIGSTKSZ for the macro PTHREAD_STACK_MIN
in <pthread.h> (soon <limits.h>) without having to include the whole
<sys/signal.h> header.
Discussed with: bde
|
| 148455 |
27-Jul-2005 |
imp |
msdosfs_conv.c references cmos_wall_clock and adjkerntz. Since these
are 0 for arm, define them as such to make msdosfs_conv.c compile
again on arm.
|
| 148453 |
27-Jul-2005 |
jhb |
Add extra constraints to tell the compiler that the memory be modified
in the arm __swp() and sparc64 casa() and casax() functions is actually
being used as an input and output and not just the value of the register
that points to the memory location. This was the underlying source of
the mbuf refcount problems on sparc64 a while back. For arm this should be
a nop because __swp() has a constraint to clobber all memory which can
probably be removed now.
Reviewed by: alc, cognet
MFC after: 1 week
|
| 148452 |
27-Jul-2005 |
jhb |
Use a + constraint modifier for a register arg in __bswap16_var().
Reviewed by: cognet
|
| 148067 |
15-Jul-2005 |
jhb |
Convert the atomic_ptr() operations over to operating on uintptr_t
variables rather than void * variables. This makes it easier and simpler
to get asm constraints and volatile keywords correct.
MFC after: 3 days
Tested on: i386, alpha, sparc64
Compiled on: ia64, powerpc, amd64
Kernel toolchain busted on: arm
|
| 147555 |
23-Jun-2005 |
jhb |
Fix a typo.
Approved by: re (scottl)
|
| 147191 |
09-Jun-2005 |
jkoshy |
MFP4:
- Implement sampling modes and logging support in hwpmc(4).
- Separate MI and MD parts of hwpmc(4) and allow sharing of
PMC implementations across different architectures.
Add support for P4 (EMT64) style PMCs to the amd64 code.
- New pmcstat(8) options: -E (exit time counts) -W (counts
every context switch), -R (print log file).
- pmc(3) API changes, improve our ability to keep ABI compatibility
in the future. Add more 'alias' names for commonly used events.
- bug fixes & documentation.
|
| 147166 |
09-Jun-2005 |
cognet |
- MFp4: modify slightly the arm intr API, there's arm CPUs with more than 32
interrupts.
- Implement teardown methods where appropriate.
|
| 147114 |
07-Jun-2005 |
cognet |
Add a new arm-specific option, ARM_USE_SMALL_ALLOC. If defined, it provides
an implementation of uma_small_alloc() which tries to preallocate memory
1MB per 1MB, and maps it into a section mapping.
|
| 146948 |
03-Jun-2005 |
cognet |
Bring in bits I forgot while importing write back support for arm9.
|
| 146734 |
29-May-2005 |
nyan |
Remove bus_{mem,p}io.h and related code for a micro-optimization on i386
and amd64. The optimization is a trivial on recent machines.
Reviewed by: -arch (imp, marcel, dfr)
|
| 146649 |
26-May-2005 |
cognet |
s/_KLD_MODULE/KLD_MODULE/
|
| 146619 |
25-May-2005 |
cognet |
Remove bits specific to CPUs we won't support (< armv4).
|
| 146594 |
24-May-2005 |
cognet |
Use asm versions of in_cksum() and friends.
|
| 146592 |
24-May-2005 |
cognet |
Asm version of bswap16().
Obtained from: NetBSD
|
| 146591 |
24-May-2005 |
cognet |
Make sure we clean the RAS start address once we're done.
This fixes the random segfaults which occurs at high interrupts rate.
|
| 145332 |
20-Apr-2005 |
marcel |
Add empty header (except of the multiple-inclusion protection) to
get hwpmc(4) to compile on this platform.
|
| 145253 |
18-Apr-2005 |
imp |
Break out the definition of bus_space_{tag,handle}_t and a few other types
into _bus.h to help with name space polution from including all of bus.h.
In a few days, I'll commit changes to the MI code to take advantage of thse
sepration (after I've made sure that these changes don't break anything in
the main tree, I've tested in my trees, but you never know...).
Suggested by: bde (in 2002 or 2003 I think)
Reviewed in principle by: jhb
|
| 144761 |
07-Apr-2005 |
cognet |
Import a basic implementation of the restartable atomic sequences to provide
atomic operations to userland (this is OK for UP only, but SMP is still so
far away).
|
| 144760 |
07-Apr-2005 |
cognet |
- Try harder to report dirty page.
- Garbage-collect pmap_update(), it became quite useless.
|
| 144637 |
04-Apr-2005 |
jhb |
Divorce critical sections from spinlocks. Critical sections as denoted by
critical_enter() and critical_exit() are now solely a mechanism for
deferring kernel preemptions. They no longer have any affect on
interrupts. This means that standalone critical sections are now very
cheap as they are simply unlocked integer increments and decrements for the
common case.
Spin mutexes now use a separate KPI implemented in MD code: spinlock_enter()
and spinlock_exit(). This KPI is responsible for providing whatever MD
guarantees are needed to ensure that a thread holding a spin lock won't
be preempted by any other code that will try to lock the same lock. For
now all archs continue to block interrupts in a "spinlock section" as they
did formerly in all critical sections. Note that I've also taken this
opportunity to push a few things into MD code rather than MI. For example,
critical_fork_exit() no longer exists. Instead, MD code ensures that new
threads have the correct state when they are created. Also, we no longer
try to fixup the idlethreads for APs in MI code. Instead, each arch sets
the initial curthread and adjusts the state of the idle thread it borrows
in order to perform the initial context switch.
This change is largely a big NOP, but the cleaner separation it provides
will allow for more efficient alternative locking schemes in other parts
of the kernel (bare critical sections rather than per-CPU spin mutexes
for per-CPU data for example).
Reviewed by: grehan, cognet, arch@, others
Tested on: i386, alpha, sparc64, powerpc, arm, possibly more
|
| 143857 |
20-Mar-2005 |
cognet |
Bring in a version of float.h more correct for softfloat.
|
| 143598 |
14-Mar-2005 |
scottl |
Refactor the bus_dma header files so that the interface is described in
sys/bus_dma.h instead of being copied in every single arch. This slightly
reorders a flag that was specific to AXP and thus changes the ABI there.
The interface still relies on bus_space definitions found in <machine/bus.h>
so it cannot be included on its own yet, but that will be fixed at a later
date. Add an MD <machine/bus_dma.h> for ever arch for consistency and to
allow for future MD augmentation of the API. sparc64 makes heavy use of
this right now due to its different bus_dma implemenation.
|
| 143063 |
02-Mar-2005 |
joerg |
netchild's mega-patch to isolate compiler dependencies into a central
place.
This moves the dependency on GCC's and other compiler's features into
the central sys/cdefs.h file, while the individual source files can
then refer to #ifdef __COMPILER_FEATURE_FOO where they by now used to
refer to #if __GNUC__ > 3.1415 && __BARC__ <= 42.
By now, GCC and ICC (the Intel compiler) have been actively tested on
IA32 platforms by netchild. Extension to other compilers is supposed
to be possible, of course.
Submitted by: netchild
Reviewed by: various developers on arch@, some time ago
|
| 142570 |
26-Feb-2005 |
cognet |
Instead of using sysarch() to store-retrieve the tp, add a magic address,
ARM_TP_ADDRESS, where the tp will be stored. On CPUs that support it, a cache
line will be allocated and locked for this address, so that it will never go
to RAM. On CPUs that does not, a page is allocated for it (it will be a bit
slower, and is wrong for SMP, but should be fine for UP).
The tp is still stored in the mdthread struct, and at each context switch,
ARM_TP_ADDRESS gets updated.
Suggested by: davidxu
|
| 142528 |
26-Feb-2005 |
cognet |
Add the field in the md part of the struct thread required by ARM_[GET|SET]_TP.
|
| 142519 |
25-Feb-2005 |
cognet |
Implement two new sysarch for arm, ARM_GET_TP and ARM_SET_TP, to work around
the lack of tls on arm.
|
| 142107 |
19-Feb-2005 |
ru |
Use a common multi-inclusion protection, and add such a
protection to alpha/include/exec.h.
|
| 141820 |
13-Feb-2005 |
cognet |
Define NIRQ to 64 for CPU_ARM9, because Cirrus Logic EP93XX cores provides
64 irqs.
This should be re-thought later.
|
| 141094 |
01-Feb-2005 |
njl |
Sort functions.
|
| 140425 |
18-Jan-2005 |
cognet |
Start to support the big endian case as well.
|
| 140312 |
15-Jan-2005 |
cognet |
Add the prototype for bus_dmamap_load_mbuf_sg().
Spotted out by: scottl
|
| 140001 |
10-Jan-2005 |
cognet |
Add support for ptrace() and gdb breakpoints.
|
| 139735 |
05-Jan-2005 |
imp |
Start all license statements with /*-
|
| 139021 |
18-Dec-2004 |
cognet |
Make sure gcc doesn't generate something such as swp r3, r4, [r3] for __swp,
as it has unpredictable results.
|
| 138413 |
05-Dec-2004 |
cognet |
Remove an unused field from the struct pv_entry.
While I'm there, fix style.
|
| 137975 |
21-Nov-2004 |
cognet |
Implement breakpoints and single stepping on arm.
Obtained from: NetBSD
|
| 137940 |
20-Nov-2004 |
cognet |
Implement enough to be able to enter and leave DDB.
|
| 137939 |
20-Nov-2004 |
cognet |
Get the kernel stack right now that the u-area is gone.
|
| 137919 |
20-Nov-2004 |
das |
Remove UAREA_PAGES and USPACE definitions. The definitions of
USPACE_SVC_STACK_TOP, USPACE_SVC_STACK_BOTTOM, USPACE_UNDEF_STACK_TOP,
and USPACE_UNDEF_STACK_BOTTOM look wrong to me, so I'm leaving them
alone.
Reviewed by: arch@
|
| 137462 |
09-Nov-2004 |
cognet |
Import a RET macro, that will use bx if the arch supports it.
Obtained from: NetBSD
|
| 137362 |
07-Nov-2004 |
cognet |
Import md bits for mem(4) on arm.
While I'm there, cleanup a bit pmap.h.
|
| 137282 |
05-Nov-2004 |
cognet |
Disable interrupts for atomic_cmpset_32, this one is just not atomic.
Don't export it to userland.
|
| 137229 |
04-Nov-2004 |
cognet |
Protect the function declarations with #ifdef _KERNEL.
|
| 137228 |
04-Nov-2004 |
cognet |
Directly use __pcpu for PCPU_* instead of pcpup.
|
| 137227 |
04-Nov-2004 |
cognet |
Decrease KSTACK_PAGES and UAREA_PAGES.
|
| 137226 |
04-Nov-2004 |
cognet |
Use interrupts_disable() and interrupts_restore() as intr_disable() and
intr_restore() instead of re-implement it.
|
| 137224 |
04-Nov-2004 |
cognet |
Don't barf if no CPU type is defined while compiling kernel modules.
|
| 137223 |
04-Nov-2004 |
cognet |
Implement get_cyclecount().
|
| 137222 |
04-Nov-2004 |
cognet |
Try to implement atomic operations using swp, instead of disabling interrupts.
|
| 137216 |
04-Nov-2004 |
cognet |
Use casts to enforce the return type of bswap16() and bswap32().
|
| 136033 |
01-Oct-2004 |
cognet |
Add optimized version of the bswap macroes for constants if __OPTIMIZED__ is
defined.
|
| 135665 |
23-Sep-2004 |
cognet |
Remove the empty definition of struct osigcontext, as it will never be used.
|
| 135664 |
23-Sep-2004 |
cognet |
Remove the pcb32_cstate field of struct pcb.
|
| 135663 |
23-Sep-2004 |
cognet |
Declare sigcode and szsigcode.
|
| 135662 |
23-Sep-2004 |
cognet |
Define VM_PROT_READ_IS_EXEC.
|
| 135661 |
23-Sep-2004 |
cognet |
Implement _mcount().
Obtained from: NetBSD
|
| 135660 |
23-Sep-2004 |
cognet |
Define STACKALIGNBYTES and STACKALIGN.
|
| 135659 |
23-Sep-2004 |
cognet |
We are using _mcount, not __mcount.
Remove the !__ELF__ case.
|
| 135650 |
23-Sep-2004 |
cognet |
Add new functions to know which irqs are pending, and to mask and unmask
interrupts, as these are CPU specific.
If the interrupt handler is not marked as INTR_FAST, don't unmask the
interrupt until it as been serviced.
|
| 135649 |
23-Sep-2004 |
cognet |
Rename macroes, as we don't need to mess with alignment faults.
Call ast() if TDF_NEEDRESCHED is set too, not just TDF_ASTPENDING.
|
| 135645 |
23-Sep-2004 |
cognet |
Remove bus_space_vaddr(), it does not exists in FreeBSD.
|
| 135642 |
23-Sep-2004 |
cognet |
Add MD syscalls to sync the icache and to drain the write buffer.
Obtained from: NetBSD
|
| 135641 |
23-Sep-2004 |
cognet |
Implement pmap_growkernel() and pmap_extract_and_hold().
Remove the cache state logic : right now, it provides more problems than it
helps.
Add helper functions for mapping devices while bootstrapping.
Reorganize the code a bit, and remove dead code.
Obtained from: NetBSD (partially)
|
| 134398 |
27-Aug-2004 |
marcel |
Move the kernel-specific logic to adjust frompc from MI to MD. For
these two reasons:
1. On ia64 a function pointer does not hold the address of the first
instruction of a functions implementation. It holds the address
of a function descriptor. Hence the user(), btrap(), eintr() and
bintr() prototypes are wrong for getting the actual code address.
2. The logic forces interrupt, trap and exception entry points to
be layed-out contiguously. This can not be achieved on ia64 and is
generally just bad programming.
The MCOUNT_FROMPC_USER macro is used to set the frompc argument to
some kernel address which represents any frompc that falls outside
the kernel text range. The macro can expand to ~0U to bail out in
that case.
The MCOUNT_FROMPC_INTR macro is used to set the frompc argument to
some kernel address to represent a call to a trap or interrupt
handler. This to avoid that the trap or interrupt handler appear to
be called from everywhere in the call graph. The macro can expand
to ~0U to prevent adjusting frompc. Note that the argument is selfpc,
not frompc.
This commit defines the macros on all architectures equivalently to
the original code in sys/libkern/mcount.c. People can take it from
here...
Compile-tested on: alpha, amd64, i386, ia64 and sparc64
Boot-tested on: i386
|
| 133084 |
03-Aug-2004 |
mux |
Instead of calling ia32_pause() conditionally on __i386__ or __amd64__
being defined, define and use a new MD macro, cpu_spinwait(). It only
expands to something on i386 and amd64, so the compiled code should be
identical.
Name of the macro found by: jhb
Reviewed by: jhb
|
| 133012 |
02-Aug-2004 |
cognet |
*blush*
Fix htonl and htons.
|
| 133011 |
02-Aug-2004 |
cognet |
Fix comments.
Spotted out by: mux
|
| 132702 |
27-Jul-2004 |
rwatson |
Correct typo in prior commit: s/cd/td/
|
| 132700 |
27-Jul-2004 |
rwatson |
Pass a thread argument into cpu_critical_{enter,exit}() rather than
dereference curthread. It is called only from critical_{enter,exit}(),
which already dereferences curthread. This doesn't seem to affect SMP
performance in my benchmarks, but improves MySQL transaction throughput
by about 1% on UP on my Xeon.
Head nodding: jhb, bmilekic
|
| 132516 |
21-Jul-2004 |
cognet |
Do not declare curpcb.
|
| 132513 |
21-Jul-2004 |
cognet |
Define pmap_page_is_mapped().
|
| 132471 |
20-Jul-2004 |
cognet |
Nuke disable_intr() and enable_intr(), as it already exists elsewhere.
|
| 132383 |
19-Jul-2004 |
das |
Make FLT_ROUNDS correctly reflect the dynamic rounding mode.
|
| 132059 |
12-Jul-2004 |
cognet |
Update to kdb.
|
| 132058 |
12-Jul-2004 |
cognet |
Remove the kbd_trap() declaration.
|
| 132057 |
12-Jul-2004 |
cognet |
Protect setjmp.h with #ifndef _MACHINE_SETJMP_H_.
|
| 132056 |
12-Jul-2004 |
cognet |
Forward declare "struct pcb", so that one does not need to include
<machine/pcb.h> before including <machine/pmap.h>.
|
| 132055 |
12-Jul-2004 |
cognet |
Implement a stub breakpoint().
|
| 132053 |
12-Jul-2004 |
cognet |
Prototype makectx().
|
| 132052 |
12-Jul-2004 |
cognet |
Import bus_memio.h and bus_pio.h for arm.
|
| 132051 |
12-Jul-2004 |
cognet |
Import a kdb.h for arm, which contains stubs right now.
|
| 130644 |
17-Jun-2004 |
cognet |
Nuke bus_space_mmap(), as it does not exist in FreeBSD.
|
| 130585 |
16-Jun-2004 |
phk |
Do the dreaded s/dev_t/struct cdev */
Bump __FreeBSD_version accordingly.
|
| 129444 |
19-May-2004 |
bde |
Moved most of the "MI" definitions and declarations from <machine/profile.h>
to <sys/gmon.h>. Cleaned them up a little by not attempting to ifdef
for incomplete and out of date support for GUPROF in userland, as in
the sparc64 version.
|
| 129393 |
18-May-2004 |
stefanf |
<stdint.h> should define WINT_M{AX,IN} independent from whether WCHAR_MIN is
defined. Otherwise first including <wchar.h> and then <stdint.h> leads to no
WINT_M{AX,IN} at all.
PR: 64956
Approved by: das (mentor)
|
| 129198 |
14-May-2004 |
cognet |
Import FreeBSD/arm kernel bits.
It only supports sa1110 (on simics) right now, but xscale support should come
soon.
Some of the initial work has been provided by :
Stephane Potvin <sepotvin at videotron.ca>
Most of this comes from NetBSD.
|
| 128940 |
04-May-2004 |
cognet |
Don't declare osigset_t, as it is done in sys/_sigset.h.
|
| 128938 |
04-May-2004 |
cognet |
Add some endianess-related functions and macros.
|
| 128937 |
04-May-2004 |
cognet |
Add the Elf32_Auxinfo declaretion.
Define AT_*.
(Maybe some of this could go in a MI header ?)
|
| 128936 |
04-May-2004 |
cognet |
Define __double_t and __float_t.
|
| 127914 |
05-Apr-2004 |
imp |
Remove advertising clause from University of California Regent's license,
per letter dated July 22, 1999.
Approved by: core
|
| 127239 |
20-Mar-2004 |
marcel |
Introduce the cpumask_t type. The purpose of the type is to create a
level of abstraction for any and all CPU mask and CPU bitmap variables
so that platforms have the ability to break free from the hard limit
of 32 CPUs, simply because we don't have more bits in an u_int. Note
that the type is not supposed to solve massive parallelism, where
the number of CPUs can be larger than the width of the widest integral
type. As such, cpumask_t is not supposed to be a compound type. If
such would be necessary in the future, we can deal with the issues
then and there. For now, it can be assumed that the type is integral
and unsigned.
With this commit, all MD definitions start off as u_int. This allows
us to phase-in cpumask_t at our leasure without breaking anything.
Once cpumask_t is used consistently, platforms can switch to wider
(or smaller) types if such would be beneficial (or not; whatever :-)
Compile-tested on: i386
|
| 120422 |
25-Sep-2003 |
peter |
Add sysentvec->sv_fixlimits() hook so that we can catch cases on 64 bit
systems where the data/stack/etc limits are too big for a 32 bit process.
Move the 5 or so identical instances of ELF_RTLD_ADDR() into imgact_elf.c.
Supply an ia32_fixlimits function. Export the clip/default values to
sysctl under the compat.ia32 heirarchy.
Have mmap(0, ...) respect the current p->p_limits[RLIMIT_DATA].rlim_max
value rather than the sysctl tweakable variable. This allows mmap to
place mappings at sensible locations when limits have been reduced.
Have the imgact_elf.c ld-elf.so.1 placement algorithm use the same
method as mmap(0, ...) now does.
Note that we cannot remove all references to the sysctl tweakable
maxdsiz etc variables because /etc/login.conf specifies a datasize
of 'unlimited'. And that causes exec etc to fail since it can no
longer find space to mmap things.
|
| 118382 |
03-Aug-2003 |
obrien |
Style sync.
|
| 115164 |
19-May-2003 |
kan |
sys/sys/limits.h:
- Fix visibilty test for LONG_BIT and WORD_BIT. `#if defined(__FOO_VISIBLE)'
is alays wrong because __FOO_VISIBLE is always defined (to 0 for
invisibility).
sys/<arch>/include/limits.h
sys/<arch>/include/_limits.h:
- Style fixes.
Submitted by: bde
Reviewed by: bsdmike
Approved by: re (scottl)
|
| 114678 |
04-May-2003 |
kan |
Style fixes.
Remove DBL_DIG, DBL_MIN, DBL_MAX and their FLT_ counterparts, they
were marked for deprecation ever since SUSv1 at least.
Only define ULLONG_MIN/MAX and LLONG_MAX if long long type is
supported.
Restore a lost comment in MI _limits.h file and remove it from
sys/limits.h where it does not belong.
|
| 114216 |
29-Apr-2003 |
kan |
Deprecate machine/limits.h in favor of new sys/limits.h.
Change all in-tree consumers to include <sys/limits.h>
Discussed on: standards@
Partially submitted by: Craig Rodrigues <rodrigc@attbi.com>
|
| 113941 |
23-Apr-2003 |
kan |
Add a new sys/limits.h file which in turn depends on machine/_limits.h
to get actual constant values. This is in preparation for machine/limits.h
retirement.
Discussed on: standards@
Submitted by: Craig Rodrigues <rodrigc@attbi.com> (*)
Modified by: kan
|
| 112569 |
25-Mar-2003 |
jake |
- Add vm_paddr_t, a physical address type. This is required for systems
where physical addresses larger than virtual addresses, such as i386s
with PAE.
- Use this to represent physical addresses in the MI vm system and in the
i386 pmap code. This also changes the paddr parameter to d_mmap_t.
- Fix printf formats to handle physical addresses >4G in the i386 memory
detection code, and due to kvtop returning vm_paddr_t instead of u_long.
Note that this is a name change only; vm_paddr_t is still the same as
vm_offset_t on all currently supported platforms.
Sponsored by: DARPA, Network Associates Laboratories
Discussed with: re, phk (cdevsw change)
|
| 108175 |
22-Dec-2002 |
tjr |
MB_LEN_MAX is not MD, move it to the MI limits.h.
|
| 105014 |
13-Oct-2002 |
mike |
Add standards visibility conditionals. Change any uses of sigset_t to
struct __sigset to avoid depending on objects from <sys/signal.h>.
|
| 103436 |
17-Sep-2002 |
peter |
Initiate deorbit burn for the i386-only a.out related support. Moves are
under way to move the remnants of the a.out toolchain to ports. As the
comment in src/Makefile said, this stuff is deprecated and one should not
expect this to remain beyond 4.0-REL. It has already lasted WAY beyond
that.
Notable exceptions:
gcc - I have not touched the a.out generation stuff there.
ldd/ldconfig - still have some code to interface with a.out rtld.
old as/ld/etc - I have not removed these yet, pending their move to ports.
some includes - necessary for ldd/ldconfig for now.
Tested on: i386 (extensively), alpha
|
| 102874 |
03-Sep-2002 |
mike |
Now that _BSD_CLK_TCK_ and _BSD_CLOCKS_PER_SEC_ are the same on all
architectures, move the definition directly into <time.h> and finish
the removal of <machine/ansi.h>.
|
| 102429 |
26-Aug-2002 |
mike |
Since arm and powerpc aren't far enough to set stathz, take a
preemptive strike and change _BSD_CLK_TCK_ and _BSD_CLOCKS_PER_SEC_
to 128.
Approved by: benno
|
| 102315 |
23-Aug-2002 |
mike |
Move several MI types from <machine/_types.h> to <sys/_types.h>.
These types are unlikely to ever become very MD. They include:
clockid_t, ct_rune_t, fflags_t, intrmask_t, mbstate_t, off_t, pid_t,
rune_t, socklen_t, timer_t, wchar_t, and wint_t.
While moving them, make a few adjustments (submitted by bde):
o __ct_rune_t needs to be precisely `int', not necessarily __int32_t,
since the arg type of the ctype functions is int.
o __rune_t, __wchar_t and __wint_t inherit this via a typedef of
__ct_rune_t.
o Some minor wording changes in the comment blocks for ct_rune_t and
mbstate_t.
Submitted by: bde (partially)
|
| 102227 |
21-Aug-2002 |
mike |
o Merge <machine/ansi.h> and <machine/types.h> into a new header
called <machine/_types.h>.
o <machine/ansi.h> will continue to live so it can define MD clock
macros, which are only MD because of gratuitous differences between
architectures.
o Change all headers to make use of this. This mainly involves
changing:
#ifdef _BSD_FOO_T_
typedef _BSD_FOO_T_ foo_t;
#undef _BSD_FOO_T_
#endif
to:
#ifndef _FOO_T_DECLARED
typedef __foo_t foo_t;
#define _FOO_T_DECLARED
#endif
Concept by: bde
Reviewed by: jake, obrien
|
| 100882 |
29-Jul-2002 |
mike |
Create a new header <machine/_stdint.h> for storing MD parts of
<stdint.h>. Previously, parts were defined in <machine/ansi.h> and
<machine/limits.h>. This resulted in two problems:
(1) Defining macros in <machine/ansi.h> gets in the way of that
header only defining types.
(2) Defining C99 limits in <machine/limits.h> adds pollution to
<limits.h>.
|
| 99733 |
10-Jul-2002 |
mike |
Remove label_t and physadr, which seem to have never been used in
FreeBSD.
Submitted by: bde
|
| 99630 |
09-Jul-2002 |
mike |
Remove an unused type.
|
| 99594 |
08-Jul-2002 |
mike |
Move __offsetof() macro from <machine/ansi.h> to <sys/cdefs.h>. It's
hardly MD, since all our platforms share the same macro. It's not
really compiler dependent either, but this helps in reducing
<machine/ansi.h> to only type definitions.
|
| 98710 |
23-Jun-2002 |
iedowse |
Make vm_pindex_t 64-bit on all platforms. This is necessary to avoid
overflows with the large file sizes that UFS2 permits.
Reviewed by: dillon, alc, tegge
|
| 96606 |
14-May-2002 |
phk |
Move MI stuff out of MD param.h files.
It can all still be overridden in the MD files should need suddenly arise.
|
| 96604 |
14-May-2002 |
phk |
Remove the unused definitions of ctod() and dotc().
|
| 96319 |
10-May-2002 |
obrien |
Sync with the other platforms.
|
| 93092 |
24-Mar-2002 |
obrien |
Guard against redefining __gnuc_va_list.
|
| 92812 |
20-Mar-2002 |
alfred |
Remove __P.
|
| 87575 |
09-Dec-2001 |
obrien |
We need machine/{signal,ucontext}.h to build a cross GCC compiler.
So craft the proper versions of these and commit em.
|
| 87574 |
09-Dec-2001 |
obrien |
Following sys/i386/include/ansi.h rev 1.33, add additional integer types
in <machine/ansi.h> and that are required by <sys/stdint.h>.
|
| 87571 |
09-Dec-2001 |
obrien |
We need machine/types.h to build a cross GCC compiler.
(copied from src/sys/i386/include/types.h rev 1.23, except for the label_t
size, which is '10' everywhere BUT on i386)
|
| 87567 |
09-Dec-2001 |
obrien |
machine/limits.h
(taken from i386/include/limits.h rev 1.19)
|
| 87158 |
01-Dec-2001 |
mike |
o Stop abusing MD headers with non-MD types.
o Hide nonstandard functions and types in <netinet/in.h> when
_POSIX_SOURCE is defined.
o Add some missing types (required by POSIX.1-200x) to <netinet/in.h>.
o Restore vendor ID from Rev 1.1 in <netinet/in.h> and make use of new
__FBSDID() macro.
o Fix some miscellaneous issues in <arpa/inet.h>.
o Correct final argument for the inet_ntop() function (POSIX.1-200x).
o Get rid of the namespace pollution from <sys/types.h> in
<arpa/inet.h>.
Reviewed by: fenner
Partially submitted by: bde
|
| 85335 |
23-Oct-2001 |
mike |
Remove funky right justification.
Pointed out by: bde
|
| 85187 |
19-Oct-2001 |
obrien |
Try two on the preprocessing logic.
Reviewed by: ru
|
| 85183 |
19-Oct-2001 |
obrien |
Blah, fix braino where ru had to remind me of proper preprocessor syntax.
Bad fingers, no cookie.
|
| 85108 |
18-Oct-2001 |
obrien |
My attempts at minimizing the number of #def's got me in trouble.
|
| 84783 |
10-Oct-2001 |
ps |
Make MAXTSIZ, DFLDSIZ, MAXDSIZ, DFLSSIZ, MAXSSIZ, SGROWSIZ loader
tunable.
Reviewed by: peter
MFC after: 2 weeks
|
| 82530 |
30-Aug-2001 |
mike |
o Remove some GCCisms in src/powerpc/include/endian.h.
o Unify <machine/endian.h>'s across all architectures.
o Make bswapXX() functions use a different spelling of u_int16_t and
friends to reduce namespace pollution. The bswapXX() functions
don't actually exist, but we'll probably import these at some
point. Atleast one driver (if_de) depends on bswapXX() for big
endian cases.
o Deprecate byteorder(3) prototypes from <sys/types.h>, these are
now prototyped indirectly in <arpa/inet.h>.
o Deprecate in_addr_t and in_port_t typedefs in <sys/types.h>, these
are now typedef'd in <arpa/inet.h>.
o Change byteorder(3) prototypes to use standards compliant uint32_t
(spelled __uint32_t to reduce namespace pollution).
o Document new preferred headers and standards compliance.
Discussed with: bde
PR: 29946
Reviewed by: bmilekic
|
| 77931 |
09-Jun-2001 |
obrien |
Fix style of defines.
|
| 76785 |
18-May-2001 |
obrien |
Make _BSD_TIME_T_ (time_t) an `int' rather than `long'. This will help
flag errors where programmers assume time_t is a long, which it is not on
64-bit platforms.
Submitted by: bde
|
| 76784 |
18-May-2001 |
obrien |
Style changes -- revert ordering to mostly two revs ago.
Embellish some comments, fix tab'ing.
Requested by: bde
|
| 76701 |
16-May-2001 |
obrien |
Consistently define the rune types.
Follow NetBSD's lead and add a _BSD_MBSTATE_T_ type.
|
| 76700 |
16-May-2001 |
obrien |
Move the int typedefs to the top so they can be used in defining other types.
Ensure every platform has __offsetof.
Make multiple inclusion detection consistent with other
<platform>/include/*.h files.
|
| 72569 |
17-Feb-2001 |
ume |
Correct disordering which is corresponding to bde's fix to
i386/include/ansi.h.
|
| 72510 |
15-Feb-2001 |
ume |
Correct 2nd argument of getnameinfo(3) to socklen_t.
Reviewed by: itojun
|
| 72358 |
11-Feb-2001 |
markm |
RIP <machine/lock.h>.
Some things needed bits of <i386/include/lock.h> - cy.c now has its
own (only) copy of the COM_(UN)LOCK() macros, and IMASK_(UN)LOCK()
has been moved to <i386/include/apic.h> (AKA <machine/apic.h>).
Reviewed by: jhb
|
| 71576 |
24-Jan-2001 |
jasone |
Convert all simplelocks to mutexes and remove the simplelock implementations.
|
| 70786 |
08-Jan-2001 |
obrien |
Remove seconds types we don't use that came in thru the NetBSD heiratage.
|
| 70651 |
04-Jan-2001 |
obrien |
StrongARM platform-specific definitions.
|