343504 |
27-Jan-2019 |
marius |
MFC: r342634 (partial)
o Don't allocate resources for SDMA in sdhci(4) if the controller or the front-end doesn't support SDMA or the latter implements a platform- specific transfer method instead. While at it, factor out allocation and freeing of SDMA resources to sdhci_dma_{alloc,free}() in order to keep the code more readable when adding support for ADMA variants.
o Base the size of the SDMA bounce buffer on MAXPHYS up to the maximum of 512 KiB instead of using a fixed 4-KiB-buffer. With the default MAXPHYS of 128 KiB and depending on the controller and medium, this reduces the number of SDHCI interrupts by a factor of ~16 to ~32 on sequential reads while an increase of throughput of up to ~84 % was seen.
Front-ends for broken controllers that only support an SDMA buffer boundary of a specific size may set SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY and supply a size via struct sdhci_slot. According to Linux, only - unsupported in stable/11 anyway - Qualcomm MSM-type SDHCI controllers are affected by this, though.
Requested by: Shreyank Amartya (unconditional bump to 512 KiB)
o Introduce a SDHCI_DEPEND macro for specifying the dependency of the front-end modules on the sdhci(4) one and bump the module version of sdhci(4) to 2 via an also newly introduced SDHCI_VERSION in order to ensure that all components are in sync WRT struct sdhci_slot.
o In sdhci(4): - Make pointers const were applicable, and - replace a few device_printf(9) calls with slot_printf() for consistency. |
340763 |
22-Nov-2018 |
marius |
MFC: r339007, r340543, r340654
- Add ACPI identifier for AMD eMMC 5.0 controller [1] - Add a quirk handling for AMDI0040 controllers allowing them to do HS400. [2]
Submitted by: Rajesh Kumar [1], Shreyank Amartya (original version) [2] |
338479 |
05-Sep-2018 |
marius |
MFC: r338261
- According to section 2.2.5 of the SDHCI specification version 4.20, SDHCI_TRNS_ACMD12 is to be set only for multiple-block read/write commands without data length information, so don't unconditionally set this bit. The result matches what e. g. Linux does. - Section 2.2.19 of the SDHCI specification version 4.20 states that SDHCI_ACMD12_ERR should be only valid if SDHCI_INT_ACMD12ERR is set and hardware may clear SDHCI_ACMD12_ERR when SDHCI_INT_ACMD12ERR is cleared (differing silicon behavior is specifically allowed, though). Thus, read SDHCI_ACMD12_ERR before clearing SDHCI_INT_ACMD12ERR. While at it, use the 16-bit accessor rather than the 32-bit one for reading the 16-bit SDHCI_ACMD12_ERR. - SDHCI_INT_TUNEERR isn't one of the ROC bits in SDHCI_INT_STATUS so clear it explicitly. - Add missing prototypes and sort them. |
333767 |
17-May-2018 |
marius |
MFC: r333613
The broken DDR52 support of Intel Bay Trail eMMC controllers rumored in the commit log of r321385 has been confirmed via the public VLI54 erratum. Thus, stop advertising DDR52 for these controllers. Note that this change should hardly make a difference in practice as eMMC chips from the same era as these SoCs most likely support HS200 at least, probably even up to HS400ES.
Approved by: re (gjb, kib) |
331501 |
24-Mar-2018 |
ian |
MFC r329479-r329480, r329483, r329506-r329507, r329526, r329529, r329536, r329541, r329730, r329841, r329988, r330397
r329479: Do not try to deallocate memory that wasn't allocated (you'd think that would be safe, but the function also tries to destroy mutexes that never got created).
I guess this can only happen when imx_ehci_detach() is called on the error-exit path from imx_ehci_attach(), and that path never got exercised before today.
r329480: Don't call sdhci_cleanup_slot() if sdhci_init_slot() never got called. Also, do callout_init() very early in attach, so that callout_drain() can be called in detach without worrying about whether it ever got init'd.
r329483: Fix fallout from the import of fresh dts source files from linux 4.15. It appears that node names no longer include leading zeroes in the @address qualifiers, so we have to search for the nodes involved in interrupt fixup using both flavors of name to be compatible with old and new .dtb files.
(You know you're in a bad place when you're applying a workaround to code that exists only as a workaround for another problem.)
r329506: Add a detach method so that this can be a kldunload-friendly module.
r329507: Build modules specific to imx5/imx6 only when building those kernels.
This adds sys/modules/imx with a SUBDIR makefile to make the whole collection of modules that are specific to these SoCs. Initially, that "whole collection" consists of the if_ffec and imx_i2c drivers.
The if_ffec driver is referenced in its existing home in ../ffec rather than moving it into the imx directory, because it's used by powerpc too, but it is no longer built for all armv6/7 systems.
The imx_i2c driver is newly added as a module.
r329526: Allow i2c hardware drivers to declare their own relationships to ofw_iicbus rather than relying on a set of canned EARLY_DRIVER_MODULE() statements in the ofw_iicbus source. This means hw drivers will no longer be required to use one of a few predefined driver names. They will also now be able to decide themselves if they want to use DRIVER_MODULE or EARLY_DRIVER_MODULE and to set which pass to attach on for early modules.
Mainly, this adds extern declarations for the driver and devclass variables. It also renames ofwiicbus_devclass to ofw_iicbus_devclass to be consistant with the way we use ofw_ prefixes on this stuff.
r329529: Give the imx_i2c driver its own name, set up its relationship to ofw_iicbus. Previously it called itself 'iichb' to link up with the EARLY_DRIVER_MODULE declaration in ofw_iicbus.c.
r329536: Add the MODULE_DEPEND()s needed so that the kernel linker can resolve all the symbols at load time when iicbus is not compiled into the kernel.
r329541: Build ofw_iicbus as a module if OPT_FDT is defined.
r329730: Add required header files.
Reported by: andreast@
r329841: Add a missing line continuation.
How many commits does it take to get a simple module makefile working? Apparently at least three.
Pointy hat to: ian
r329988: Instead of building ofw_iicbus as a separate module, just compile it in to the iicbus module for FDT-based systems.
The primary motivation for this is that host controller drivers which declare DRIVER_MODULE(ofw_iicbus, thisdriver, etc, etc) now only need a single MODULE_DEPEND(thisdriver, ofw_iicbus) for runtime linking to resolve all the symbols. With ofw_iicbus and iicbus in separate modules, drivers would need to declare a MODULE_DEPEND() on both, because symbol lookup is non-recursive through the dependency chain. Requiring a driver to have MODULE_DEPENDS() on both amounts to requiring the drivers to understand the kobj inheritence details of how ofw_iicbus is implemented, which seems like something they shouldn't have to know (and could even change some day).
Also, this is somewhat analogous to how the drivers get built when compiled into the kernel. You don't have to ask for ofw_iicbus separately, it just gets built in along with iicbus when option FDT is in effect.
r330397: Fix a paste-o: use the IICBUS version constants, not IICBB bitbang driver's. |
331044 |
16-Mar-2018 |
eadler |
MFC r305373,r312344,r318095,r319117,r320948,r320953,r328528:
siba(4): Add missing bhnd_device/bhnd_device_quirk table terminator entries.
This resulted in an over-read on siba chipsets that failed to match the existing entries.
r312344 | sbruno | 2017-01-17 14:52:48 +0000 (Tue, 17 Jan 2017) | 7 lines
Add 4k quirk for Micron 5100 and Intel S3610 SSDs
r318095 | loos | 2017-05-09 19:01:57 +0000 (Tue, 09 May 2017) | 9 lines
Add a new SDHCI quirk, SDHCI_QUIRK_BROKEN_AUTO_STOP, to workaround controllers that do not support or have broken ACMD12 implementations.
r319117 | wma | 2017-05-29 09:22:53 +0000 (Mon, 29 May 2017) | 16 lines
Introduce Genesys GL3224 quirks
The Genesys chip is failing when issueing READ_CAP(16) command. Force a quirk to disable it and use READ_CAP(10) instead.
Also, depending on used firmware, GL3224 can be recognized either as 'storage device' or 'mass storage class' - enable both variants in scsi_quirk_table.
r320948 | sbruno | 2017-07-13 15:33:08 +0000 (Thu, 13 Jul 2017) | 6 lines
Add 4K quirks for Samsung 750 EVO SSD
r320953 | sbruno | 2017-07-13 16:56:26 +0000 (Thu, 13 Jul 2017) | 5 lines
Add 4k and NCQ_TRIM_BROKEN quirks for Samsung 845 SSDs.
r328528 | ian | 2018-01-29 03:24:02 +0000 (Mon, 29 Jan 2018) | 3 lines
Add a NO_GETMAXLUN quirk for the JMicron JMS567 USB to SATA bridge, to prevent lengthy timeout pauses while probing/attaching drives. |
331034 |
15-Mar-2018 |
marius |
MFC: r327339, r327924
- There is no need to keep the tuning error and re-tuning interrupts enabled (though, no interrupt generation enabled for them) all the time as soon as (re-)tuning is supported; only enable them and let them generate interrupts when actually using (re-)tuning. - Also disable all interrupts except SDHCI_INT_DATA_AVAIL ones while executing tuning and not just their signaling. - Set the tuning error and re-tuning interrupt enable bits based on the SDHCI_TUNING_ENABLED rather than the SDHCI_TUNING_SUPPORTED flag, i. e. only when (re-)tuning is actually used. Currently, this change makes no net difference, though. |
327638 |
06-Jan-2018 |
ian |
MFC r325045, r325054-r325056, r325061, r325063, r325065
r325045: Actually release resources in detach() rather than just returning EBUSY. This will enable use of 'devctl disable', allow creation of a module, etc.
r325054: Increase the alignment of the rx/tx descriptor ring buffers to 64 bytes.
16 was the correct alignment for older hardware, but the imx7 requires 64-byte alignment, which is a fine value to use on all systems.
PR: 222634 Submitted by: sebastian.huber@embedded-brains.de
r325055: Add FECFLAG_AVB variant flag to support new features on imx7.
This flag is analogous to the Linux driver FEC_QUIRK_HAS_AVB. It indicates an FEC with support for Audio Video Bridging (AVB). This indicator is used for various other parts in the Linux driver (drivers/net/ethernet/freescale/fec_main.c).
Use it to customize the receive/transmit buffer alignment. The receive buffer alignment increased to 64-bytes on the i.MX 6SoloX and i.MX 7Dual. There are no hard alignment restrictions for transmit buffers on these chips.
Fix the ffec_softc::fectype type to provide enough storage for the feature flags.
PR: 222634 Submitted by: sebastian.huber@embedded-brains.de
r325056: Avoid AXI bus issues due to a MAC reset on imx6sx and imx7.
When the FEC is connected to the AXI bus (indicated by AVB flag), a MAC reset while a bus transaction is pending can hang the bus. Instead of resetting, turn off the ENABLE bit, which allows the hardware to complete any in-progress transfers (appending a bad CRC to any partial packet) and release the AXI bus. This could probably be done unconditionally for all hardware variants, but that hasn't been tested.
PR: 222634 Submitted by: sebastian.huber@embedded-brains.de
r325061: Support up to 3 IRQs in the ffec driver.
Newer hardware splits the interrupts onto 3 different irq lines, but the docs barely mention that there are multiple interrupts, and do not detail how they're split up. The code now supports 1-3 irqs, and uses the same interrupt service routine to handle all of them.
I modified the submitted changes to use bus_alloc_resources() instead of using loops to allocate each irq separately. Thus, blame any bugs on me (I can't actually test on imx7 hardware).
PR: 222634 Submitted by: sebastian.huber@embedded-brains.de
r325063: Use the 16-bit receive shift feature in ffec hardware that supports it.
When available, enabling this feature causes the hardware to write data to the receive buffer starting at a 16-bit offset from the start address. This eliminates the need to copy the data after receiving to re-align the protocol headers to a 32-bit boundary.
PR: 222634 Submitted by: sebastian.huber@embedded-brains.de
r325065: Split the hardware type enum and the hw feature flags bits into separate fields in the softc; they're ORed together in the ofw_compat_data.
I already caught myself doing 'sc->fectype == <enum val>' without masking out the feature bits in one place, and that's sure to happen again. Glomming them together is convenient for storing them in the ofw_compat_data array, but there's no reason to keep them together in the softc. |
322121 |
06-Aug-2017 |
marius |
MFC: r321589
- Check the slot type capability, set SDHCI_SLOT_{EMBEDDED,NON_REMOVABLE} for embedded slots. Fail in the sdhci(4) initialization for slot type shared, which is completely unsupported by this driver at the moment. [1] For Intel eMMC controllers, taking the embedded slot type into account obsoltes setting SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE so remove these quirk entries. - Hide the 1.8 V VDD capability when the slot is detected as non-embedded, as the SDHCI specification explicitly states that 1.8 V VDD is applicable to embedded slots only. [2] - Define some easy bits of the SDHCI specification v4.20. [3] - Don't leak bus_dma(9) resources in failure paths of sdhci_init_slot().
Obtained from: DragonFlyBSD 65704a46 [1], 7ba10b88 [2], 0df14648 [3] |
322119 |
06-Aug-2017 |
marius |
MFC: r319350, r321385, r321490, r321588, r321948
o Use SDHCI_CAN_DRIVE_TYPE_{A,C,D} to check for driver type support in SDHCI_CAPABILITIES2 instead of SDHCI_CTRL2_DRIVER_TYPE_{A,C,D} which are meant for setting the driver type in SDHCI_HOST_CONTROL2.
o Add support for eMMC HS200 and HS400 bus speed modes at 200 MHz to sdhci(4), mmc(4) and mmcsd(4).
On the system where the addition of DDR52 support increased the read throughput to ~80 MB/s (from ~45 MB/s at high speed), HS200 yields ~154 MB/s and HS400 ~187 MB/s, i. e. performance now has more than quadrupled compared to pre-r315598 (pre-r318494 in stable/11).
However, in fact this isn't a feature-only change; there are boards based on Intel Bay Trail where DDR52 is problematic and the suggested workaround is to use HS200 mode instead. So far exact details are unknown, however, i. e. whether that's due to a defect in these SoCs or on the boards.
Moreover, due to the above changes requiring to be aware of possible MMC siblings in the fast path of mmc(4), corresponding information now is cached in mmc_softc. As a side-effect, mmc_calculate_clock(), now longer will trigger a panic in low memory situations and all of mmc(4) operate on the same set of child devices.
o Fix a bug in the failure reporting of mmcsd_delete() that could lead to a panic.
o Fix 2 bugs on resume, one in mmcsd(4) that could lead to a panic and another one in mmc(4) that could lead to devices no longer working.
o Fix a memory leak in mmcsd_ioctl() in case copyin(9) fails. [1]
o Fix missing variable initialization in mmc_switch_status(). [2]
o Fix R1_SWITCH_ERROR detection in mmc_switch_status(). [3]
o Handle the case of device_add_child(9) failing, for example due to a memory shortage, gracefully in mmc(4) and sdhci(4), including not leaking memory for the instance variables in case of mmc(4), also fixing [4].
o Correctly use the size of a pointer rather than that of a pointer to a pointer (this bug was present in head r321385 only, i. e. not in a stable branch). [5]
o Handle the case of an unknown SD CSD version in mmc_decode_csd_sd() gracefully instead of calling panic(9).
o Again, check and handle the return values of some additional function calls in mmc(4) instead of assuming that everything went right or mark non-fatal errors by casting the return value to void.
o Correct a typo in the Linux IOCTL compatibility; it should have been MMC_IOC_MULTI_CMD rather than MMC_IOC_CMD_MULTI.
o Now that we are reaching ever faster speeds (more improvement in this regard is to be expected when adding ADMA support to sdhci(4)), apply a few micro-optimizations to mmc(4), mmcsd(4) and sdhci(4).
o Correct confusing and error prone mix-ups between "br" or "bridge" in mmc(4) and mmcsd(4) where - according to the terminology outlined in comments of bridge.h and mmcbr_if.m around since their addition in r163516 - the bus is meant and used instead.
o Remove comment lines from bridge.h incorrectly suggesting that there would be a MMC bridge base class driver.
o Update comments in bridge.h regarding the star topology of SD and SDIO; since version 3.00 of the SDHCI specification, for eSD and eSDIO bus topologies are actually possible in form of so called "shared buses" (in some subcontext later on renamed to "embedded" buses).
Reported by: Coverity CID: 1372612 [1], 1372624 [2], 1372594 [3], 1007069 [4], 1378432 [5] |
320898 |
11-Jul-2017 |
marius |
MFC: r320577, r320620
Retry up to 2 ms to enable bus power as at least with some Intel SDHCI/eMMC controllers the first attempt after a D3 to D0 transition, i. e. when the firmware has put the devices into D3 state before, can fail. |
318496 |
18-May-2017 |
marius |
MFC: r318282
- Unlike as in the PCI case, when attached to ACPI, Intel Bay Trail and Braswell eMMC and SDXC controllers share the same IDs. Like in the PCI case, Braswell eMMC needs the SDHCI_QUIRK_DATA_TIMEOUT_1MHZ quirk (see r311794 for the corresponding change to the sdhci(4) PCI PCI front-end), though. However, due to the shared ACPI IDs, this is trickier to do. - Intel Apollo Lake eMMC and SDXC controllers are affected by the APL18 ("Using 32-bit Addressing Mode With SD/eMMC Controller May Lead to Unpredictable System Behavior") silicon bug. When this erratum hits, typically both SDHCI and XHCI controllers wedge. According to Intel, using ADMA2 with 64-bit addressing and 96-bit descriptors serves as a workaround. Until such times when sdhci(4) has ADMA2 support, flag DMA as broken for affected interfaces. This turns out to work around the problem, too, at the cost of performance. - In the sdhci(4) ACPI front-end, probe the Intel Apollo Lake eMMC and SDXC controllers, too. |
318494 |
18-May-2017 |
marius |
MFC: r315598
o Add support for eMMC DDR bus speed mode up to 52 MHz to sdhci(4) and mmc(4). Given that support for DDR52 is not denoted by SDHCI capability registers, availability of that timing is indicated by a new quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI controllers so far.
Compared to 50 MHz at SDR high speed typically yielding ~45 MB/s read throughput with the eMMC chips tested, read performance goes up to ~80 MB/s at DDR52.
As a side-effect, this change also fixes communication with some eMMC devices at SDR high speed mode due to the signaling voltage and UHS bits in the SDHCI controller no longer being left in an inappropriate state.
o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as hw.sdhci.quirk_set, which (when hooked up in the front-end) allow to set/clear sdhci(4) quirks for debugging and testing purposes. However, especially for SDHCI controllers on the PCI bus which have no specific support code so far and, thus, are picked up as generic SDHCI controllers, hw.sdhci.quirk_set allows for setting the necessary quirks (if required).
o In mmc(4), check and handle the return values of some more function calls instead of assuming that everything went right. In case failures actually are not problematic, indicate that by casting the return value to void. |
318199 |
11-May-2017 |
marius |
MFC: r315431
- Adds macros for the content of SDHCI_ADMA_ERR and SDHCI_HOST_CONTROL2 registers. - Add slot type capability bits. These bits should allow recognizing removable card slots, embedded cards and shared buses (shared bus supposedly is always comprised of non-removable cards). - Dump CAPABILITIES2, ADMA_ERR, HOST_CONTROL2 and ADMA_ADDRESS_LO registers in sdhci_dumpregs(). - The drive type support flags in the CAPABILITIES2 register are for drive types A,C,D, drive type B is the default setting (value 0) of the drive strength field in the SDHCI_HOST_CONTROL2 register.
Obtained from: DragonFlyBSD (9e3c8f63, 455bd1b1) |
318197 |
11-May-2017 |
marius |
MFC: r312939, r313250, r314811 (partial), r314887 (partial), r315760, r315845, 315430, r317981, r315466
o Fix some overly long lines, whitespace and other bugs according to style(9) as well as spelling etc. in mmc(4), mmcsd(4) and sdhci(4).
o In the mmc(4) bridges and sdhci(4) (bus) front-ends: - Remove redundant assignments of the default bus_generic_print_child device method, - use DEVMETHOD_END, - use NULL instead of 0 for pointers.
o Trim/adjust includes.
o Add and use a MMC_DECLARE_BRIDGE macro for declaring mmc(4) bridges as kernel drivers and their dependency onto mmc(4).
o Add support for eMMC "partitions". Besides the user data area, i. e. the default partition, eMMC v4.41 and later devices can additionally provide up to: 1 enhanced user data area partition 2 boot partitions 1 RPMB (Replay Protected Memory Block) partition 4 general purpose partitions (optionally with a enhanced or extended attribute)
Besides simply subdividing eMMC devices, some Intel NUCs having UEFI code in the boot partitions etc., another use case for the partition support is the activation of pseudo-SLC mode, which manufacturers of eMMC chips typically associate with the enhanced user data area and/ or the enhanced attribute of general purpose partitions.
CAVEAT EMPTOR: Partitioning eMMC devices is a one-time operation.
o Now that properly issuing CMD6 is crucial (so data isn't written to the wrong partition for example), make a step into the direction of correctly handling the timeout for these commands in the MMC layer. Also, do a SEND_STATUS when CMD6 is invoked with an R1B response as recommended by relevant specifications.
o Add an IOCTL interface to mmcsd(4); this is sufficiently compatible with Linux so that the GNU mmc-utils can be ported to and used with FreeBSD (note that due to the remaining deficiencies outlined above SANITIZE operations issued by/with `mmc` currently most likely will fail). These latter have been added to ports as sysutils/mmc-utils. Among others, the `mmc` tool of mmc-utils allows for partitioning eMMC devices (tested working).
o For devices following the eMMC specification v4.41 or later, year 0 is 2013 rather than 1997; so correct this for assembling the device ID string properly.
o Let mmcsd.ko depend on mmc.ko. Additionally, bump MMC_VERSION as at least for some of the above a matching pair is required.
o In the ACPI front-end of sdhci(4) describe the Intel eMMC and SDXC controllers as such in order to match the PCI one. Additionally, in the entry for the 80860F14 SDXC controller remove the eMMC-only SDHCI_QUIRK_INTEL_POWER_UP_RESET. |
314510 |
01-Mar-2017 |
ian |
MFC r308186, r308188, r308231, r308232:
Move imx_sdhci driver over to a dev/sdhci in preparation for QorIQ support. Freescale uses eSDHC in both i.MX (ARM) and QorIQ (PowerPC), with slight differences. This is part one in unifying the drivers.
Merge i.MX and PowerPC SDHCI drivers Summary: i.MX5 and PowerPC use a very similar eSDHC controller, which is also similar to the uSDHC controller used by i.MX6. The imx_sdhci driver works almost completely with PowerPC, with some minor tweaks.
Fix the build. protctl is only used on powerpc. While here, remove the need to check the SVR SPR, as others may be compatible with the p1022-esdhc type.
Since it's no longer accessing a powerpc-specific register, drop the #ifdef. |
314508 |
01-Mar-2017 |
ian |
MFC r311734, r311735, r311951, r314071:
Add new helper routines for sdhci bridge drivers that use gpio pins for card presence and write protect switch detection.
Use the new sdhci_fdt_gpio helper functions to add full support for FDT gpio pins for detecting card insert/remove and write protect for ti_sdhci.
Include sys/systm.h for use of bootverbose.
Revert to ti_sdhci driver's historic behavior: assume an sd card is writable if the fdt data doesn't provide a gpio pin for reading the write protect switch and also doesn't contain a "wp-disable" property. |
312399 |
18-Jan-2017 |
marius |
MFC: r310309, r310340-310341, r311664, r311793-r311794
o sdhci/mmc: Minor whitespace cleanups
o Add Braswell PCI IDs for Intel Cherryview
o mmc: Accept even lower voltage for Cherryview
And HP x2 210, per DragonFlyBSD 240bd9cd58f8259c12c14a8006837e698.
o In mmcsd_task(), bio_resid was not being set to 0 on a successful read or write, resulting in random short-read and short-write returns for requests. Fixing this fixes nominal block I/O via mmcsd(4).
Obtained from: DragonFlyBSD (fd4b97583be1a1e57234713c25f6e81bc0411cb0)
o Add support for Intel Apollo Lake and Bay Trail eMMC PCI controllers.
o Flesh out the support for Intel Braswell eMMC controllers further.
o In sdhci_init_slot(), use the right capability field for determining the announced bus width based on MMC_CAP_*_BIT_DATA. |
312244 |
15-Jan-2017 |
ian |
MFC r308187, r311660, r311693, r311727, r311797:
Toggle card insert/remove interrupt enable bits on events.
Add a new sdhci interface method, get_card_present().
Now that the PRESENT_STATE register is only used for the inhibit bits loop in this function, sdhci_start_command(), eliminate the state variable and restructure the loop to read the register just once at the top of the loop.
Add support for non-removable media, and a quirk to use polling to detect card insert/remove events on controllers that don't implement the insert and remove interrupts.
Add sdhci_handle_card_present_locked() that can be called from the interrupt handler which already holds the mutex, and have sdhci_handle_card_present() be just a tiny wrapper that does the locking for external callers. |
299414 |
11-May-2016 |
trasz |
Make sdhci(4) work after suspend/resume for chipsets that require the frequency quirk. This makes it work on eg ThinkPad T420.
Without it, after resume one can see this:
mmc0: ACMD42 failed, RESULT: 4 mmcsd0: Error indicated: 1 Timeout mmcsd0: Error indicated: 2 Bad CRC mmcsd0: Error indicated: 2 Bad CRC mmcsd0: Error indicated: 2 Bad CRC mmcsd0: Error indicated: 2 Bad CRC sdhci_pci0-slot0: Got data interrupt 0x00200000, but there is no active command. sdhci_pci0-slot0: ============== REGISTER DUMP ============== sdhci_pci0-slot0: Sys addr: 0x06317200 | Version: 0x00000502 sdhci_pci0-slot0: Blk size: 0x00000200 | Blk cnt: 0x00000010 sdhci_pci0-slot0: Argument: 0x00000200 | Trn mode: 0x00000037 sdhci_pci0-slot0: Present: 0x01ff0000 | Host ctl: 0x00000007 sdhci_pci0-slot0: Power: 0x0000000f | Blk gap: 0x00000000 sdhci_pci0-slot0: Wake-up: 0x00000000 | Clock: 0x00000007 sdhci_pci0-slot0: Timeout: 0x0000000d | Int stat: 0x00000000 sdhci_pci0-slot0: Int enab: 0x01ff00fb | Sig enab: 0x01ff00fb sdhci_pci0-slot0: AC12 err: 0x00000000 | Slot int: 0x00000000 sdhci_pci0-slot0: Caps: 0x21e8c8b2 | Max curr: 0x00000040 sdhci_pci0-slot0: =========================================== sdhci_pci0-slot0: Got data interrupt 0x00200000, but there is no active command. sdhci_pci0-slot0: ============== REGISTER DUMP ============== sdhci_pci0-slot0: Sys addr: 0x06317200 | Version: 0x00000502 sdhci_pci0-slot0: Blk size: 0x00000200 | Blk cnt: 0x00000001 sdhci_pci0-slot0: Argument: 0x00000040 | Trn mode: 0x00000013 sdhci_pci0-slot0: Present: 0x01ff0000 | Host ctl: 0x00000007 sdhci_pci0-slot0: Power: 0x0000000f | Blk gap: 0x00000000 sdhci_pci0-slot0: Wake-up: 0x00000000 | Clock: 0x00000007 sdhci_pci0-slot0: Timeout: 0x0000000d | Int stat: 0x00000000 autofs_flush: /net flushed sdhci_pci0-slot0: Int enab: 0x01ff00fb | Sig enab: 0x01ff00fb autofs_flush: /media flushed sdhci_pci0-slot0: AC12 err: 0x00000000 | Slot int: 0x00000000 sdhci_pci0-slot0: Caps: 0x21e8c8b2 | Max curr: 0x00000040 sdhci_pci0-slot0: ===========================================
Afterwards all operations on /dev/mmcsd0 fail with EIO.
Reviewed by: jhb@ MFC after: 1 month Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D6265
|
296135 |
27-Feb-2016 |
jhibbits |
Replace several bus_alloc_resource() calls with bus_alloc_resource_any()
Most of these are BARs, and we allocate them in their entirety. The one outlier in this is amdsbwd, which calls bus_set_resource() prior.
Reviewed by: jhb Differential Revision: https://reviews.freebsd.org/D5370 (partial)
|
289359 |
15-Oct-2015 |
adrian |
Add support for the BCM57765 card reader.
This patch adds support for the BCM57765[2] card reader function included in Broadcom's BCM57766 ethernet/sd3.0 controller. This controller is commonly found in laptops and Apple hardware (MBP, iMac, etc).
The BCM57765 chipset is almost fully compatible with the SD3.0 spec, but does not support deriving a frequency below 781KHz from its default base clock via the standard SD3.0-configured 10-bit clock divisor.
If such a divisor is set, card identification (which requires a 400KHz clock frequency) will time out[1].
As a work-around, I've made use of an undocumented device-specific clock control register to switch the controller to a 63MHz clock source when targeting clock speeds below 781KHz; the clock source is likewise switched back to the 200MHz clock when targeting speeds greater than 781KHz.
Additionally, this patch fixes a small sdhci_pci bug; the sdhci_pci_softc->quirks flag was not copied to the sdhci_slot, resulting in `quirk` behavior not being applied by sdhci.c.
[1] A number of Linux/FreeBSD users have noted that bringing up the chipsets' associated ethernet interface will allow SD cards to enumerate (slowly). This is a controller implementation side-effect triggered by the ethernet driver's reading of the hardware statistics registers.
[2] This may also fix card detection when using the BCM57785 chipset, but I don't have access to the BCM57785 chipset and can't verify.
I actually snagged some BCM57785 hardware recently (2012 Retina MacBook Pro) and can confirm that this also fixes card enumeration with the BCM57785 chipset; with the patch, I can boot off of the internal sdcard reader.
PR: kern/203385 Submitted by: Landon Fuller <landon@landonf.org>
|
283263 |
21-May-2015 |
loos |
Raise the SDHCI timeout to 10 seconds and add a sysctl to allow changing this value at runtime.
The SD card specification says that a block write or a block erase can take up to 250ms to complete and thus, under some circumstances, the existent 2 seconds timeout was triggering with normal usage.
This change fixes the sporadic controller timeout that happens on RPi and RPi 2.
Discussed with: ian (some time ago)
|
277307 |
17-Jan-2015 |
ian |
Add a new SDHCI quirk, SDHCI_QUIRK_DONT_SET_HISPD_BIT. Apparently some sdhci controllers, such as the one on a Raspberry Pi, mishandle the signal timing in high speed signaling mode, but run just fine in standard mode with the bus running at frequencies between 25-50MHz (which shouldn't work).
This is the solution adopted by U-Boot and other OSes (linux and *BSD) for the timeouts on Raspberry Pi boards with certain SD cards. Some research shows that this quirk is also used on a few other boards, so the fix is a generic quirk instead of being in the RPi-specific driver code.
This change is based on information discovered by Michal Meloun.
|
276469 |
31-Dec-2014 |
marius |
- Switching the mode of Ricoh R5CE823 to SD2.0 causes their PCI device ID to change to 0xe822, which may be persistent across reboots and, thus, confuse other OSes. Therefore, restore the original mode and frequency setting on detach and shutdown. - Report Ricoh R5CE822 as such. - According to Linux, Ricoh R5CE822 also need SDHCI_QUIRK_LOWER_FREQUENCY. - Nuke an unused softc member.
MFC after: 3 days
|
275950 |
20-Dec-2014 |
ian |
Add a new sdhci quirk, SDHCI_QUIRK_WAITFOR_RESET_ASSERTED, to work around TI OMAP controllers which will return the reset-in-progress bit as zero if you read the status register too fast after setting the reset bit.
The zero is apparently from a stale snapshot of the internal state presented in the interface register, and leads to a false indication that the reset is complete when it either hasn't started yet or is in-progress. The workaround is to first loop until the bit is seen as asserted, then do the normal loop waiting to see it de-asserted.
Submitted by: Michal Meloun <meloun@miracle.cz>
|
267961 |
27-Jun-2014 |
hselasky |
Extend the meaning of the CTLFLAG_TUN flag to automatically check if there is an environment variable which shall initialize the SYSCTL during early boot. This works for all SYSCTL types both statically and dynamically created ones, except for the SYSCTL NODE type and SYSCTLs which belong to VNETs. A new flag, CTLFLAG_NOFETCH, has been added to be used in the case a tunable sysctl has a custom initialisation function allowing the sysctl to still be marked as a tunable. The kernel SYSCTL API is mostly the same, with a few exceptions for some special operations like iterating childrens of a static/extern SYSCTL node. This operation should probably be made into a factored out common macro, hence some device drivers use this. The reason for changing the SYSCTL API was the need for a SYSCTL parent OID pointer and not only the SYSCTL parent OID list pointer in order to quickly generate the sysctl path. The motivation behind this patch is to avoid parameter loading cludges inside the OFED driver subsystem. Instead of adding special code to the OFED driver subsystem to post-load tunables into dynamically created sysctls, we generalize this in the kernel.
Other changes: - Corrected a possibly incorrect sysctl name from "hw.cbb.intr_mask" to "hw.pcic.intr_mask". - Removed redundant TUNABLE statements throughout the kernel. - Some minor code rewrites in connection to removing not needed TUNABLE statements. - Added a missing SYSCTL_DECL(). - Wrapped two very long lines. - Avoid malloc()/free() inside sysctl string handling, in case it is called to initialize a sysctl from a tunable, hence malloc()/free() is not ready when sysctls from the sysctl dataset are registered. - Bumped FreeBSD version to indicate SYSCTL API change.
MFC after: 2 weeks Sponsored by: Mellanox Technologies
|
264097 |
04-Apr-2014 |
ian |
When changing the sd bus clock divisor, clear just the bus clock enable bit before changing the divisor bits in the register. We were writing a zero to the register, which clears the enable, but also cleared the divisor bits at the same time. That's a violation of the sdhci spec, which says the divisor can only be changed when the clock is disabled. This has worked okay on most hardware for years, but the TI OMAP controller would misbehave after changing the divisor improperly.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>
|
261983 |
16-Feb-2014 |
ian |
After a timeout, reset the controller using SDHCI_RESET_CMD|SDHCI_RESET_DATA rather than SDHCI_RESET_ALL; the latter turns off clocks and power, removing any possibility of recovering from the error.
Also, double the timeout to 2 seconds. Despite what the SD spec says about all transactions completing in 250ms or less, I have a card which sometimes takes more than a second to complete a write.
|
261945 |
15-Feb-2014 |
ian |
Add timeout logic to sdhci, separate from the timeouts done by the hardware.
If the hardware is not in a good state (like maybe clocks aren't running because of a configuration glitch) its timeout clock may also not work correctly, and the next command sent will hang that thread forever. The thread in question is usually the one and only thread (at init time) or a bio queue worker thread whose lockup will eventually lead to the whole system locking up when it runs out of buffers.
No sd card command should take longer than 250ms. This new code establishes a 1-second timeout to allow plenty of safety margin over that.
|
261940 |
15-Feb-2014 |
ian |
Increase the wait time for acquiring the bus from 10 to 250ms.
Normally it never needs to wait here at all; waiting is done at the end of the prior command. When doing a crash dump, the normal interrupt mechanism isn't used; instead the interrupt handler is called repeatedly in a polling-like manner. This can subvert hardware-specific drivers and lead to trying to start a new command while the previous command is still busy on the bus. Since the SD spec says the longest a card can take to execute any command is 250ms, use that as a timeout.
|
261410 |
02-Feb-2014 |
ian |
Follow r261352 by updating all drivers which are children of simplebus to check the status property in their probe routines.
Simplebus used to only instantiate its children whose status="okay" but that was improper behavior, fixed in r261352. Now that it doesn't check anymore and probes all its children; the children all have to do the check because really only the children know how to properly interpret their status property strings.
Right now all existing drivers only understand "okay" versus something- that's-not-okay, so they all use the new ofw_bus_status_okay() helper.
|
254507 |
19-Aug-2013 |
ian |
Allow a hardware driver to pass clock frequencies into the sdhci driver.
The sdhci spec says that if the base or timeout clock frequency in the capabilities register is zero, the driver must obtain the frequency "from another source." This change defines that other source to be the low-level hardware driver, which can pre-set the frequencies in slot.max_clk and slot.timeout_clk before calling sdhci_init_slot().
This helps with a growing number of SoCs that have sdhci base clock frequencies that either won't fit into the range allowed by the number of bits available in the capabilities register, or the frequency is runtime- configurable.
|
254423 |
16-Aug-2013 |
ian |
When the timeout clock is based on the SD clock, the timeout counter has to be recalculated every time the SD clock frequency changes.
Also, tidy up the counter calculation... it makes no sense to calculate a value one larger than the limit, then whine that it's too large and truncate it to the limit. If the BROKEN_TIMEOUT quirk is set, don't calculate the counter at all, just set it to the limit value.
|