ig4_pci.c revision 312399
1/* 2 * Copyright (c) 2014 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Matthew Dillon <dillon@backplane.com> and was subsequently ported 6 * to FreeBSD by Michael Gmelin <freebsd@grem.de> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36#include <sys/cdefs.h> 37__FBSDID("$FreeBSD: stable/11/sys/dev/ichiic/ig4_pci.c 312399 2017-01-18 23:25:46Z marius $"); 38 39/* 40 * Intel fourth generation mobile cpus integrated I2C device. 41 * 42 * See ig4_reg.h for datasheet reference and notes. 43 */ 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/kernel.h> 48#include <sys/module.h> 49#include <sys/errno.h> 50#include <sys/lock.h> 51#include <sys/mutex.h> 52#include <sys/sx.h> 53#include <sys/syslog.h> 54#include <sys/bus.h> 55 56#include <machine/bus.h> 57#include <sys/rman.h> 58#include <machine/resource.h> 59 60#include <dev/pci/pcivar.h> 61#include <dev/pci/pcireg.h> 62#include <dev/iicbus/iiconf.h> 63 64#include <dev/ichiic/ig4_reg.h> 65#include <dev/ichiic/ig4_var.h> 66 67static int ig4iic_pci_detach(device_t dev); 68 69#define PCI_CHIP_LYNXPT_LP_I2C_1 0x9c618086 70#define PCI_CHIP_LYNXPT_LP_I2C_2 0x9c628086 71#define PCI_CHIP_BRASWELL_I2C_1 0x22c18086 72#define PCI_CHIP_BRASWELL_I2C_2 0x22c28086 73#define PCI_CHIP_BRASWELL_I2C_3 0x22c38086 74#define PCI_CHIP_BRASWELL_I2C_5 0x22c58086 75#define PCI_CHIP_BRASWELL_I2C_6 0x22c68086 76#define PCI_CHIP_BRASWELL_I2C_7 0x22c78086 77 78static int 79ig4iic_pci_probe(device_t dev) 80{ 81 switch(pci_get_devid(dev)) { 82 case PCI_CHIP_LYNXPT_LP_I2C_1: 83 device_set_desc(dev, "Intel Lynx Point-LP I2C Controller-1"); 84 break; 85 case PCI_CHIP_LYNXPT_LP_I2C_2: 86 device_set_desc(dev, "Intel Lynx Point-LP I2C Controller-2"); 87 break; 88 case PCI_CHIP_BRASWELL_I2C_1: 89 device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 1"); 90 break; 91 case PCI_CHIP_BRASWELL_I2C_2: 92 device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 2"); 93 break; 94 case PCI_CHIP_BRASWELL_I2C_3: 95 device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 3"); 96 break; 97 case PCI_CHIP_BRASWELL_I2C_5: 98 device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 5"); 99 break; 100 case PCI_CHIP_BRASWELL_I2C_6: 101 device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 6"); 102 break; 103 case PCI_CHIP_BRASWELL_I2C_7: 104 device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 7"); 105 break; 106 default: 107 return (ENXIO); 108 } 109 return (BUS_PROBE_DEFAULT); 110} 111 112static int 113ig4iic_pci_attach(device_t dev) 114{ 115 ig4iic_softc_t *sc = device_get_softc(dev); 116 int error; 117 118 sc->dev = dev; 119 sc->regs_rid = PCIR_BAR(0); 120 sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 121 &sc->regs_rid, RF_ACTIVE); 122 if (sc->regs_res == NULL) { 123 device_printf(dev, "unable to map registers\n"); 124 ig4iic_pci_detach(dev); 125 return (ENXIO); 126 } 127 sc->intr_rid = 0; 128 if (pci_alloc_msi(dev, &sc->intr_rid)) { 129 device_printf(dev, "Using MSI\n"); 130 } 131 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 132 &sc->intr_rid, RF_SHAREABLE | RF_ACTIVE); 133 if (sc->intr_res == NULL) { 134 device_printf(dev, "unable to map interrupt\n"); 135 ig4iic_pci_detach(dev); 136 return (ENXIO); 137 } 138 sc->platform_attached = 1; 139 140 error = ig4iic_attach(sc); 141 if (error) 142 ig4iic_pci_detach(dev); 143 144 return (error); 145} 146 147static int 148ig4iic_pci_detach(device_t dev) 149{ 150 ig4iic_softc_t *sc = device_get_softc(dev); 151 int error; 152 153 if (sc->platform_attached) { 154 error = ig4iic_detach(sc); 155 if (error) 156 return (error); 157 sc->platform_attached = 0; 158 } 159 160 if (sc->intr_res) { 161 bus_release_resource(dev, SYS_RES_IRQ, 162 sc->intr_rid, sc->intr_res); 163 sc->intr_res = NULL; 164 } 165 if (sc->intr_rid != 0) 166 pci_release_msi(dev); 167 if (sc->regs_res) { 168 bus_release_resource(dev, SYS_RES_MEMORY, 169 sc->regs_rid, sc->regs_res); 170 sc->regs_res = NULL; 171 } 172 173 return (0); 174} 175 176static device_method_t ig4iic_pci_methods[] = { 177 /* Device interface */ 178 DEVMETHOD(device_probe, ig4iic_pci_probe), 179 DEVMETHOD(device_attach, ig4iic_pci_attach), 180 DEVMETHOD(device_detach, ig4iic_pci_detach), 181 182 DEVMETHOD(iicbus_transfer, ig4iic_transfer), 183 DEVMETHOD(iicbus_reset, ig4iic_reset), 184 DEVMETHOD(iicbus_callback, iicbus_null_callback), 185 186 DEVMETHOD_END 187}; 188 189static driver_t ig4iic_pci_driver = { 190 "ig4iic_pci", 191 ig4iic_pci_methods, 192 sizeof(struct ig4iic_softc) 193}; 194 195static devclass_t ig4iic_pci_devclass; 196 197DRIVER_MODULE_ORDERED(ig4iic_pci, pci, ig4iic_pci_driver, ig4iic_pci_devclass, 0, 0, 198 SI_ORDER_ANY); 199MODULE_DEPEND(ig4iic_pci, pci, 1, 1, 1); 200MODULE_DEPEND(ig4iic_pci, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); 201MODULE_VERSION(ig4iic_pci, 1); 202