sdhci.h revision 322119
1/*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/sdhci/sdhci.h 322119 2017-08-06 16:07:25Z marius $ 26 */ 27 28#ifndef __SDHCI_H__ 29#define __SDHCI_H__ 30 31#define DMA_BLOCK_SIZE 4096 32#define DMA_BOUNDARY 0 /* DMA reload every 4K */ 33 34/* Controller doesn't honor resets unless we touch the clock register */ 35#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1 << 0) 36/* Controller really supports DMA */ 37#define SDHCI_QUIRK_FORCE_DMA (1 << 1) 38/* Controller has unusable DMA engine */ 39#define SDHCI_QUIRK_BROKEN_DMA (1 << 2) 40/* Controller doesn't like to be reset when there is no card inserted. */ 41#define SDHCI_QUIRK_NO_CARD_NO_RESET (1 << 3) 42/* Controller has flaky internal state so reset it on each ios change */ 43#define SDHCI_QUIRK_RESET_ON_IOS (1 << 4) 44/* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 45#define SDHCI_QUIRK_32BIT_DMA_SIZE (1 << 5) 46/* Controller needs to be reset after each request to stay stable */ 47#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1 << 6) 48/* Controller has an off-by-one issue with timeout value */ 49#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1 << 7) 50/* Controller has broken read timings */ 51#define SDHCI_QUIRK_BROKEN_TIMINGS (1 << 8) 52/* Controller needs lowered frequency */ 53#define SDHCI_QUIRK_LOWER_FREQUENCY (1 << 9) 54/* Data timeout is invalid, should use SD clock */ 55#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1 << 10) 56/* Timeout value is invalid, should be overriden */ 57#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1 << 11) 58/* SDHCI_CAPABILITIES is invalid */ 59#define SDHCI_QUIRK_MISSING_CAPS (1 << 12) 60/* Hardware shifts the 136-bit response, don't do it in software. */ 61#define SDHCI_QUIRK_DONT_SHIFT_RESPONSE (1 << 13) 62/* Wait to see reset bit asserted before waiting for de-asserted */ 63#define SDHCI_QUIRK_WAITFOR_RESET_ASSERTED (1 << 14) 64/* Leave controller in standard mode when putting card in HS mode. */ 65#define SDHCI_QUIRK_DONT_SET_HISPD_BIT (1 << 15) 66/* Alternate clock source is required when supplying a 400 KHz clock. */ 67#define SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC (1 << 16) 68/* Card insert/remove interrupts don't work, polling required. */ 69#define SDHCI_QUIRK_POLL_CARD_PRESENT (1 << 17) 70/* All controller slots are non-removable. */ 71#define SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE (1 << 18) 72/* Issue custom Intel controller reset sequence after power-up. */ 73#define SDHCI_QUIRK_INTEL_POWER_UP_RESET (1 << 19) 74/* Data timeout is invalid, use 1 MHz clock instead. */ 75#define SDHCI_QUIRK_DATA_TIMEOUT_1MHZ (1 << 20) 76/* Controller doesn't allow access boot partitions. */ 77#define SDHCI_QUIRK_BOOT_NOACC (1 << 21) 78/* Controller waits for busy responses. */ 79#define SDHCI_QUIRK_WAIT_WHILE_BUSY (1 << 22) 80/* Controller supports eMMC DDR52 mode. */ 81#define SDHCI_QUIRK_MMC_DDR52 (1 << 23) 82/* Controller support for UHS DDR50 mode is broken. */ 83#define SDHCI_QUIRK_BROKEN_UHS_DDR50 (1 << 24) 84/* Controller support for eMMC HS200 mode is broken. */ 85#define SDHCI_QUIRK_BROKEN_MMC_HS200 (1 << 25) 86/* Controller reports support for eMMC HS400 mode as SDHCI_CAN_MMC_HS400. */ 87#define SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 (1 << 26) 88/* Controller support for SDHCI_CTRL2_PRESET_VALUE is broken. */ 89#define SDHCI_QUIRK_PRESET_VALUE_BROKEN (1 << 27) 90 91/* 92 * Controller registers 93 */ 94#define SDHCI_DMA_ADDRESS 0x00 95 96#define SDHCI_BLOCK_SIZE 0x04 97#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 98 99#define SDHCI_BLOCK_COUNT 0x06 100 101#define SDHCI_ARGUMENT 0x08 102 103#define SDHCI_TRANSFER_MODE 0x0C 104#define SDHCI_TRNS_DMA 0x01 105#define SDHCI_TRNS_BLK_CNT_EN 0x02 106#define SDHCI_TRNS_ACMD12 0x04 107#define SDHCI_TRNS_READ 0x10 108#define SDHCI_TRNS_MULTI 0x20 109 110#define SDHCI_COMMAND_FLAGS 0x0E 111#define SDHCI_CMD_RESP_NONE 0x00 112#define SDHCI_CMD_RESP_LONG 0x01 113#define SDHCI_CMD_RESP_SHORT 0x02 114#define SDHCI_CMD_RESP_SHORT_BUSY 0x03 115#define SDHCI_CMD_RESP_MASK 0x03 116#define SDHCI_CMD_CRC 0x08 117#define SDHCI_CMD_INDEX 0x10 118#define SDHCI_CMD_DATA 0x20 119#define SDHCI_CMD_TYPE_NORMAL 0x00 120#define SDHCI_CMD_TYPE_SUSPEND 0x40 121#define SDHCI_CMD_TYPE_RESUME 0x80 122#define SDHCI_CMD_TYPE_ABORT 0xc0 123#define SDHCI_CMD_TYPE_MASK 0xc0 124 125#define SDHCI_COMMAND 0x0F 126 127#define SDHCI_RESPONSE 0x10 128 129#define SDHCI_BUFFER 0x20 130 131#define SDHCI_PRESENT_STATE 0x24 132#define SDHCI_CMD_INHIBIT 0x00000001 133#define SDHCI_DAT_INHIBIT 0x00000002 134#define SDHCI_DAT_ACTIVE 0x00000004 135#define SDHCI_RETUNE_REQUEST 0x00000008 136#define SDHCI_DOING_WRITE 0x00000100 137#define SDHCI_DOING_READ 0x00000200 138#define SDHCI_SPACE_AVAILABLE 0x00000400 139#define SDHCI_DATA_AVAILABLE 0x00000800 140#define SDHCI_CARD_PRESENT 0x00010000 141#define SDHCI_CARD_STABLE 0x00020000 142#define SDHCI_CARD_PIN 0x00040000 143#define SDHCI_WRITE_PROTECT 0x00080000 144#define SDHCI_STATE_DAT_MASK 0x00f00000 145#define SDHCI_STATE_CMD 0x01000000 146 147#define SDHCI_HOST_CONTROL 0x28 148#define SDHCI_CTRL_LED 0x01 149#define SDHCI_CTRL_4BITBUS 0x02 150#define SDHCI_CTRL_HISPD 0x04 151#define SDHCI_CTRL_SDMA 0x08 152#define SDHCI_CTRL_ADMA2 0x10 153#define SDHCI_CTRL_ADMA264 0x18 154#define SDHCI_CTRL_DMA_MASK 0x18 155#define SDHCI_CTRL_8BITBUS 0x20 156#define SDHCI_CTRL_CARD_DET 0x40 157#define SDHCI_CTRL_FORCE_CARD 0x80 158 159#define SDHCI_POWER_CONTROL 0x29 160#define SDHCI_POWER_ON 0x01 161#define SDHCI_POWER_180 0x0A 162#define SDHCI_POWER_300 0x0C 163#define SDHCI_POWER_330 0x0E 164 165#define SDHCI_BLOCK_GAP_CONTROL 0x2A 166 167#define SDHCI_WAKE_UP_CONTROL 0x2B 168 169#define SDHCI_CLOCK_CONTROL 0x2C 170#define SDHCI_DIVIDER_MASK 0xff 171#define SDHCI_DIVIDER_MASK_LEN 8 172#define SDHCI_DIVIDER_SHIFT 8 173#define SDHCI_DIVIDER_HI_MASK 3 174#define SDHCI_DIVIDER_HI_SHIFT 6 175#define SDHCI_CLOCK_CARD_EN 0x0004 176#define SDHCI_CLOCK_INT_STABLE 0x0002 177#define SDHCI_CLOCK_INT_EN 0x0001 178#define SDHCI_DIVIDERS_MASK \ 179 ((SDHCI_DIVIDER_MASK << SDHCI_DIVIDER_SHIFT) | \ 180 (SDHCI_DIVIDER_HI_MASK << SDHCI_DIVIDER_HI_SHIFT)) 181 182#define SDHCI_TIMEOUT_CONTROL 0x2E 183 184#define SDHCI_SOFTWARE_RESET 0x2F 185#define SDHCI_RESET_ALL 0x01 186#define SDHCI_RESET_CMD 0x02 187#define SDHCI_RESET_DATA 0x04 188 189#define SDHCI_INT_STATUS 0x30 190#define SDHCI_INT_ENABLE 0x34 191#define SDHCI_SIGNAL_ENABLE 0x38 192#define SDHCI_INT_RESPONSE 0x00000001 193#define SDHCI_INT_DATA_END 0x00000002 194#define SDHCI_INT_BLOCK_GAP 0x00000004 195#define SDHCI_INT_DMA_END 0x00000008 196#define SDHCI_INT_SPACE_AVAIL 0x00000010 197#define SDHCI_INT_DATA_AVAIL 0x00000020 198#define SDHCI_INT_CARD_INSERT 0x00000040 199#define SDHCI_INT_CARD_REMOVE 0x00000080 200#define SDHCI_INT_CARD_INT 0x00000100 201#define SDHCI_INT_INT_A 0x00000200 202#define SDHCI_INT_INT_B 0x00000400 203#define SDHCI_INT_INT_C 0x00000800 204#define SDHCI_INT_RETUNE 0x00001000 205#define SDHCI_INT_ERROR 0x00008000 206#define SDHCI_INT_TIMEOUT 0x00010000 207#define SDHCI_INT_CRC 0x00020000 208#define SDHCI_INT_END_BIT 0x00040000 209#define SDHCI_INT_INDEX 0x00080000 210#define SDHCI_INT_DATA_TIMEOUT 0x00100000 211#define SDHCI_INT_DATA_CRC 0x00200000 212#define SDHCI_INT_DATA_END_BIT 0x00400000 213#define SDHCI_INT_BUS_POWER 0x00800000 214#define SDHCI_INT_ACMD12ERR 0x01000000 215#define SDHCI_INT_ADMAERR 0x02000000 216#define SDHCI_INT_TUNEERR 0x04000000 217 218#define SDHCI_INT_NORMAL_MASK 0x00007FFF 219#define SDHCI_INT_ERROR_MASK 0xFFFF8000 220 221#define SDHCI_INT_CMD_ERROR_MASK (SDHCI_INT_TIMEOUT | \ 222 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 223 224#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_CMD_ERROR_MASK) 225 226#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 227 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 228 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 229 SDHCI_INT_DATA_END_BIT) 230 231#define SDHCI_ACMD12_ERR 0x3C 232 233#define SDHCI_HOST_CONTROL2 0x3E 234#define SDHCI_CTRL2_PRESET_VALUE 0x8000 235#define SDHCI_CTRL2_ASYNC_INTR 0x4000 236#define SDHCI_CTRL2_SAMPLING_CLOCK 0x0080 237#define SDHCI_CTRL2_EXEC_TUNING 0x0040 238#define SDHCI_CTRL2_DRIVER_TYPE_MASK 0x0030 239#define SDHCI_CTRL2_DRIVER_TYPE_B 0x0000 240#define SDHCI_CTRL2_DRIVER_TYPE_A 0x0010 241#define SDHCI_CTRL2_DRIVER_TYPE_C 0x0020 242#define SDHCI_CTRL2_DRIVER_TYPE_D 0x0030 243#define SDHCI_CTRL2_S18_ENABLE 0x0008 244#define SDHCI_CTRL2_UHS_MASK 0x0007 245#define SDHCI_CTRL2_UHS_SDR12 0x0000 246#define SDHCI_CTRL2_UHS_SDR25 0x0001 247#define SDHCI_CTRL2_UHS_SDR50 0x0002 248#define SDHCI_CTRL2_UHS_SDR104 0x0003 249#define SDHCI_CTRL2_UHS_DDR50 0x0004 250#define SDHCI_CTRL2_MMC_HS400 0x0005 /* non-standard */ 251 252#define SDHCI_CAPABILITIES 0x40 253#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 254#define SDHCI_TIMEOUT_CLK_SHIFT 0 255#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 256#define SDHCI_CLOCK_BASE_MASK 0x00003F00 257#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 258#define SDHCI_CLOCK_BASE_SHIFT 8 259#define SDHCI_MAX_BLOCK_MASK 0x00030000 260#define SDHCI_MAX_BLOCK_SHIFT 16 261#define SDHCI_CAN_DO_8BITBUS 0x00040000 262#define SDHCI_CAN_DO_ADMA2 0x00080000 263#define SDHCI_CAN_DO_HISPD 0x00200000 264#define SDHCI_CAN_DO_DMA 0x00400000 265#define SDHCI_CAN_DO_SUSPEND 0x00800000 266#define SDHCI_CAN_VDD_330 0x01000000 267#define SDHCI_CAN_VDD_300 0x02000000 268#define SDHCI_CAN_VDD_180 0x04000000 269#define SDHCI_CAN_DO_64BIT 0x10000000 270#define SDHCI_CAN_ASYNC_INTR 0x20000000 271#define SDHCI_SLOTTYPE_MASK 0xC0000000 272#define SDHCI_SLOTTYPE_REMOVABLE 0x00000000 273#define SDHCI_SLOTTYPE_EMBEDDED 0x40000000 274#define SDHCI_SLOTTYPE_SHARED 0x80000000 275 276#define SDHCI_CAPABILITIES2 0x44 277#define SDHCI_CAN_SDR50 0x00000001 278#define SDHCI_CAN_SDR104 0x00000002 279#define SDHCI_CAN_DDR50 0x00000004 280#define SDHCI_CAN_DRIVE_TYPE_A 0x00000010 281#define SDHCI_CAN_DRIVE_TYPE_C 0x00000020 282#define SDHCI_CAN_DRIVE_TYPE_D 0x00000040 283#define SDHCI_RETUNE_CNT_MASK 0x00000F00 284#define SDHCI_RETUNE_CNT_SHIFT 8 285#define SDHCI_TUNE_SDR50 0x00002000 286#define SDHCI_RETUNE_MODES_MASK 0x0000C000 287#define SDHCI_RETUNE_MODES_SHIFT 14 288#define SDHCI_CLOCK_MULT_MASK 0x00FF0000 289#define SDHCI_CLOCK_MULT_SHIFT 16 290#define SDHCI_CAN_MMC_HS400 0x80000000 /* non-standard */ 291 292#define SDHCI_MAX_CURRENT 0x48 293#define SDHCI_FORCE_AUTO_EVENT 0x50 294#define SDHCI_FORCE_INTR_EVENT 0x52 295 296#define SDHCI_ADMA_ERR 0x54 297#define SDHCI_ADMA_ERR_LENGTH 0x04 298#define SDHCI_ADMA_ERR_STATE_MASK 0x03 299#define SDHCI_ADMA_ERR_STATE_STOP 0x00 300#define SDHCI_ADMA_ERR_STATE_FDS 0x01 301#define SDHCI_ADMA_ERR_STATE_TFR 0x03 302 303#define SDHCI_ADMA_ADDRESS_LO 0x58 304#define SDHCI_ADMA_ADDRESS_HI 0x5C 305 306#define SDHCI_PRESET_VALUE 0x60 307#define SDHCI_SHARED_BUS_CTRL 0xE0 308 309#define SDHCI_SLOT_INT_STATUS 0xFC 310 311#define SDHCI_HOST_VERSION 0xFE 312#define SDHCI_VENDOR_VER_MASK 0xFF00 313#define SDHCI_VENDOR_VER_SHIFT 8 314#define SDHCI_SPEC_VER_MASK 0x00FF 315#define SDHCI_SPEC_VER_SHIFT 0 316#define SDHCI_SPEC_100 0 317#define SDHCI_SPEC_200 1 318#define SDHCI_SPEC_300 2 319#define SDHCI_SPEC_400 3 320 321SYSCTL_DECL(_hw_sdhci); 322 323extern u_int sdhci_quirk_clear; 324extern u_int sdhci_quirk_set; 325 326struct sdhci_slot { 327 struct mtx mtx; /* Slot mutex */ 328 u_int quirks; /* Chip specific quirks */ 329 u_int caps; /* Override SDHCI_CAPABILITIES */ 330 u_int caps2; /* Override SDHCI_CAPABILITIES2 */ 331 device_t bus; /* Bus device */ 332 device_t dev; /* Slot device */ 333 u_char num; /* Slot number */ 334 u_char opt; /* Slot options */ 335#define SDHCI_HAVE_DMA 0x01 336#define SDHCI_PLATFORM_TRANSFER 0x02 337#define SDHCI_NON_REMOVABLE 0x04 338#define SDHCI_TUNING_SUPPORTED 0x08 339#define SDHCI_TUNING_ENABLED 0x10 340#define SDHCI_SDR50_NEEDS_TUNING 0x20 341 u_char version; 342 int timeout; /* Transfer timeout */ 343 uint32_t max_clk; /* Max possible freq */ 344 uint32_t timeout_clk; /* Timeout freq */ 345 bus_dma_tag_t dmatag; 346 bus_dmamap_t dmamap; 347 u_char *dmamem; 348 bus_addr_t paddr; /* DMA buffer address */ 349 struct task card_task; /* Card presence check task */ 350 struct timeout_task 351 card_delayed_task;/* Card insert delayed task */ 352 struct callout card_poll_callout;/* Card present polling callout */ 353 struct callout timeout_callout;/* Card command/data response timeout */ 354 struct callout retune_callout; /* Re-tuning mode 1 callout */ 355 struct mmc_host host; /* Host parameters */ 356 struct mmc_request *req; /* Current request */ 357 struct mmc_command *curcmd; /* Current command of current request */ 358 359 struct mmc_request *tune_req; /* Tuning request */ 360 struct mmc_command *tune_cmd; /* Tuning command of tuning request */ 361 struct mmc_data *tune_data; /* Tuning data of tuning command */ 362 uint32_t retune_ticks; /* Re-tuning callout ticks [hz] */ 363 uint32_t intmask; /* Current interrupt mask */ 364 uint32_t clock; /* Current clock freq. */ 365 size_t offset; /* Data buffer offset */ 366 uint8_t hostctrl; /* Current host control register */ 367 uint8_t retune_count; /* Controller re-tuning count [s] */ 368 uint8_t retune_mode; /* Controller re-tuning mode */ 369#define SDHCI_RETUNE_MODE_1 0x00 370#define SDHCI_RETUNE_MODE_2 0x01 371#define SDHCI_RETUNE_MODE_3 0x02 372 uint8_t retune_req; /* Re-tuning request status */ 373#define SDHCI_RETUNE_REQ_NEEDED 0x01 /* Re-tuning w/o circuit reset needed */ 374#define SDHCI_RETUNE_REQ_RESET 0x02 /* Re-tuning w/ circuit reset needed */ 375 u_char power; /* Current power */ 376 u_char bus_busy; /* Bus busy status */ 377 u_char cmd_done; /* CMD command part done flag */ 378 u_char data_done; /* DAT command part done flag */ 379 u_char flags; /* Request execution flags */ 380#define CMD_STARTED 1 381#define STOP_STARTED 2 382#define SDHCI_USE_DMA 4 /* Use DMA for this req. */ 383#define PLATFORM_DATA_STARTED 8 /* Data xfer is handled by platform */ 384}; 385 386int sdhci_generic_read_ivar(device_t bus, device_t child, int which, 387 uintptr_t *result); 388int sdhci_generic_write_ivar(device_t bus, device_t child, int which, 389 uintptr_t value); 390int sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num); 391void sdhci_start_slot(struct sdhci_slot *slot); 392/* performs generic clean-up for platform transfers */ 393void sdhci_finish_data(struct sdhci_slot *slot); 394int sdhci_cleanup_slot(struct sdhci_slot *slot); 395int sdhci_generic_suspend(struct sdhci_slot *slot); 396int sdhci_generic_resume(struct sdhci_slot *slot); 397int sdhci_generic_update_ios(device_t brdev, device_t reqdev); 398int sdhci_generic_tune(device_t brdev, device_t reqdev, bool hs400); 399int sdhci_generic_switch_vccq(device_t brdev, device_t reqdev); 400int sdhci_generic_retune(device_t brdev, device_t reqdev, bool reset); 401int sdhci_generic_request(device_t brdev, device_t reqdev, 402 struct mmc_request *req); 403int sdhci_generic_get_ro(device_t brdev, device_t reqdev); 404int sdhci_generic_acquire_host(device_t brdev, device_t reqdev); 405int sdhci_generic_release_host(device_t brdev, device_t reqdev); 406void sdhci_generic_intr(struct sdhci_slot *slot); 407uint32_t sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot); 408bool sdhci_generic_get_card_present(device_t brdev, struct sdhci_slot *slot); 409void sdhci_generic_set_uhs_timing(device_t brdev, struct sdhci_slot *slot); 410void sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present); 411 412#endif /* __SDHCI_H__ */ 413