| 352083 |
09-Sep-2019 |
kevans |
MFC r351681: mips: fix some mcount nits
The symbol version for _mcount was removed 12 years ago in r169525 from
gmon/Symbol.map, to be added to the per-arch Symbol.map. mips was overlooked
in this, so _mcount has no symver. Add it back to where it should have been,
rather than where it would go if it were added today, since we're correcting
a historical mistake.
Additionally, _mcount is getting thrown into .mdebug.abi32 in the llvm80/90
world as it's not getting explicitly thrown into .text, so do this now. This
fixes the libc build that was previously failing due to relocations in
.mdebug.abi32. This is specifically due to the way clang's integrated AS
works and that they emit the .mdebug.abiNN section early in the process. An
LLVM bug has been submitted (and since committed) and an agreement has been
made that the mips backend should switch to .text following .mdebug.abiNN
for compatibility. |
| 351793 |
03-Sep-2019 |
kevans |
MFC r351227: mips: avoid empty mdproc struct
Compiling with a more modern toolchain than GCC 4.2 in base warns about the
empty struct. Take a hint and comment from r350902+r350953 by luporl@. |
| 351792 |
03-Sep-2019 |
kevans |
MFC r351408-r351410: reduce pollution from mips machine/regnum.h
r351408:
libsa: mips: use _JB_* from machine/asm.h, remove regnum dep
This brings the libsa/mips _setjmp implementation closer to parity with the
libc version.
r351409:
mips: hide regnum definitions behind _KERNEL/_WANT_MIPS_REGNUM
machine/regnum.h ends up being included by sys/procfs.h and sys/ptrace.h via
machine/reg.h. Many of the regnum definitions are too short and too generic
to be exposing to any userland application including one of these two
headers. Moreover, these actively cause build failures in googletest
(template <typename T1 ...> expanding to template <typename 9 ...>).
Hide the definitions behind _KERNEL or _WANT_MIPS_REGNUM, and patch all of
the userland consumers to define as needed.
r351410:
libsa: mips: fix typo that had slipped into the diff on local machine |
| 340270 |
08-Nov-2018 |
jhb |
MFC 340164,340168,340170: Add custom cpu_lock_delay() for x86.
340164:
Add a KPI for the delay while spinning on a spin lock.
Replace a call to DELAY(1) with a new cpu_lock_delay() KPI. Currently
cpu_lock_delay() is defined to DELAY(1) on all platforms. However,
platforms with a DELAY() implementation that uses spin locks should
implement a custom cpu_lock_delay() doesn't use locks.
340168:
Add a delay_tsc() static function for when DELAY() uses the TSC.
This uses slightly simpler logic than the existing code by using the
full 64-bit counter and thus not having to worry about counter
overflow.
340170:
Add a custom implementation of cpu_lock_delay() for x86.
Avoid using DELAY() since it can try to use spin locks on CPUs without
a P-state invariant TSC. For cpu_lock_delay(), always use the TSC if
it exists (even if it is not P-state invariant) to delay for a
microsecond. If the TSC does not exist, read from I/O port 0x84 to
delay instead.
PR: 228768 |
| 338514 |
06-Sep-2018 |
jhb |
MFC 332906,332907,332976,333679,336053: Expand testing of breakpoints.
332906:
Extend support for ptrace() tests using breakpoints.
- Use a single list of platforms to define HAVE_BREAKPOINT for platforms
that expose a functional breakpoint() inline to userland. Replace
existing lists of platform tests with HAVE_BREAKPOINT instead.
- Add support for advancing PC past a breakpoint inserted via breakpoint()
to support the existing ptrace__PT_CONTINUE_different_thread test on
non-x86 platforms (x86 advances the PC past the breakpoint instruction,
but other platforms do not). This is implemented by defining a new
SKIP_BREAK macro which accepts a pointer to a 'struct reg' as its sole
argument and modifies the contents to advance the PC. The intention is
to use it in between PT_GETREGS and PT_SETREGS.
332907:
Expose breakpoint() to userland from <machine/cpufunc.h> on MIPS.
Enable ptrace() tests using breakpoint on MIPS as well.
332976:
Shorten some recently-added lines that are an extra indent over 80 columns.
333679:
Export a breakpoint() function to userland for riscv.
As a result, enable tests using breakpoint() on riscv.
336053:
Export a breakpoint() function to userland for arm and arm64.
Enable ptrace() tests using breakpoint() on these architectures. |
| 332135 |
06-Apr-2018 |
kevans |
MFC r329859,r329860: Float protection in stand
r329859: Do not include float interfaces when using libsa.
We don't support float in the boot loaders, so don't include
interfaces for float or double in systems headers. In addition, take
the unusual step of spiking double and float to prevent any more
accidental seepage.
r329860: Floaty McFloatface is funnier... |
| 331722 |
29-Mar-2018 |
eadler |
Revert r330897:
This was intended to be a non-functional change. It wasn't. The commit
message was thus wrong. In addition it broke arm, and merged crypto
related code.
Revert with prejudice.
This revert skips files touched in r316370 since that commit was since
MFCed. This revert also skips files that require $FreeBSD$ property
changes.
Thank you to those who helped me get out of this mess including but not
limited to gonzo, kevans, rgrimes.
Requested by: gjb (re) |
| 331017 |
15-Mar-2018 |
kevans |
MFC r317055,r317056 (glebius): Include sys/vmmeter.h as included
r317055: All these files need sys/vmmeter.h, but now they got it implicitly
included via sys/pcpu.h.
r317056: Typo! |
| 330897 |
14-Mar-2018 |
eadler |
Partial merge of the SPDX changes
These changes are incomplete but are making it difficult
to determine what other changes can/should be merged.
No objections from: pfg |
| 328386 |
25-Jan-2018 |
pkelsey |
MFC r316648:
Corrected misspelled versions of rendezvous.
The MFC maintains smp_no_rendevous_barrier() as a symbol alias of
smp_no_rendezvous_barrier().
__FreeBSD_version bumped to indicate presence of the new name
smp_no_rendezvous_barrier().
Reviewed by: gnn, jhb (email), kib
Differential Revision: https://reviews.freebsd.org/D10313 |
| 327195 |
26-Dec-2017 |
kib |
MFC r326971, r327047 (by ian), r327053 (by marius), r327074, r327097:
Add atomic_load(9) and atomic_store(9) operations. |
| 325810 |
14-Nov-2017 |
jhb |
MFC 323580,323933,323934,324814,324817: Enable AT_HWCAP on arm.
I reused the SV_HWCAP stub to cover the sv_hwcap2 field as well.
323580:
Add AT_HWCAP flags for VFP settings for FreeBSD/arm.
These flags match the meaning and value of flags in Linux, though
Linux has many more flags.
323933:
Correct HWCAP_VFP3* values to match Linux.
323934:
Detect NEON and set HWCAP_NEON if present.
324814:
Add AT_HWCAP2 ELF auxiliary vector.
- allocate value for new AT_HWCAP2 auxiliary vector on all platforms.
- expand 'struct sysentvec' by new 'u_long *sv_hwcap2', in exactly
same way as for AT_HWCAP.
324817:
Fullify implementation of AT_HWCAP and AT_HWCAP2 for ARMv6,7.
This makes elf_aux_info(3) useable for ARM ports.
Tested by: mmel |
| 324687 |
17-Oct-2017 |
jhb |
MFC 323579,323585: Add AT_HWCAP and AT_EHDRFLAGS on all platforms.
To preserve KBI on stable/11, a new SV_HWCAP flag is added which
indicates if the sv_hwcap field is present and valid to avoid examining
the field in old modules. Only sysentvec's which wish to use sv_hwcap
need to set the flag in stable/11.
323579:
Add AT_HWCAP and AT_EHDRFLAGS on all platforms.
A new 'u_long *sv_hwcap' field is added to 'struct sysentvec'. A
process ABI can set this field to point to a value holding a mask of
architecture-specific CPU feature flags. If an ABI does not wish to
supply AT_HWCAP to processes the field can be left as NULL.
The support code for AT_EHDRFLAGS was already present on all systems,
just the #define was not present. This is a step towards unifying the
AT_* constants across platforms.
323585:
Add AT_EHDRFLAGS and AT_HWCAP on amd64.
x86 has two separate (but identical) list of AT_* constants and the
earlier commit to add AT_HWCAP only updated the i386 list. |
| 321324 |
21-Jul-2017 |
kib |
MFC r319871:
Make struct syscall_args visible to userspace compilation environment
from machine/proc.h, consistently on all architectures. |
| 318576 |
20-May-2017 |
kib |
MFC efivar(8) (by imp):
List of revisions merged:
r307070
r307071
r307072
r307074
r307189
r307224
r307339
r307390
r307391
r309776
r314231
r314232
r314615
r314616
r314617
r314618
r314619
r314620
r314621
r314623
r314890
r314925
r314926
r314927
r314928
r315770
r315771
Discussed with: gjb (re), imp
Sponsored by: The FreeBSD Foundation |
| 315371 |
16-Mar-2017 |
mjg |
MFC r311169,r311898,r312925,r312973,r312975,r313007,r313040,r313080,
r313254,r313341
amd64: add atomic_fcmpset
==
sparc64: add atomic_fcmpset
==
Implement atomic_fcmpset_* for arm and arm64.
==
Add atomic_fcmpset_*() inlines for powerpc
Summary:
atomic_fcmpset_*() is analogous to atomic_cmpset(), but saves off the read value
from the target memory location into the 'old' pointer in the case of failure.
==
i386: add atomic_fcmpset
==
Don't retry a lost reservation in atomic_fcmpset()
The desired behavior of atomic_fcmpset_() is to always exit on error. Instead
of retrying on lost reservation, leave the retry to the caller, and return
==
Add atomic_fcmpset_*() inlines for MIPS
atomic_fcmpset_*() is analogous to atomic_cmpset(), but saves off the
read value from the target memory location into the 'old' pointer.
==
i386: fixup fcmpset
An incorrect output specifier was used which worked with clang by accident,
but breaks with the in-tree gcc version.
While here plug a whitespace nit.
==
Implement atomic_fcmpset_*() for RISC-V.
==
Use 64bit store instruction in atomic_fcmpset_64. |
| 313574 |
11-Feb-2017 |
kib |
MFC r313194:
Define the vm_ooffset_t and vm_pindex_t types as machine-independend. |
| 308333 |
05-Nov-2016 |
mmel |
MFC r304459,r305527:
r304459:
INTRNG: Rework handling with resources. Partially revert r301453.
- Read interrupt properties at bus enumeration time and store
it into global mapping table.
- At bus_activate_resource() time, given mapping entry is resolved and
connected to real interrupt source. A copy of mapping entry is attached
to given resource.
- At bus_setup_intr() time, mapping entry stored in resource is used
for delivery of requested interrupt configuration.
- For MSI/MSIX interrupts, mapping entry is created within
pci_alloc_msi()/pci_alloc_msix() call.
- For legacy PCI interrupts, mapping entry must be created within
pcib_route_interrupt() by pcib driver itself.
r305527:
Fix MIPS INTRNG (both FDT and non-FDT) behaviour broken by r304459 |
| 302408 |
08-Jul-2016 |
gjb |
Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, as nothing has been merged
here.
Additional commits post-branch will follow.
Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation |
| 300306 |
20-May-2016 |
rwatson |
Garbage collect unused prototype for clockintr().
MFC after: 3 days
|
| 298859 |
30-Apr-2016 |
rwatson |
When attempting to satisfy mmap() requests for superpage alignment on
64-bit MIPS, use superpage rather than physical-segment constants, or
we may improperly fail to apply suitable alignment -- yet still allow
mmap() to appear to succeed.
Reviewed by: sson
MFC after: 1 week
Sponsored by: DARPA, AFRL
|
| 298068 |
15-Apr-2016 |
andrew |
Rename ARM_INTRNG and MIPS_INTRNG to INTRNG. This will help with machine
independent code that needs to know about INTRNG such as PCI drivers.
Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
|
| 298065 |
15-Apr-2016 |
sgalabov |
Make NIRQ configurable for MIPS
Submitted by: kan
Reviewed by: kan
Approved by: adrian (mentor)
Differential Revision: https://reviews.freebsd.org/D5964
|
| 297849 |
12-Apr-2016 |
sgalabov |
Define PCI_RES_BUS for MIPS.
This is done as part of the work on D5908, but as a separate commit.
Approved by: adrian (mentor)
Sponsored by: Smartcom - Bulgaria AD
|
| 295561 |
12-Feb-2016 |
kib |
POSIX states that #include <signal.h> shall make both mcontext_t and
ucontext_t available. Our code even has XXX comment about this.
Add a bit of compliance by moving struct __ucontext definition into
sys/_ucontext.h and including it into signal.h and sys/ucontext.h.
Several machine/ucontext.h headers were changed to use namespace-safe
types (like uint64_t->__uint64_t) to not depend on sys/types.h.
struct __stack_t from sys/signal.h is made always visible in private
namespace to satisfy sys/_ucontext.h requirements.
Apparently mips _types.h pollutes global namespace with f_register_t
type definition. This commit does not try to fix the issue.
PR: 207079
Reported and tested by: Ting-Wei Lan <lantw44@gmail.com>
Sponsored by: The FreeBSD Foundation
MFC after: 2 weeks
|
| 295502 |
11-Feb-2016 |
adrian |
Missing commit - remove MIPS fdt bus space.
Differential Revision: https://reviews.freebsd.org/D5184
|
| 295501 |
11-Feb-2016 |
adrian |
Remove bus space fdt for MIPS.
This was originall done by kan@.
Submitted by: Stanislav Galabov <sgalabov@gmail.com>
Reviewed by: kan
Differential Revision: https://reviews.freebsd.org/D5184
|
| 295498 |
11-Feb-2016 |
adrian |
Begin the MIPS_INTRNG support.
This is a prelude to intr-ng support for MIPS boards that need it -
notably the CI20 port from kan@ that's upcoming, but also work that
Stanislav is doing for the Mediatek platforms.
This is the initial platform dependent bits in include/intr.h, some
#defines for the nexus code for the intrng initialisation/runtime
bits, some changed naming (which I'll fix later to be the same, much
like what I did for ARM intr-ng) in exception.S, and the first cut
at a PIC.
Stanislav and I refactored out the common code for intrng support,
so the mips intrng definitions are quite small (sys/mips/include/intr.h.)
This is all work done by kan@, which stanislav has been cherry picking
into common code for his mediatek chipset work.
Tested:
* Carambola2 - no regressions (not intr-ng though!)
Submitted by: Stanislav Galabov <sgalabov@gmail.com>
Reviewed by: kan (original author)
Differential Revision: https://reviews.freebsd.org/D5182
|
| 295150 |
02-Feb-2016 |
adrian |
Move MIPS32 Release 2 and Release 3 CPUs to use the EHB instruction for
clearing hazards.
This revision makes currently known MIPS32 Release 2 and Release 3 CPUs use
the EHB instruction when clearing hazards. So far the MIPS 74K and MIPS1004K
(somewhat) were already using the EHB. Now we add more r2 and r3 CPUs to
this list.
Also, for the cases of MIPS coherent processing systems (currently 1004K,
1074K, interAptiv and proAptiv) - define proper CCA attributes.
Submitted by: Stanislav Galabov <sgalabov@gmail.com>
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D5078
|
| 295138 |
02-Feb-2016 |
adrian |
Rename some CPU_MIPSxxx options and add new CPU_MIPSxxx options
This revision does the following renames:
CPU_MIPS24KC -> CPU_MIPS24K
CPU_MIPS74KC -> CPU_MIPS74K
CPU_MIPS1004KC -> CPU_MIPS1004K
It also adds the following new CPU_MIPSxxx options:
CPU_MIPS24KE, CPU_MIPS34K, CPU_MIPS1074K, CPU_INTERAPTIV, CPU_PROAPTIV
CPU_MIPSxxxxKC is limiting and possibly misleading as it implies the
MIPSxxxxK CPU has no FPU.
It would be better if the CPUs are named after their standard functionalities
only and the presence or absence of FPU can then be controlled via the
CPU_HAVEFPU option.
I will send out another dependent revision that moves MIPS 32 r2 and r3
CPUs to use the EHB instruction for clearing hazards instead of NOP/SSNOP.
Submitted by: Stanislav Galabov <sgalabov@gmail.com>
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D5077
|
| 294463 |
20-Jan-2016 |
brooks |
Shift saved floating point registers up in jmp_buf.
sigmask_t is 128-bits so requires two slots.
Approved by: CheriBSD (93699cb9b6e73980ac369e379cea9772c9494ccc)
MFC after: 1 week
Sponsored by: DARPA, AFRL
|
| 292692 |
24-Dec-2015 |
adrian |
Begin the initial support for the mips1004kc core.
* add build option;
* add initial coherence manager config register bits;
* use the right hazard instruction (ehb);
* add page attributes.
Tested:
* MT7621A SoC (not yet in-tree)
Submitted by: Stanislav Galabov <sgalabov@gmail.com>
|
| 292609 |
22-Dec-2015 |
adrian |
[mips] Add TLB pagemask probing code, and print out the allowable page sizes.
This is from Stacey's work on larger kernel stack sizes for MIPS. Thanks!
Submitted by: sson
|
| 292519 |
20-Dec-2015 |
ian |
Tidy up mips ofw_machdep.h. Don't include openfirm.h because openfirm.h
is what includes machine/ofw_machdep.h. Don't declare OF_decode_addr();
it isn't implemented yet on mips and the declaration for it is about to
be commonized into openfirm.h.
|
| 292469 |
19-Dec-2015 |
alc |
Introduce a new mechanism for relocating virtual pages to a new physical
address and use this mechanism when:
1. kmem_alloc_{attr,contig}() can't find suitable free pages in the physical
memory allocator's free page lists. This replaces the long-standing
approach of scanning the inactive and inactive queues, converting clean
pages into PG_CACHED pages and laundering dirty pages. In contrast, the
new mechanism does not use PG_CACHED pages nor does it trigger a large
number of I/O operations.
2. on 32-bit MIPS processors, uma_small_alloc() and the pmap can't find
free pages in the physical memory allocator's free page lists that are
covered by the direct map. Tested by: adrian
3. ttm_bo_global_init() and ttm_vm_page_alloc_dma32() can't find suitable
free pages in the physical memory allocator's free page lists.
In the coming months, I expect that this new mechanism will be applied in
other places. For example, balloon drivers should use relocation to
minimize fragmentation of the guest physical address space.
Make vm_phys_alloc_contig() a little smarter (and more efficient in some
cases). Specifically, use vm_phys_segs[] earlier to avoid scanning free
page lists that can't possibly contain suitable pages.
Reviewed by: kib, markj
Glanced at: jhb
Discussed with: jeff
Sponsored by: EMC / Isilon Storage Division
Differential Revision: https://reviews.freebsd.org/D4444
|
| 292114 |
11-Dec-2015 |
imp |
Correct the CONFIG0_VI value. According to
http://www.t-es-t.hu/download/mips/md00090c.pdf this is bit 3 of the
config0 word, not bit 2. This should fix virtually indexed caches
(relatively new in the MIPS world, so no current platforms used this
and current code just uses it as an optimization). It was causing
false positives on newer platforms that default to large values for
the kseg0 cache coherency attribute.
Submitted by: Stanislav Galabov
PR: 205249
|
| 290218 |
31-Oct-2015 |
adrian |
mips74k: use cache-writeback for memory, not writethrough.
When I ported this code from netbsd I was .. slightly mips74k greener.
I used writethrough because (a) it's what netbsd did, and (b) if I used
writethrough then things "didn't work."
Fast-forward a couple years, more MIPS hacking and a whole lot more
understanding of the bus APIs (the last few commits notwithstanding;
it's been a long week, ok?) and I have this working for arge,
argemdio, spi and ath. Hans has it working for USB. The ath barrier
code will come in a later commit.
This gets the routing throughput up from 220mbit -> 337mbit.
I'm sure the bridging throughput will be similarly improved.
Tested:
* QCA955x SoC, routing workload.
|
| 289699 |
21-Oct-2015 |
ian |
Switch from a stub to a real implementation of pmap_page_set_attr() for mips,
and implement support for VM_MEMATTR_UNCACHEABLE. This will be used in
upcoming changes to support BUS_DMA_COHERENT in bus_dmamem_alloc().
Reviewed by: adrian, imp
|
| 286336 |
05-Aug-2015 |
emaste |
Rationalize BSD license on sys/*/include/in_cksum.h
Remove the advertising clause from the Regents of the University of
California's license, per the letter dated July 22, 1999.
Update clause numbering.
|
| 286327 |
05-Aug-2015 |
emaste |
Rationalize BSD license on sys/*/include/float.h
Remove the advertising clause from the Regents of the University of
California's license, per the letter dated July 22, 1999.
Update clause numbering.
|
| 285283 |
08-Jul-2015 |
kib |
Add the atomic_thread_fence() family of functions with intent to
provide a semantic defined by the C11 fences with corresponding
memory_order.
atomic_thread_fence_acq() gives r | r, w, where r and w are read and
write accesses, and | denotes the fence itself.
atomic_thread_fence_rel() is r, w | w.
atomic_thread_fence_acq_rel() is the combination of the acquire and
release in single operation. Note that reads after the acq+rel fence
could be made visible before writes preceeding the fence.
atomic_thread_fence_seq_cst() orders all accesses before/after the
fence, and the fence itself is globally ordered against other
sequentially consistent atomic operations.
Reviewed by: alc
Discussed with: bde
Sponsored by: The FreeBSD Foundation
MFC after: 3 weeks
|
| 284147 |
08-Jun-2015 |
alc |
Retire VM_FREEPOOL_CACHE as the next step in eliminating PG_CACHE pages.
Differential Revision: https://reviews.freebsd.org/D2712
Reviewed by: kib
Sponsored by: EMC / Isilon Storage Division
|
| 283645 |
28-May-2015 |
bz |
Similarly to other architecture, add the include for cpufunc.h which is
needed for pte.h by vmstat to resolve MIPS_CCA_UNCACHED.
|
| 283022 |
16-May-2015 |
adrian |
Increment the vm stats "v_intr" counter so the global system interrupt
statistics work again.
I'm not sure why/when this broke, only that it used to work fine.
This commit is brought to you by Maker Faire Bay Area 2015.
|
| 281266 |
08-Apr-2015 |
jhb |
Move the 32-bit compatible procfs types from freebsd32.h to <sys/procfs.h>
and export them to userland.
- Define __HAVE_REG32 on platforms that define a reg32 structure and check
for this in <sys/procfs.h> to control when to export prstatus32, etc.
- Add prstatus32_t and prpsinfo32_t typedefs for the 32-bit structures.
libbfd looks for these types, and having them fixes 'gcore' in gdb of a
32-bit process on a 64-bit platform.
- Use the structure definitions from <sys/procfs.h> in gcore's elf32 core
dump code instead of duplicating the definitions.
Differential Revision: https://reviews.freebsd.org/D2142
Reviewed by: kib, nathanw (powerpc bits)
MFC after: 1 week
|
| 280691 |
26-Mar-2015 |
br |
Add 64 byte linesize cache flushing routines for L1 instruction, L1 data
and L2 data caches.
Sponsored by: HEIF5
|
| 277414 |
20-Jan-2015 |
br |
Add 128-byte cache flushing routines.
Leave CNMIPS untouched as these functions depends on config2
register.
|
| 276772 |
07-Jan-2015 |
markj |
Factor out duplicated code from dumpsys() on each architecture into generic
code in sys/kern/kern_dump.c. Most dumpsys() implementations are nearly
identical and simply redefine a number of constants and helper subroutines;
a generic implementation will make it easier to implement features around
kernel core dumps. This change does not alter any minidump code and should
have no functional impact.
PR: 193873
Differential Revision: https://reviews.freebsd.org/D904
Submitted by: Conrad Meyer <conrad.meyer@isilon.com>
Reviewed by: jhibbits (earlier version)
Sponsored by: EMC / Isilon Storage Division
|
| 276539 |
02-Jan-2015 |
emaste |
Update ELF headers to include additional defines
The elftoolchain project includes these additional defines for various
userland programs. Given that arch-specific defines are still interesting
in the context of userland programs reading or writing ELF metadata, they
should be included in top-level ELF headers.
Remove duplicate defines from ARM and MIPS elf headers.
Submitted by: will (initial version)
Reviewed by: imp, will
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D844
|
| 276439 |
31-Dec-2014 |
alc |
The physical memory allocator supports the use of distinct free lists for
managing pages from different address ranges. Generally speaking, this
feature is used to increase the likelihood that physical pages are
available that can meet special DMA requirements or can be accessed through
a limited-coverage direct mapping (e.g., MIPS). However, prior to this
change, the configuration of the free lists was static, i.e., it was
determined at compile time. Consequentally, free lists could be created
for address ranges that held no actual pages, for example, on 32-bit MIPS-
based systems with 512 MB or less of physical memory. This change makes
the creation of the free lists dynamic, i.e., it is based on the available
physical memory at boot time.
On 64-bit x86-based systems with 64 GB or more of physical memory, create
free lists for managing pages with physical addresses below 4 GB. This
change is to address reported problems with initializing devices that
require the allocation of physical pages below 4 GB on some systems with
128 GB or more of physical memory.
PR: 185727
Differential Revision: https://reviews.freebsd.org/D1274
Reviewed by: jhb, kib
MFC after: 3 weeks
Sponsored by: EMC / Isilon Storage Division
|
| 274928 |
23-Nov-2014 |
br |
Correct the functions declaration.
|
| 274816 |
21-Nov-2014 |
brooks |
Add FPU support for MIPS setjmp(3)/longjmp(3).
This change saves/restores the callee-saved MIPS floating point
registers as documented by the o32/n32/n64 spec ("MIPSpro N32
ABI Handbook", Table 2-1) for the _setjmp(3), _longjmp(3),
setjmp(3) and longjmp(3) C library functions. This is only
included when the C library is built with hardware floating point
support (or when "SOFTFLOAT" is not defined).
Submitted by: sson
MFC after: 1 month
Sponsored by: DARPA, AFRL
|
| 274752 |
20-Nov-2014 |
br |
Add L2-cache writeback/flush operations. Supported 32,128-byte line-size,
else ignored. Cavium Networks also ignored as it has non-standard config
registers.
Obtained from: NetBSD
Sponsored by: DARPA, AFRL
|
| 273783 |
28-Oct-2014 |
kib |
Add fueword(9) and casueword(9) functions. They are like fuword(9)
and casuword(9), but do not mix value read and indication of fault.
I know (or remember) enough assembly to handle x86 and powerpc. For
arm, mips and sparc64, implement fueword() and casueword() as wrappers
around fuword() and casuword(), which means that the functions cannot
distinguish between -1 and fault.
On architectures where fueword() and casueword() are native, implement
fuword() and casuword() using fueword() and casuword(), to reduce
assembly code duplication.
Sponsored by: The FreeBSD Foundation
Tested by: pho
MFC after: 2 weeks (ia64 needs treating)
|
| 272766 |
08-Oct-2014 |
markj |
Pass up the error status of minidumpsys() to its callers.
PR: 193761
Submitted by: Conrad Meyer <conrad.meyer@isilon.com>
Sponsored by: EMC / Isilon Storage Division
|
| 271217 |
07-Sep-2014 |
glebius |
style(9)
|
| 271213 |
06-Sep-2014 |
adrian |
Implement local sfbuf_map and sfbuf_unmap for MIPS32.
The pre-rework behaviour was not to keep the cached mappings around after
the sfbuf was used but instead to recycle said mappings.
PR: kern/193400
|
| 269577 |
05-Aug-2014 |
glebius |
Merge all MD sf_buf allocators into one MI, residing in kern/subr_sfbuf.c
The MD allocators were very common, however there were some minor
differencies. These differencies were all consolidated in the MI allocator,
under ifdefs. The defines from machine/vmparam.h turn on features required
for a particular machine. For details look in the comment in sys/sf_buf.h.
As result no MD code left in sys/*/*/vm_machdep.c. Some arches still have
machine/sf_buf.h, which is usually quite small.
Tested by: glebius (i386), tuexen (arm32), kevlo (arm32)
Reviewed by: kib
Sponsored by: Netflix
Sponsored by: Nginx, Inc.
|
| 269137 |
26-Jul-2014 |
marcel |
Add missing definition of ELF_MACHINE_OK, now used by gcore(1).
|
| 263998 |
01-Apr-2014 |
tijl |
Rename __wchar_t so it no longer conflicts with __wchar_t from clang 3.4
-fms-extensions.
MFC after: 2 weeks
|
| 263289 |
18-Mar-2014 |
emaste |
Update NetBSD Foundation copyrights to 2-clause BSD
The NetBSD Foundation states "Third parties are encouraged to change the
license on any files which have a 4-clause license contributed to the
NetBSD Foundation to a 2-clause license."
This change removes clauses 3 and 4 from copyright / license blocks that
list The NetBSD Foundation as the only copyright holder.
Sponsored by: The FreeBSD Foundation
|
| 262217 |
19-Feb-2014 |
rwatson |
Update MIPS bootinfo.h to reflect the actual MIPS boot2/loader boot-time
interface.
MFC after: 3 weeks
Sponsored by: DARPA, AFRL
|
| 260327 |
05-Jan-2014 |
nwhitehorn |
Retire machine/fdt.h as a header used by MI code, as its function is now
obsolete. This involves the following pieces:
- Remove it entirely on PowerPC, where it is not used by MD code either
- Remove all references to machine/fdt.h in non-architecture-specific code
(aside from uart_cpu_fdt.c, shared by ARM and MIPS, and so is somewhat
non-arch-specific).
- Fix code relying on header pollution from machine/fdt.h includes
- Legacy fdtbus.c (still used on x86 FDT systems) now passes resource
requests to its parent (nexus). This allows x86 FDT devices to allocate
both memory and IO requests and removes the last notionally MI use of
fdtbus_bs_tag.
- On those architectures that retain a machine/fdt.h, unused bits like
FDT_MAP_IRQ and FDT_INTR_MAX have been removed.
|
| 257854 |
08-Nov-2013 |
alc |
As of r257209, all architectures have defined VM_KMEM_SIZE_SCALE. In other
words, every architecture is now auto-sizing the kmem arena. This revision
changes kmeminit() so that the definition of VM_KMEM_SIZE_SCALE becomes
mandatory and the definition of VM_KMEM_SIZE becomes optional.
Replace or eliminate all existing definitions of VM_KMEM_SIZE. With
auto-sizing enabled, VM_KMEM_SIZE effectively became an alternate spelling
for VM_KMEM_SIZE_MIN on most architectures. Use VM_KMEM_SIZE_MIN for
clarity.
Change kmeminit() so that the effect of defining VM_KMEM_SIZE is similar to
that of setting the tunable vm.kmem_size. Whereas the macros
VM_KMEM_SIZE_{MAX,MIN,SCALE} have had the same effect as the tunables
vm.kmem_size_{max,min,scale}, the effects of VM_KMEM_SIZE and vm.kmem_size
have been distinct. In particular, whereas VM_KMEM_SIZE was overridden by
VM_KMEM_SIZE_{MAX,MIN,SCALE} and vm.kmem_size_{max,min,scale}, vm.kmem_size
was not. Remedy this inconsistency. Now, VM_KMEM_SIZE can be used to set
the size of the kmem arena at compile-time without that value being
overridden by auto-sizing.
Update the nearby comments to reflect the kmem submap being replaced by the
kmem arena. Stop duplicating the auto-sizing formula in every machine-
dependent vmparam.h and place it in kmeminit() where auto-sizing takes
place.
Reviewed by: kib (an earlier version)
Sponsored by: EMC / Isilon Storage Division
|
| 257017 |
23-Oct-2013 |
brooks |
MFP4:
Change 221534 by rwatson@rwatson_zenith_cl_cam_ac_uk on 2013/01/27 16:05:30
FreeBSD/mips stores page-table entries in a near-identical format
to MIPS TLB entries -- only it overrides certain "reserved" bits
in the MIPS-defined EntryLo register to hold software-defined bits
(swbits) to avoid significantly increasing the page table memory
footprint. On n32 and n64, these bits were (a) colliding with
MIPS64r2 physical memory extensions and (b) being improperly
cleared.
Attempt to fix both of these problems by pushing swbits further
along 64-bit EntryLo registers into the reserved space, and
improving consistency between C-based and assembly-based clearing
of swbits -- in particular, to use the same definition. This
should stop swbits from leaking into TLB entries -- while ignored
by most current MIPS hardware, this would cause a problem with
(much) larger physical memory sizes, and also leads to confusing
hardware-level tracing as physical addresses contain unexpected
(and inconsistent) higher bits.
Discussed with: imp, jmallett
Change 1187301 by brooks@brooks_zenith on 2013/10/23 14:40:10
Loop back the initial commit of 221534 to HEAD. Correct its
implementation for mips32.
MFC after: 3 days
Sponsored by: DARPA/AFRL
|
| 256963 |
23-Oct-2013 |
brooks |
Revert r256934, it needs work to build on mips32.
|
| 256935 |
22-Oct-2013 |
brooks |
MFP4:
Change 228019 by bz@bz_zenith on 2013/04/23 13:55:30
Add kernel side support for large TLB on BERI/CHERI.
Modelled similar to NLM
MFC after: 3 days
Sponsored by: DAPRA/AFRL
|
| 256934 |
22-Oct-2013 |
brooks |
MFP4:
Change 221534 by rwatson@rwatson_zenith_cl_cam_ac_uk on 2013/01/27 16:05:30
FreeBSD/mips stores page-table entries in a near-identical format
to MIPS TLB entries -- only it overrides certain "reserved" bits
in the MIPS-defined EntryLo register to hold software-defined bits
(swbits) to avoid significantly increasing the page table memory
footprint. On n32 and n64, these bits were (a) colliding with
MIPS64r2 physical memory extensions and (b) being improperly
cleared.
Attempt to fix both of these problems by pushing swbits further
along 64-bit EntryLo registers into the reserved space, and
improving consistency between C-based and assembly-based clearing
of swbits -- in particular, to use the same definition. This
should stop swbits from leaking into TLB entries -- while ignored
by most current MIPS hardware, this would cause a problem with
(much) larger physical memory sizes, and also leads to confusing
hardware-level tracing as physical addresses contain unexpected
(and inconsistent) higher bits.
Discussed with: imp, jmallett
MFC after: 3 days
Sponsored by: DARPA/AFRL
|
| 256497 |
15-Oct-2013 |
imp |
Elminate NON_LEAF and use NESTED instead to unify our assembler
conventions.
Reviewed by: jmallet@
|
| 256496 |
15-Oct-2013 |
imp |
Replace NLEAF with LEAF_NOPROFILE to unify the conventions we use in
our assembler files.
Reviewed by: jmallet@
|
| 256495 |
15-Oct-2013 |
imp |
Replace uses of the ALEAF macro with XLEAF and remove ALEAF macro to
try to unify the conventions used in our assembler.
Reviewed by: jmallet@
|
| 256494 |
15-Oct-2013 |
imp |
Move DO_AST into pcb.h where it should have been all along. Move some
common macros for saving/restoring registers into pcb.h as well.
|
| 256172 |
09-Oct-2013 |
adrian |
Add "better" MIPS24k and MIPS74k barriers.
* the mips74k cores only need EHB (which is 'sll $0, $0, 3')
here; NOPs don't actually work.
* add EHB as the last NOP for the default barriers/hazards;
that is "better" behaviour and should work on a wider
variety of processors.
This allows the existing (icky) TLB code to work, allowing
the AR9344 SoC (mips74k) to actually get through kernel startup.
Tested:
* AR9344 SoC - (mips74k)
* AR9331 SoC - (mips24k)
TODO:
* test on mips4k CPUs, just to be sure.
* document that sll $0, $0, 3 is actually "EHB" and that it
falls back to being a NOP for pre-mips32r1.
* mips24k has an errata that we currently don't correctly explicitly
state - ie, that after DERET/ERET, the only valid instruction is
a NOP.
Reviewed by: imp@
Approved by: re@ (gjb)
|
| 255318 |
06-Sep-2013 |
glebius |
Fix build with gcc. Move sf_buf_alloc()/sf_buf_free() declarations
to MD headers.
|
| 255289 |
06-Sep-2013 |
glebius |
On those machines, where sf_bufs do not represent any real object, make
sf_buf_alloc()/sf_buf_free() inlines, to save two calls to an absolutely
empty functions.
Reviewed by: alc, kib, scottl
Sponsored by: Nginx, Inc.
Sponsored by: Netflix
|
| 255194 |
03-Sep-2013 |
imp |
Newer versions of gcc define __INT64_C and __UINT64_C, so avoid
redefining them if gcc provides them.
|
| 253750 |
28-Jul-2013 |
avg |
Revert r253748,253749
This WIP should not have been committed yet.
Pointyhat to: avg
|
| 253748 |
28-Jul-2013 |
avg |
put contents of cpu.h under _KERNEL
no userland-serviceable parts inside
MFC after: 20 days
|
| 253103 |
09-Jul-2013 |
imp |
Nearly a complete rewrite of elf.h.
Start with NetBSD's sys/arch/mips/include/elf_machdep.h 1.18. Remove the NetBSD
specific glue pieces (leaving mostly just relocation types).
Add in FreeBSD specific glue pieces from older versions of this file, and
move to the top of the file:
r237430 | kib | 2012-06-22 00:38:31 -0600 (Fri, 22 Jun 2012) | 5 lines
r232449 | jmallett | 2012-03-03 01:19:18 -0700 (Sat, 03 Mar 2012) | 18 lines
r217097 | kib | 2011-01-07 07:22:34 -0700 (Fri, 07 Jan 2011) | 3 lines
r211412 | kib | 2010-08-17 02:55:45 -0600 (Tue, 17 Aug 2010) | 7 lines
r202908 | gonzo | 2010-01-23 19:59:22 -0700 (Sat, 23 Jan 2010) | 4 lines
r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines
r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines
r197933 | kib | 2009-10-10 09:31:24 -0600 (Sat, 10 Oct 2009) | 9 lines
r189926 | kib | 2009-03-17 06:50:16 -0600 (Tue, 17 Mar 2009) | 9 lines
r186191 | imp | 2008-12-16 13:07:47 -0700 (Tue, 16 Dec 2008) | 7 lines
as closely as I can tell, the projects/mips branch merge was disruptive
to good history.
This should make merges easier in the future from NetBSD and vice versa.
|
| 252965 |
07-Jul-2013 |
imp |
Remove all the NOPs after SYNC. They aren't needed.
They originated in the original Octeon port. They weren't present, as
far as I can tell, on the projects/mips branch until after this
point. They were in the original Octeon port in code picked up from
the vendor, who I've been able to find out trolling old email put them
there to get around an SMP problem that most likely was fixed in other
ways.
NetBSD and Linux don't have these, except for some specific uses of
SYNC on the alchemy parts (which we don't support, but even if we did
it is only a specific case and would be specifically coded
anyway). This is true of the current Linux code, as well as one old
version I polled.
I looked back at the old R12000, R8000, R6000, R4000, R4400 errata
that I have, and could find no mention of SYNC needing NOPs for
silicon bugs (although plenty of other cases where NOPs and other
contortions were needed).
An Google search turned up no old mailing list discussions on this on
Linux, NetBSD or FreeBSD (except the disussion that kicked off these
studies).
I've test booted this on my Octeon Plus eval board and survived a
buildworld. Adrian Chadd reports that this patch has no ill effects on
the Ahteros platforms he tested it on.
I conclude it is safe to just remove the NOPs. But added
__MIPS_PLATFORM_SYNC_NOPS as a failsafe in case we find some platform
where these are, in fact, required.
Reviewed by: adrian@
|
| 252434 |
01-Jul-2013 |
kib |
Fix issues with zeroing and fetching the counters, on x86 and ppc64.
Issues were noted by Bruce Evans and are present on all architectures.
On i386, a counter fetch should use atomic read of 64bit value,
otherwise carry from the increment on other CPU could be lost for the
given fetch, making error of 2^32. If 64bit read (cmpxchg8b) is not
available on the machine, it cannot be SMP and it is enough to disable
preemption around read to avoid the split read.
On x86 the counter increment is not atomic on purpose, which makes it
possible for the store of the incremented result to override just
zeroed per-cpu slot. The effect would be a counter going off by
arbitrary value after zeroing. Perform the counter zeroing on the
same processor which does the increments, making the operations
mutually exclusive. On i386, same as for the fetching, if the
cmpxchg8b is not available, machine is not SMP and we disable
preemption for zeroing.
PowerPC64 is treated the same as amd64.
For other architectures, the changes made to allow the compilation to
succeed, without fixing the issues with zeroing or fetching. It
should be possible to handle them by using the 64bit loads and stores
atomic WRT preemption (assuming the architectures also converted from
using critical sections to proper asm). If architecture does not
provide the facility, using global (spin) mutex would be non-optimal
but working solution.
Noted by: bde
Sponsored by: The FreeBSD Foundation
|
| 250338 |
07-May-2013 |
attilio |
Rename VM_NDOMAIN into MAXMEMDOM and move it into machine/param.h in
order to match the MAXCPU concept. The change should also be useful
for consolidation and consistency.
Sponsored by: EMC / Isilon storage division
Obtained from: jeff
Reviewed by: alc
|
| 250138 |
01-May-2013 |
imp |
Don't include asm.h in non-asm files.
Remove #define to get kludges that asm.h used to define
Move clever macros to access assembler instructions to trap.c
Remove __ASSEMBLER__ ifdefs in regdef.h: they aren't needed anymore.
|
| 250136 |
01-May-2013 |
imp |
Import NetBSD's version, which is perfectly fine.
Submitted by: jmallet@
|
| 250135 |
01-May-2013 |
imp |
Add the standard #ifdef header protection.
|
| 250134 |
01-May-2013 |
imp |
Import virgin regdef.h from 4.4 Lite 2's sys/pmax/include/regdef.h,
expand the %sccs.include.redist.c% directive with the standard
3-clause license, and add $FreeBSD$ to keep the commit script happy.
# This may break some mips stuff, which will be fixed in the next commit.
|
| 249901 |
25-Apr-2013 |
imp |
Use the offsets from pcb.h rather than regnum.h to store the registers
in the pcb. setjmp/longjmp in the kernel also used these values, so
continue to use them although their use isn't technically the pcb
register array (matching is all that's important for setjmp/longjmp in
the kernel). Finally, eliminate the old register names from regnum.h.
This is a lexical change only. The non-debug .o files have the same md5.
|
| 249882 |
25-Apr-2013 |
imp |
Make it possible to include this file in assembler .S sources.
|
| 249790 |
23-Apr-2013 |
imp |
Update trapframe to be consistent with the changes made to regnum.h. This
should fix the booting problems people have been seeing.
|
| 249776 |
22-Apr-2013 |
brooks |
MFP4 223084, 227821:
Partially implement generic_bs_*_8() for MIPS platforms.
This is known to work with TARGET_ARCH=mips64 with FreeBSD/BERI.
Assuming that other definitions in cpufunc.h are correct it will
work on non-o64 ABI systems except sibyte. On sibyte and o32 systems
generic_bs_*_8() will remain panic() implementations.
Sponsored by: DARPA, AFRL
Reviewed by: imp, jmallett (older versions)
|
| 249551 |
16-Apr-2013 |
imp |
Point to regdef.h. May need to dig up references to the N32 standard
that support this usage (which may be a bit rough, since different
parts of the standard say mutually contradictory things).
|
| 249523 |
15-Apr-2013 |
imp |
Fix N32/N64 register saving by ensuring that all registers resolve
to unique values.
There's some confusion about what the n32 assembler API really is
(since on page 9 of the spec they say that t0-t3 don't exist, then
turn around on page 22 and say that t4-t7 don't exist), and this
doesn't touch that.
NetBSD's version of this file follows the convention I used here, and
is likely to be correct.
This should fix gdb/ptrace.
|
| 249415 |
12-Apr-2013 |
jchandra |
Move MIPS_MAX_TLB_ENTRIES definition from cpuregs.h to tlb.c
Having MIPS_MAX_TLB_ENTRIES defined to 128 is misleading, since it used
to be 64 in older releases of MIPS architecture (where it could be read
from Config1) and can be much more than 128 for the newer processors.
For now, move the definition to the only file using it (mips/mips/tlb.c)
and define MIPS_MAX_TLB_ENTRIES depending on the MIPS cpu defined. Also
add few checks so that we do not write beyond the end of the tlb_state
array.
This fixes a kernel data corruption seen in Netlogic XLP, which was casued
by tlb_save() writing beyond the end of tlb_state array when breaking into
debugger.
|
| 249268 |
08-Apr-2013 |
glebius |
Merge from projects/counters: counter(9).
Introduce counter(9) API, that implements fast and raceless counters,
provided (but not limited to) for gathering of statistical data.
See http://lists.freebsd.org/pipermail/freebsd-arch/2013-April/014204.html
for more details.
In collaboration with: kib
Reviewed by: luigi
Tested by: ae, ray
Sponsored by: Nginx, Inc.
|
| 249265 |
08-Apr-2013 |
glebius |
Merge from projects/counters:
Pad struct pcpu so that its size is denominator of PAGE_SIZE. This
is done to reduce memory waste in UMA_PCPU_ZONE zones.
Sponsored by: Nginx, Inc.
|
| 245337 |
12-Jan-2013 |
alc |
Define VM_KMEM_SIZE_MAX as a fraction of the kernel address space size
rather than a constant so that VM_KMEM_SIZE_MAX will scale automatically
with the kernel address space size. This is particularly important for
MIPS because the same definition is used by both 32- and 64-bit kernels.
Tested by: jchandra
|
| 245332 |
12-Jan-2013 |
rwatson |
Merge Perforce changeset 219925 to head:
Provided a bus_space implementation for FDT, modelled on
bus_space_generic, but with a local version of the map address
routine that does a P->V translation, as is the case with NLM's
similar routine for XLP. It's not clear to me that this is the
right solution -- possibly this belongs in simplebus -- however,
it is sufficient to get the DE4 LED driver working.
Sponsored by: DARPA, AFRL
|
| 245330 |
12-Jan-2013 |
rwatson |
Merge Perforce change @219948 to head:
Add code so that the BERI boot process can ask the kernel linker for
DTB blobs that may have been left for it by the boot loader, as done
on PowerPC and ARM. This will require both a more mature boot
loader, and more mature boot loader argument passing mechanism,
than currently supported on BERI.
Sponsored by: DARPA, AFRL
|
| 244417 |
19-Dec-2012 |
alc |
Eliminate some definitions that haven't been used in a decade or more.
|
| 243030 |
14-Nov-2012 |
alc |
The function pmap_alloc_direct_page() unconditionally zeroes the returned
page. Therefore, it is really inappropriate for use by the function
uma_small_alloc(). The effect of using it was that every page was zeroed
at least once and possibly twice if M_ZERO was passed as a "wait" flag.
|
| 241374 |
09-Oct-2012 |
attilio |
Add an unified macro to deny ability from the compiler to reorder
instruction loads/stores at its will.
The macro __compiler_membar() is currently supported for both gcc and
clang, but kernel compilation will fail otherwise.
Reviewed by: bde, kib
Discussed with: dim, theraven
MFC after: 2 weeks
|
| 241123 |
02-Oct-2012 |
alc |
Introduce a new TLB invalidation function for efficiently invalidating
address ranges, and use this function in pmap_remove().
Tested by: jchandra
|
| 239964 |
01-Sep-2012 |
alc |
Introduce a new software PTE flag that indicates whether the mapping is
for a managed page.
Tested by: jchandra
|
| 239684 |
25-Aug-2012 |
rwatson |
Add MD syscons header file for MIPS.
Sponsored by: DARPA, AFRL
|
| 239681 |
25-Aug-2012 |
alc |
Retire PV_TABLE_MOD. When we destroy or write protect a dirty mapping,
we call vm_page_dirty(). Maintaining the PV_TABLE_MOD flag, in addition,
serves no useful purpose.
|
| 239236 |
13-Aug-2012 |
alc |
Port the new PV entry allocator from amd64/i386. This allocator has two
advantages. First, PV entries are roughly half the size. Second, this
allocator doesn't access the paging queues, and thus it will allow for the
removal of the page queues lock from this pmap.
Fix a rather serious bug in pmap_remove_write(). After removing write
access from the specified page's first mapping, pmap_remove_write() then
used the wrong "next" pointer. Consequently, the page's second, third,
etc. mappings were not write protected.
Tested by: jchandra
|
| 239152 |
09-Aug-2012 |
alc |
Merge r132141 and r111272 from amd64/i386:
Reduce the size of a PV entry by eliminating pv_ptem. There is no need
to store a pointer to the page table page in the PV entry because it is
easily computed during the walk down the page table.
Eliminate the ptphint from the pmap. Long, long ago, page table pages
belonged to a vm object, and we would look up page table pages based
upon their offset within this vm object. In those days, this hint may
have had tangible benefits.
Tested by: jchandra
|
| 237517 |
24-Jun-2012 |
andrew |
Make the wchar_t type machine dependent.
This is required for ARM EABI. Section 7.1.1 of the Procedure Call for the
ARM Architecture (AAPCS) defines wchar_t as either an unsigned int or an
unsigned short with the former preferred.
Because of this requirement we need to move the definition of __wchar_t to
a machine dependent header. It also cleans up the macros defining the limits
of wchar_t by defining __WCHAR_MIN and __WCHAR_MAX in the same machine
dependent header then using them to define WCHAR_MIN and WCHAR_MAX
respectively.
Discussed with: bde
|
| 237433 |
22-Jun-2012 |
kib |
Implement mechanism to export some kernel timekeeping data to
usermode, using shared page. The structures and functions have vdso
prefix, to indicate the intended location of the code in some future.
The versioned per-algorithm data is exported in the format of struct
vdso_timehands, which mostly repeats the content of in-kernel struct
timehands. Usermode reading of the structure can be lockless.
Compatibility export for 32bit processes on 64bit host is also
provided. Kernel also provides usermode with indication about
currently used timecounter, so that libc can fall back to syscall if
configured timecounter is unknown to usermode code.
The shared data updates are initiated both from the tc_windup(), where
a fast task is queued to do the update, and from sysctl handlers which
change timecounter. A manual override switch
kern.timecounter.fast_gettime allows to turn off the mechanism.
Only x86 architectures export the real algorithm data, and there, only
for tsc timecounter. HPET counters page could be exported as well, but
I prefer to not further glue the kernel and libc ABI there until
proper vdso-based solution is developed.
Minimal stubs neccessary for non-x86 architectures to still compile
are provided.
Discussed with: bde
Reviewed by: jhb
Tested by: flo
MFC after: 1 month
|
| 237430 |
22-Jun-2012 |
kib |
Reserve AT_TIMEKEEP auxv entry for providing usermode the pointer to
timekeeping information.
MFC after: 1 week
|
| 237168 |
16-Jun-2012 |
alc |
The page flag PGA_WRITEABLE is set and cleared exclusively by the pmap
layer, but it is read directly by the MI VM layer. This change introduces
pmap_page_is_write_mapped() in order to completely encapsulate all direct
access to PGA_WRITEABLE in the pmap layer.
Aesthetics aside, I am making this change because amd64 will likely begin
using an alternative method to track write mappings, and having
pmap_page_is_write_mapped() in place allows me to make such a change
without further modification to the MI VM layer.
As an added bonus, tidy up some nearby comments concerning page flags.
Reviewed by: kib
MFC after: 6 weeks
|
| 235941 |
24-May-2012 |
bz |
MFp4 bz_ipv6_fast:
in_cksum.h required ip.h to be included for struct ip. To be
able to use some general checksum functions like in_addword()
in a non-IPv4 context, limit the (also exported to user space)
IPv4 specific functions to the times, when the ip.h header is
present and IPVERSION is defined (to 4).
We should consider more general checksum (updating) functions
to also allow easier incremental checksum updates in the L3/4
stack and firewalls, as well as ponder further requirements by
certain NIC drivers needing slightly different pseudo values
in offloading cases. Thinking in terms of a better "library".
Sponsored by: The FreeBSD Foundation
Sponsored by: iXsystems
Reviewed by: gnn (as part of the whole)
MFC After: 3 days
|
| 234785 |
29-Apr-2012 |
dim |
Add a convenience macro for the returns_twice attribute, and apply it to
the prototypes of the appropriate functions (getcontext, savectx,
setjmp, sigsetjmp and vfork).
MFC after: 2 weeks
|
| 233670 |
29-Mar-2012 |
jhb |
Use VM_MEMATTR_UNCACHEABLE for the constant for UC memory rather than
VM_MEMATTR_UNCACHED. VM_MEMATTR_UNCACHEABLE is the constant other
platforms use.
MFC after: 2 weeks
|
| 233644 |
29-Mar-2012 |
jmallett |
Assume a big-endian default on MIPS and drop the "eb" suffix from MACHINE_ARCH.
This makes our naming scheme more closely match other systems and the
expectations of much third-party software. MIPS builds which are little-endian
should require and exhibit no changes. Big-endian TARGET_ARCHes must be
changed:
From: To:
mipseb mips
mipsn32eb mipsn32
mips64eb mips64
An entry has been added to UPDATING and some foot-shooting protection (complete
with warnings which should become errors in the near future) to the top-level
base system Makefile.
|
| 233628 |
28-Mar-2012 |
fabient |
Add software PMC support.
New kernel events can be added at various location for sampling or counting.
This will for example allow easy system profiling whatever the processor is
with known tools like pmcstat(8).
Simultaneous usage of software PMC and hardware PMC is possible, for example
looking at the lock acquire failure, page fault while sampling on
instructions.
Sponsored by: NETASQ
MFC after: 1 month
|
| 233381 |
23-Mar-2012 |
gonzo |
Fix pmap_kextract prototype to align it with pmap.c change
|
| 233319 |
22-Mar-2012 |
gonzo |
Rework MIPS PMC code:
- Replace MIPS24K-specific code with more generic framework that will
make adding new CPU support easier
- Add MIPS24K support for new framework
- Limit backtrace depth to 1 for stability reasons and add option
HWPMC_MIPS_BACKTRACE to override this limitation
|
| 232896 |
12-Mar-2012 |
jmallett |
o) Use ABI, not ISA_* options, to determine whether to compile bits if libkern
required for the ABI the kernel is being built for.
XXX This is implemented in a kind-of nasty way that involves including source
files, but it's still an improvement.
o) Retire ISA_* options since they're unused and were always wrong.
|
| 232881 |
12-Mar-2012 |
jmallett |
Use 64-bit bus space constants on 64-bit kernels.
|
| 232872 |
12-Mar-2012 |
jmallett |
Remove more unused stuff, primarily a set of (unused, thankfully) PIO
functions.
Adjust nearby style of one assembly function END().
|
| 232855 |
12-Mar-2012 |
jmallett |
Remove more unused code and declarations, and add dire warnings to the 64-bit
atomic ops used by 32-bit kernels.
|
| 232853 |
12-Mar-2012 |
jmallett |
Remove platform APIs which are not used by any code and which had only stub
implementations or no implementation on all platforms.
Some of these functions might be good ideas, but their semantics were unclear
given the lack of implementation, and an unlucky porter could be fooled into
trying to implement them or, worse, being baffled when something like
platform_trap_enter() failed to be called.
|
| 232801 |
10-Mar-2012 |
jmallett |
Remove some headers not used by kernel or world and which are not present in
other ports.
|
| 232789 |
10-Mar-2012 |
jmallett |
Fix reversed logic in previous commit that broke build and earned me quite the
pointy hat.
Submitted by: bz
|
| 232773 |
10-Mar-2012 |
jmallett |
Use ABI to determine bus_addr_t for cnMIPS.
|
| 232630 |
06-Mar-2012 |
jmallett |
Get rid of duplicated versions of the KSU bits.
|
| 232615 |
06-Mar-2012 |
jmallett |
At the risk of reducing source compatibility with old NetBSD and Sprite:
o) Get rid of some unused macros related to features we don't intend to
provide.
o) Get rid of macro definitions for MIPS-I CPUs. We are not likely to
support anything that predartes MIPS-III.
o) Respell MIPS3_* macros as MIPS_*, which is how most of them were being
used already.
o) Eliminate a duplicate and mostly-unused set of exception vector macros.
There's still considerable duplication and lots more obsolete in our headers,
but this reduces one of the larger files to a size where one could reckon
about the correctness of its contents with a mere few hours of contemplation.
There is, of course, a question of whether we need definitions for fields,
registers and configurations that we are unlikely to ever use or implement,
even if they're not obsolete since 1991. FreeBSD is not a processor
reference manual, and things that aren't used may be wrong, or may be
duplicated because nobody could possibly actually know whether they're
already defined.
|
| 232584 |
06-Mar-2012 |
jmallett |
Fix two and a half oversights in COMPAT_FREEBSD32 related to contexts and
TLS:
o) The mc_tls field used to store the TLS base when doing context gets and
restores was left a pointer and not converted to a 32-bit integer. This
had the bug of not correctly capturing the TLS value desired by the user,
and the extra nastiness of making the structure the wrong size.
o) The mc_tls field was not being saved by sendsig. As a result, the TLS base
would always be set to NULL when restoring from a signal handler.
Thanks to gonzo for helping track down a bunch of other TLS bugs that came out
of tracking these down.
|
| 232583 |
06-Mar-2012 |
jmallett |
When emulating rdhwr for TLS, use the 32-bit offset under COMPAT_FREEBSD32.
|
| 232577 |
06-Mar-2012 |
gonzo |
Prepare for large TLS redo. Save pointer to the beginning of TLS area,
and offset it only if requested by RDHWR handler. Otherwise things
get overly complicated - we need to track whether address passsed in
request for setting td_md.md_tls is already offseted or not.
|
| 232449 |
03-Mar-2012 |
jmallett |
o) Add COMPAT_FREEBSD32 support for MIPS kernels using the n64 ABI with userlands
using the o32 ABI. This mostly follows nwhitehorn's lead in implementing
COMPAT_FREEBSD32 on powerpc64.
o) Add a new type to the freebsd32 compat layer, time32_t, which is time_t in the
32-bit ABI being used. Since the MIPS port is relatively-new, even the 32-bit
ABIs use a 64-bit time_t.
o) Because time{spec,val}32 has the same size and layout as time{spec,val} on MIPS
with 32-bit compatibility, then, disable some code which assumes otherwise
wrongly when built for MIPS. A more general macro to check in this case would
seem like a good idea eventually. If someone adds support for using n32
userland with n64 kernels on MIPS, then they will have to add a variety of
flags related to each piece of the ABI that can vary. That's probably the
right time to generalize further.
o) Add MIPS to the list of architectures which use PAD64_REQUIRED in the
freebsd32 compat code. Probably this should be generalized at some point.
Reviewed by: gonzo
|
| 231406 |
10-Feb-2012 |
gonzo |
- Fix spelling of R_MIPS_RELGOT
- Add R_MIPS_JALR relocation
- Add TLS relocation types
Obtained from: NetBSD
|
| 231312 |
09-Feb-2012 |
gonzo |
- Emulate RDHWR instruction for TLS support
Reading register $29 with RDHWR is becoming the de-facto standard to
implement TLS. According to linux-mips wiki, MIPS Technologies has
reserved hardware register $29 for ABI use. Furthermore current GCC
makes the following assumptions:
- RDHWR is natively available or otherwise emulated by the kernel
- Register $29 holds the TLS pointer
Submitted by: Robert Millan <rmh@debian.org>
|
| 230475 |
23-Jan-2012 |
das |
Add C11 macros describing subnormal numbers to float.h.
Reviewed by: bde
|
| 230366 |
20-Jan-2012 |
das |
Add parentheses where required. Without them, `sizeof LDBL_MAX'
is a syntax error and shouldn't be, while `1 FLT_ROUNDS' isn't a
syntax error and should be. Thanks to bde for the examples.
|
| 230229 |
16-Jan-2012 |
das |
Fix the value of float_t to match what is implied by FLT_EVAL_METHOD.
|
| 230199 |
16-Jan-2012 |
das |
Remove a confused comment and fix some minor bugs.
|
| 230094 |
13-Jan-2012 |
gonzo |
Fix backtrace for MIPS64:
- Properly print 64-bit addresses
- Get whole 64 bits of address using kdbpeekd
- Make check for kernel address compatible with MIPS64
|
| 229677 |
06-Jan-2012 |
gonzo |
- Add better COP2 (crypto coprocessor) context handler for Octeon. Keep
COP2 disabled and lazily allocate COP2 context structure in exception
handler. Keep kernel and userland contexts separated.
|
| 229496 |
04-Jan-2012 |
andreast |
Apply the same change as in r229494.
Requested by: ed
|
| 228982 |
30-Dec-2011 |
marcel |
Remove trailing white-space.
|
| 228469 |
13-Dec-2011 |
ed |
Replace __signed by signed.
The signed keyword is an integral part of the C syntax. There's no need
to use __signed.
|
| 227782 |
21-Nov-2011 |
jchandra |
XLP processors have the release 2 pagegrain register
Add accessors to cpufunc.h
Obtained from: prabhath at netlogicmicro com
|
| 227658 |
18-Nov-2011 |
jchandra |
Fix COP0 hazards for XLR and XLP
The XLR CPUs do not have any software visible hazards for COP0 operations.
On XLP the hazard is a ehb, since it is mips64r2.
|
| 226607 |
21-Oct-2011 |
das |
People porting FreeBSD to new architectures ought not have to
implement a deprecated FPU control interface in addition to the
standard one. To make this clearer, further deprecate ieeefp.h
by not declaring the function prototypes except on architectures
that implement them already.
Currently i386 and amd64 implement the ieeefp.h interface for
compatibility, and for fp[gs]etprec(), which doesn't exist on
most other hardware. Powerpc, sparc64, and ia64 partially implement
it and probably shouldn't, and other architectures don't implement it
at all.
|
| 226517 |
18-Oct-2011 |
jchandra |
Fix wakeup latency when sleeping with 'wait'
If we handle an interrupt just before the 'wait' and the interrupt
schedules some work, we need to skip the 'wait' call. The simple solution
of calling sched_runnable() with interrupts disabled immediately before
wait still leaves a window after the call and before 'wait' in which
the same issue can occur.
The solution implemented is to check the EPC in the interrupt handler, and
if it is in a region before the 'wait' call, to fix up the EPC to skip the
wait call.
Reported/analysed by: adrian
Fix suggested by: kib
Reviewed by: jmallett, imp
|
| 226501 |
18-Oct-2011 |
jchandra |
Support for booting XLP using FDT.
- update xlp_machdep.c to read arguments from FDT if FDT support is
compiled in.
- define rmi_uart_bus_space, and use it as fdtbus_bs_tag
- update conf files for FDT support
- add default dts file xlp-basic.dts
|
| 226496 |
18-Oct-2011 |
jchandra |
FDT support for MIPS.
Add architecture specific files needed to compile MIPS with
flattened device tree support.
|
| 226112 |
07-Oct-2011 |
kib |
Remove unused define.
MFC after: 1 month
|
| 226065 |
06-Oct-2011 |
kib |
Convert MIPS to the syscallenter/syscallret system call sequence handlers.
This was the last architecture used custom syscall entry sequence.
Reviewed, debugged, tested and approved by: jchandra
MFC after: 1 month
|
| 226021 |
04-Oct-2011 |
marcel |
Remove bogus and wrong definition of BLKDEV_IOSIZE.
Wrong in that it must be guarded (it's configurable)
and bogus in that there's absolutely no rationale for
it not default to a page size like all other archs.
|
| 224207 |
19-Jul-2011 |
attilio |
Add the possibility to specify from kernel configs MAXCPU value.
This patch is going to help in cases like mips flavours where you
want a more granular support on MAXCPU.
No MFC is previewed for this patch.
Tested by: pluknet
Approved by: re (kib)
|
| 224115 |
16-Jul-2011 |
jchandra |
MIPS changes for Netlogic XLP support.
This patch adds support for the Netlogic XLP mips64 processors in
the common MIPS code. The changes are :
- Add CPU_NLM processor type
- Add cases for CPU_NLM, mostly were CPU_RMI is used.
- Update cache flush changes for CPU_NLM
- Add kernel build configuration files for xLP.
In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com>
Approved by: bz(re), jmallett, imp(mips)
|
| 222813 |
07-Jun-2011 |
attilio |
etire the cpumask_t type and replace it with cpuset_t usage.
This is intended to fix the bug where cpu mask objects are
capped to 32. MAXCPU, then, can now arbitrarely bumped to whatever
value. Anyway, as long as several structures in the kernel are
statically allocated and sized as MAXCPU, it is suggested to keep it
as low as possible for the time being.
Technical notes on this commit itself:
- More functions to handle with cpuset_t objects are introduced.
The most notable are cpusetobj_ffs() (which calculates a ffs(3)
for a cpuset_t object), cpusetobj_strprint() (which prepares a string
representing a cpuset_t object) and cpusetobj_strscan() (which
creates a valid cpuset_t starting from a string representation).
- pc_cpumask and pc_other_cpus are target to be removed soon.
With the moving from cpumask_t to cpuset_t they are now inefficient
and not really useful. Anyway, for the time being, please note that
access to pcpu datas is protected by sched_pin() in order to avoid
migrating the CPU while reading more than one (possible) word
- Please note that size of cpuset_t objects may differ between kernel
and userland. While this is not directly related to the patch itself,
it is good to understand that concept and possibly use the patch
as a reference on how to deal with cpuset_t objects in userland, when
accessing kernland members.
- KTR_CPUMASK is changed and now is represented through a string, to be
set as the example reported in NOTES.
Please additively note that no MAXCPU is bumped in this patch, but
private testing has been done until to MAXCPU=128 on a real 8x8x2(htt)
machine (amd64).
Please note that the FreeBSD version is not yet bumped because of
the upcoming pcpu changes. However, note that this patch is not
targeted for MFC.
People to thank for the time spent on this patch:
- sbruno, pluknet and Nicholas Esborn (nick AT desert DOT net) tested
several revision of the patches and really helped in improving
stability of this work.
- marius fixed several bugs in the sparc64 implementation and reviewed
patches related to ktr.
- jeff and jhb discussed the basic approach followed.
- kib and marcel made targeted review on some specific part of the
patch.
- marius, art, nwhitehorn and andreast reviewed MD specific part of
the patch.
- marius, andreast, gonzo, nwhitehorn and jceel tested MD specific
implementations of the patch.
- Other people have made contributions on other patches that have been
already committed and have been listed separately.
Companies that should be mentioned for having participated at several
degrees:
- Yahoo! for having offered the machines used for testing on big
count of CPUs.
- The FreeBSD Foundation for having sponsored my devsummit attendance,
which has been instrumental.
- Sandvine for having offered offices and infrastructure during
development.
(I really hope I didn't forget anyone, if it happened I apologize in
advance).
|
| 222234 |
23-May-2011 |
attilio |
Merge r221846 from largeSMP project branch:
Fix arguments passing to _long() version of atomic function for mips.
The native implementation is bogus in that regard and offers the same
problem solved for powerpc as r222198, but mips' guys just wanted a
small and self-contained patch for mips rather than rewriting the
whole support.
Reviewed by: art, imp
Tested by: gonzo
MFC after: 2 weeks
|
| 221855 |
13-May-2011 |
mdf |
Move the ZERO_REGION_SIZE to a machine-dependent file, as on many
architectures (i386, for example) the virtual memory space may be
constrained enough that 2MB is a large chunk. Use 64K for arches
other than amd64 and ia64, with special handling for sparc64 due to
differing hardware.
Also commit the comment changes to kmem_init_zero_region() that I
missed due to not saving the file. (Darn the unfamiliar development
environment).
Arch maintainers, please feel free to adjust ZERO_REGION_SIZE as you
see fit.
Requested by: alc
MFC after: 1 week
MFC with: r221853
|
| 219693 |
16-Mar-2011 |
jmallett |
o) Properly size caches and TLB on Octeon.
o) Make COP0_SYNC do nothing on Octeon, which is fully interlocked.
Submitted by: Bhanu Prakash (with modifications)
|
| 219122 |
01-Mar-2011 |
jchandra |
Increase NKPT in case of n32 and n64 to support more physical memory.
On n32, vm_page_startup() needs more virtual mem to map vm_page structs.
The new value of 256 will allow us to support 16GB RAM.
|
| 218773 |
17-Feb-2011 |
alc |
Remove pmap fields that are either unused or not fully implemented.
Discussed with: kib
|
| 218591 |
12-Feb-2011 |
jmallett |
Allow the platform code to return a bitmask of running cores rather than just
a number of cores, this allows for a sparse set of CPUs. Implement support
for sparse core masks on Octeon.
XXX jeff@ suggests that all_cpus should include cores that are offline or
running other applications/OSes, so the platform API should be further
extended to allow us to set all_cpus to include all cores that are
physically-present as opposed to only those that are running FreeBSD.
Submitted by: Bhanu Prakash (with modifications)
Reviewed by: jchandra
Glanced at by: kib, jeff, jhb
|
| 218383 |
06-Feb-2011 |
jmallett |
o) Cavium Octeon doesn't need nop barriers.
o) Have mips_wblush just do syncw, not sync on Cavium Octeon.
o) Add support for reading and writing some Octeon-specific registers.
NB: Some of these are not entirely Octeon-specific.
Submitted by: Bhanu Prakash
|
| 218266 |
04-Feb-2011 |
tijl |
Replace __LP64__ with __mips_n64. This partly reverts r217147.
Requested by: jmallett, imp
Approved by: kib (mentor)
|
| 217944 |
27-Jan-2011 |
jchandra |
Implement sf_buf using direct map (XKPHYS) in MIPS n64.
- Provide trivial implementation of sf_buf_alloc(), sf_buf_free(),
sf_buf_kva() and sf_buf_page() using direct map for n64.
- uio_machdep.c - use macros so that the direct map will be used in
case of n64.
Reviewed by: imp (earlier version)
Obtained from: jmallett (user/jmallett/octeon)
|
| 217515 |
17-Jan-2011 |
jkim |
Add reader/writer lock around mem_range_attr_get() and mem_range_attr_set().
Compile sys/dev/mem/memutil.c for all supported platforms and remove now
unnecessary dev_mem_md_init(). Consistently define mem_range_softc from
mem.c for all platforms. Add missing #include guards for machine/memdev.h
and sys/memrange.h. Clean up some nearby style(9) nits.
MFC after: 1 month
|
| 217354 |
13-Jan-2011 |
jchandra |
Support for 64 bit PTEs on n32 and n64 compilation.
In n32 and n64, add support for physical address above 4GB by having
64 bit page table entries and physical addresses. Major changes are:
- param.h: update PTE sizes, masks and shift values to support 64 bit PTEs.
- param.h: remove DELAY(), mips_btop(same as atop), mips_ptob (same as
ptoa), and reformat.
- param.h: remove casting to unsigned long in trunc_page and round_page
since this will be used on physical addresses.
- _types.h: have 64 bit __vm_paddr_t for n32.
- pte.h: update TLB LO0/1 access macros to support 64 bit PTE
- pte.h: assembly macros for PTE operations.
- proc.h: md_upte is now 64 bit for n32 and n64.
- exception.S and swtch.S: use the new PTE macros for PTE operations.
- cpufunc.h: TLB_LO0/1 registers are 64bit for n32 and n64.
- xlr_machdep.c: Add memory segments above 4GB to phys_avail[] as they are
supported now.
Reviewed by: jmallett (earlier version)
|
| 217345 |
13-Jan-2011 |
jchandra |
Cleanup physical address and PTE types on MIPS.
1. Use vm_paddr_t for physical addresses.
There are a few places in the MIPS platform code where vm_offset_t is
used for physical addresses, change these to use vm_paddr_t:
- phys_avail[], physmem_desc[] arrays
- pmap_mapdev(), page_is_managed(), is_cacheable_mem() pmap_map() args
- local variables of various pmap functions
2. Change init_pte_prot() return from int to pt_entry_t, as this can be
64 bit when using 64 bit TLB entries.
3. Update printing of pt_entry_t and of vm_paddr_t to use 'j' format with
uintmax_t. This will be useful later if we plan to use 64bit phsical addr
on 32 bit n32 compilation.
Reviewed by: imp
|
| 217192 |
09-Jan-2011 |
kib |
Move repeated MAXSLP definition from machine/vmparam.h to sys/vmmeter.h.
Update the outdated comments describing MAXSLP and the process
selection algorithm for swap out.
Comments wording and reviewed by: alc
|
| 217156 |
08-Jan-2011 |
tijl |
White space changes to align comments. The mips and powerpc _inttypes.h
are now exactly the same.
Approved by: kib (mentor)
|
| 217155 |
08-Jan-2011 |
tijl |
Rename PRIreg helper macro to PRIptr to better reflect its use. Registers
and pointers don't always have the same size, e.g. the __mips_n32 ABI
(ILP32) has 64 bit registers but 32 bit pointers.
On mips introduce PRIptr to fix the format specifier for (u)intptr_t.
Prefix PRI64 and PRIptr with underscores because macro names starting with
PRI[a-zX] are reserved for future use.
Approved by: kib (mentor)
|
| 217147 |
08-Jan-2011 |
tijl |
On mixed 32/64 bit architectures (mips, powerpc) use __LP64__ rather than
architecture macros (__mips_n64, __powerpc64__) when 64 bit types (and
corresponding macros) are different from 32 bit. [1]
Correct the type of INT64_MIN, INT64_MAX and UINT64_MAX.
Define (U)INTMAX_C as an alias for (U)INT64_C matching the type definition
for (u)intmax_t. Do this on all architectures for consistency.
Suggested by: bde [1]
Approved by: kib (mentor)
|
| 217146 |
08-Jan-2011 |
tijl |
On 32 bit architectures define (u)int64_t as (unsigned) long long instead
of (unsigned) int __attribute__((__mode__(__DI__))). This aligns better
with macros such as (U)INT64_C, (U)INT64_MAX, etc. which assume (u)int64_t
has type (unsigned) long long.
The mode attribute was used because long long wasn't standardised until
C99. Nowadays compilers should support long long and use of the mode
attribute is discouraged according to GCC Internals documentation.
The type definition has to be marked with __extension__ to support
compilation with "-std=c89 -pedantic".
Discussed with: bde
Approved by: kib (mentor)
|
| 217145 |
08-Jan-2011 |
tijl |
Fix types of some values in machine/_limits.h.
On some architectures UCHAR_MAX and USHRT_MAX had type unsigned int.
However, lacking integer suffixes for types smaller than int, their type
should correspond to that of an object of type unsigned char (or short)
when used in an expression with objects of type int. In that case unsigned
char (short) are promoted to int (i.e. signed) so the type of UCHAR_MAX and
USHRT_MAX should also be int.
Where MIN/MAX constants implicitly have the correct type the suffix has
been removed.
While here, correct some comments.
Reviewed by: bde
Approved by: kib (mentor)
|
| 217128 |
07-Jan-2011 |
tijl |
Remove unused support for 64 bit long on 32 bit architectures.
It was used mainly to discover and fix some 64-bit portability problems
before 64-bit arches were widely available.
Discussed with: bde
Approved by: kib (mentor)
|
| 217097 |
07-Jan-2011 |
kib |
Add AT_STACKPROT elf aux vector. Will be used to inform rtld about the
initial stack protection set by the kernel image activator.
|
| 216972 |
04-Jan-2011 |
jmallett |
Correct an 8-year-old typo which reliably leads to typo after typo today:
The macros here for generating coprocessor 0 accessors are named like:
MIPS_RDRW32_COP0
That macro would produce mips_rd_<register>() and mips_wr_<register>()
inlines to access the specified register by name from C. The problem is that
the R and the W were swapped in the macros originally; it was meant to be named
RDWR because it generated mips_rd_* and mips_wr_* functions, but was instead
spelled RDRW, which nobody should be expected to get right by anything other
than copy and paste.
It's too many consonants in a row to keep straight anyway, so just prefer e.g.:
MIPS_RW32_COP0
While here, add a missing #undef.
|
| 216947 |
04-Jan-2011 |
jmallett |
o) Add MIPS_COP_0_EXC_PC accessors to <machine/cpufunc.h>.
o) Make the octeon_wdog driver work on multi-CPU systems and to also print more
information on NMI that may aid debugging. Simplify and clean up internal
API and structure.
|
| 216315 |
09-Dec-2010 |
jchandra |
UMA_MD_SMALL_ALLOC for mips.
Implement uma_small_alloc() and uma_small_free() for mips that allocates
pages from direct mapped memory. Uses the same mechanism as the page table
page allocator, so that we allocate from KSEG0 in 32 bit, and from XKPHYS
on 64 bit.
Reviewed by: alc, jmallett
|
| 216157 |
03-Dec-2010 |
jchandra |
1. Fix off by one errors in calls to MIPS_DIRECT_MAPPABLE, reported by alc@
2. Remove unnecessary #defines from vmparam.h
Submitted by: alc (2)
Reviewed by: alc (1)
|
| 216148 |
03-Dec-2010 |
jchandra |
Fixup for r216141, dump_add_page needs to be non-static now.
Add it to sys/mips/include/md_var.h, make dump_drop_page non-static too
for completeness.
|
| 216143 |
03-Dec-2010 |
brucec |
Revert r216134. This checkin broke platforms where bus_space are macros:
they need to be a single statement, and do { } while (0) doesn't work in this
situation so revert until a solution can be devised.
|
| 216134 |
02-Dec-2010 |
brucec |
Disallow passing in a count of zero bytes to the bus_space(9) functions.
Passing a count of zero on i386 and amd64 for [I386|AMD64]_BUS_SPACE_MEM
causes a crash/hang since the 'loop' instruction decrements the counter
before checking if it's zero.
PR: kern/80980
Discussed with: jhb
|
| 215971 |
28-Nov-2010 |
jmallett |
Set MACHINE_ARCH based on ABI and endianness.
Reviewed by: imp
|
| 215054 |
09-Nov-2010 |
jhb |
- Remove <machine/mutex.h>. Most of the headers were empty, and the
contents of the ones that were not empty were stale and unused.
- Now that <machine/mutex.h> no longer exists, there is no need to allow it
to override various helper macros in <sys/mutex.h>.
- Rename various helper macros for low-level operations on mutexes to live
in the _mtx_* or __mtx_* namespaces. While here, change the names to more
closely match the real API functions they are backing.
- Drop support for including <sys/mutex.h> in assembly source files.
Suggested by: bde (1, 2)
|
| 214903 |
07-Nov-2010 |
gonzo |
- Add minidump support for FreeBSD/mips
|
| 212989 |
22-Sep-2010 |
neel |
Enforce that 'pmap_kenter()' is only used to establish cacheable mappings.
Mappings with other cacheability attributes can be established, if needed,
by using 'pmap_kenter_attr()'.
Suggested by: jchandra, imp
|
| 212777 |
17-Sep-2010 |
neel |
Get rid of the unnecessary redirection of 'is_cacheable_mem()' to
'is_physical_memory()' through a macro.
Implement 'is_cacheable_mem()' directly instead.
|
| 212776 |
17-Sep-2010 |
neel |
Get rid of unused macros.
|
| 212632 |
15-Sep-2010 |
neel |
Make the meaning of the 'mask' argument to 'set_intr_mask(mask)' consistent
with the meaning of IM bits in the status register.
Reviewed by: jmallett, jchandra
|
| 212541 |
13-Sep-2010 |
mav |
Refactor timer management code with priority to one-shot operation mode.
The main goal of this is to generate timer interrupts only when there is
some work to do. When CPU is busy interrupts are generating at full rate
of hz + stathz to fullfill scheduler and timekeeping requirements. But
when CPU is idle, only minimum set of interrupts (down to 8 interrupts per
second per CPU now), needed to handle scheduled callouts is executed.
This allows significantly increase idle CPU sleep time, increasing effect
of static power-saving technologies. Also it should reduce host CPU load
on virtualized systems, when guest system is idle.
There is set of tunables, also available as writable sysctls, allowing to
control wanted event timer subsystem behavior:
kern.eventtimer.timer - allows to choose event timer hardware to use.
On x86 there is up to 4 different kinds of timers. Depending on whether
chosen timer is per-CPU, behavior of other options slightly differs.
kern.eventtimer.periodic - allows to choose periodic and one-shot
operation mode. In periodic mode, current timer hardware taken as the only
source of time for time events. This mode is quite alike to previous kernel
behavior. One-shot mode instead uses currently selected time counter
hardware to schedule all needed events one by one and program timer to
generate interrupt exactly in specified time. Default value depends of
chosen timer capabilities, but one-shot mode is preferred, until other is
forced by user or hardware.
kern.eventtimer.singlemul - in periodic mode specifies how much times
higher timer frequency should be, to not strictly alias hardclock() and
statclock() events. Default values are 2 and 4, but could be reduced to 1
if extra interrupts are unwanted.
kern.eventtimer.idletick - makes each CPU to receive every timer interrupt
independently of whether they busy or not. By default this options is
disabled. If chosen timer is per-CPU and runs in periodic mode, this option
has no effect - all interrupts are generating.
As soon as this patch modifies cpu_idle() on some platforms, I have also
refactored one on x86. Now it makes use of MONITOR/MWAIT instrunctions
(if supported) under high sleep/wakeup rate, as fast alternative to other
methods. It allows SMP scheduler to wake up sleeping CPUs much faster
without using IPI, significantly increasing performance on some highly
task-switching loads.
Tested by: many (on i386, amd64, sparc64 and powerc)
H/W donated by: Gheorghe Ardelean
Sponsored by: iXsystems, Inc.
|
| 212532 |
13-Sep-2010 |
jchandra |
The functions in sys/mips/mips/psraccess.S can be implemented with
mips_rd_status/mips_wr_status. Implement them in mips/include/cpufunc.h,
and remove psraccess.S.
Reviewed by: neel, imp
|
| 211991 |
30-Aug-2010 |
jchandra |
Remove misleading comment in pte.h. MIPS PTE entries are software managed
and does not need atomics.
Submitted by: alc
|
| 211958 |
29-Aug-2010 |
jchandra |
Apply MIPS pmap clean up patch from alc@ (with minor change to KASSERT):
PMAP_DIAGNOSTIC was eliminated from amd64/i386, and, in fact, the
non-MIPS parts of the kernel, several years ago. Any of the interesting
checks were turned into KASSERT()s. Basically, the motivation was that
lots of people run with INVARIANTS but no one runs with DIAGNOSTIC.
panic strings needn't and shouldn't have a terminating newline.
Finally, there is one functional change. The sched_pin() in
pmap_remove_pages() is an artifact of the way we temporarily map page
table pages on i386. (The mappings are processor private. We don't do
a system-wide shootdown.) It isn't needed by MIPS.
Tested by: jchandra
Submitted by: alc
|
| 211862 |
27-Aug-2010 |
jchandra |
Whitespace fixes in mips/include, remove unused 'struct tlb' from locore.h
PR: misc/147471
|
| 211453 |
18-Aug-2010 |
jchandra |
MIPS n64 support - continued...
1. On n64, use XKPHYS to map page table pages instead of KSEG0. Maintain
just one freepages list on n64.
The changes are mainly to introduce MIPS_PHYS_TO_DIRECT(pa),
MIPS_DIRECT_TO_PHYS(), which will use KSEG0 in 32 bit compilation
and XKPHYS in 64 bit compilation.
2. Change macro based PMAP_LMEM_MAP1(), PMAP_LMEM_MAP2(), PMAP_LMEM_UNMAP()
to inline functions.
3. Introduce MIPS_DIRECT_MAPPABLE(pa), which will further reduce the cases
in which we will need to have a special case for 64 bit compilation.
4. Update CP0 hazard definitions for CPU_RMI - the cpu does not need any
nops
Reviewed by: neel
|
| 211412 |
17-Aug-2010 |
kib |
Supply some useful information to the started image using ELF aux vectors.
In particular, provide pagesize and pagesizes array, the canary value
for SSP use, number of host CPUs and osreldate.
Tested by: marius (sparc64)
MFC after: 1 month
|
| 211280 |
13-Aug-2010 |
jchandra |
Rename TARGET_XLR_XLS to CPU_RMI to match other CPU_xxx definitions.
use CPU_RMI all XLR configurations. Update ident string for N32 and
N64 kernels.
|
| 211217 |
12-Aug-2010 |
jchandra |
Implement pmap changes suggested by alc@:
1. Move dirty bit emulation code that is duplicted for kernel and user
in trap.c to a function pmap_emulate_modified() in pmap.c.
2. While doing dirty bit emulation, it is not necessary to update the
TLB entry on all CPUs using smp_rendezvous(), we can just update the
TLB entry on the current CPU, and let the other CPUs update their TLB
entry lazily if they get an exception.
Reviewed by: alc, neel
|
| 211197 |
11-Aug-2010 |
jhb |
Update various places that store or manipulate CPU masks to use cpumask_t
instead of int or u_int. Since cpumask_t is currently u_int on all
platforms this should just be a cosmetic change.
|
| 211159 |
11-Aug-2010 |
neel |
Add parentheses around the argument 'x' used in the __bswapXX(x) macros. Revert
r211130 in favor of this more general fix.
This fixes a compilation error for mips 64-bit little endian build.
libexec/rtld-elf/mips/reloc.c:196: warning: right shift count >= width of type
Suggested by: stefanf, jchandra, bde
|
| 210986 |
07-Aug-2010 |
neel |
- Consolidate the the cache coherence attribute definitions in a single place.
Adapted from Juli's changes to pte.h in the octeon branch:
http://svn.freebsd.org/viewvc/base/user/jmallett/octeon/sys/mips/include/pte.h
- Set the KX and UX bits in the status register for n64 kernels.
Reviewed by: jmallett
|
| 210939 |
06-Aug-2010 |
jhb |
Add a new ipi_cpu() function to the MI IPI API that can be used to send an
IPI to a specific CPU by its cpuid. Replace calls to ipi_selected() that
constructed a mask for a single CPU with calls to ipi_cpu() instead. This
will matter more in the future when we transition from cpumask_t to
cpuset_t for CPU masks in which case building a CPU mask is more expensive.
Submitted by: peter, sbruno
Reviewed by: rookie
Obtained from: Yahoo! (x86)
MFC after: 1 month
|
| 210914 |
06-Aug-2010 |
jchandra |
Fix the issue reported by alc:
pmap_page_wired_mappings() counts the number of pv entries for the
specified page that have the pv entry wired flag set to TRUE.
pmap_enter() correctly initializes this flag. However,
pmap_change_wiring() doesn't update the corresponding pv entry flag,
only the PTE. So, the count returned by pmap_page_wired_mappings()
will sometimes be wrong.
In the short term, the best fix would be to eliminate the pv entry
flag and use only the PTE. That flag is wasting non-trivial memory.
Remove pv_wired flag, and use PTE flag to count the wired mappings.
Reviewed by: alc
|
| 210846 |
04-Aug-2010 |
jchandra |
Add 3 level page tables for MIPS in n64.
- 32 bit compilation will still use old 2 level page tables
- re-arrange pmap code so that adding another level is easier
- pmap code for 3 level page tables for n64
- update TLB handler to traverse 3 levels in n64
Reviewed by: jmallett
|
| 210627 |
29-Jul-2010 |
jchandra |
Prepare for 3 level page tables for MIPS.
- Move page table second level shift and mask to param.h
- rename SEGOFSET to SEGMASK
- fix values for 64 bit maximum kernel and user addresses.
|
| 210606 |
29-Jul-2010 |
jchandra |
Update MIPS _stdint.h for 64 bit. Initial 64 bit changes for profile.h.
|
| 210605 |
29-Jul-2010 |
jchandra |
Fix RQB_FFS for 64 bit, we need to use ffsl() for 64bit.
Use 'ifdef __mips_n64' instead of 'if defined' to be consistant with other
usage.
|
| 210550 |
27-Jul-2010 |
jhb |
Very rough first cut at NUMA support for the physical page allocator. For
now it uses a very dumb first-touch allocation policy. This will change in
the future.
- Each architecture indicates the maximum number of supported memory domains
via a new VM_NDOMAIN parameter in <machine/vmparam.h>.
- Each cpu now has a PCPU_GET(domain) member to indicate the memory domain
a CPU belongs to. Domain values are dense and numbered from 0.
- When a platform supports multiple domains, the default freelist
(VM_FREELIST_DEFAULT) is split up into N freelists, one for each domain.
The MD code is required to populate an array of mem_affinity structures.
Each entry in the array defines a range of memory (start and end) and a
domain for the range. Multiple entries may be present for a single
domain. The list is terminated by an entry where all fields are zero.
This array of structures is used to split up phys_avail[] regions that
fall in VM_FREELIST_DEFAULT into per-domain freelists.
- Each memory domain has a separate lookup-array of freelists that is
used when fulfulling a physical memory allocation. Right now the
per-domain freelists are listed in a round-robin order for each domain.
In the future a table such as the ACPI SLIT table may be used to order
the per-domain lookup lists based on the penalty for each memory domain
relative to a specific domain. The lookup lists may be examined via a
new vm.phys.lookup_lists sysctl.
- The first-touch policy is implemented by using PCPU_GET(domain) to
pick a lookup list when allocating memory.
Reviewed by: alc
|
| 210460 |
25-Jul-2010 |
imp |
Get N64 building by defining VM_FREELIST_DIRECT to be
VM_FREELIST_DEFAULT. I believe this is correct, since KX is set in
n64, and thus all RAM can be direct mapped.
|
| 210403 |
23-Jul-2010 |
mav |
Update MIPS timer code (except RMI) to utilize new MI event timer
infrastructure.
Reviewed by: neel
|
| 210327 |
21-Jul-2010 |
jchandra |
Redo the page table page allocation on MIPS, as suggested by
alc@.
The UMA zone based allocation is replaced by a scheme that creates
a new free page list for the KSEG0 region, and a new function
in sys/vm that allocates pages from a specific free page list.
This also fixes a race condition introduced by the UMA based page table
page allocation code. Dropping the page queue and pmap locks before
the call to uma_zfree, and re-acquiring them afterwards will introduce
a race condtion(noted by alc@).
The changes are :
- Revert the earlier changes in MIPS pmap.c that added UMA zone for
page table pages.
- Add a new freelist VM_FREELIST_HIGHMEM to MIPS vmparam.h for memory that
is not directly mapped (in 32bit kernel). Normal page allocations will first
try the HIGHMEM freelist and then the default(direct mapped) freelist.
- Add a new function 'vm_page_t vm_page_alloc_freelist(int flind, int
order, int req)' to vm/vm_page.c to allocate a page from a specified
freelist. The MIPS page table pages will be allocated using this function
from the freelist containing direct mapped pages.
- Move the page initialization code from vm_phys_alloc_contig() to a
new function vm_page_alloc_init(), and use this function to initialize
pages in vm_page_alloc_freelist() too.
- Split the function vm_phys_alloc_pages(int pool, int order) to create
vm_phys_alloc_freelist_pages(int flind, int pool, int order), and use
this function from both vm_page_alloc_freelist() and vm_phys_alloc_pages().
Reviewed by: alc
|
| 210311 |
20-Jul-2010 |
jmallett |
Update the port of FreeBSD to Cavium Octeon to use the Cavium Simple Executive
library:
o) Increase inline unit / large function growth limits for MIPS to accommodate
the needs of the Simple Executive, which uses a shocking amount of inlining.
o) Remove TARGET_OCTEON and use CPU_CNMIPS to do things required by cnMIPS and
the Octeon SoC.
o) Add OCTEON_VENDOR_LANNER to use Lanner's allocation of vendor-specific
board numbers, specifically to support the MR320.
o) Add OCTEON_BOARD_CAPK_0100ND to hard-wire configuration for the CAPK-0100nd,
which improperly uses an evaluation board's board number and breaks board
detection at runtime. This board is sold by Portwell as the CAM-0100.
o) Add support for the RTC available on some Octeon boards.
o) Add support for the Octeon PCI bus. Note that rman_[sg]et_virtual for IO
ports can not work unless building for n64.
o) Clean up the CompactFlash driver to use Simple Executive macros and
structures where possible (it would be advisable to use the Simple Executive
API to set the PIO mode, too, but that is not done presently.) Also use
structures from FreeBSD's ATA layer rather than structures copied from
Linux.
o) Print available Octeon SoC features on boot.
o) Add support for the Octeon timecounter.
o) Use the Simple Executive's routines rather than local copies for doing reads
and writes to 64-bit addresses and use its macros for various device
addresses rather than using local copies.
o) Rename octeon_board_real to octeon_is_simulation to reduce differences with
Cavium-provided code originally written for Linux. Also make it use the
same simplified test that the Simple Executive and Linux both use rather
than our complex one.
o) Add support for the Octeon CIU, which is the main interrupt unit, as a bus
to use normal interrupt allocation and setup routines.
o) Use the Simple Executive's bootmem facility to allocate physical memory for
the kernel, rather than assuming we know which addresses we can steal.
NB: This may reduce the amount of RAM the kernel reports you as having if
you are leaving large temporary allocations made by U-Boot allocated
when starting FreeBSD.
o) Add a port of the Cavium-provided Ethernet driver for Linux. This changes
Ethernet interface naming from rgmxN to octeN. The new driver has vast
improvements over the old one, both in performance and functionality, but
does still have some features which have not been ported entirely and there
may be unimplemented code that can be hit in everyday use. I will make
every effort to correct those as they are reported.
o) Support loading the kernel on non-contiguous cores.
o) Add very conservative support for harvesting randomness from the Octeon
random number device.
o) Turn SMP on by default.
o) Clean up the style of the Octeon kernel configurations a little and make
them compile with -march=octeon.
o) Add support for the Lanner MR320 and the CAPK-0100nd to the Simple
Executive.
o) Modify the Simple Executive to build on FreeBSD and to build without
executive-config.h or cvmx-config.h. In the future we may want to
revert part of these changes and supply executive-config.h and
cvmx-config.h and access to the options contained in those files via
kernel configuration files.
o) Modify the Simple Executive USB routines to support getting and setting
of the USB PID.
|
| 210161 |
16-Jul-2010 |
imp |
Move common macros into asm.h. Replace MIPS_CPU_NOP_DELAY with
HAZARD_DELAY. Move HAZARD_DELAY and ITLBNOPFIX into asm.h, for
possible later optimization...
Reviewed by: jmallet, jchandra
|
| 210159 |
16-Jul-2010 |
imp |
This file appears not to be used.
|
| 210158 |
16-Jul-2010 |
imp |
Use #define for get_cyclecount rather than inline function.
mips_rd_count() isn't defined in userland, and cpu.h is included there
in alias_scpt.h (maybe they don't need it in the first place).
|
| 210142 |
15-Jul-2010 |
imp |
Better description of this file
|
| 210105 |
15-Jul-2010 |
imp |
Move TLB definitions to tlb.h
|
| 210104 |
15-Jul-2010 |
imp |
This file has been unused for a while now...
|
| 210100 |
15-Jul-2010 |
imp |
Remove unused stuff from cpu.h.
Move inappropriate stuff in cpu.h elsewhere:
{s,g}et_intr_mask -> md_var.h
num_tlbentries -> tlb.h
Remove #define clockframe trapframe and fix clock, which was the only place
this was used.
All the rest of this stuff was unused.
# we're not quite minimal yet, since we duplicate a few status register things
# here...
Inspired by: bde@
|
| 210099 |
15-Jul-2010 |
imp |
We don't need sys/cdefs.h for __CONCAT here.
|
| 210041 |
14-Jul-2010 |
imp |
Use cpuregs.h spellings over the cpu.h spellings.
|
| 210039 |
14-Jul-2010 |
imp |
Remove the unused part of cpu.h now that the rest of the tree has been
transitioned to use cpuregs.h spellings. Now we're only 4x too big,
according to the bde-ometer.
|
| 210029 |
13-Jul-2010 |
imp |
union cpuprid is also unused now
|
| 210028 |
13-Jul-2010 |
imp |
Add INFO config register from mips32/64 land
|
| 210009 |
13-Jul-2010 |
imp |
Define break value for ddb.
Use int32/intptr casts for exception vector names.
Define MIPS_SR_INT_MASK again
Change MIPS_XKPHYS_CCA_* to MIPS_CCA_* since we can use them in many contexts
Minor gratuitous whitespace churn
|
| 209996 |
13-Jul-2010 |
imp |
cpu_id and fpu_id are unused, except to be set early in the boot code.
The problem with setting it there is that the last CPU to come up
wins, it seems. This also removes one more ifdef in locore.S, a noble
goal too. Since they are unused, and pollute cpu.h, remove them.
Submitted by: bde.h (cpu.h pollution)
Approved in theory by: jmallet@
|
| 209994 |
13-Jul-2010 |
imp |
Remove obsolete define "COPY_SIGCODE". This is unused in FreeBSD.
Submitted by: bde@
|
| 209929 |
12-Jul-2010 |
jchandra |
Merge jmallett@'s n64 work into HEAD
64 bit TLB definitions in pte.h
Reviewed by: imp
Obtained from: jmallett (http://svn.freebsd.org/base/user/jmallett/octeon)
|
| 209928 |
12-Jul-2010 |
jchandra |
Move KSEG address definitions from cpu.h to cpuregs.h with the other
definitions, add some XKPHYS related definitions for n64.
Reviewed by: imp
|
| 209811 |
08-Jul-2010 |
jchandra |
Use 64 bit type for rqb_word_t in n64 kernel.
Reviewed by: imp
Approved by: rrs
|
| 209805 |
08-Jul-2010 |
jchandra |
Merge jmallett@'s n64 work into HEAD - changeset 8
Updated PTE/PDE macros from http://svn.freebsd.org/base/user/jmallett/octeon
Introduce pmap_segshift() macro, use pmap_segmap() in place of pmap_pde, and
remove pmap_pde().
Approved by: rrs (mentor)
Obtained from: jmallett@
|
| 209645 |
02-Jul-2010 |
jchandra |
Remove save/restore of PageMask in tlb.c functions introduced in r209243.
If we save/restore the PageMask, the value set by the bootloader will
persist, and will cause problems later in TLB exception handler.
This caused a crash in AR71xx boards.
Also fixes the EntryHi mask in pte.h
Reported by: Luiz Otavio O Souza <lists.br@gmail.com>
Tested by: Luiz Otavio O Souza <lists.br@gmail.com>
Approved by: rrs (mentor)
|
| 209500 |
24-Jun-2010 |
jchandra |
Merge jmallett@'s n64 work into HEAD - changeset 7
Initial support for n32 and n64 ABIs from
http://svn.freebsd.org/base/user/jmallett/octeon
Changes are:
- syscall, exception and trap support for n32/n64 ABIs
- 64-bit address space defines
- _jmp_buf for n32/n64
- casts between registers and ptr/int updated to work on n32/n64
Approved by: rrs(mentor), jmallett
|
| 209482 |
23-Jun-2010 |
jchandra |
Merge jmallett@'s n64 work into HEAD - changeset 6
PTE flag cleanup from http://svn.freebsd.org/base/user/jmallett/octeon
- Rename PTE_xx flags to match their MIPS names
- Use the new pte_set/test/clear macros uniformly, instead of a mixture
of mips_pg_xxx(), pmap_pte_x() macros and direct access.
- Remove unused macros and defines from pte.h and pmap.c
Discussed on freebsd-mips@
Approved by: rrs(mentor), jmallett
|
| 209314 |
18-Jun-2010 |
jchandra |
Merge jmallett@'s n64 work into HEAD - changeset 5
Remove unnecessary locking and sched_pin() call while creating a temporary
mapping.
Changes from http://svn.freebsd.org/base/user/jmallett/octeon
Approved by: rrs (mentor), jmallett
|
| 209243 |
17-Jun-2010 |
jchandra |
Merge jmallett@'s n64 work into HEAD - changeset 4
Re-write tlb operations in C with a simpler API.
Update callers to use the new API.
Changes from http://svn.freebsd.org/base/user/jmallett/octeon
Approved by: rrs(mentor), jmallett
|
| 208533 |
25-May-2010 |
neel |
Get rid of empty and unused KSEG0TEXT macros.
|
| 208249 |
18-May-2010 |
rrs |
Adds JC's cleanup patches that fix it so
we call an platform dependant topo function as
well as clean up all the XLR specific ifdefs around
smp platform init.
Obtained from: JC
|
| 208165 |
16-May-2010 |
rrs |
This pushes all of JC's patches that I have in place. I
am now able to run 32 cores ok.. but I still will hang
on buildworld with a NFS problem. I suspect I am missing
a patch for the netlogic rge driver.
JC check and see if I am missing anything except your
core-mask changes
Obtained from: JC
|
| 207692 |
06-May-2010 |
alc |
Eliminate dead code.
|
| 207410 |
30-Apr-2010 |
kmacy |
On Alan's advice, rather than do a wholesale conversion on a single
architecture from page queue lock to a hashed array of page locks
(based on a patch by Jeff Roberson), I've implemented page lock
support in the MI code and have only moved vm_page's hold_count
out from under page queue mutex to page lock. This changes
pmap_extract_and_hold on all pmaps.
Supported by: Bitgravity Inc.
Discussed with: alc, jeffr, and kib
|
| 207269 |
27-Apr-2010 |
kib |
Style: use #define<TAB> instead of #define<SPACE>.
Noted by: bde, pluknet gmail com
MFC after: 11 days
|
| 207152 |
24-Apr-2010 |
kib |
Move the constants specifying the size of struct kinfo_proc into
machine-specific header files. Add KINFO_PROC32_SIZE for struct
kinfo_proc32 for architectures providing COMPAT_FREEBSD32. Add
CTASSERT for the size of struct kinfo_proc32.
Submitted by: pluknet
Reviewed by: imp, jhb, nwhitehorn
MFC after: 2 weeks
|
| 207139 |
24-Apr-2010 |
jmallett |
Most MIPS systems have a comparatively-sparse physical memory layout. Switch
to using the sparse physseg layout in the VM system.
|
| 206834 |
19-Apr-2010 |
jmallett |
o) Eliminate the "stand" frame and its use. Use CALLFRAME_* everywhere.
o) Use <machine/asm.h> macros for register-width, etc., rather than doing it
by hand in a few more assembly files.
o) Reduce diffs between various bits of TLB refill code in exception.S and
between interrupt processing code.
o) Use PTR_* to operate on registers that are pointers (e.g. sp).
o) Add and use a macro, CLEAR_PTE_SWBITS rather than using the
mysteriously-named WIRED_SHIFT to select bits to truncate when loading PTEs.
o) Don't doubly disable interrupts by moving zero to the status register,
especially since that has the nasty side-effect of taking us out of 64-bit
mode.
o) Use CLEAR_STATUS to disable interrupts the first time.
o) Keep SR_PX set as well as SR_[KSU]X when doing exception processing. This
is the bit that determines whether 64-bit operations are allowed.
o) Don't enable interrupts until configure_final(), like most other ports.
|
| 206829 |
19-Apr-2010 |
jmallett |
o) Fix XKPHYS physical address extraction. Also define cache coherency
attributes for XKPHYS.
o) Make coprocessor 0 accessor function macros for register+selector registers
take the full name so that e.g. (as done in this commit), prid selector 1
can be written through mips_wr_ebase() rather than mips_wr_prid1().
o) Allow for sign extension of 32-bit segment addresses.
o) Remove an unused MIPS-I register number.
|
| 206819 |
18-Apr-2010 |
jmallett |
o) Add a VM find-space option, VMFS_TLB_ALIGNED_SPACE, which searches the
address space for an address as aligned by the new pmap_align_tlb()
function, which is for constraints imposed by the TLB. [1]
o) Add a kmem_alloc_nofault_space() function, which acts like
kmem_alloc_nofault() but allows the caller to specify which find-space
option to use. [1]
o) Use kmem_alloc_nofault_space() with VMFS_TLB_ALIGNED_SPACE to allocate the
kernel stack address on MIPS. [1]
o) Make pmap_align_tlb() on MIPS align addresses so that they do not start on
an odd boundary within the TLB, so that they are suitable for insertion as
wired entries and do not have to share a TLB entry with another mapping,
assuming they are appropriately-sized.
o) Eliminate md_realstack now that the kstack will be appropriately-aligned on
MIPS.
o) Increase the number of guard pages to 2 so that we retain the proper
alignment of the kstack address.
Reviewed by: [1] alc
X-MFC-after: Making sure alc has not come up with a better interface.
|
| 206749 |
17-Apr-2010 |
jmallett |
o) Make pcb_onfault a pointer rather than an obscure integer value.
o) Mask off PAGE_MASK bits in pmap_update_page, etc., rather than modifying the
badvaddr in trapframe. Some nearby interfaces already did this.
o) Make PTEs "unsigned int" for now, not "unsigned long" -- we are only ready
for them to be 32-bit on 64-bit platforms.
o) Rather than using pmap_segmap and calculating the offset into the page table
by hand in trap.c, use pmap_pte().
o) Remove unused quad_syscall variable in trap.c.
o) Log things for illegal instructions like we do for bad page faults.
o) Various cast cleanups related to how to print registers.
o) When logging page faults, show the page table information not just for the
program counter, but for the fault address.
o) Modify support.S to use ABI-neutral macros for operating on pointers.
o) Consistently use CALLFRAME_SIZ rather than STAND_FRAME_SIZE, etc.
o) Remove unused insque/remque functions.
o) Remove some coprocessor 0 accessor functions implemented in assembly that
are unused and have inline assembly counterparts.
|
| 206746 |
17-Apr-2010 |
jmallett |
o) Add NPDEPG, like NPTEPG but for PDEs.
o) Remove NBPG, PGOFSET and PGSHIFT. Use the standard names.
o) Remove some unused macros and move things from param.h to vmparam.h that
belong in the latter. (Actually, all of the kernel segment values, virtual
addresses, etc., belong in one place, but this is a step in the right
direction.)
|
| 206717 |
17-Apr-2010 |
jmallett |
o) Use inline functions to access coprocessor 0 registers rather than external
ones implemented using assembly.
o) Use TRAPF_USERMODE() consistently rather than USERMODE(). Eliminate
<machine/psl.h> as a result.
o) Use intr_*() rather than *intr(), consistently.
o) Use register_t instead of u_int in some trap code.
o) Merge some more endian-related macros to machine/asm.h from NetBSD.
o) Add PTR_LI macro, which loads an address with the correct sign-extension for
a pointer.
o) Restore interrupts when bailing out due to an excessive IRQ in
nexus_setup_intr().
o) Remove unused functions from psraccess.S.
o) Enter temporary virtual entries for large memory access into the page tables
rather than simply hoping they stay resident in the TLB and we don't need to
do a refill for them.
o) Abstract out large memory mapping setup/teardown using some macros.
o) Do mips_dcache_wbinv_range() when using temporary virtual addresses just
like we do when we can use the direct map.
|
| 206716 |
17-Apr-2010 |
jmallett |
o) Remove code related to VM_ALLOC_WIRED_TLB_PG_POOL, VM_KERNEL_ALLOC_OFFSET
and floating pages. They are unused and unsupported.
|
| 206715 |
16-Apr-2010 |
jmallett |
Adjust limits and formats for ABIs with 64-bit longs.
|
| 206714 |
16-Apr-2010 |
jmallett |
o) Use the direct map where possible for uiomove_fromphys, based on code from
sparc64.
o) Use uiomove_fromphys rather than the broken fpage mechanism for /dev/mem.
o) Update sf_buf allocator to not share buffers and to do a pmap_qremove when
done with an sf_buf so as to better track valid mappings.
|
| 206713 |
16-Apr-2010 |
jmallett |
o) Fix the intr_* functions to not spam the whole status register, just the IE
bit.
o) Remove some unused inlines.
o) Generate CP0 access functions for 64-bit TLB registers when building for
n64.
o) Add an inline function version of the COP0_SYNC macro.
|
| 206695 |
16-Apr-2010 |
jmallett |
Remove some unused header files.
|
| 206404 |
08-Apr-2010 |
imp |
Add BUS_SPACE_UNRESTRICTED and define it to be ~0, just like all the
other platforms.
|
| 205675 |
26-Mar-2010 |
neel |
Replace sb_store64()/sb_load64() with mips3_sd()/mips3_ld() respectively.
Obtained from NetBSD.
Suggested by: jmallett@
|
| 205364 |
20-Mar-2010 |
neel |
Sibyte provides a 64-bit read-only counter that counts at half the processor
frequency. This counter can be accessed coherently from both cores.
Use this as the preferred timecounter for the SWARM kernels.
The CP0 COUNT register is unusable as the timecounter on SMP platforms because
the COUNT registers on different CPUs are not guaranteed to be in sync.
|
| 205360 |
20-Mar-2010 |
neel |
This change enables use of physical memory that is beyond the direct
mapped kseg0 region.
The basic idea is to use KVA from the kseg2 region for mapping page
table pages that lie beyond the direct mapped region.
The TLB miss handler can now recursively fault into the TLB invalid
handler if it dereferences a kseg2 page table page address that is not
in the TLB.
Tested by: JC (c.jayachandran@gmail.com)
|
| 205072 |
12-Mar-2010 |
neel |
- Enable kernel stack guard page.
- Unmap the unused kernel stack page that we cannot use because it is
not aligned on a (PAGE_SIZE * 2) boundary.
|
| 205064 |
12-Mar-2010 |
neel |
Make the ddb command "show tlb" SMP friendly.
It now accepts an argument to dump out the tlb of a particular cpu.
|
| 204997 |
11-Mar-2010 |
neel |
Stash the context of the running thread at the time an IPI_STOP is received
in 'stoppcbs[]'. We use the 'stoppcbs[]' context to generate the backtrace
of such stopped threads.
|
| 204788 |
06-Mar-2010 |
jmallett |
o) Consistently use MIPS_KSEGn_TO_PHYS instead of MIPS_{,UN}CACHED_TO_PHYS etc.
Get rid of the macros that spell KSEG0 CACHED and KSEG1 UNCACHED.
o) Get rid of some nearby duplicated and unused macros.
Reviewed by: imp
|
| 204690 |
04-Mar-2010 |
neel |
Remove some unused cruft.
|
| 204689 |
04-Mar-2010 |
neel |
Add support for CPUs with cache coherent DMA. The two main changes are:
- We don't need to fall back to uncacheable memory to satisfy BUS_DMA_COHERENT
requests on these CPUs.
- The bus_dmamap_sync() is a no-op for these CPUs.
A side-effect of this change is rename DMAMAP_COHERENT flag to
DMAMAP_UNCACHEABLE. This conveys the purpose of the flag more accurately.
Reviewed by: gonzo, imp
|
| 204646 |
03-Mar-2010 |
joel |
The NetBSD Foundation has granted permission to remove clause 3 and 4 from
the software.
Obtained from: NetBSD
|
| 204635 |
03-Mar-2010 |
gnn |
Add support for hwpmc(4) on the MIPS 24K, 32 bit, embedded processor.
Add macros for properly accessing coprocessor 0 registers that
support performance counters.
Reviewed by: jkoshy rpaulo fabien imp
MFC after: 1 month
|
| 204577 |
02-Mar-2010 |
rrs |
- Move rmi_pci_bus_space to header and avoid extern
- remove unused and commented code (MIPS_BUS_SPACE_PCI, pic_usb_ack)
- use rmi_pci_bus_space for USB too (needs byteswap)
- uncomment xls_ehci.c in files.xlr
- changes to xls_ehci.c - updated with dev/usb/controller/ehci_*.c as
Obtained from: JC - c.jayachandran@gmail.com
|
| 204557 |
02-Mar-2010 |
imp |
Update macros for multiple ABI support from NetBSD.
Also update SZREG define in ucontext
|
| 204130 |
20-Feb-2010 |
rrs |
Some fixes to the current RMI interrupt handling, changes in this patch are:
- (cleanup) remove rmi specific 'struct mips_intrhand' - this is no
longer needed since 'struct intr_event' have all the required hooks
- add xlr_cpu_establish_hardintr, which has args for pre/post ithread
and filter hooks, so that the PCI code can add the PCI controller
interrupt ack code here
- make 'cpu_establish_hardintr' use the above function.
- (fix) change type of eirr/eimr from register_t to uint64_t. These
have to be 64bit otherwise we cannot handle interrupts from 32.
- (fix) use eimr to mask eirr before checking interrupts, so that we
will not handle masked interrupts.
Obtained from: C. Jayachandran - c.jayachandran@gmail.com
|
| 203697 |
09-Feb-2010 |
neel |
SMP support for the mips port.
The platform that supports SMP currently is a SWARM with a dual-core Sibyte
processor. The kernel config file to use is SWARM_SMP.
Reviewed by: imp, rrs
|
| 203415 |
03-Feb-2010 |
neel |
Reduce the size of the array used to store the TLB mappings for the kernel
stack from 3 to 2.
We only map in 2 pages for the kernel stack.
Approved by: imp (mentor)
|
| 203180 |
30-Jan-2010 |
neel |
Provide access to pcpu structures for SMP kernels.
The basic idea is to use a the same virtual address as a window onto
distinct physical memory locations - one per processor. The physical
address that you access through this mapping depends on which cpu you
are currently executing on. We can now use the same virtual address
on any processor to access its per-cpu area.
The details are:
- The virtual address for 'struct pcpu *pcpup' is obtained by
stealing 2 pages worth of KVA in pmap_bootstrap().
- The mapping from the constant virtual address to a distinct
physical page is done in cpu_pcpu_init() through a wired TLB entry.
- A side-effect of this is that we reserve 2 pages worth of memory
for the pcpu but in reality it needs much less than that. The unused
memory is now used as the boot stack for the BSP and APs.
Remove SMP-specific bits from locore.S. The plan is to use a separate
mpboot.S for AP bootstrap.
Discussed on: freebsd-mips
Approved by: imp (mentor)
|
| 202996 |
26-Jan-2010 |
neel |
Fix a problem seen when a new process was returning to userland
through fork_trampoline.
This was caused because we were clearing the SR_INT_IE and setting
SR_EXL bits of the status register at the same time. This meant
that if an interrupt happened while this MTC0 was making its way
through the pipeline the exception processing would see the
status register with SR_EXL bit set. This in turn would mean that
the COP_0_EXC_PC would not be updated so the return from exception
would be to an incorrect address.
It is easy to verify this fix by a program that forks in a loop
and the child just exits:
while (1) {
pid_t pid = vfork();
if (pid == 0)
_exit(0);
if (pid != -1)
waitpid(pid, NULL, 0);
}
Also remove two instances where we set SR_EXL bit gratuitously in exception.S.
Approved by: imp (mentor)
|
| 202909 |
24-Jan-2010 |
gonzo |
- Introduce kernel_kseg0_end variable that marks first address in KSEG0
available for use. All data below this address considered to be used
by kernel. Along with kernel own data it might be symbol tables
prepeared by trampoline code, boot loader service data passed for
further analysis by kernel, etc... By default kernel_kseg0_end points
to the end of loaded kernel.
- Introduce mips_postboot_fixup function. It checks for symbol information
copied by ELF trampoline and passes it to KDB
|
| 202908 |
24-Jan-2010 |
gonzo |
- Copy symbol-related tables (.symtab and .strtab) to the end of
relocated kernel. We use magic number to signal kernel that
symbol data is present.
|
| 202864 |
23-Jan-2010 |
neel |
Remove Sibyte specific code from locore.S that sets the k0seg coherency.
Move it to platform_start() instead.
Approved by: imp (mentor)
|
| 202830 |
22-Jan-2010 |
imp |
Create a method of last resort for rebooting the mips processor: jump
to the reset vector. This works for many SoCs where other reset
hardware is either missing or unknown.
|
| 202698 |
20-Jan-2010 |
neel |
Get rid of unused function MipsTLBInvalidException().
Approved by: imp (mentor)
|
| 202175 |
12-Jan-2010 |
imp |
Set the svn:eol-style = native and svn:mime-type = text/plain
properties on all files in this tree.
Submitted by: rpaulo@
|
| 202173 |
12-Jan-2010 |
imp |
Place proper svn:keywords tag on all these files. They were created
somehow without them on projects/mips, and that mistake was propigated
over to head.
Submitted by: rpaulo@
|
| 202105 |
11-Jan-2010 |
imp |
Using svn cp rather than cp to copy these files over had the benefit
of preserving their history. It had the problem that it also copied
over mergeinfo data. Since we're retiring the projects/mips branch,
I'm removing the svn:mergeinfo property from them all.
Submitted by: jhb
|
| 202044 |
10-Jan-2010 |
imp |
Fix mis-merge from projects/mips... the diff didn't apply correctly
and I didn't notice until after the commit.
|
| 202031 |
10-Jan-2010 |
imp |
Merge from projects/mips to head by hand:
r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines
Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the
BSP. Provide a missing prototype.
r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines
Get the sense of this right. We use uintpr_t for bus_addr_t when
we're building everything except octeon && 32-bit. As note before, we
need a clearner way, but at least now the hack is right.
r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines
Add in Cavium's CID. Report what the unknown CID is.
r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines
Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON.
Spell ld script name right.
r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines
Another kludge for 64-bit bus_addr_t with 32-bit pointers...
r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines
- Add cpu_init_interrupts function that is supposed to
prepeare stuff required for spinning out interrupts later
- Add API for managing intrcnt/intrnames arrays
- Some minor style(9) fixes
r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines
For XLR adds extern for its bus space routines
r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines
With this commit our friend RMI will now compile. I have
not tested it and the chances of it running yet are about
ZERO.. but it will now compile. The hard part now begins,
making it run ;-)
r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines
Add some newer MIPS CO cores.
r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines
db_expr_t is really closer to a register_t.
Submitted by: bde@
r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines
- Remove bunch of declared but not defined cach-related variables
- Add mips_picache_linesize and mips_pdcache_linesize variables
r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines
Get rid of the hardcoded constants to define cacheable memory:
SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE
Instead we now keep a copy of the memory regions enumerated by
platform-specific code and use that to determine whether an address
is cacheable or not.
r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines
- Commit missing part of "bt" fix: store PC register in pcb_context struct
in cpu_switch and use it in stack_trace function later. pcb_regs contains
state of the process stored by exception handler and therefor is not
valid for sleeping processes.
r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines
Undo spamage of last MFC.
r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines
_ALIGN has to return u_long, since pointers don't fit into u_int in
64-bit mips.
r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines
- Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe.
Context info could be obtained from other sources (see below) no only from
td_pcb field
- Do not show a0..a3 values unless they're obtained from the stack. These
are only confirmed values.
- Fix bt command in DDB. Previous implementation used thread's trapframe
structure as a source info for trace unwinding, but this structure
is filled only when exception occurs. Valid register values for sleeping
processes are in pcb_context array. For curthread use pc/sp/ra for current
frame
r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines
- Get rid of label_t. It came from NetBSD and was used only in one place
r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines
Does 4 things:
1) Adds future RMI directories
2) Places intr_machdep.c in specfic files.arch pointing to the generic
intr_machdep.c. This allows us to have an architecture dependant
intr_machdep.c (which we will need for RMI) in the machine specific
directory
3) removes intr_machdep.c from files.mips
4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We
may need to look at finding a better place to put this. But first I want to
get this thing compiling.
r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines
- Move stack tracing function to db_trace.c
- Axe unused extern MipsXXX declarations
- Move all declarations for functions in exceptions.S/swtch.S
from trap.c to respective headers
r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines
- Sync caches properly when dealing with sf_buf
r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines
(u_int) is the wrong type here. Use unsigned long instead, even
though that's only less wrong...
r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines
Use unsigned long instead of unsigned for the integer casts here. The
former works for both ILP32 and LP64 programming models, while the
latter fails LP64.
r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines
- Make i/d cache size field 32-bit to prevent overflow
Submited by: Neelkanth Natu
r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines
fix prototype for MipsEmulateBranch.
r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines
Better definitions for a few types for n32/n64.
r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines
Fixed aligned macros...
r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines
- Port busdma code from FreeBSD/arm. This is more mature version
that takes into account all limitation to DMA memory (boundaries,
alignment) and implements bounce pages.
- Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf
r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines
Fix atomic_store_64 prototype for 64-bit systems.
r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines
The MCOUNT macro isn't going to work in 64-bit mode. Add a note to
this effect.
r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines
Provide a macro for PTR_ADDU as well. We may need to implement this
differently for N32... Use PTR_ADDU in DO_AST macro.
r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines
Change the addu here to daddu.
addu paranoina prodded by: jmallet@
r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines
addu and subu are special. We need to use daddu and dsubu here to get
proper behavior.
Submitted by: jmallet@
r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines
The SB1 has cohernet memory, so add it.
Also, Maxmem is better as a long.
Submitted by: Neelkanth Natu
r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines
The SB1 needs a special value for the cache field of the pte.
Submitted by: Neelkanth Natu
r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines
compute the areas to save registers in for 64-bit access correctly.
r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines
First cut at 64-bit types. not 100% sure these are all correct for
N32 ABI.
r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines
Trim unreferenced goo. SDRAM likely should be next, but it is still
referenced.
r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines
First cut at atomics for 64-bit machines and SMP machines.
# Note: Cavium provided a port that has atomics similar to these, but
# that does a syncw; sync; atomic; sync; syncw where we just do the classic
# mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why
# the extra is needed. Since my initial target is one core, I'll defer
# investigation until I bring up multiple cores. syncw is an octeon specific
# instruction.
r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines
Bring in cdefs.h from NetBSD to define ABI goo.
Obtained from: NetBSD
r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines
Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA,
ala sgi, and use it in preference to a bare 'la' so that it gets
translated to a 'dla' for the 64-bit pointer ABIs.
r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines
Use uintptr_t rather than unsigned here for 64-bit correctness.
r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines
Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe
this is correct. While registers are 64-bit, n32 is a 32-bit ABI and
lives in a 32-bit world (with explicit 64-bit registers, however).
Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4
+ SZREG' to reflect the actual offset of the structure in question.
r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines
(1) Use uintptr_t in preference to unsigned. The latter isn't right for
64-bit case, while the former is.
(2) include a SB1 specific coherency mapping
Submitted by: Neelkanth Nath (2)
r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines
db_expr_t should be a intptr_t, not an int. These expressions can be
addresses or numbers, and that's a intptr_t if I ever saw one.
r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines
Define COP0_SYNC for SB1 CPU.
Submitted by: Neelkanth Natu
r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines
Switch to ABI agnostic ta0-ta3. Provide defs for this in the right
places. Provide n32/n64 register name defintions. This should have
no effect for the O32 builds that everybody else uses, but should help
make N64 builds possible (lots of other changes are needed for that).
Obtained from: NetBSD (for the regdef.h changes)
r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines
- Add support for handling TLS area address in kernel space.
From the userland point of view get/set operations are
performed using sysarch(2) call.
r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines
- Add guards to ensure that these files are included only once
r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines
- Mark temp variable as "earlyclobber" in assembler inline in
atomic_fetchadd_32. Without it gcc would use it as input
register for v and sometimes generate following code for
function call like atomic_fetchadd_32(&(fp)->f_count, -1):
801238b4: 2402ffff li v0,-1
801238b8: c2230018 ll v1,24(s1)
801238bc: 00431021 addu v0,v0,v1
801238c0: e2220018 sc v0,24(s1)
801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8>
801238c8: 00000000 nop
Which is definitly wrong because if sc fails v0 is set to 0
and previous value of -1 is overriden hence whole operation
turns to bogus
r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines
bye bye. This is no longer referenced, but much code from it will
resurface for a bus-space implementation.
r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines
Cavium-specific goo is no longer necessary here. Of course, I now
have to write a bus space for cavium, but that shouldn't be too hard.
r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines
Move this to a more approrpiate plae.
r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines
Bring this in from the cavium port.
r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines
- Use restoreintr instead of enableint while accessing pcpu in DO_AST
r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines
- Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default
we assume that there is no FPU, because majority of SoC does
not have it.
r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines
- Add type cast for atomic_cmpset_acq_ptr arguments
r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines
- Remove now unused NetBSDism intr.h
r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines
- Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR
macroses thet check if address belongs to KSEG0, KSEG1 or both
of them respectively.
r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines
- Cast argument to proper type in order to avoid warnings like
"shift value is too large for given type"
r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines
- Use naming convention the same as MIPS spec does: eliminate _sel1 sufix
and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1
- Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes)
r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines
- Define accessor functions for CP0 Config(16) register selects 1, 2, 3.
Content of these registers is defined in MIPS spec and can be used
for obtaining info about CPU capabilities.
r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines
- Make mips_bus_space_generic be of type bus_space_tag_t instead of
struct bus_space and update all relevant places.
r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines
Use FreeBSD/arm approach for handling bus space access: space tag is a pointer
to bus_space structure that defines access methods and hence every bus can
define own accessors. Default space is mips_bus_space_generic. It's a simple
interface to physical memory, values are read with regard to host system
byte order.
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| 202030 |
10-Jan-2010 |
imp |
Merge from projects/mips to head by hand:
Merge in rmi's fls64 code...
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| 202029 |
10-Jan-2010 |
imp |
Merge from projects/mips to head by hand:
Copy over new cdefs.h..
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| 202028 |
10-Jan-2010 |
imp |
Remove files that were deleted in the projects/mips branch.
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| 201883 |
09-Jan-2010 |
imp |
Merge r195128 from project/mips to head.
r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines
- Add support for handling TLS area address in kernel space.
From the userland point of view get/set operations are
performed using sysarch(2) call.
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| 199135 |
10-Nov-2009 |
kib |
Extract the code that records syscall results in the frame into MD
function cpu_set_syscall_retval().
Suggested by: marcel
Reviewed by: marcel, davidxu
PowerPC, ARM, ia64 changes: marcel
Sparc64 tested and reviewed by: marius, also sunv reviewed
MIPS tested by: gonzo
MFC after: 1 month
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| 197933 |
10-Oct-2009 |
kib |
Define architectural load bases for PIE binaries. Addresses were selected
by looking at the bases used for non-relocatable executables by gnu ld(1),
and adjusting it slightly.
Discussed with: bz
Reviewed by: kan
Tested by: bz (i386, amd64), bsam (linux)
MFC after: some time
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| 197316 |
18-Sep-2009 |
alc |
Add a new sysctl for reporting all of the supported page sizes.
Reviewed by: jhb
MFC after: 3 weeks
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| 196994 |
08-Sep-2009 |
phk |
Get rid of the _NO_NAMESPACE_POLLUTION kludge by creating an
architecture specific include file containing the _ALIGN*
stuff which <sys/socket.h> needs.
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| 196196 |
13-Aug-2009 |
attilio |
* Completely Remove the option STOP_NMI from the kernel. This option
has proven to have a good effect when entering KDB by using a NMI,
but it completely violates all the good rules about interrupts
disabled while holding a spinlock in other occasions. This can be the
cause of deadlocks on events where a normal IPI_STOP is expected.
* Adds an new IPI called IPI_STOP_HARD on all the supported architectures.
This IPI is responsible for sending a stop message among CPUs using a
privileged channel when disponible. In other cases it just does match a
normal IPI_STOP.
Right now the IPI_STOP_HARD functionality uses a NMI on ia32 and amd64
architectures, while on the other has a normal IPI_STOP effect. It is
responsibility of maintainers to eventually implement an hard stop
when necessary and possible.
* Use the new IPI facility in order to implement a new userend SMP kernel
function called stop_cpus_hard(). That is specular to stop_cpu() but
it does use the privileged channel for the stopping facility.
* Let KDB use the newly introduced function stop_cpus_hard() and leave
stop_cpus() for all the other cases
* Disable interrupts on CPU0 when starting the process of APs suspension.
* Style cleanup and comments adding
This patch should fix the reboot/shutdown deadlocks many users are
constantly reporting on mailing lists.
Please don't forget to update your config file with the STOP_NMI
option removal
Reviewed by: jhb
Tested by: pho, bz, rink
Approved by: re (kib)
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| 195649 |
12-Jul-2009 |
alc |
Add support to the virtual memory system for configuring machine-
dependent memory attributes:
Rename vm_cache_mode_t to vm_memattr_t. The new name reflects the
fact that there are machine-dependent memory attributes that have
nothing to do with controlling the cache's behavior.
Introduce vm_object_set_memattr() for setting the default memory
attributes that will be given to an object's pages.
Introduce and use pmap_page_{get,set}_memattr() for getting and
setting a page's machine-dependent memory attributes. Add full
support for these functions on amd64 and i386 and stubs for them on
the other architectures. The function pmap_page_set_memattr() is also
responsible for any other machine-dependent aspects of changing a
page's memory attributes, such as flushing the cache or updating the
direct map. The uses include kmem_alloc_contig(), vm_page_alloc(),
and the device pager:
kmem_alloc_contig() can now be used to allocate kernel memory with
non-default memory attributes on amd64 and i386.
vm_page_alloc() and the device pager will set the memory attributes
for the real or fictitious page according to the object's default
memory attributes.
Update the various pmap functions on amd64 and i386 that map pages to
incorporate each page's memory attributes in the mapping.
Notes: (1) Inherent to this design are safety features that prevent
the specification of inconsistent memory attributes by different
mappings on amd64 and i386. In addition, the device pager provides a
warning when a device driver creates a fictitious page with memory
attributes that are inconsistent with the real page that the
fictitious page is an alias for. (2) Storing the machine-dependent
memory attributes for amd64 and i386 as a dedicated "int" in "struct
md_page" represents a compromise between space efficiency and the ease
of MFCing these changes to RELENG_7.
In collaboration with: jhb
Approved by: re (kib)
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| 195376 |
05-Jul-2009 |
sam |
Cleanup ALIGNED_POINTER:
o add to platforms where it was missing (arm, i386, powerpc, sparc64, sun4v)
o define as "1" on amd64 and i386 where there is no restriction
o make the type returned consistent with ALIGN
o remove _ALIGNED_POINTER
o make associated comments consistent
Reviewed by: bde, imp, marcel
Approved by: re (kensmith)
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| 195060 |
26-Jun-2009 |
alc |
Correct the #endif comment.
Noticed by: jmallett
Approved by: re (kib)
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| 195033 |
26-Jun-2009 |
alc |
This change is the next step in implementing the cache control functionality
required by video card drivers. Specifically, this change introduces
vm_cache_mode_t with an appropriate VM_CACHE_DEFAULT definition on all
architectures. In addition, this changes adds a vm_cache_mode_t parameter
to kmem_alloc_contig() and vm_phys_alloc_contig(). These will be the
interfaces for allocating mapped kernel memory and physical memory,
respectively, with non-default cache modes.
In collaboration with: jhb
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| 191735 |
02-May-2009 |
alc |
A variety of changes:
Reimplement "kernel_pmap" in the standard way.
Eliminate unused variables. (These are mostly variables that were
discarded by the machine-independent layer after FreeBSD 4.x.)
Properly handle a vm_page_alloc() failure in pmap_init().
Eliminate dead or legacy (FreeBSD 4.x) code.
Eliminate unnecessary page queues locking.
Eliminate some excess white space.
Correct the synchronization of pmap_page_exists_quick().
Tested by: gonzo
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| 191309 |
20-Apr-2009 |
rwatson |
Don't conditionally define CACHE_LINE_SHIFT, as we anticipate sizing
a fair number of static data structures, making this an unlikely
option to try to change without also changing source code. [1]
Change default cache line size on ia64, sparc64, and sun4v to 128
bytes, as this was what rtld-elf was already using on those
platforms. [2]
Suggested by: bde [1], jhb [2]
MFC after: 2 weeks
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| 191278 |
19-Apr-2009 |
rwatson |
Add description and cautionary note regarding CACHE_LINE_SIZE.
MFC after: 2 weeks
Suggested by: alc
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| 191276 |
19-Apr-2009 |
rwatson |
For each architecture, define CACHE_LINE_SHIFT and a derived
CACHE_LINE_SIZE constant. These constants are intended to
over-estimate the cache line size, and be used at compile-time
when a run-time tuning alternative isn't appropriate or
available.
Defaults for all architectures are 64 bytes, except powerpc
where it is 128 bytes (used on G5 systems).
MFC after: 2 weeks
Discussed on: arch@
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| 190515 |
28-Mar-2009 |
bz |
Mark the declaration of bus_space_map 'static' as the implementation is.
Follow one of the two most common indent schemes in this file.
This unbreaks a few mips kernel builds.
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| 189926 |
17-Mar-2009 |
kib |
Add AT_EXECPATH ELF auxinfo entry type. The value's a_ptr is a pointer
to the full path of the image that is being executed.
Increase AT_COUNT.
Remove no longer true comment about types used in Linux ELF binaries,
listed types contain FreeBSD-specific entries.
Reviewed by: kan
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| 188653 |
15-Feb-2009 |
imp |
It appears that none of the contents of this file are necessary, so
replace the amd64-ish version with a blank version.
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| 188627 |
15-Feb-2009 |
imp |
Remove stray __P()
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| 188431 |
10-Feb-2009 |
alc |
Eliminate an unused definition.
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| 187327 |
16-Jan-2009 |
imp |
Eliminate the PMAP_INLINE macro. It isn't really used here. If we
need to bring it back, we can.
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| 187301 |
15-Jan-2009 |
gonzo |
MFp4:
- Add debug output
- Fix pmap_zero_page and related places: use uncached segments and invalidate
cache after zeroing memory.
- Do not test for modified bit if it's not neccessary
(merged from mips-juniper p4 branch)
- Some #includes reorganization
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| 186212 |
17-Dec-2008 |
imp |
AT_DEBUG and AT_BRK were OBE like 10 years ago, so retire them.
Reviewed by: peter
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| 186191 |
16-Dec-2008 |
imp |
Start to clean up the MIPS elf machine dependent file.
o Add support for compiling elf64 for this file (the rest of the changes are
coming later)
o Fill in some misssing relocation types. We need to support these in
elf_machdep.c's relocation routines eventually, but that's future work
too.
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| 185427 |
29-Nov-2008 |
imp |
Unbreak mips build by taking first WAG at mb(), wmb() and rmb(). The
latter two are likely pessimal...
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| 183441 |
28-Sep-2008 |
imp |
Catch up with svn r96606 (cvs rev 1.127 2002/05/14 20:35:29) of
sys/param.h and move the MI numbers out of here. Also move the MI
defines. Also remove a couple defines not in use (not sure if it is
age, or OpenBSD origins for thse). Note the current values that are
overrides that appear to be odd in some way.
More cleanup could be done here: NBPG appears to be spelled PAGE_SIZE
these days. There's new ways to spell PGOFSET and PGSHIFT too, I
think. These constants duplicate the MI constants and are sprinkled
into the mips code only. Further investigation is needed.
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| 183439 |
28-Sep-2008 |
marius |
Remove ipi_all() and ipi_self() as the former hasn't been used at
all to date and the latter also is only used in ia64 and powerpc
code which no longer serves a real purpose after bring-up and just
can be removed as well. Note that architectures like sun4u also
provide no means of implementing IPI'ing a CPU itself natively
in the first place.
Suggested by: jhb
Reviewed by: arch, grehan, jhb
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| 181875 |
19-Aug-2008 |
jhb |
Export 'struct pcpu' to userland w/o requiring _KERNEL. A few ports
already define _KERNEL to get to this and I'm about to add hooks to
libkvm to access per-CPU data.
MFC after: 1 week
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| 179990 |
25-Jun-2008 |
ed |
Remove the unused major/minor numbers from iodev and memdev.
Now that st_rdev is being automatically generated by the kernel, there
is no need to define static major/minor numbers for the iodev and
memdev. We still need the minor numbers for the memdev, however, to
distinguish between /dev/mem and /dev/kmem.
Approved by: philip (mentor)
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| 179648 |
08-Jun-2008 |
wkoszek |
Fix spelling of "virtual".
There should be no visible change.
Reviewed by: rink
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| 178748 |
03-May-2008 |
gonzo |
Add FLT_EVAL_METHOD and DECIMAL_DIG, required by C99 standard.
Approved by: cognet (mentor)
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| 178745 |
03-May-2008 |
imp |
These files are unused, so remove them for now. If they turn out to
be needed later, they can be restored.
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| 178729 |
02-May-2008 |
imp |
This file is unused, so remove it for now.
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| 178688 |
30-Apr-2008 |
alc |
Eliminate an unused field from the pmap.
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| 178608 |
27-Apr-2008 |
alc |
Remove two unused declarations. These variables are now fields within
vm.h's struct kva_md_info.
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| 178212 |
15-Apr-2008 |
imp |
This isn't used, so remove it. It isn't relevant to most mips platforms.
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| 178211 |
15-Apr-2008 |
imp |
Copied from amd64, where it wasn't used, into mips, where it wasn't used.
Remove it.
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| 178172 |
13-Apr-2008 |
imp |
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
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