| 340145 |
04-Nov-2018 |
mmacy |
Backport of r338074 - generalize uart_bus_probe and add SNPS support to x86
Submitted by: Rajesh Kumar
Differential Revision: https://reviews.freebsd.org/D17381 |
| 331722 |
29-Mar-2018 |
eadler |
Revert r330897:
This was intended to be a non-functional change. It wasn't. The commit
message was thus wrong. In addition it broke arm, and merged crypto
related code.
Revert with prejudice.
This revert skips files touched in r316370 since that commit was since
MFCed. This revert also skips files that require $FreeBSD$ property
changes.
Thank you to those who helped me get out of this mess including but not
limited to gonzo, kevans, rgrimes.
Requested by: gjb (re) |
| 331506 |
24-Mar-2018 |
ian |
MFC r310017, r310229, r312289, r327260, r329539, r329544-r329546, r329620,
r329729, r329911, r329999
r310017:
[spi] reformat message
This commit corrects print of nomatch (newline was too early)
Submitted by: Hiroki Mori <yamori813@yahoo.co.jp>
Reviewed by: ray, loos, mizhka
Differential Revision: https://reviews.freebsd.org/D8749
r310229:
ofw_spi: Parse property for the SPI mode and CS polarity.
As cs is stored in a uint32_t, use the last bit to store the
active high flag as it's unlikely that we will have that much CS.
Reviewed by: loos
Differential Revision: https://reviews.freebsd.org/D8614
r312289:
[spibus] small code refactoring
Merge 3 sequential printf calls into one.
Reported by: rpokala
Reviewed by: rpokala, adrian
Approved by: adrian (mentor)
Differential Revision: https://reviews.freebsd.org/D8795
r327260:
SPDX: fix wrong license ID tag in dev/spibus.
r329539:
Provide public declarations for ofw_spibus_driver and ofw_spibus_devclass
so other drivers can refer to them in DRIVER_MODULE() decls.
r329544:
Add modules/spi as a gathering point for SPI-related modules, analagous to
modules/i2c for i2c/iicbus modules. Build spibus as a module.
r329545:
Add ofw_bus_if.h to SRCS.
r329546:
Build at45d and mx25l SPI flash drivers as modules.
r329620:
Add missing MODULE_DEPENDS().
r329729:
Remove some files that snuck in via cut and paste.
Having these compiled into the module causes the kobj method descriptors
to be resolved incorrectly (by the compile-time linker instead of the
kernel linker), which then leads to hours of frustrating debugging.
r329911:
Add a functional detach() routine, to make things kldunload-friendly.
r329999:
Add a SPI driver for imx5 and imx6.
It can be compiled into the kernel with "device imx_spi" or loaded as a
module, which is also named "imx_spi". |
| 330897 |
14-Mar-2018 |
eadler |
Partial merge of the SPDX changes
These changes are incomplete but are making it difficult
to determine what other changes can/should be merged.
No objections from: pfg |
| 323205 |
06-Sep-2017 |
emaste |
MFC r323022: arge: correct bzero sizeof (pointed-to object, not pointer)
Sponsored by: The FreeBSD Foundation |
| 322716 |
20-Aug-2017 |
delphij |
MFC r322527:
Plug memory leak in arge_encap().
Reported by: Ilja Van Sprundel <ivansprundel ioactive.com>
Submitted by: Domagoj Stolfa <domagoj.stolfa gmail.com>
Reviewed by: adrian |
| 310158 |
16-Dec-2016 |
manu |
MFC r309935:
Use the spibus accessor when applicable. |
| 308401 |
07-Nov-2016 |
hselasky |
MFC r307518:
Fix device delete child function.
When detaching device trees parent devices must be detached prior to
detaching its children. This is because parent devices can have
pointers to the child devices in their softcs which are not
invalidated by device_delete_child(). This can cause use after free
issues and panic().
Device drivers implementing trees, must ensure its detach function
detaches or deletes all its children before returning.
While at it remove now redundant device_detach() calls before
device_delete_child() and device_delete_children(), mostly in
the USB controller drivers.
Tested by: Jan Henrik Sylvester <me@janh.de>
Reviewed by: jhb
Differential Revision: https://reviews.freebsd.org/D8070 |
| 302408 |
08-Jul-2016 |
gjb |
Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, as nothing has been merged
here.
Additional commits post-branch will follow.
Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation |
| 302190 |
25-Jun-2016 |
landonf |
Replace mips/sentry5 with mips/broadcom
The delta between SENTRY5 and BCM was already small due to BCM being
derived from SENTRY5; re-integrating the two avoids the maintenance
overhead of keeping them both in sync with bhnd(4) changes.
- Re-integrate minor SENTRY5 deltas in bcm_machdep.c
- Modify uart_cpu_chipc to allow specifying UART debug/console flags via
kenv and device hints.
- Switch SENTRY5 to std.broadcom
- Enabled CFI flash support for SENTRY5
Reviewed by: Michael Zhilin <mizkha@gmail.com> (Broadcom MIPS support)
Approved by: re (gjb), adrian (mentor)
Differential Revision: https://reviews.freebsd.org/D6897
|
| 299418 |
11-May-2016 |
trasz |
Remove NULL checks after M_WAITOK allocations from sys/mips/.
Reviewed by: adrian@
MFC after: 1 month
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D6301
|
| 298848 |
30-Apr-2016 |
pfg |
sys: Make use of our rounddown() macro when sys/param.h is available.
No functional change.
|
| 298053 |
15-Apr-2016 |
pfg |
mips: for pointers replace 0 with NULL.
These are mostly cosmetical, no functional change.
Found with devel/coccinelle.
Reviewed by: adrian
|
| 297199 |
22-Mar-2016 |
jhibbits |
Fix the resource_list_print_type() calls to use uintmax_t.
Missed a bunch from r297000.
|
| 297000 |
18-Mar-2016 |
jhibbits |
Use uintmax_t (typedef'd to rman_res_t type) for rman ranges.
On some architectures, u_long isn't large enough for resource definitions.
Particularly, powerpc and arm allow 36-bit (or larger) physical addresses, but
type `long' is only 32-bit. This extends rman's resources to uintmax_t. With
this change, any resource can feasibly be placed anywhere in physical memory
(within the constraints of the driver).
Why uintmax_t and not something machine dependent, or uint64_t? Though it's
possible for uintmax_t to grow, it's highly unlikely it will become 128-bit on
32-bit architectures. 64-bit architectures should have plenty of RAM to absorb
the increase on resource sizes if and when this occurs, and the number of
resources on memory-constrained systems should be sufficiently small as to not
pose a drastic overhead. That being said, uintmax_t was chosen for source
clarity. If it's specified as uint64_t, all printf()-like calls would either
need casts to uintmax_t, or be littered with PRI*64 macros. Casts to uintmax_t
aren't horrible, but it would also bake into the API for
resource_list_print_type() either a hidden assumption that entries get cast to
uintmax_t for printing, or these calls would need the PRI*64 macros. Since
source code is meant to be read more often than written, I chose the clearest
path of simply using uintmax_t.
Tested on a PowerPC p5020-based board, which places all device resources in
0xfxxxxxxxx, and has 8GB RAM.
Regression tested on qemu-system-i386
Regression tested on qemu-system-mips (malta profile)
Tested PAE and devinfo on virtualbox (live CD)
Special thanks to bz for his testing on ARM.
Reviewed By: bz, jhb (previous)
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D4544
|
| 295880 |
22-Feb-2016 |
skra |
As <machine/pmap.h> is included from <vm/pmap.h>, there is no need to
include it explicitly when <vm/pmap.h> is already included.
Reviewed by: alc, kib
Differential Revision: https://reviews.freebsd.org/D5373
|
| 295832 |
20-Feb-2016 |
jhibbits |
Introduce a RMAN_IS_DEFAULT_RANGE() macro, and use it.
This simplifies checking for default resource range for bus_alloc_resource(),
and improves readability.
This is part of, and related to, the migration of rman_res_t from u_long to
uintmax_t.
Discussed with: jhb
Suggested by: marcel
|
| 294989 |
28-Jan-2016 |
mmel |
EHCI: Make core reset and port speed reading more generic.
Use driver settable callbacks for handling of:
- core post reset
- reading actual port speed
Typically, OTG enabled EHCI cores wants setting of USBMODE register,
but this register is not defined in EHCI specification and different
cores can have it on different offset.
Also, for cores with TT extension, actual port speed must be determinable.
But again, EHCI specification not covers this so this patch provides
function for two most common variant of speed bits layout.
Reviewed by: hselasky
Differential Revision: https://reviews.freebsd.org/D5088
|
| 294883 |
27-Jan-2016 |
jhibbits |
Convert rman to use rman_res_t instead of u_long
Summary:
Migrate to using the semi-opaque type rman_res_t to specify rman resources. For
now, this is still compatible with u_long.
This is step one in migrating rman to use uintmax_t for resources instead of
u_long.
Going forward, this could feasibly be used to specify architecture-specific
definitions of resource ranges, rather than baking a specific integer type into
the API.
This change has been broken out to facilitate MFC'ing drivers back to 10 without
breaking ABI.
Reviewed By: jhb
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D5075
|
| 292766 |
27-Dec-2015 |
adrian |
Fix missing path conversion from the previous commit to shuffle mdio around.
It turns out the recent work to cut down the number of atheros kernels built
didnt include one with ARGE_MDIO defined..
|
| 292247 |
15-Dec-2015 |
adrian |
[qca953x] remove unneeded initialisation.
This was copied from another chip file and it's not required on Honeybee.
Tested:
* AP143, QCA9531 SoC.
Obtained from: OpenWRT
|
| 292246 |
15-Dec-2015 |
adrian |
[ar71xx] always count interrupts, spurious or otherwise.
This aids in debugging.
|
| 292245 |
15-Dec-2015 |
adrian |
[arge] add a comment about needing mdio busses in order to use the interface.
This is a holdover from how reset is handled in the ARGE_MDIO world.
You need to define the mdio bus device if you want to use the ethernet
device or the arge setup path doesn't bring the MAC out of reset.
|
| 290918 |
16-Nov-2015 |
adrian |
Add QCA9533 to the list of SoCs that require IRQ's be ACKed.
|
| 290910 |
16-Nov-2015 |
adrian |
Add initial support for the QCA953x ("Honeybee") from Qualcomm Atheros.
The QCA953x SoC is an integrated 2x2 2GHz 11n + MIPS24k core, with
a 5 port FE switch, gige WAN port, and all the same stuff you'd find on
its predecessor - the AR9331.
However, buried deep in here somewhere is also a PCIe EP/RC for various
applications and some other weird bits I don't yet know about.
This is enough to get the reference board up and booting. I haven't yet
had it pass lots of packets - I need to finalise the ethernet switch
bits and the GMAC configuration (ie, how the ethernet ports and switch
are wired up) and I'll bring that in when I commit the base configuration
files to use the thing.
The wifi stuff will come much later. I have to port that support from
Linux ath9k and extend our vendor HAL to support it.
The reference board (AP143) comes with 32MB RAM and 4MB flash, so in order
to use it I need to get USB working fully so I can run root from there.
Thankyou to Qualcomm Atheros for access to the reference design board.
Details:
* Add register definitions from openwrt;
* It looks like a QCA955x but shrunk down to a QCA933x footprint, so
use the QCA955x bits and fix up the clock detection code to do the
QCA953x bits (they're very subtly different);
* Teach GPIO about it;
* Teach EHCI about it;
* Teach if_arge about it;
* Teach the CPU detection code about it.
Tested:
* AP143, QCA9533v2 SoC
Obtained from: Linux, Linux OpenWRT
|
| 290338 |
03-Nov-2015 |
adrian |
Remove this; it's also in sys/conf/files.mips.
|
| 290217 |
31-Oct-2015 |
adrian |
arge_mdio: fix barriers; correctly check MII indicator register.
* use barriers in a slightly better fashion. You can blame this
glass of whiskey on putting barriers in the wrong spot. Grr adrian.
* steal/rewrite the mdio busy check from ag7100 from openwrt and
refactor the existing code out. This is .. more correct.
This seems to fix the boot-to-boot variation that I've been seeing
and it quietens the switch port status flapping.
Tested:
* QCA9558 SoC (AP135.)
Obtained from: Linux OpenWRT
|
| 290216 |
31-Oct-2015 |
adrian |
arge: fix barrier macro.
|
| 290215 |
30-Oct-2015 |
adrian |
arge: attempt to close a transmit race by only enabling the descriptor at the end of setup.
This driver and the linux ag71xx driver both treat the transmit ring
as a circular linked list of descriptors. There's no "end" pointer
that is ever NULL - instead, it expects the MAC to hit a finished
descriptor (ARGE_DESC_EMPTY) and stop.
Now, since it's a circular buffer, we may end up with the hardware
hitting the beginning of our multi-descriptor frame before we've finished
setting it up. It then DMA's it in, starts sending it, and we finish
writing out the new descriptor. The hardware may then write its
completion for the next descriptor out; then we do, and when we next
read it it'll show up as "not done" and transmit completion stops.
This unfortunately manifests itself as the transmit queue always
being active and a massive TX interrupt storm. We need to actively
ACK packets back from the transmit engine and if we don't (eg because
we think the transmit isn't finished but it is) then the unit will
just keep generating interrupts.
I hit this finally with the below testing setup. This fixed it for me.
Strictly speaking I should put in a sync in between writing out all of
the descriptors and writing out that final descriptor.
Tested:
* QCA9558 SoC (AP135 reference board) w/ arge1 + vlans acting as a
router, and iperf -d (tcp, bidirectional traffic.)
Obtained from: Linux OpenWRT (ag71xx_main.c.)
|
| 290214 |
30-Oct-2015 |
adrian |
arge: just use 1U since it's a 32 bit unsigned destination value.
|
| 290213 |
30-Oct-2015 |
adrian |
arge: do an explicit flush between updating the TX ring and starting transmit.
The MIPS busdma sync operations currently are a big no-op on coherent memory.
This isn't strictly correct behaviour as we need a SYNC in here to ensure that
the writes have finished and are visible in main memory before the MMIO accesses
occur. This will have to be addressed in a later commit.
But, before that happens, let's at least do a flush here to make things
more "correct".
This is required for even remotely sensible behaviour on mips74k with
write-through memory enabled.
|
| 290212 |
30-Oct-2015 |
adrian |
arge_mdio: add explicit read barriers for MDIO_READs.
The mips74k programmers guide notes that reads can be re-ordered, even
uncached ones, so we need an explicit SYNC between them.
Yes, this is a case of a driver author actively doing a bus barrier
operation.
This ends up being necessary when the mips74k core is run in write-back
mode rather than write-through mode. That's coming in an upcoming
commit.
Tested:
* mips74k, QCA9558 SoC (AP135 reference board), arge<->arge interface
routing traffic tests.
|
| 290211 |
30-Oct-2015 |
adrian |
arge: ensure there's enough space in the TX ring before attempting to
send frames.
This matches the other check for space.
"enough" is a misnomer, for "reasons". The biggest reason is that
the TX ring is actually a circular linked list, with no head/tail pointers.
This is just a bit more headroom between head/tail so we have time to
schedule frames before we hit where the hardware is at.
Ideally this would be tunable and a little larger.
|
| 290210 |
30-Oct-2015 |
adrian |
arge: do a read-after-write on all arge register writes, not just MDIO writes.
This flushes out the write to the system before anything continues.
The mips74k guide, chapter 3.3.3 (write gathering) notes that writes
can be buffered in FIFOs - even uncached ones - so we can't guarantee
the device has felt its effects. Now, since we're all lazy driver
authors and don't pepper read/write barriers everywhere, fake it here.
tested:
* mips74k - QCA9558 SoC (AP135 reference board)
|
| 290123 |
28-Oct-2015 |
adrian |
Oops - use the wrong array offset.
|
| 290090 |
28-Oct-2015 |
adrian |
Add some debugging code (under ARGE_DEBUG) that counts each interrupt source.
This should make it easier to track down interrupt storms from arge.
Tested:
* AP135 (QCA955x) SoC - defaults to ARGE_DEBUG enabled
* Carambola2 (AR9331 SoC) - defaults to ARGE_DEBUG disabled
|
| 289898 |
24-Oct-2015 |
adrian |
arge(4): flip this on for AR9344 SoCs.
I couldn't test arge0->arge1 bridging, only arge0 VLAN bridging.
The DIR-825C1 only hooks up arge0 to the switch GMAC0 and so
you need to abuse VLANs to test.
Tested:
* DIR-825C1 (AR9344)
|
| 289744 |
22-Oct-2015 |
adrian |
arge: use 1-byte TX and RX alignment for AR9330/AR9331.
This part seems to work bug-free with single byte TX/RX buffer alignment.
This drops the CPU requirement to bridge 100mbit iperf from 100% CPU
to ~ 50% CPU.
Tested:
* AP121 (AR9330) SoC, highly magic netbooted kernel + USB rootfs
due to 4mb flash, 16mb RAM; doing bridging between arge0 and arge1.
Notes:
* Yes, I likely can also turn this on for the AR934x SoC family now.
But since hardware design apparently follows similar branching
strategies to software design, I'll go and make sure all the AR934x's
that made it out into shipping products work before I flip it on.
|
| 289678 |
21-Oct-2015 |
adrian |
arge: Remove the debugging printf that snuck in.
This was triggering when using it as an AP bridge rather than an ethernet
bridge.
The code is unclear but it works; I'll fix it to be clearer and test
performance at a later stage.
|
| 289671 |
21-Oct-2015 |
adrian |
arge: don't do the rx fixup copy and just offset the mbuf by 2 bytes
The existing code meets the "alignment" requirement for the l3 payload
by offsetting the mbuf by uint64_t and then calling an rx fixup routine
to copy the frame backwards by 2 bytes. This DWORD aligns the
L3 payload so tcp, etc doesn't panic on unaligned access.
This is .. slow.
For arge MACs that support 1 byte TX/RX address alignment, we can do
the "other" hack: offset the RX address of the mbuf so the L3 payload
again is hopefully DWORD aligned.
This is much cheaper - since TX/RX is both 1 byte align ready (thanks
to the previous commit) there's no bounce buffering going on and there
is no rx fixup copying.
This gets bridging performance up from 180mbit/sec -> 410mbit/sec.
There's around 10% of CPU cycles spent in _bus_dmamap_sync(); I'll
investigate that later.
Tested:
* QCA955x SoC (AP135 reference board), bridging arge0/arge1
by programming the switch to have two vlangroups in dot1q mode:
# ifconfig bridge0 inet 192.168.2.20/24
# etherswitchcfg config vlan_mode dot1q
# etherswitchcfg vlangroup0 members 0,1,2,3,4
# etherswitchcfg vlangroup1 vlan 2 members 5,6
# etherswitchcfg port5 pvid 2
# etherswitchcfg port6 pvid 2
# ifconfig arge1 up
# ifconfig bridge0 addm arge1
|
| 289476 |
18-Oct-2015 |
adrian |
if_arge: fix up TX workaround; add TX/RX requirements for busdma; add stats
The early ethernet MACs (I think AR71xx and AR913x) require that both
TX and RX require 4-byte alignment for all packets.
The later MACs have started relaxing the requirements.
For now, the 1-byte TX and 1-byte RX alignment requirements are only for
the QCA955x SoCs. I'll add in the relaxed requirements as I review the
datasheets and do testing.
* Add a hardware flags field and 1-byte / 4-byte TX/RX alignment.
* .. defaulting to 4-byte TX and 4-byte RX alignment.
* Only enforce the TX alignment fixup if the hardware requires a 4-byte
TX alignment. This avoids a call to m_defrag().
* Add counters for various situations for further debugging.
* Set the 1-byte and 4-byte busdma alignment requirement when
the tag is created.
This improves the straight bridging performance from 130mbit/sec
to 180mbit/sec, purely by removing the need for TX path bounce buffers.
The main performance issue is the RX alignment requirement and any RX
bounce buffering that's occuring. (In a local test, removing the RX
fixup path and just aligning buffers raises the performance to above
400mbit/sec.
In theory it's a no-op for SoCs before the QCA955x.
Tested:
* QCA9558 SoC in AP135 board, using software bridging between arge0/arge1.
|
| 287911 |
17-Sep-2015 |
bz |
Remove more unused variables leading to compile time errors.
|
| 287907 |
17-Sep-2015 |
bz |
Remove unused variable leading to compile errors.
|
| 287882 |
16-Sep-2015 |
zbb |
Add domain support to PCI bus allocation
When the system has more than a single PCI domain, the bus numbers
are not unique, thus they cannot be used for "pci" device numbering.
Change bus numbers to -1 (i.e. to-be-determined automatically)
wherever the code did not care about domains.
Reviewed by: jhb
Obtained from: Semihalf
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D3406
|
| 285524 |
14-Jul-2015 |
adrian |
Populate hw.model with the CPU model information.
Now you see something like:
# sysctl hw.model
hw.model: Atheros AR9330 rev 1
Tested:
* Carambola 2, AR9331 SoC
|
| 285121 |
04-Jul-2015 |
adrian |
Reshuffle all of the DDR flush operations into a single switch/mux,
and start teaching subsystems about it.
The Atheros MIPS platforms don't guarantee any kind of FIFO consistency
with interrupts in hardware. So software needs to do a flush when it
receives an interrupt and before it calls the interrupt handler.
There are new ones for the QCA934x and QCA955x, so do a few things:
* Get rid of the individual ones (for ethernet and IP2);
* Create a mux and enum listing all the variations on DDR flushes;
* replace the uses of IP2 with the relevant one (which will typically
be "PCI" here);
* call the USB DDR flush before calling the real USB interrupt handlers;
* call the ethernet one upon receiving an interrupt that's for us,
rather than never calling it during operation.
Tested:
* QCA9558 (TP-Link archer c7 v2)
* AR9331 (Carambola 2)
TODO:
* PCI, USB, ethernet, etc need to do a double-check to see if the
interrupt was truely for them before doing the DDR. For now I
prefer "correct" over "fast".
|
| 285083 |
03-Jul-2015 |
adrian |
Oops - fix typo.
|
| 285073 |
03-Jul-2015 |
adrian |
Enable setting the QCA955x GPIO output mux configuration.
It's not used by any boards yet, but it's going to creep up soon
as more boards show up.
|
| 285072 |
03-Jul-2015 |
adrian |
Add register defines for the QCA955x DDR flush and GPIO control.
|
| 283095 |
19-May-2015 |
adrian |
Add initial support for the QCA955x PCIe host controller.
The QCA955x looks a lot like the AR724x PCIe controller, except it
supports two root complexes. Unfortunately I only have one, so
although this code has started down the path of supporting more than
one, it's definitely not yet ready.
Tested:
* AP135 board (QCA9558 SoC), with the 11ac NIC swapped for an AR9380
PCIe NIC.
Notes:
* Yes, this driver isn't very pretty. I decided to commit what I have
versus holding onto something that isn't yet finished. It is enough
to bring up the above NIC and interrupt routing works, so it's a good
start.
* However, yes, the DDR flush routine hooks need to be fixed up.
I don't think I'm firing the right one at the moment.
|
| 281438 |
11-Apr-2015 |
andrew |
Add support for the uart classes to set their default register shift value.
This is needed with the pl011 driver. Before this change it would default
to a shift of 0, however the hardware places the registers at 4-byte
addresses meaning the value should be 2.
This patch fixes this for the pl011 when configured using the fdt. The
other drivers have a default value of 0 to keep this a no-op.
MFC after: 1 week
|
| 280798 |
28-Mar-2015 |
adrian |
Begin moving support for board MAC addresses over to being explicitly defined.
A lot of these dinky atheros based MIPS boards don't have a nice, well,
anything consistent defining their MAC addresses for things.
The Atheros reference design boards will happily put MAC addresses
into the wifi module calibration data like they should, and individual
ethernet MAC addresses into the calibration area in flash.
That makes my life easy - "hint.arge.X.eeprommac=<addr>" reads from
that flash address to extract a MAC, and everything works fine.
However, aside from some very well behaved vendors (eg the Carambola 2
board), everyone else does something odd.
eg:
* a MAC address in the environment (eg ubiquiti routerstation/RSPRO)
that you derive arge0/arge1 MAC addresses from.
* a MAC address in flash that you derive arge0/arge1 MAC addresses from.
* The wifi devices having their own MAC addresses in calibration data,
like normal.
* The wifi devices having a fixed, default or garbage value for a MAC
address in calibration data, and it has to be derived from the
system MAC.
So to support this complete nonsense of a situation, there needs to be
a few hacks:
* The "board" MAC address needs to be derived from somewhere and squirreled
away. For now it's either redboot or a MAC address stored in calibration
flash.
* Then, a "map" set of hints to populate kenv with some MAC addresses
that are derived/local, based on the board address. Each board has
a totally different idea of what you do to derive things, so each
map entry has an "offset" (+ve or -ve) that's added to the board
MAC address.
* Then if_arge (and later, if_ath) should check kenv for said hint and
if it's found, use that rather than the EEPROM MAC address - which may
be totally garbage and not actually work right.
In order to do this, I've undone some of the custom redboot expecting
hacks in if_arge and the stuff that magically adds one to the MAC
address supplied by the board - instead, as I continue to test this
out on more hardware, I'll update the hints file with a map explaining
(a) where the board MAC should come from, and (b) what offsets to use
for each device.
The aim is to have all of the tplink, dlink and other random hardware
we run on have valid MAC addresses at boot, so (a) people don't get
random B:S:D:x:x:x ethernet MACs, and (b) the wifi MAC is valid
so it works rather than trying to use an invalid address that
actually upsets systems (think: multicast bit set in BSSID.)
Tested:
* TP-Link TL_WDR3600 - subsequent commits will add the hints map
and the if_ath support.
TODO:
* Since this is -HEAD, and I'm all for debugging, there's a lot of
printf()s in here. They'll eventually go under bootverbose.
* I'd like to turn the macaddr routines into something available
to all drivers - too many places hand-roll random MAC addresses
and parser stuff. I'd rather it just be shared code.
However, that'll require more formal review.
* More boards.
|
| 280315 |
21-Mar-2015 |
adrian |
Add GPIO function mux configuration for AR934x SoCs.
The AR934x (and maybe others in this family) have a more complicated
GPIO mux. The AR71xx just has a single function register for a handful
of "GPIO or X" options, however the AR934x allows for one of roughly
100 behaviours for each GPIO pin.
So, this adds a quick hints based mechanism to configure the output
functions, which is required for some of the more interesting board
configurations. Specifically, some use external LNAs to improve
RX, and without the MUX/output configured right, the 2GHz RX side
will be plain terrible.
It doesn't yet configure the "input" side yet; I'll add that if
it's required.
Tested:
* TP-Link TL-WDR3600, testing 2GHz STA/AP modes, checking some
basic RX sensitivity things (ie, "can I see the AP on the other
side of the apartment that intentionally has poor signal reception
from where I am right now.")
Whilst here, fix a silly bug in the maxpin routine; I was missing
a break.
|
| 280314 |
21-Mar-2015 |
adrian |
add QCA955x PCIe configuration registers.
These are /not/ absolute addresses, as the QCA955x SoC has 2 PCIe RC's
(and 1 PCIe EP.)
|
| 280313 |
21-Mar-2015 |
adrian |
Note that the AR724x PCIe registers are actually from the PCI_CTRL
register range.
|
| 280124 |
15-Mar-2015 |
adrian |
Use ar71xx_mac_addr_random_init() instead of a hand-rolled random
MAC address.
|
| 280123 |
15-Mar-2015 |
adrian |
Start fleshing out some MAC address helper functions.
A lot of these embedded boards don't have a unique MAC address per
device stored somewhere unique - sometimes they'll have one MAC
for both arge NICs; someties they'll have one MAC for both arge NICs
/and/ the ath NICs. In these instances, we need to derive device
specific MAC addresses from the base MAC address.
These functions will be used by some follow-up code that'll slot
into if_arge and if_ath.
|
| 279791 |
08-Mar-2015 |
adrian |
Modify the if_arge code to use a /fixed/ media mode when it's configured.
Otherwise, the initial media speed would change if a PHY is hooked up,
sending PHY speed notifications. For the AP135 at least, the RGMII
PHY has a static speed/duplex configured and if the PHY plumbing
attaches the PHY to the if_arge interface, the first link speed change
from 1000/full will set the MAC to something that isn't useful.
This shouldn't affect any other platforms - everything I looked at is
using hard-coded speed/duplex as static, as they're facing a switch
with no PHY attached.
|
| 279579 |
04-Mar-2015 |
adrian |
Add ethernet MAC DDR flush hookups for QCA955x.
Tested:
* AP135
|
| 279578 |
04-Mar-2015 |
adrian |
Add DDR flush registers for QCA955x.
|
| 279511 |
02-Mar-2015 |
adrian |
[QCA955x] make the USB EHCI interrupts shareable.
There's two EHCI controllers in the QCA955x SoCs - they have different
interrupts available via various demux registers, but they both tie to
IP3.
So for now, allow them to be sharable so they can hang off of IP3.
|
| 279510 |
02-Mar-2015 |
adrian |
Add initial QCA955x support to if_arge.c.
Tested:
* AP135 development board, QCA9558 SoC.
|
| 279509 |
02-Mar-2015 |
adrian |
Add a MII mode for SGMII.
This appears on the AR934x and later chips, although it's not
something that's programmed via the arge0/arge1 register space.
It's just cosmetic.
|
| 279480 |
01-Mar-2015 |
adrian |
Add very initial QCA955x awareness to the GPIO code.
There's a lot more to come - the QCA955x has a bunch more GPIO MUX
configuration, reminiscent of what the ARM chips let you do - but
it'll have to come later.
|
| 279479 |
01-Mar-2015 |
adrian |
Flesh out some more QCA955x ethernet PLL setup.
|
| 279478 |
01-Mar-2015 |
adrian |
Add Ethernet PLL values for the QCA955x.
These are the same as the AR934x.
Obtained from: Linux openwrt
|
| 279477 |
01-Mar-2015 |
adrian |
Make QCA955X_GMAC_REG_ETH_CFG defined like most other registers like this.
|
| 279476 |
01-Mar-2015 |
adrian |
Add QCA955x support to the EHCI setup path.
Tested:
* QCA AP135 development board, USB rootfs.
|
| 278104 |
02-Feb-2015 |
sbruno |
The linux driver code for the MDIO bus does a read-after-write
which seems to be required on MIPS74k platforms for correct
behaviour.
Reviewed by: adrian
|
| 277996 |
31-Jan-2015 |
loos |
Implement GPIO_GET_BUS() method for all GPIO drivers.
Add helper routines to deal with attach and detach of gpiobus and gpioc
devices that are common to all drivers.
|
| 277971 |
31-Jan-2015 |
loos |
Replace spaces with tabs, this will easier future changes on softc
structure.
No functional changes.
|
| 277968 |
31-Jan-2015 |
loos |
Clean up and fix the device detach routine and the failure path on GPIO
drivers.
This paves the way for upcoming work.
|
| 276741 |
06-Jan-2015 |
adrian |
Make the apb.c code optional behind ar71xx_apb rather than standard.
The QCA955x has more mux interrupts going on - and the AR934x actually does,
but I cheated and assigned wlan and pcie to the same interrupt line.
They are, there's just a status register mux that I should've been using.
Luckily this isn't too bad a change in itself - almost all of the
Atheros MIPS configurations use a _BASE file to inherit from.
Except PB92, which I should really fix up at some point.
The AR934x will use the legacy apb for now until I write its replacement.
The QCA955x SoC I'm doing bring-up on will have a separate qca955x_apb.c
implementation that includes hooking into IP2/IP3 and doing further
interrupt demuxing as appropriate.
|
| 276739 |
06-Jan-2015 |
adrian |
Add an APB base/size for the QCA955X for an upcoming QCA955x specific
APB mux.
It's larger than the AR71xx because it needs to replace the nexus
for some devices (notably wifi) and the wifi driver (if_ath_ahb.c)
reads the SPI data directly at early boot whilst it's memory mapped
in.
I'm eventually going to rip it out and replace it with a firmware
interface similar to what exists for the if_ath_pci.c path -
something early on (likely something new that I'll write) will
suck in the calibration data into a firmware API blob and that'll
be accessed from if_ath_ahb.c.
But, one thing at a time.
Tested:
* QCA955x SoC, AP135 development board
|
| 276738 |
06-Jan-2015 |
adrian |
The QCA955x USB init path doesn't require any of this, so delete it.
Obtained from: Linux/OpenWRT
|
| 276717 |
05-Jan-2015 |
hselasky |
Add 64-bit DMA support in the XHCI controller driver.
- Fix some comments and whitespace while at it.
MFC after: 1 month
Submitted by: marius@
|
| 276691 |
05-Jan-2015 |
adrian |
Remove the remnants of the OpenWRT/Linux bits that this was based off
of.
Obtained from: Linux/OpenWRT
|
| 276690 |
05-Jan-2015 |
adrian |
Oops - missed refclk.
Tested:
* AP135, QCA955x SoC
|
| 276685 |
05-Jan-2015 |
adrian |
Add initial Qualcomm Atheros QCA955x SoC support.
This adds the initial frequency poking and configures up enough
for it to boot and spit out data over the console.
There's still a whole bunch of work to do in the reset path
and devices to support this thing, but hey, it's alive!
ath> go 0x80050100
## Starting application at 0x80050100 ...
CPU platform: Atheros AR9558 rev 0
CPU Frequency=720 MHz
CPU DDR Frequency=600 MHz
CPU AHB Frequency=200 MHz
platform frequency: 720 MHz
CPU reference clock: 0 MHz
CPU MDIO clock: 40 MHz
Done at: hackathon
Obtained from: Linux OpenWRT, Qualcomm Atheros
|
| 276684 |
05-Jan-2015 |
adrian |
ACK interrupts on the new SoCs.
|
| 276683 |
05-Jan-2015 |
adrian |
add QCA955x SoC types.
|
| 276682 |
05-Jan-2015 |
adrian |
Add QCA955x series register definitions.
There's likely a bunch of register offsets that I have to add the
register window base to before I use them.
Done at: Hackathon
Obtained from: Linux OpenWRT
|
| 276610 |
03-Jan-2015 |
adrian |
Add a GPIO output mux configuration method.
The AR934x and later (which will turn up eventually) have a new GPIO
output configuration option - a real MUX rather than a "GPIO or this
function."
For now I'm squirreling it away in the CPU code just so it's done -
I may move this to the GPIO layer later.
Specifically, this is required for setting up some boards that have
external receive side LNA (low noise amplifier) that gets switched on/off
by the on-chip wireless MAC. If we don't add this support for those
boards then we'll end up with really poor performance.
(I don't yet have one of those APs, but it'll likely show up in a week.)
Obtained from: Linux OpenWRT
|
| 276609 |
03-Jan-2015 |
adrian |
Add AR934x specific GPIO functions and output MUX configuration.
Obtained from: Linux OpenWRT
|
| 276608 |
03-Jan-2015 |
adrian |
Add AR934x GPIO function configuration.
Obtained from: Linux OpenWRT
|
| 274670 |
18-Nov-2014 |
loos |
Moves all the duplicate code to a single function.
Verify for invalid modes and unwanted flags before pass the new flags to
driver.
|
| 273799 |
28-Oct-2014 |
loos |
Make the GPIO children attach to the first unit available and not only to
unit 0.
It seems that this 'simplification' was copied to all GPIO drivers in tree.
This fix a bug where a GPIO controller could fail to attach its children
(gpioc and gpiobus) if another GPIO driver attach first.
|
| 273174 |
16-Oct-2014 |
davide |
Follow up to r225617. In order to maximize the re-usability of kernel code
in userland rename in-kernel getenv()/setenv() to kern_setenv()/kern_getenv().
This fixes a namespace collision with libc symbols.
Submitted by: kmacy
Tested by: make universe
|
| 272239 |
28-Sep-2014 |
adrian |
Fix the AR724x PCIe glue to correctly probe the BAR on AR7240 devices.
There's a bug in the AR7240 PCIe hardware where a correct BAR will end
up having the device disappear.
It turns out that for the device address it should be all 0's.
However, this meant that the PCI probe code would try writing 0xffffffff
in to see how big the window was, read back 0x0, and think the window
was 32 bits. It then ended up calculating a resource size of 0 bytes,
failed to find anything via an rman call, and this would fail to attach.
I have quite absolutely no idea how in the various planes of existence
this particular bit of code and how it worked with the PCI bus code
ever worked. But, well, it did.
Tested:
* Atheros AP93 - AR7240 + AR9280 reference board
|
| 272237 |
28-Sep-2014 |
adrian |
Fix the ar724x PCI config space register read.
It was doing incorrect things with masks. This was fixed in the
AR71xx codebase but it wasn't yet fixed in the AR724x code.
This ended up having config space reads return larger/incorrect values
in some situations.
Tested:
* AR7240
TODO:
* test ar7241, AR7242, and AR934x.
|
| 271858 |
19-Sep-2014 |
glebius |
Mechanically convert to if_inc_counter().
|
| 269148 |
27-Jul-2014 |
adrian |
Commit some sins in the name of "oh god oh god I don't really want to
be able to claim I know how the UART code works."
* Just return 115200 as the current baud rate. I should cache it in the
device struct and return that but I'm lazy right now.
* don't error out on other ioctl settings for now, just silently ignore them.
* remove some code that was copied from the 8250 driver that isn't needed
any longer.
Tested:
* AR9331, Carambola-2 board.
|
| 268235 |
03-Jul-2014 |
loos |
Properly advertise that if_arge can handle long frames (if_arge is set to
handle packets up to 1536 bytes)
This fixes the need to frag that could happen when using vlans on top of
if_arge (which is a common case for the use the switch ports as individual
NICs).
Previously to this commit any vlan setup with if_arge as parent would have
the MTU of the parent interface reduced by the size of dot1q header
(4 bytes).
Tested on TP-Link 1043ND (where the WAN port is just a switch port setup to
tag packets in a different VLAN than the LAN ports).
Reported and tested by: Harm Weites (harm at weites.com)
|
| 267363 |
11-Jun-2014 |
jhb |
Fix various NIC drivers to properly cleanup static DMA resources.
In particular, don't check the value of the bus_dma map against NULL
to determine if either bus_dmamem_alloc() or bus_dmamap_load() succeeded.
Instead, assume that bus_dmamap_load() succeeeded (and thus that
bus_dmamap_unload() should be called) if the bus address for a resource
is non-zero, and assume that bus_dmamem_alloc() succeeded (and thus
that bus_dmamem_free() should be called) if the virtual address for a
resource is not NULL.
In many cases these bugs could result in leaks when a driver was detached.
Reviewed by: yongari
MFC after: 2 weeks
|
| 265816 |
10-May-2014 |
loos |
Do not configure all pins as outputs as this can lead to short circuits when
the GPIO pin is connected to a push button (or other devices).
Instead keep the boot loader settings.
Calling ar71xx_gpio_pin_configure() with DEFAULT_CAPS was probably a
mistake and was causing all the pins to be set as outputs.
|
| 265814 |
10-May-2014 |
loos |
Remove an old mistake of mine. This has sneak in the code i sent to gonzo
at that time, but AFAIK it is only used on routerboards.
Enabling GPIO_FUNC_SPI_CS[1|2]_EN will claim the use of gpio pins 0 and 1
respectivelly for use as SPI CS pins.
When really needed, this can still be enabled on kernel hints using the
function_set and function_clear knobs.
|
| 265775 |
09-May-2014 |
loos |
Add support for reading RouterBoard's memory which is passed by the loader
(RouterBOOT).
Tested on RouterBoards, various and on RSPRO, TP-Link MR3x20
(for regressions).
|
| 265774 |
09-May-2014 |
loos |
When a GPIO pin is set to be turned on by kernel hints (hint.gpio.X.pinon)
make sure the GPIO pin is configured as an output as this is not always the
case.
|
| 263296 |
18-Mar-2014 |
adrian |
Extend the Atheros SoC support to include a method to enable/disable
the NAND flash controller.
Add the AR934x NAND flash controller reset routines.
(It's different on subsequent SoCs.)
Tested:
* AR9344, Atheros DB120 reference platform
Obtained from: OpenWRT
|
| 263295 |
18-Mar-2014 |
adrian |
Add the AR934x NAND flash controller register definitions.
Obtained from: OpenWRT
|
| 263279 |
17-Mar-2014 |
adrian |
Implement apb_print_child().
Tested:
* AR9344, Atheros DB120 Reference board
|
| 263229 |
16-Mar-2014 |
adrian |
The AR71xx has APB interrupts in the MISC registers from 0-7, later
chips have more.
So for now, let's allow more. We should teach the apb code to just
reject interrupts that lie outside what the chip can do at runtime.
|
| 263228 |
16-Mar-2014 |
adrian |
* Handle the three other timer interrupts for now, from the AR724x
later. If the interrupts are ACKed even if they're not masked, we get
the interrupts again later. Grr.
* The AR724x and later chips want the interrupt bits cleared by writing the
relevant bit to it, NOT by writing all but the current interrupt to it.
Tested:
* AR9344, DB120 reference board
TODO:
* Test ar724x and later chips to ensure no regressions have occured.
|
| 263224 |
16-Mar-2014 |
adrian |
Handle the case where both arge0 and arge1 MAC addresses are available via
'eeprommac'.
The existing driver would just make arge units past 0 take the primary
MAC and increment it by the unit number, without correct address wrapping.
That has to be fixed at a later date.
Tested:
* Atheros DB120 reference obard
|
| 262677 |
02-Mar-2014 |
adrian |
Add the USB EHCI flags required for the post-AR71xx devices.
Tested:
* DB120, AR9344
|
| 261870 |
14-Feb-2014 |
adrian |
Disable this check for now; it fails on the AR9344 PCI fixup code.
I'll make it conditional later.
Tested:
* DB120
|
| 261006 |
22-Jan-2014 |
adrian |
Use the correct bitshift operators for the GPIO definitions.
Submitted by: Daan Vreeken <Daan@vitsch.nl>
MFC after: 1 week
|
| 260889 |
19-Jan-2014 |
imp |
Introduce grab and ungrab upcalls. When the kernel desires to grab the
console, it calls the grab functions. These functions should turn off
the RX interrupts, and any others that interfere. This makes mountroot
prompt work again. If there's more generalized need other than
prompting, many of these routines should be expanded to do those new
things.
Reviewed by: bde (with reservations)
|
| 258780 |
30-Nov-2013 |
eadler |
Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this
shifts into the sign bit. Instead use (1U << 31) which gets the
expected result.
This fix is not ideal as it assumes a 32 bit int, but does fix the issue
for most cases.
A similar change was made in OpenBSD.
Discussed with: -arch, rdivacky
Reviewed by: cperciva
|
| 257338 |
29-Oct-2013 |
nwhitehorn |
Devices that rely on hints or identify routines for discovery need to
return BUS_PROBE_NOWILDCARD from their probe routines to avoid claiming
wildcard devices on their parent bus. Do a sweep through the MIPS tree.
MFC after: 2 weeks
|
| 257284 |
28-Oct-2013 |
glebius |
- Provide necessary includes, that before came via if.h pollution.
- Remove unnecessary ones.
Sponsored by: Netflix
Sponsored by: Nginx, Inc.
|
| 256649 |
16-Oct-2013 |
adrian |
Whilst here, document that this TX alignment requirement may acutally
not be required on later hardware.
It would allow for higher packet rates so yes, it would be nice
to disable it.
|
| 256648 |
16-Oct-2013 |
adrian |
Allow the MDIO bus frequency to be selected.
The MDIO bus frequency is configured as a divisor off of the MDIO bus
reference clock. For the AR9344 and later, the MDIO bus frequency can
be faster than normal (ie, up to 100MHz) and thus a static divisor may
not be very applicable.
So, for those boards that may require an actual frequency to be selected
regardless of what crazy stuff the vendor throws in uboot, one can now
set the MDIO bus frequency. It uses the MDIO frequency and the target
frequency to choose a divisor that doesn't exceed the target frequency.
By default it will choose:
* DIV_28 on everything; except
* DIV_58 on the AR9344 to be conservative.
Whilst I'm here, add some comments about the defaults being not quite
right. For the other internal switch devices (like the AR933x, AR724x)
the divisor can be higher - it's internal and the reference MDIO clock
is much lower than 100MHz.
The divisor tables and loop code is inspired from Linux/OpenWRT. It's very
simple; I didn't feel that reimplementing it would yield a substantially
different solution.
Tested:
* AR9331 (mips24k)
* AR9344 (mips74k)
Obtained from: Linux/OpenWRT
|
| 256575 |
16-Oct-2013 |
adrian |
Add in the platform specific quirks to get the AR934x SoC ethernet
up and running.
* The MAC FIFO configurations needed updating;
* Reset the MDIO block at the same time the MAC block is reset;
* The default divisor needs changing as the DB120 runs at a higher
base MDIO bus clock compared to other chips.
The long-term fix is to allow the system to have a target MDIO bus
clock rate and then calculate the most suitable divider to meet
that. This will likely need implementing before stable external
PHY or switch support can be committed.
Tested:
* AR9344 (mips74k)
* AR9331 (mips24k)
|
| 256573 |
16-Oct-2013 |
adrian |
Add in a write barrier after each if_arge write.
Without correct barriers, this code just plain doesn't work on the
mips74k cores (specifically the AR9344.)
In particular, the MDIO register accesses need this barriering or MII bus
access results in out-of-order garbage.
Tested:
* AR9344 (mips74k)
* AR9331 (mips24k)
|
| 256572 |
16-Oct-2013 |
adrian |
Add bus space barriers to the AR71xx SPI code.
This is required for correct, stable operation on the MIPS74k SoCs
that are dual-issue, superscalar pipelines.
Tested:
* AR9344 SoC (MIPS74k)
* AR9331 SoC (MIPS24k)
|
| 256491 |
15-Oct-2013 |
adrian |
Update the AR934x SoC support.
* Add the MDIO clock probe during clock initialisation;
* Update the ethernet PLL configuration function to use the correct
values;
* Add a GMAC block configuration to pull the configuration out of hints;
* Add an ethernet switch reconfiguration method.
Tested:
* AR9344 SoC (DB120)
.. however, this has been tested with extra patches in my tree (to fix
the ethernet/MDIO support, SPI support, ethernet switch support)
and thus it isn't enough to bring the full board support up.
|
| 256490 |
15-Oct-2013 |
adrian |
Update the AR933x SoC support to include a few new knobs:
* Initialise the MDIO clock to default to the reference clock;
* Add some code to allow the hints mechanism to allow setup of the GMAC
config block.
* Document how the switch is wired up internally.
Tested:
* AR9331 SoC (Carambola 2)
|
| 256488 |
15-Oct-2013 |
adrian |
Fix the Atheros MIPS startup path a little.
* Print out the platform frequency the same as the other frequencies.
* Print out the MDIO frequency.
* Optionally do GMAC and ethernet switch setup if required.
Tested:
* AR9344
|
| 256487 |
15-Oct-2013 |
adrian |
Add new features - an MDIO clock, WMAC reset, GMAC reset and ethernet
switch reset/initialise functions.
The AR934x and QC955x SoCs both have a configurable MDIO base clock.
The others have the MDIO clock use the same clock as the system
reference clock, whatever that may be.
Tested:
* AR9344 SoC
TODO:
* mips24k - AR933x would be fine for now, just to ensure that things
are sane.
|
| 256483 |
15-Oct-2013 |
adrian |
Add the rest of the AR934x SoC reset register definitions.
Obtained from: Linux/OpenWRT
|
| 256482 |
15-Oct-2013 |
adrian |
Add register definitions for the AR933x SoC GMAC (ie, ethernet MAC)
control block.
The GMAC configuration block allows for some configuration of how
the GMAC0 (ie, arge0) port is connected to the on-board switch
(if indeed there is one.) It both can be pushed into the on-board
switch; it could also be torn out and exposed via an external
MII (and that operational mode is also controllable.)
Obtained from: Linux/OpenWRT
|
| 256175 |
09-Oct-2013 |
adrian |
Add some missing AR934x register definitions.
These are needed for ethernet bootstrap.
Approved by: re@ (gjb)
|
| 256174 |
09-Oct-2013 |
adrian |
Fix interrupt handling from the APB periperals (ie, UART) - it
also requires an explicit acknowledgement.
Tested:
* AR9344 (DB120) SoC
Approved by: re@ (gjb)
|
| 255764 |
21-Sep-2013 |
adrian |
Fix the AR933x CPU UART support by using the correct clock when calculating
the UART frequency.
Tested:
* AR933x (carambola 2 board), UART now works again
Approved by: re
|
| 255335 |
06-Sep-2013 |
loos |
Remove the hardcoded limit for the number of gpio_pins that can be used.
Allocate it dynamically.
Approved by: adrian (mentor)
|
| 255334 |
06-Sep-2013 |
loos |
Fix an off-by-one bug in ar71xx_gpio and bcm2835_gpio which makes the last
pin unavailable.
Reported and tested by: sbruno (ar71xx)
Approved by: adrian (mentor)
Pointy hat to: loos
|
| 255300 |
06-Sep-2013 |
loos |
Fix the leakage of dma tags on if_arge. The leak occur when arge_start()
add some packet(s) to tx ring and arge_stop() is called before receive the
sent packet interrupt from hardware. Fix arge_stop() to unload the in use
dma tags and free the associated mbuf.
PR: 178319, 163670
Approved by: adrian (mentor)
|
| 255021 |
29-Aug-2013 |
loos |
Prevent the full restart cycle every time arge_start() is called. Only
(re)start the interface when it is down. This change fix a race with
BOOTP where the response packet is lost because the interface is being
reset by a netmask change right after send the packet.
PR: 178318
Approved by: adrian (mentor)
|
| 254990 |
28-Aug-2013 |
loos |
Make ar71xx_spi attach the next free unit of spibus and not only spibus0.
Approved by: adrian (mentor)
|
| 254690 |
23-Aug-2013 |
sbruno |
Some vendors store the mac addresses of arge(4) as a literal sring in the
form xx:xx:xx:xx:xx:xx complete with ":" characters taking of 18 bytes
instead of 6 integers. Expose a "readascii" tuneable to handle this case.
Remove restriction on eepromac assignement for the first dev instance only.
Add eepromac address for DIR-825 to hints file.
Add readascii hint for DIR-825
Reviewed by: adrian@
|
| 254234 |
12-Aug-2013 |
adrian |
Add a missing break.
|
| 253511 |
21-Jul-2013 |
adrian |
Implement some initial AR934x support routines.
This code reads the PLL configuration registers and correctly programs
things so the UART and such can come up.
There's MIPS74k platform issues that need fixing; but this at least brings
things up enough to echo stuff out the serial port and allow for interactive
debugging with ddb.
Tested:
* AR71xx SoCs
* AR933x SoC
* AR9344 board (DB120)
Obtained from: Qualcomm Atheros; Linux/OpenWRT
|
| 253510 |
21-Jul-2013 |
adrian |
Teach the GPIO code about the AR934x GPIO register and pin counts.
|
| 253509 |
21-Jul-2013 |
adrian |
Use the UART frequency when programming the UART clock.
This allows the 16550 support to work correctly on the upcoming
AR934x support.
|
| 253508 |
21-Jul-2013 |
adrian |
Initialise the watchdog and UART frequencies.
For all pre-AR933x chips, the frequency is just the APB frequency.
For the AR933x, the UART frequency is different but we just hacked around
it.
For the AR934x, there's a different PLL setting for these, so they have
to be broken out.
|
| 253507 |
21-Jul-2013 |
adrian |
Add two new CPU specific definitions - the watchdog clock frequency and
the UART clock frequency.
The AR933x and AR934x have separate PLL settings for these.
|
| 253028 |
08-Jul-2013 |
adrian |
Import the initial SoC register definitions for the AR934x MIPS74k SoC.
Obtained from: Linux/OpenWRT
|
| 253027 |
08-Jul-2013 |
adrian |
Add AR9341, AR9342, AR9344 SoC types.
|
| 250165 |
02-May-2013 |
adrian |
Add the AR933x SoC GPIO pin count limitation.
|
| 249449 |
13-Apr-2013 |
dim |
Fix undefined behaviour in several gpio_pin_setflags() routines (under
sys/arm and sys/mips), squelching the clang 3.3 warnings about this.
Noticed by: tinderbox and many irate spectators
Submitted by: Luiz Otavio O Souza <loos.br@gmail.com>
PR: kern/177759
MFC after: 3 days
|
| 249126 |
05-Apr-2013 |
adrian |
Implement USB device reset and poweron.
Tested:
* Atheros AP131, AR9331 SoC
|
| 249125 |
05-Apr-2013 |
adrian |
Fix AR933x USB support - this needs the same controller initialisation
as the AR7242.
Tested:
* Atheros AP121, AR9331
* ZyDas wifi device, and 64MB (yes, ew) USB flash storage
|
| 249123 |
05-Apr-2013 |
adrian |
Implement the AR933x ethernet support.
Obtained from: OpenWRT
|
| 249120 |
05-Apr-2013 |
adrian |
Implement the AR933x interrupt driven UART code.
* Enable RX and host interrupts during bus probe/attach
* Disable all interrupts (+ host ISR) during bus detach
* Enable TX DONE interrupt only when we start transmitting; clear it when
we're done.
* The RX/TX FIFO depth is still conjecture on my part. I'll fix this
shortly.
* The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty"
interrupt. Sigh. So..
* .. in ar933x_bus_transmit(), wait for the FIFO to drain before
continuing.
I dislike having to wait for the FIFO to drain, alas.
Tested:
* Atheros AP121 board, AR9331 SoC.
TODO:
* RX/TX overflow, RX error, BREAK support, etc.
* Figure out the true RX/TX FIFO depth.
|
| 249119 |
05-Apr-2013 |
adrian |
AR9330/AR9331 also needs to ACK the APB interrupt register, same as
AR724x.
This fixes 'stuck interrupt' problems I was having when writing the
uart interrupt code.
|
| 249118 |
05-Apr-2013 |
adrian |
* Add AR9330/AR9331 to the soc identifier enum;
* Set it when probing the CPU type.
|
| 249093 |
04-Apr-2013 |
adrian |
Implement AR933x polled IO uart bus code.
This implements the bus transmit/receive/sigchg/ipend methods with
a polled interrupt handler (ipend) rather than enabling hardware
interrupts.
The FIFO is faked at 16 bytes deep for now, just so the transmit
IO side doesn't suck too bad (the callout frequency limits how quickly
IO is flushed to the sender, rather than scheduling the callout more
frequently whilst there's active TX. But I digress.)
Tested:
* Atheros AP121 (AR9330) reference board, booting to multi-user interactive
mode.
|
| 248927 |
30-Mar-2013 |
adrian |
AR933x CPU device improvements:
* Add baud rate and divisor programming code. See below for more
information.
* Flesh out ar933x_init() to disable interrupts and program the initial
console setup.
* Remove #if 0'ed code from ar933x_term().
* Explain what these functions do.
Now, the baud rate and divisor code comes from Linux, as a submission
to the OpenWRT project and Linux kernel from
Gabor Juhos <juhosg@openwrt.org>.
The original ticket for this code is https://dev.openwrt.org/ticket/12031 .
I've contacted Gabor and asked for his permission to also licence the patch
in question (which covers this code) to BSD lience and he's agreed.
Hence why I'm including it here in FreeBSD.
Tested:
* AP121 (AR9330)
|
| 248926 |
30-Mar-2013 |
adrian |
AR933x UART updates:
* Default clock is 25MHz;
* Remove the UART register macro here - it's not needed as we don't need
to "adjust" the register offset / spacing at all;
* Remove unused fields in the softc.
Tested:
* AP121
|
| 248867 |
29-Mar-2013 |
adrian |
For the AR933x UART, the serial clock is not the AHB clock, it's the
reference clock. So use that instead.
|
| 248866 |
29-Mar-2013 |
adrian |
* Fix clock register definitions
* Add maximum clock register values
|
| 248865 |
29-Mar-2013 |
adrian |
Print out the platform reference frequency.
This is useful for AR933x platforms where that matters.
|
| 248844 |
28-Mar-2013 |
adrian |
Tie in the AR933x support into -HEAD.
|
| 248843 |
28-Mar-2013 |
adrian |
Bring over the initial, CPU-only UART support for the AR933x SoC.
This implements the kernel glue needed (getc, putc, rxready).
This isn't a 16550 UART, even if the datasheet overview claims so.
The Linux ar933x support was used as a reference, however the uart code
is a reimplementation.
Attentive viewers will note that the uart code is based off of the ns8250
code and the UART bus code is a stubbed-out version of this. I'll be
replacing it with non-stubbed versions soon, making this a fully featured
driver.
Tested:
* AP121 reference board (AR933x), booting through the mountroot> prompt;
then doing some basic interactive tests in ddb.
|
| 248809 |
28-Mar-2013 |
adrian |
Fix the AR933x platform device start/stop code.
This was ported from the AR724x code and I think that also doesn't
quite work. I'll investigate that soon.
With this in place the system reset path works, so 'reset' from kdb
actually resets the SoC.
Tested:
* AP121 test board
|
| 248782 |
27-Mar-2013 |
adrian |
Commit initial (unfinished!) support for the AR933x series of embedded
CPUs.
The AR933x is a mips24k based SoC with an AR9380 series SoC on board,
two gigabit ethernet interfaces and an internal 10/100mbit ethernet
switch. There's also the normal interfaces (USB, ethernet, uart, GPIO.)
The downside? There's a non-ns8250 UART device.
With a very basic UART driver (not in this commit) the SoC is initialised
and boots up. I'll commit the UART code soon and then link it into the
general setup path.
This code is a re-implementation based from the Linux kernel / openwrt
AR933x support.
TODO:
* UART (obviously)
* All of the ethernet, USB and wifi SoC glue, including ethernet PLL
programming.
|
| 248781 |
27-Mar-2013 |
adrian |
Add the reference clock for each supported chip.
Obtained from: Linux (openwrt)
|
| 245112 |
06-Jan-2013 |
monthadar |
Mips Atheros AR71XX: make PCI base slot configurable through hints.
* Mikrotik RouterBoard 433AH have PCI slot 18 wired to INT0 on the PCI Bus.
This is different from e.g. Atheros PB42 and Ubiquiti boards.
* Check for hint hint.pcib.0.baseslot=X, where X is number of base slot;
* If hint not supplied print a warning and use default AR71XX_PCI_BASE_SLOT;
PR: kern/174978
Approved by: adrian (mentor)
|
| 243882 |
05-Dec-2012 |
glebius |
Mechanically substitute flags from historic mbuf allocator with
malloc(9) flags within sys.
Exceptions:
- sys/contrib not touched
- sys/mbuf.h edited manually
|
| 243179 |
17-Nov-2012 |
adrian |
Make MIPS24k PMC optional on "hwpmc_mips24k."
Requested by: juli
|
| 243177 |
17-Nov-2012 |
adrian |
Migrate the AR71xx UART (an 8250 derivative) to hide behind uart_ar71xx.
The AR9330/AR9331 UART is a totally different thing, so having it included
with 'uart' is not going to work out.
|
| 239706 |
26-Aug-2012 |
adrian |
Ensure that BAR(0) is set for the PCI slot before the ath(4) PCI registers
are written out.
This allows EEPROM-less NICs on the AR7241 PCIe bus to be correctly
initialised.
Tested:
* AP91 (AR7240+AR9285) - the existing board support didn't break;
* AP99 (AR7241+AR9287) - this fixed the configuration of the AR9287 PCI.
|
| 239351 |
17-Aug-2012 |
rpaulo |
The GPIO drivers were initialising their mutexes with type of
MTX_NETWORK_LOCK. This is wrong since these mutexes have nothing to do
with networking.
|
| 234992 |
04-May-2012 |
adrian |
Disable setting the MII port speed.
This seems to break at least my test board here (AR71xx + AR8316 switch
PHY). Since I do have a whole sleuth of "normal" PHY boards (with
an AR71xx on a normal PHY port), I'll do some further testing with those
to determine whether this is a general issue, or whether it's limited
to the behaviour of the "fake" dedicated PHY port mode on these atheros
switches.
|
| 234941 |
03-May-2012 |
adrian |
Fix a totally bone-headed, last minute bounds check snafu that somehow
I must've missed when booting a test kernel.
This has been validated on the AR7161.
|
| 234919 |
02-May-2012 |
adrian |
Implement PLL configuration override support, similar to what openwrt
implements.
|
| 234910 |
02-May-2012 |
adrian |
Allow the MII mode to be overridden via 'hint.arge.X.miimode'.
It takes a number at the moment, rather than a string.
Some of the Linux board configurations specify the MII mode explicitly.
|
| 234909 |
02-May-2012 |
adrian |
Add a missing newline.
|
| 234907 |
02-May-2012 |
adrian |
Further ar71xx MII support improvements.
* Flesh out the PLL configuration fetch function, which will return the PLL
configuration based on the unit number and speed.
* Remove the PLL speed config logic from the AR71xx/AR91xx chip PLL config
function - pass in a 'pll' value instead.
* Modify arge_set_pll() to:
+ fetch the PLL configuration
+ write the PLL configuration
+ update the MII speed configuration.
This will allow if_arge to override the PLL configuration as required.
Obtained from: Linux/Atheros/OpenWRT
|
| 234906 |
02-May-2012 |
adrian |
MII related infrastructure changes.
* Add a new method to set the MII mode - GMII, RGMII, RMII, MII.
+ arge0 supports all four (two for non-Gige interfaces.)
+ arge1 only supports two (one for non-gige interfaces.)
* Set the MII clock speed when changing the MAC PLL speed.
+ Needed for AR91xx and AR71xx; not needed for AR724x.
Tested:
* AR71xx only, I'll do AR913x testing tonight and fix whichever issues
creep up.
TODO:
* Implement the missing AR7242 arge0 PLL configuration, but don't
adjust the MII speed accordingly.
* .. the AR7240/AR7241 don't require this, so make sure it's not set
accidentally.
Bugs (not fixed here):
* Statically configured arge speeds are still broken - investigate why
that is on the AP96 board. Autonegotiate is working fine, but there
still seems to be an occasionally heavy packet loss issue.
Obtained from: Linux/Atheros/OpenWRT
|
| 234905 |
02-May-2012 |
adrian |
Introduce an enum which encapsulates the PHY interface types that can be
configured.
|
| 234900 |
01-May-2012 |
adrian |
Add in the MII configuration parameters for the AR71xx.
Obtained from: Linux/OpenWRT
|
| 234862 |
01-May-2012 |
adrian |
Break out the arge MDIO bus code into an optional argemdio device.
This is only done if the ARGE_MDIO option is included.
* Shuffle the arge MDIO bus into a separate device, that needs to be
probed early (use hint.argemdio.X.order=0)
* hint.arge.X.mdio now specifies which miiproxy to rendezvous with.
* Call MAC/MDIO bus init during MDIO attach, not arge attach.
This is done regardless:
* Shift the arge MAC and MDIO bus reset code into separate functions
and call it early during MDIO bus attach. It's required for
correct MDIO bus IO to occur on AR71xx/AR91xx devices.
* Remove the AR71xx/AR91xx centric assumption that there's only one
MDIO bus. The initial code mapped miibus0(arge0) and miibus1(arge1)
MII register operations to the MII0 (arge0) register space. The
AR724x (and later, upcoming chipsets) have two MDIO busses and
the second is very much in use.
TODO:
* since the multiphy behaviour has changed (where now a phymask of >1
PHY will still be enumerated), multiphy setups may be quite wrong.
I'll go and fix these so they still have a chance of working, at least.
until the switch PHY support appears in -HEAD.
Submitted by: Stefan Bethke <stb@lassitu.de>
|
| 234859 |
01-May-2012 |
adrian |
Migrate ARGE_DEBUG to opt_arge.h.
Submitted by: Stefan Bethke <stb@lassitu.de>
|
| 234515 |
20-Apr-2012 |
adrian |
Allow for a default GPIO pin "high", which is required for some boards
which tie the USB device enable to a GPIO line.
Submitted by: Stefan Bethke <stb@lassitu.de>
|
| 234485 |
20-Apr-2012 |
adrian |
Introduce the matching PCI ath(4) fixup code from ar71xx_pci into
ar724x_pci.c.
* Move out the code which populates the firmware into ar71xx_fixup.c
* Shuffle around the ar724x fixup code to match what the ar71xx fixup
code does.
I've validated this on an AR7240 with AR9285 on-board NIC. It doesn't
yet load, as the AR9285 EEPROM code needs to be made "flash aware."
TODO:
* Validate that I haven't broken AR71xx
* Test AR9285/AR9287 onboard NICs, complete with EEPROM code changes
* Port over the needed BAR hacks for AR7240, AR7241 and AR7242 from
Linux OpenWRT. The current WAR has only been tested on the AR7240
and I'm not sure the way the BAR register is treated is "right".
The "fixup" method here is right when setting the BAR for local access -
ie, the BAR address is either 0xffff (AR7240) or 0x1000ffff (AR7241/AR7242),
but the ath9k-fixup.c code (Linux OpenWRT) does this when setting the
initial "fixup" BAR. It then restores the original BAR.
I'll have to read the ar724x PCI bus glue to see what other special cases
await.
|
| 234366 |
17-Apr-2012 |
adrian |
Style(9) and white space fixes.
|
| 234365 |
17-Apr-2012 |
adrian |
Protect the PCI space registers behind a mutex.
Obtained from: Linux/OpenWRT, Atheros
|
| 234326 |
15-Apr-2012 |
adrian |
The AR913x MII speed configuration matches the AR71xx MII configuration.
So share the code.
Don't do it for the AR724x - that has a completely different set of PLL
and MII configuration parameters.
|
| 234306 |
15-Apr-2012 |
adrian |
Fix the mask logic when reading PCI configuration space registers.
|
| 234217 |
13-Apr-2012 |
adrian |
(ab)Use the firmware API to store away EEPROM calibration data for
future use by the ath(4) driver.
These embedded devices put the calibration/PCI bootstrap data on the
on board SPI flash rather than on an EEPROM connected to the NIC.
For some boards, there's two NICs and two sets of EEPROM data in the
main SPI flash.
The particulars:
* Introduce ath_fixup_size, which is the size of the EEPROM area in
bytes.
* Create a firmware image with a name based on the PCI device identifier
(bus/slot/device/function).
* Hide some verbose debugging behind 'bootverbose'.
ath(4) can then use this to load in the EEPROM data.
This requires AR71XX_ATH_EEPROM to be defined.
|
| 234205 |
13-Apr-2012 |
adrian |
Remove an unused variable. Grr.
|
| 234204 |
13-Apr-2012 |
adrian |
Sync this code against what's in OpenWRT trunk.
* the openwrt code doesn't treat 0/0/0 any differently
from other bus/slot/func combinations.
* A "local write" function writes to the LCONF area, and
so I've added it.
* The PCI workaround at attach time uses this LCONF code,
which it already did ..
* .. but it is a 4 byte write, not a 2 byte write.
Even though it's PCIR_COMMAND which is a two byte PCI register.
Tested on: AR7161
TODO: The other two AR71xx derivatives
TODO: More thoroughly stare at the datasheets I do have
and if it indeed is incorrect, push fixes to both
FreeBSD and Linux/OpenWRT.
Obtained from: Linux OpenWRT
|
| 233644 |
29-Mar-2012 |
jmallett |
Assume a big-endian default on MIPS and drop the "eb" suffix from MACHINE_ARCH.
This makes our naming scheme more closely match other systems and the
expectations of much third-party software. MIPS builds which are little-endian
should require and exhibit no changes. Big-endian TARGET_ARCHes must be
changed:
From: To:
mipseb mips
mipsn32eb mipsn32
mips64eb mips64
An entry has been added to UPDATING and some foot-shooting protection (complete
with warnings which should become errors in the near future) to the top-level
base system Makefile.
|
| 233319 |
22-Mar-2012 |
gonzo |
Rework MIPS PMC code:
- Replace MIPS24K-specific code with more generic framework that will
make adding new CPU support easier
- Add MIPS24K support for new framework
- Limit backtrace depth to 1 for stability reasons and add option
HWPMC_MIPS_BACKTRACE to override this limitation
|
| 233318 |
22-Mar-2012 |
gonzo |
Move PMC hook invocation to cpu_intr. The idea is the same as with ast()
call but there is no reason to implement it in assembler.
|
| 233104 |
18-Mar-2012 |
gonzo |
- Fix logic for detection if further processing of PMC should be performed.
pmc_intr returns one if one of the counters actually triggered the IRQ
- style(9) fixed
|
| 233082 |
17-Mar-2012 |
adrian |
style(9) changes.
|
| 233081 |
17-Mar-2012 |
adrian |
Begin fleshing out MII clock rate configuration changes.
These are needed for some particular port configurations where the default
speed isn't suitable for all link speed types. (Ie, changing 10/100/1000MBit
PLL rate requires a similar MII clock rate, rather than a fixed MII rate.)
This is:
* only currently implemented for the ar71xx;
* isn't used anywhere (yet), as the final interface for this hasn't yet
been determined.
|
| 232916 |
13-Mar-2012 |
adrian |
Remove a now unneeded ARGE_UNLOCK().
Whilst I'm here, remove a couple blank lines.
|
| 232914 |
13-Mar-2012 |
adrian |
Fix link status handling on if_arge upon system boot to allow bootp/NFS to
function.
From the submitter:
This patch fixes an issue I encountered using an NFS root with an
ar71xx-based MikroTik RouterBoard 450G on -current where the kernel fails
to contact a DHCP/BOOTP server via if_arge when it otherwise should be able
to. This may be the same issue that Monthadar Al Jaberi reported against
an RSPRO on 6 March, as the signature is the same:
%%%
DHCP/BOOTP timeout for server 255.255.255.255
DHCP/BOOTP timeout for server 255.255.255.255
DHCP/BOOTP timeout for server 255.255.255.255
.
.
.
DHCP/BOOTP timeout for server 255.255.255.255
DHCP/BOOTP timeout for server 255.255.255.255
arge0: initialization failed: no memory for rx buffers
DHCP/BOOTP timeout for server 255.255.255.255
arge0: initialization failed: no memory for rx buffers
%%%
The primary issue that I found is that the DHCP/BOOTP message that
bootpc_call() is sending never makes it onto the wire, which I believe is
due to the following:
- Last December, a change was made to the ifioctl that bootpc_call() uses
to adjust the netmask around the sosend().
- The new ioctl (SIOCAIFADDR) performs an if_init when invoked, whereas the
old one (SIOCSIFNETMASK) did not.
- if_arge maintains its own sense of link state in sc->arge_link_status.
- On a single-phy interface, sc->arge_link_status is initialized to 0 in
arge_init_locked().
- sc->arge_link_status remains 0 until a phy state change notification
causes arge_link_task to run, notice the link is up, and set it to 1.
- The inits caused by the ifioctls in bootpc_call are reinitializing the
interface, but not the phy, so sc->arge_link_status goes to 0 and remains
there.
- arge_start_locked() always sees sc->arge_link_status == 0 and returns
without queuing anything.
The attached patch changes arge_init_locked() such that in the single-phy
case, instead of initializing sc->arge_link_status to 0, it runs
arge_link_task() to set it according to the current phy state. This change
has allowed my setup to mount an NFS root successfully.
Submitted by: Patrick Kelsey <kelsey@ieee.org>
Reviewed by: juli
|
| 232912 |
13-Mar-2012 |
adrian |
Correctly (I hope) deallocate the if_arge RX buffer ring on arge_stop().
I had some interesting hangs until I realised I should try flushing the
DDR FIFO register and lo and behold, hangs stopped occuring.
I've put in a few DDR flushes here and there in case people decide to
reuse some of these functions. It's very very likely they're almost
all superflous.
To test:
* Connect to a network with a _lot_ of broadcast traffic
* Do this:
# while true; do ifconfig arge0 down; ifconfig arge0 up; done
This fixes the mbuf exhaustion that has been reported when the interface
state flaps up/down.
|
| 232896 |
12-Mar-2012 |
jmallett |
o) Use ABI, not ISA_* options, to determine whether to compile bits if libkern
required for the ABI the kernel is being built for.
XXX This is implemented in a kind-of nasty way that involves including source
files, but it's still an improvement.
o) Retire ISA_* options since they're unused and were always wrong.
|
| 232853 |
12-Mar-2012 |
jmallett |
Remove platform APIs which are not used by any code and which had only stub
implementations or no implementation on all platforms.
Some of these functions might be good ideas, but their semantics were unclear
given the lack of implementation, and an unlucky porter could be fooled into
trying to implement them or, worse, being baffled when something like
platform_trap_enter() failed to be called.
|
| 232847 |
12-Mar-2012 |
gonzo |
- Rename apb_intr to apb_filter since it's a filter handler
- Pass interrupt trapframe for handlers dow the chain
- Add PMC interrupt handler
PMC interrupt is a special case, so we want handle it as soon as possible
with minimum overhead. So we handle it apb filter routine.
|
| 232628 |
06-Mar-2012 |
ray |
Break long lines.
Approved by: adri (mentor)
|
| 232627 |
06-Mar-2012 |
ray |
Remove EoL whitespaces.
Approved by: adri (mentor)
|
| 230195 |
16-Jan-2012 |
adrian |
Stop overloading opt_global.h.
|
| 230148 |
15-Jan-2012 |
adrian |
Some of the atheros based embedded devices use one or more PCI NICs
on-board, glued to the AR71xx CPU. These may forgo separate WMAC EEPROMs
(which store configuration and calibration data) and instead store
it in the main board SPI flash.
Normally the NIC reads the EEPROM attached to it to setup various PCI
configuration registers. If this isn't done, the device will probe as
something different (eg 0x168c:abcd, or 0x168c:ff??.) Other setup registers
are also written to which may control important functions.
This introduces a new compile option, AR71XX_ATH_EEPROM, which enables the
use of this particular code. The ART offset in the SPI flash can be
specified as a hint against the relevant slot/device number, for example:
hint.pcib.0.bus.0.17.0.ath_fixup_addr=0x1fff1000
hint.pcib.0.bus.0.18.0.ath_fixup_addr=0x1fff5000
TODO:
* Think of a better name;
* Make the PCIe version of this fixup code also use this option;
* Maybe also check slot 19;
* This has to happen _before_ the SPI flash is set from memory-mapped
to SPI-IO - so document that somewhere.
|
| 229765 |
07-Jan-2012 |
adrian |
Fix the ar724x shift calculation when writing to the PCI config space.
This was preventing the ath driver from being loaded at runtime.
It worked fine when compiled statically into the kernel but not when
kldload'ed after the system booted.
The root cause was that PCIR_INTLINE (register 60) was being
overwritten by zeros when register 62 was being written to.
A subsequent read of this register would return 0, and thus
the rest of the PCI glue assumed an IRQ resource had already
been allocated. This caused the device to fail to attach at
runtime as the device itself didn't contain any IRQ resources.
TODO: go back over the ar71xx and ar724x PCI config read/write
code and ensure it's correct.
|
| 228725 |
20-Dec-2011 |
adrian |
Remove these locks - they aren't strictly needed and cause measurable
performance issues.
* Access to the GPIO bus is already locked by requesting
and releasing the bus - thus the lock isn't really needed
for each GPIO pin change.
* Don't lock and unlock the GPIO bus for -each- i2c access -
the i2c bus code is already doing this by calling the upper
layer callback to request/release the bus. This thus locks
the bus for the entirety of the transaction.
TODO:
* Further verify that everything is correctly requesting/
releasing the GPIO bus.
* Look at how to lock the GPIO pin configuration stuff,
potentially by locking/unlocking the bus at the gpiobus
layer.
|
| 228518 |
15-Dec-2011 |
adrian |
Re-jiggle the GPIO code a little to remove the hard-coded AR71xx GPIO
config and function mask setup.
* "gpiomask" now specifies which GPIO pins to enable, for devices to bind to.
* "function_set" allows bits in the function register to be set at GPIO setup.
* "function_clear" allows bits in the function register to be cleared at
GPIO setup.
The function_set/function_clear bits allow for individual GPIO pins to either
drive a GPIO line or an alternate function - eg USB, JTAG, etc. This allows
for things like CS1/CS2 be enabled for those boards w/ >1 SPI device connected,
or disabling JTAG for the AR7240 (which is apparently needed ..)
I've verified this on the AR71xx.
|
| 228483 |
14-Dec-2011 |
hselasky |
Implement better support for USB controller suspend and resume.
This patch should remove the need for kldunload of USB
controller drivers at suspend and kldload of USB controller
drivers at resume.
This patch also fixes some build issues in avr32dci.c
MFC after: 2 weeks
|
| 228450 |
13-Dec-2011 |
adrian |
Style(9) changes.
|
| 228064 |
28-Nov-2011 |
ray |
Simplify arge_flush_ddr to use updated ar71xx_device_flush_ddr_ge(unit).
Approved by: adrian (mentor)
|
| 228050 |
28-Nov-2011 |
glebius |
Fix build, fininshing r228018.
|
| 228018 |
27-Nov-2011 |
ray |
Join chip depended methods for arge0 and arge1 into single call with unit.
Approved by: adrian (mentor)
|
| 227924 |
24-Nov-2011 |
adrian |
Introduce a new (global, sorry!) option which controls whether
the ar71xx platform code should assume a uboot or redboot environment.
The current code gets very confused (and just crashes) on a uboot
environment, where each attribute=value pair is in a single entry.
Redboot on the other hand stores it as "attribute", "value", "attribute",
"value", ...
This allows the kernel to boot on a TP-LINK TL-WR1043ND from flash,
where the uboot environment gets setup. This didn't show up during a netboot
as "tftpboot" and "go" don't setup the uboot environment variables.
|
| 227849 |
22-Nov-2011 |
hselasky |
Rename device_delete_all_children() into device_delete_children().
Suggested by: jhb @ and marius @
MFC after: 1 week
|
| 227843 |
22-Nov-2011 |
marius |
- There's no need to overwrite the default device method with the default
one. Interestingly, these are actually the default for quite some time
(bus_generic_driver_added(9) since r52045 and bus_generic_print_child(9)
since r52045) but even recently added device drivers do this unnecessarily.
Discussed with: jhb, marcel
- While at it, use DEVMETHOD_END.
Discussed with: jhb
- Also while at it, use __FBSDID.
|
| 226478 |
17-Oct-2011 |
yongari |
Close a race where SIOCGIFMEDIA ioctl get inconsistent link status.
Because driver is accessing a common MII structure in
mii_pollstat(), updating user supplied structure should be done
before dropping a driver lock.
Reported by: Karim (fodillemlinkarimi <> gmail dot com)
|
| 223562 |
26-Jun-2011 |
kevlo |
Remove duplicate header includes
|
| 221518 |
06-May-2011 |
adrian |
Fix GPIO_MAXPINS calculation for the AR71xx, AR724x, AR913x SoC.
Submitted by: Luiz Otavio O Souza <loos.br@gmail.com>
|
| 221407 |
03-May-2011 |
marius |
- Remove attempts to implement setting of BMCR_LOOP/MIIF_NOLOOP
(reporting IFM_LOOP based on BMCR_LOOP is left in place though as
it might provide useful for debugging). For most mii(4) drivers it
was unclear whether the PHYs driven by them actually support
loopback or not. Moreover, typically loopback mode also needs to
be activated on the MAC, which none of the Ethernet drivers using
mii(4) implements. Given that loopback media has no real use (and
obviously hardly had a chance to actually work) besides for driver
development (which just loopback mode should be sufficient for
though, i.e one doesn't necessary need support for loopback media)
support for it is just dropped as both NetBSD and OpenBSD already
did quite some time ago.
- Let mii_phy_add_media() also announce the support of IFM_NONE.
- Restructure the PHY entry points to use a structure of entry points
instead of discrete function pointers, and extend this to include
a "reset" entry point. Make sure any PHY-specific reset routine is
always used, and provide one for lxtphy(4) which disables MII
interrupts (as is done for a few other PHYs we have drivers for).
This includes changing NIC drivers which previously just called the
generic mii_phy_reset() to now actually call the PHY-specific reset
routine, which might be crucial in some cases. While at it, the
redundant checks in these NIC drivers for mii->mii_instance not being
zero before calling the reset routines were removed because as soon
as one PHY driver attaches mii->mii_instance is incremented and we
hardly can end up in their media change callbacks etc if no PHY driver
has attached as mii_attach() would have failed in that case and not
attach a miibus(4) instance.
Consequently, NIC drivers now no longer should call mii_phy_reset()
directly, so it was removed from EXPORT_SYMS.
- Add a mii_phy_dev_attach() as a companion helper to mii_phy_dev_probe().
The purpose of that function is to perform the common steps to attach
a PHY driver instance and to hook it up to the miibus(4) instance and to
optionally also handle the probing, addition and initialization of the
supported media. So all a PHY driver without any special requirements
has to do in its bus attach method is to call mii_phy_dev_attach()
along with PHY-specific MIIF_* flags, a pointer to its PHY functions
and the add_media set to one. All PHY drivers were updated to take
advantage of mii_phy_dev_attach() as appropriate. Along with these
changes the capability mask was added to the mii_softc structure so
PHY drivers taking advantage of mii_phy_dev_attach() but still
handling media on their own do not need to fiddle with the MII attach
arguments anyway.
- Keep track of the PHY offset in the mii_softc structure. This is done
for compatibility with NetBSD/OpenBSD.
- Keep track of the PHY's OUI, model and revision in the mii_softc
structure. Several PHY drivers require this information also after
attaching and previously had to wrap their own softc around mii_softc.
NetBSD/OpenBSD also keep track of the model and revision on their
mii_softc structure. All PHY drivers were updated to take advantage
as appropriate.
- Convert the mebers of the MII data structure to unsigned where
appropriate. This is partly inspired by NetBSD/OpenBSD.
- According to IEEE 802.3-2002 the bits actually have to be reversed
when mapping an OUI to the MII ID registers. All PHY drivers and
miidevs where changed as necessary. Actually this now again allows to
largely share miidevs with NetBSD, which fixed this problem already
9 years ago. Consequently miidevs was synced as far as possible.
- Add MIIF_NOMANPAUSE and mii_phy_flowstatus() calls to drivers that
weren't explicitly converted to support flow control before. It's
unclear whether flow control actually works with these but typically
it should and their net behavior should be more correct with these
changes in place than without if the MAC driver sets MIIF_DOPAUSE.
Obtained from: NetBSD (partially)
Reviewed by: yongari (earlier version), silence on arch@ and net@
|
| 221307 |
01-May-2011 |
adrian |
Some AR724x PCIe fixes, which should wrap up the first round
of endian-ness issues with the AR724x.
From Luiz:
* Fix the bus space tag used so endian-ness is correctly handled;
* Only do the workaround for the AR7240; AR7241/AR7242 (PB92)
don't require this
From me:
* Add a read flush from openwrt
Submitted by: Luiz Otavio O Souza
|
| 221257 |
30-Apr-2011 |
adrian |
The AR724x SoC's require the irq status line to be acked/cleared.
This allows console IO to occur correctly once the kernel is in multi-user
mode.
Submitted by: Luiz Otavio O Souza
|
| 221256 |
30-Apr-2011 |
adrian |
Call the DDR FIFO flush method when IP2 interrupts occur.
|
| 221255 |
30-Apr-2011 |
adrian |
Flip off debugging for now.
|
| 221254 |
30-Apr-2011 |
adrian |
Add some initial PCIe bridge support for the AR724x chipsets.
This is reported to work on the AR7240 based Ubiquiti Rocket M5
but I haven't tested it on that hardware. I also don't yet have
it fully working on the AR7242 based development board here;
probe/attach functions but the register space resource looks like
the endian-ness is wrong (0x10000000 instead of 0x00001000).o
Further digging will be required.
Submitted by: Luiz Otavio O Souza
|
| 221252 |
30-Apr-2011 |
adrian |
In preparation for the AR724x PCIe bus code, make the AR71xx PCI bus
glue require 'device ar71xx_pci' .
Users of the AR71xx board configs will now require this for functioning
PCI:
device pci
device ar71xx_pci
|
| 221240 |
30-Apr-2011 |
adrian |
Add a missing DDR FIFO method for the ar71xx.
|
| 221198 |
29-Apr-2011 |
adrian |
Tidy up the naming of the ip2 DDR flush routine, and add an inline
accessor method (which is currently unused) in there.
|
| 221160 |
28-Apr-2011 |
adrian |
Add the IP2 DDR flush handlers.
These aren't yet used in the interrupt handler path but should be.
|
| 220558 |
12-Apr-2011 |
hselasky |
We don't need to call EOWRITE4(sc, EHCI_USBINTR, 0) directly from each EHCI
bus driver at detach, hence ehci_detach() does exactly this since r199718.
Submitted by: Luiz Otavio O Souza
MFC after: 7 days
Approved by: thompsa (mentor)
|
| 220357 |
05-Apr-2011 |
adrian |
if_arge has had a strange bug that only appears during high traffic
levels. TX would hang, RX wouldn't. A bit of digging showed the interface
send queue was full, but IFF_DRV_OACTIVE was clear and the hardware TX
queue was empty.
It turns out that there wasn't a check to drain the interface send
queue once hardware TX had completed, so if the interface send queue
had filled up in the meantime, subsequent packets would be dropped
by the higher layers and if_start (and thus arge_start()) would never
be called.
The fix is simple - call arge_start_locked() in the software interrupt
handler after the hardware TX queue has been handled or a TX underrun
occured. This way the interface send queue gets drained.
|
| 220356 |
05-Apr-2011 |
adrian |
* Add some more debugging to if_arge
* Make doubly sure that IFF_DRV_OACTIVE is set if the hardware TX queue is full
|
| 220355 |
05-Apr-2011 |
adrian |
Put the ARGE_DEBUG behind a kernel config option.
|
| 220354 |
05-Apr-2011 |
adrian |
Begin fleshing out a functioning debugging setup for if_arge.
I'm seeing TX hangs when doing large amounts of TX traffic;
an interface reset fixes it. This will hopefully help me identify
why.
|
| 220303 |
03-Apr-2011 |
hselasky |
- Correct EHCI interrupt disabling at detach.
Submitted by: Luiz Otavio O Souza
MFC after: 7 days
Approved by: thompsa (mentor)
|
| 220296 |
03-Apr-2011 |
adrian |
Add in some missing flags in the EHCI initialisation code,
needed to get USB working on the AR913x/AR724x.
|
| 220260 |
02-Apr-2011 |
adrian |
A handful of the openwrt devices use a MAC address that's at a hard-coded
offset in the flash.
Some devices (eg the TPLink WR-1043ND) don't have a flash environment
partition which can be queried for the current board settings.
This particular workaround allows for image creators to use a hint
to set the base MAC address. For example:
hint.arge.0.eeprommac=0x1f01fc00
|
| 220180 |
31-Mar-2011 |
adrian |
Implement AR724x USB initialisation code.
This (again) still requires an offset for the AR913x/AR724x before USB will
function.
Submitted by: Luiz Otavio O Souzau <loos.br@gmail.com>
|
| 220096 |
28-Mar-2011 |
adrian |
The previous commit didn't completely rename this to what it should be.
|
| 220056 |
27-Mar-2011 |
adrian |
Refactor out the ar71xx mac address code into something that's
just for Redboot.
At some point we're going to need to build options for different
boot environments - for example, the UBoot setups I've seen simply
have the MAC address hard-coded at a fixed location in flash.
The OpenWRT support simply yanks the if_arge MAC directly from that
in code, rather than trying to find a uboot environment to pull it
from.
|
| 220052 |
27-Mar-2011 |
adrian |
Add an option - AR71XX_REALMEM - which overrides the amount of
memory detected from Redboot, or overrides the "otherwise" case
if no Redboot information was found.
Some AR71XX platforms don't use Redboot (eg TP-LINK devices using
UBoot; some later Ubiquiti devices which apparently also use
UBoot) and at least one plain out lies - the Ubiquiti LS-SR71A
Redboot says there's 16mb of RAM when in fact there's 32mb.
A more "clean" solution will be needed at a later date.
|
| 220051 |
27-Mar-2011 |
adrian |
Add some missing flags needed for AR913x/AR724x USB to correctly operate.
The AR913x/AR724x USB lives at a different offset to the AR71xx
USB, so this needs to be either adjusted for in a subsequent
commit, or updated in hints for kernels compiled for those
platforms.
Submitted by: Luiz Otavio O Souzau <loos.br@gmail.com>
|
| 219592 |
13-Mar-2011 |
adrian |
* Add wireless MAC reset, in prep for bringing over AR9130 support.
* Whilst I'm here, reformat to fit inside 80 characters.
|
| 219591 |
13-Mar-2011 |
adrian |
Add the missing AR724x DDR flush routines for if_arge0.
Submitted by: Luiz Otavio O Souza
|
| 219590 |
13-Mar-2011 |
adrian |
Fix the TX underrun status reset; remove a now unused variable.
Submitted by: Luiz Otavio O Souza
|
| 219589 |
13-Mar-2011 |
adrian |
Commit FIFO configuration fixes from OpenWRT. This fixes performance
issues with if_arge on the AR913x and AR724x.
Reference: https://dev.openwrt.org/ticket/6754
Submitted by: Luiz Otavio O Souza
|
| 217184 |
09-Jan-2011 |
adrian |
Add missing ar91xx definition for the WMAC reset control.
|
| 216318 |
09-Dec-2010 |
gonzo |
- Populate dump_avail with proper values from phys_avail
|
| 215270 |
13-Nov-2010 |
imp |
Remove the 'machine mips' from DEFAULTS. Put the proper 'machine mips
mipsel' or 'machine mips mipseb' into the config file (with a few 64's
tossed in for good measure). This will let us build the proper
kernels with different worlds as part of make universe.
|
| 213894 |
15-Oct-2010 |
marius |
Converted the remainder of the NIC drivers to use the mii_attach()
introduced in r213878 instead of mii_phy_probe(). Unlike r213893 these
are only straight forward conversions though.
Reviewed by: yongari
|
| 213286 |
29-Sep-2010 |
gonzo |
- Fix values of CS1_EN and CS2_EN flags
- Unbreak kernel build by fixing naming convention of
GPIO_FUNC flags
Spotted by: Luiz Otavio O Souza, Andrew Thompson
|
| 213278 |
29-Sep-2010 |
gonzo |
AR71XX_GPIO_* defines were introduced by adrian@ a while ago,
remove duplicated.
|
| 213239 |
28-Sep-2010 |
gonzo |
Add AR71XX GPIO bus driver.
|
| 212775 |
17-Sep-2010 |
thompsa |
Make a note of which platforms the mac strings come from.
Suggested by: adrian
|
| 212774 |
17-Sep-2010 |
thompsa |
Use getenv to find the mac address since it could be in the bootloader
environment or command line and under different names.
|
| 212413 |
10-Sep-2010 |
avg |
bus_add_child: change type of order parameter to u_int
This reflects actual type used to store and compare child device orders.
Change is mostly done via a Coccinelle (soon to be devel/coccinelle)
semantic patch.
Verified by LINT+modules kernel builds.
Followup to: r212213
MFC after: 10 days
|
| 211511 |
19-Aug-2010 |
adrian |
Migrate if_arge to use the PLL cpuops.
This has been lightly tested on the AR7161 and AR9132.
|
| 211510 |
19-Aug-2010 |
adrian |
Implement PLL generalisation in preparation for use in if_arge.
* Add a function to write to the relevant PLL register
* Break out the PLL configuration for the AR71XX into the CPU ops,
lifted from if_arge.c.
* Add the AR91XX PLL configuration ops, using the AR91XX register
definitions.
|
| 211509 |
19-Aug-2010 |
adrian |
add the PLL set functions to cpuops
|
| 211504 |
19-Aug-2010 |
adrian |
Fix mistaken indenting.
|
| 211503 |
19-Aug-2010 |
adrian |
Add some initial AR724X chipset support.
This is untested but should at least allow an AR724X to boot.
The current code is lacking the detail needed to expose the PCIe bus.
It is also lacking any NIC, PLL or flush/WB code.
|
| 211502 |
19-Aug-2010 |
adrian |
Add initial Atheros AR91XX support.
This works well enough to bring a system up to single-user mode
using an MDROOT.
Known Issues:
* The EHCI USB doesn't currently work and will panic the kernel during
attach.
* The onboard ethernet won't work until the PLL routines have been
fleshed out and shoe-horned into if_arge.
* The WMAC device glue (and quite likely the if_ath support)
hasn't yet been implemented.
|
| 211498 |
19-Aug-2010 |
adrian |
Add missing licence.
|
| 211497 |
19-Aug-2010 |
adrian |
style(9) pick from imp@ .
|
| 211482 |
19-Aug-2010 |
adrian |
Remove now unused 'reg'.
|
| 211481 |
19-Aug-2010 |
adrian |
Initialise the USB system using cpuops rather than the AR71XX specific method.
|
| 211480 |
19-Aug-2010 |
adrian |
Migrate the CPU reset path to use the new cpuops.
|
| 211479 |
19-Aug-2010 |
adrian |
Remove the now-unused DDR flush register value.
|
| 211478 |
19-Aug-2010 |
adrian |
Make the PCI initialisation path use the new cpuops rather than directly
programming the reset register.
|
| 211477 |
19-Aug-2010 |
adrian |
Make if_arge use the new cpuops rather than hard coding the DDR flush registers.
|
| 211476 |
19-Aug-2010 |
adrian |
Preparation work for supporting the AR91xx and AR724x.
* Implement a SoC probe function, from Linux, which determines the
SoC family, type and revision. This only probes the AR71xx series
SoC and (currently) panics on others.
* Migrate some of the AR71XX specific hardware init (USB device, determining
system frequencies) into using the cpuops introduced in an earlier commit.
Other SoC specific hardware stuff (per-device flush/WB, GPIO pin wiring,
Ethernet PLL setup, other things I've likely missed) will be introduced in
subsequent commits.
Reviewed by: imp@
Obtained from: (partially) Linux
|
| 211449 |
18-Aug-2010 |
adrian |
Add a DDR flush function, inspired by both Linux and if_arge.c.
|
| 211448 |
18-Aug-2010 |
adrian |
Add a further register definition for USB device initialisation.
Obtained from: Linux
|
| 211447 |
18-Aug-2010 |
adrian |
Bring over the first cut of the Atheros-specific SoC operations.
Each of these SoCs have different devices, different hardware initialisation
methods and, quite likely, different quirks. These functions will abstract
out the SoC differences and keep these differences out of the drivers (eg
USB init, if_arge, etc.)
|
| 211440 |
18-Aug-2010 |
adrian |
Import initial AR91XX and AR724X CPU register definitions.
Obtained from: Linux
|
| 210900 |
05-Aug-2010 |
gonzo |
- Add interrupts counter for PCI devices
|
| 209809 |
08-Jul-2010 |
adrian |
Add TX-path aligned/unaligned stats for if_arge.
|
| 209807 |
08-Jul-2010 |
adrian |
Address PR kern/148307 - fix if_ath TX mbuf alignment/size constraint checks
The existing code only checked the alignment of the first mbuf and
didn't enforce the size constraints.
This commit introduces a simple function to check the alignment and
size of all mbufs in the list. This fixes the initial issue in the
PR.
PR: kern/148307
Reviewed by: gonzo@
|
| 209802 |
08-Jul-2010 |
adrian |
Introduce a sysctl block for if_arge and, for now, a blank debug sysctl
placeholder for later.
Add in a missing FreeBSD ID string.
|
| 209769 |
07-Jul-2010 |
adrian |
Fix the CS line definitions. These bits are for the CS2/CS1 lines
rather than CS1/CS0.
This has been tested on the Ubiqiti Routerstation Pro board.
|
| 209494 |
24-Jun-2010 |
adrian |
Comment about the shared pins I know about.
|
| 209454 |
23-Jun-2010 |
adrian |
AR71XX GPIO register definitions.
Reviewed by: gonzo@
|
| 209338 |
19-Jun-2010 |
adrian |
Extend the AR71XX watchdog debugging and data.
* Add some per-device sysctl entries which record the watchdog state -
whether it is armed; whether the last reboot was due to the watchdog.
* Add a per-device sysctl debug flag to enable logging watchdog arming/
disarming.
Reviewed by: gonzo@
|
| 207554 |
03-May-2010 |
sobomax |
Add new tunable 'net.link.ifqmaxlen' to set default send interface
queue length. The default value for this parameter is 50, which is
quite low for many of today's uses and the only way to modify this
parameter right now is to edit if_var.h file. Also add read-only
sysctl with the same name, so that it's possible to retrieve the
current value.
MFC after: 1 month
|
| 206400 |
08-Apr-2010 |
gonzo |
- Fix mutex type for miibus_mtx: it's not spinlock, it's def lock
|
| 204093 |
19-Feb-2010 |
kan |
Define DMA_RX_STATUS_OVERFLOW with correct value.
The RX overflow is reported in bit 2 on real hardware and Linux driver
for the same device already has this defined correctly.
This fixes frequent interrupt storms seen on RouterStation Pro boards.
Discussed with: gonzo
|
| 203132 |
28-Jan-2010 |
gonzo |
- Increase timeouts to 100 milliseconds, 1 millisecond is definitely not
enough for PCI controller to get into shape
Thanks to: adrian@
|
| 202954 |
25-Jan-2010 |
gonzo |
- Call post-boot fixup function in order to get proper static
symbols resolving in DDB
- When zeroing .bss/.sbss do not round end address to page boundary,
it's not neccessary and might destroy data pased by trampoline or
boot loader
|
| 202849 |
23-Jan-2010 |
imp |
Update from old DDB convetion to initialize debugger to new KDB way.
Always call kdb_init(). If we have KDB enabled, then provide a handy
place to break to the debugger.
|
| 202839 |
22-Jan-2010 |
gonzo |
- Add driver for PCF2123, SPI real time clock/calendar
|
| 202723 |
21-Jan-2010 |
gonzo |
- Remove unnecessary register writes in activate_device
and deactivate_device
- Save state before attaching driver and restore it when
detaching
- Clear CLK bit after last bit of byte has been sent over
the bus providing falling edge for last byte in transfer
- Fix several places where CS0 was always assumed
- Add $FreeBSD$ to ar71xxreg.h
|
| 202175 |
12-Jan-2010 |
imp |
Set the svn:eol-style = native and svn:mime-type = text/plain
properties on all files in this tree.
Submitted by: rpaulo@
|
| 202173 |
12-Jan-2010 |
imp |
Place proper svn:keywords tag on all these files. They were created
somehow without them on projects/mips, and that mistake was propigated
over to head.
Submitted by: rpaulo@
|
| 202105 |
11-Jan-2010 |
imp |
Using svn cp rather than cp to copy these files over had the benefit
of preserving their history. It had the problem that it also copied
over mergeinfo data. Since we're retiring the projects/mips branch,
I'm removing the svn:mergeinfo property from them all.
Submitted by: jhb
|
| 201906 |
09-Jan-2010 |
imp |
Merge from projects/mips to head by hand:
Merge support files for the Atheros AR71xx (and soon AR9xxx)
processors, except files from sys/conf and sys/mips/conf. This work
was done primarily by Olecksandr Tymoshenko and works on the
RouterStation and RouterStation PRO. Other AR71xx-based boards have
been reported as working as well (RouterBoard, for example).
|
| 201881 |
09-Jan-2010 |
imp |
Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the
BSP. Provide a missing prototype.
|
| 201845 |
08-Jan-2010 |
imp |
Centralize initialization of pcpu, and set curthread early...
|
| 199497 |
18-Nov-2009 |
gonzo |
- Add intr counters for APB interrupts
|
| 199234 |
12-Nov-2009 |
gonzo |
- Handle multiphy MAC case: create interface with
fixed-state media with parameters set via hints
and configure MAC accordingly to these parameters.
All the underlying PHY magic is done by boot manager
on startup. At the moment there is no proper way
to make active and control all PHYs simultaneously
from one MII bus and there is no way to associate
incoming/outgoing packet with specific PHY.
|
| 199233 |
12-Nov-2009 |
gonzo |
- include register definitions for respective controllers
|
| 199038 |
08-Nov-2009 |
gonzo |
- Access to all 5 PHYs goes through registers in MAC0 memory
space, rewrite miibus accessors respectively
|
| 199005 |
06-Nov-2009 |
gonzo |
- Fix: Wrong register is used for initial value reading
|
| 198970 |
06-Nov-2009 |
gonzo |
- Fix initialization of PLL registers (different shifts for
arge0/arge1)
- Use base MAC address to generate MACs for arge1 and above
|
| 198939 |
05-Nov-2009 |
gonzo |
- Replace dumb cut'n'paste call with not to self (XXX)
|
| 198933 |
04-Nov-2009 |
gonzo |
- style(9): replace whitespaces with tabs
|
| 198932 |
04-Nov-2009 |
gonzo |
- Remove noisy "Implement me" stubs
- Handle SIOCSIFFLAGS ioctl
|
| 198669 |
30-Oct-2009 |
rrs |
With this commit our friend RMI will now compile. I have
not tested it and the chances of it running yet are about
ZERO.. but it will now compile. The hard part now begins,
making it run ;-)
|
| 198667 |
30-Oct-2009 |
gonzo |
- Fix build with DEVICE_POLLING enabled
|
| 198562 |
28-Oct-2009 |
thompsa |
Parse and save the command line passed in from RedBoot (exec -c "xxx") and also
the board specific environment variables.
This is not ar71xx specific and should be shared better.
|
| 198154 |
15-Oct-2009 |
rrs |
Does 4 things:
1) Adds future RMI directories
2) Places intr_machdep.c in specfic files.arch pointing to the generic
intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c
(which we will need for RMI) in the machine specific directory
3) removes intr_machdep.c from files.mips
4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We
may need to look at finding a better place to put this. But first I want to
get this thing compiling.
|
| 197973 |
11-Oct-2009 |
gonzo |
- Fix CPU divisor mask
Repored by: Luiz Otavio O Souza
|
| 196795 |
03-Sep-2009 |
gonzo |
- Remove flags accidently brought by dumb cut'n'paste coding
|
| 196794 |
03-Sep-2009 |
gonzo |
- Fix phy address calculation
|
| 195985 |
31-Jul-2009 |
gonzo |
- Make USB part of AR71XX kernel buildable again
|
| 195514 |
09-Jul-2009 |
gonzo |
- Add AR71XX watchdog timer driver
|
| 195513 |
09-Jul-2009 |
gonzo |
- Move CPU/AHB frequency calculations to functions to
prevent code duplication
|
| 195474 |
08-Jul-2009 |
gonzo |
- Fix PCI routing code
|
| 195434 |
08-Jul-2009 |
gonzo |
- Fix off-by-one bug in arge_fixup_rx. If mbuf is located
by the end of the page and even number of bytes long,
that may cause TLBMiss exception for unallocated address.
- Fix mess with DMA sync opeartions
|
| 194470 |
19-Jun-2009 |
gonzo |
- Flush PCI register write before delay
Spotted by: Pyun YongHyeon
|
| 194273 |
16-Jun-2009 |
gonzo |
- Take into account only unmasked bits in interrupt status register
|
| 194059 |
12-Jun-2009 |
gonzo |
- Fix functions prototypes to make compiler happy
|
| 192946 |
28-May-2009 |
gonzo |
- Revert fix by dwhite that has been accidentally lost in r192783
commit.
|
| 192822 |
26-May-2009 |
gonzo |
- style(9) fixes
- Get rid of obsolete mask_fn
|
| 192821 |
26-May-2009 |
gonzo |
- arge_poll should be decalred only if DEVICE_POLLING is enabled
- Revert Rx buffer nsegments from BUS_SPACE_UNRESTRICTED to
ARGE_MAXFRAGS
|
| 192783 |
26-May-2009 |
gonzo |
- Add polling support
- Get rid of arge_fix_chain, use m_defrag like if_vr
- Rework interrupt handling routine to avoid race that lead
to disabling RX interrupts
- Enable full duplex if requested
- Properly set station MAC address
- Slightly optimize RX loop
- Initialize FILTERMATCH and FILTERMASK registers as linux driver does
|
| 192656 |
23-May-2009 |
gonzo |
- Calculate clock frequency using PLL registers
|
| 192624 |
23-May-2009 |
gonzo |
- Wrong logical operator was used for flag check
|
| 192600 |
22-May-2009 |
dwhite |
Remove unused variable.
|
| 192569 |
21-May-2009 |
dwhite |
Add some missing bits to arge:
* In arge_attach(), hard reset the MAC blocks before configuring the MAC.
* In arge_reset_dma(), clear pending packet interrupts based off
the hardware counter instead of acking every packet in the ring,
as the hardware counter can exceed the ring size. If the reset
was successful the counters will be zero anyway.
* In arge_encap(), remove an unused variable.
* In arge_tx_locked(), remove redundant setting of the EMPTY flag as
the TX DMA engine sets it for us.
* In arge_intr(), remember to clear the interrupt status bits
relayed from arge_intr_filter().
* Handle RX overflow and TX underflow.
* In arge_tx_intr(), remember to unmask the TX interrupt bits
after processing them.
|
| 192365 |
19-May-2009 |
gonzo |
- ar71xx increases Count value every two cycles
|
| 192357 |
18-May-2009 |
gonzo |
- Add SPI bus driver for ar71xx SoC
|
| 192179 |
16-May-2009 |
gonzo |
- Set MAC Address obtained from RedBoot or generate random one
|
| 192178 |
16-May-2009 |
gonzo |
- Get memory size and base MAC address from RedBoot (if available)
|
| 192161 |
15-May-2009 |
gonzo |
- Add pci bus space that translates byte order to little endian,
may be it will be merged with bus_space_reversed later
- Handle memory resources close to bus in order to control
bus_space_tag
|
| 192133 |
15-May-2009 |
gonzo |
- Calculate clock frequency using PLL registers
- Remove stale comments
|
| 192132 |
15-May-2009 |
gonzo |
- Calculate CPU frequency using dividers from PLL registers
|
| 192131 |
15-May-2009 |
gonzo |
- Add definitions for PLL CPU Config register fields
|
| 192120 |
14-May-2009 |
gonzo |
- Add SPI-related registers
|
| 192117 |
14-May-2009 |
gonzo |
- Remove garbage debug output
|
| 191872 |
07-May-2009 |
gonzo |
- Add interrupt handling for AR71XX PCI bridge
|
| 191840 |
06-May-2009 |
gonzo |
- Rollback to the hack with 3-bytes offset in base address.
uart_bus_XXXXX resources are handled in uart(4) code
and we need more sophysticated way to define which space
should be used for device based on hints
|
| 191838 |
06-May-2009 |
gonzo |
- Add APB base and size for memory rman in apb
|
| 191837 |
06-May-2009 |
gonzo |
- Handle memory requests on apb level, do not pass them up to
nexus
- Unmask IRQ in bus_intr_setup
- Do not count timer IRQ (IRQ0) as stray
|
| 191644 |
29-Apr-2009 |
gonzo |
- accummulate interrupt causes in filter instead of rewriting old. The only
place where status should be overrided - interrupt handler
|
| 191293 |
19-Apr-2009 |
gonzo |
- Remove garbage debug output
- ar71xx_bus_space_reversed is bus_space_tag_t, use it this way
|
| 191290 |
19-Apr-2009 |
gonzo |
- Add EHCI controller driver for AR71XX-based boards.
|
| 191289 |
19-Apr-2009 |
gonzo |
- Handle byte-order issue for non-word accesses to memory mapped
registers with ar71xx_bus_space_reversed. Note, that byte order
of values is handled by drivers. bus_spaces fixes only position
of register in word.
- Replace .hints hack for AR71XX UART with ar71xx_bus_space_reversed.
|
| 191101 |
15-Apr-2009 |
gonzo |
Fix USB2 quick'n'dirty porting, now system successfully detects OHCI
|
| 191086 |
15-Apr-2009 |
gonzo |
- Port AR71XX OHCI controller to new USB stack
|
| 191079 |
14-Apr-2009 |
gonzo |
- Revert changes accidentally killed by merge operation
|
| 188885 |
21-Feb-2009 |
gonzo |
- Remove some garbage output
|
| 188884 |
21-Feb-2009 |
gonzo |
- Add integrated OHCI controller driver, just a
wrapper around generic ohci driver
|
| 188883 |
21-Feb-2009 |
gonzo |
- Add some debug output
- Do not manage memory, it's not neccessary. Just pass
request up to nexus to map it to KSEG1
|
| 188882 |
21-Feb-2009 |
gonzo |
- Reset USB chip and init control registers
|
| 188881 |
21-Feb-2009 |
gonzo |
- Add USB-related registers
|
| 188809 |
19-Feb-2009 |
gonzo |
- Add if_arge to build
|
| 188808 |
19-Feb-2009 |
gonzo |
- Driver for on-board AR71XX ethernet
|
| 188807 |
19-Feb-2009 |
gonzo |
- Add PLL, reset, ethernet and DMA registers/values
|
| 187706 |
26-Jan-2009 |
gonzo |
- Add ar71xx PCI bridge implementation and link it to the build
|
| 187705 |
26-Jan-2009 |
gonzo |
- Rename RESET-related registers
- Add PCI registers
|
| 187518 |
21-Jan-2009 |
gonzo |
- Forgot to add this file to r187515
|
| 187517 |
21-Jan-2009 |
gonzo |
- Add apb device. apb is bridge that connects UART, GPIO,
I2S and PCM to main bus
- Connect apb and uart_bus to build
|
| 187516 |
21-Jan-2009 |
gonzo |
- Use new register naming convention
- Properly initialize bus_space tags for uart
|
| 187515 |
21-Jan-2009 |
gonzo |
- Change register/bitnumber/masks naming convention (again)
o For register names use AR71XX_REGISTER_NAME (prefix varies depending
on platform AR71XX/AR91XX/... Yes, let's hope other families are
on their way to tree, they call it positive thinking)
o For bit number use REGISTER_NAME_FIELD_NAME
o For field mask use REGISTER_NAME_FIELD_NAME_MASK
|
| 187514 |
21-Jan-2009 |
gonzo |
- Add newbus uart driver implementation
|
| 187513 |
21-Jan-2009 |
gonzo |
- Use ATH_READ_REG/ATH_WRITE_REG instead of direct memory access
|
| 187463 |
20-Jan-2009 |
gonzo |
- Fix platform_reset function
|
| 187462 |
20-Jan-2009 |
gonzo |
- Use more generic prefix for register names (ATH instead of AR71XX
|
| 187456 |
20-Jan-2009 |
gonzo |
- Use more generic name for atheros-based devices subdirectory. Keep old
naming scheme for files until we'll figure out common parts.
Suggested by: imp@
|
| 187424 |
19-Jan-2009 |
gonzo |
- style(9) fix: replace spaces with tabs
|
| 187423 |
19-Jan-2009 |
gonzo |
- First bits of Atheros' AR71XX port. Only UART supported ATM.
|