axi_quad_spi.c revision 331506 
1/*-
2 * Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * Portions of this software were developed by SRI International and the
6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Portions of this software were developed by the University of Cambridge
10 * Computer Laboratory as part of the CTSRD Project, with support from the
11 * UK Higher Education Innovation Fund (HEIF).
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 *    notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 *    notice, this list of conditions and the following disclaimer in the
20 *    documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35/*
36 * Xilinx AXI_QUAD_SPI
37 */
38
39#include <sys/cdefs.h>
40__FBSDID("$FreeBSD: stable/11/sys/dev/xilinx/axi_quad_spi.c 331506 2018-03-24 23:23:31Z ian $");
41
42#include <sys/param.h>
43#include <sys/systm.h>
44#include <sys/bus.h>
45#include <sys/kernel.h>
46#include <sys/module.h>
47#include <sys/malloc.h>
48#include <sys/rman.h>
49#include <sys/timeet.h>
50#include <sys/timetc.h>
51#include <sys/watchdog.h>
52
53#include <dev/spibus/spi.h>
54#include <dev/spibus/spibusvar.h>
55
56#include "spibus_if.h"
57
58#include <dev/fdt/fdt_common.h>
59#include <dev/ofw/openfirm.h>
60#include <dev/ofw/ofw_bus.h>
61#include <dev/ofw/ofw_bus_subr.h>
62
63#include <machine/bus.h>
64#include <machine/cpu.h>
65#include <machine/intr.h>
66
67#define	READ4(_sc, _reg)	\
68	bus_space_read_4(_sc->bst, _sc->bsh, _reg)
69#define	WRITE4(_sc, _reg, _val)	\
70	bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
71
72#define	SPI_SRR		0x40		/* Software reset register */
73#define	 SRR_RESET	0x0A		/* The only reset value */
74#define	SPI_CR		0x60		/* Control register */
75#define	 CR_LSB_FIRST	(1 << 9)	/* LSB first */
76#define	 CR_MASTER_TI	(1 << 8)	/* Master Transaction Inhibit */
77#define	 CR_MSS		(1 << 7)	/* Manual Slave Select */
78#define	 CR_RST_RX	(1 << 6)	/* RX FIFO Reset */
79#define	 CR_RST_TX	(1 << 5)	/* TX FIFO Reset */
80#define	 CR_CPHA	(1 << 4)	/* Clock phase */
81#define	 CR_CPOL	(1 << 3)	/* Clock polarity */
82#define	 CR_MASTER	(1 << 2)	/* Master (SPI master mode) */
83#define	 CR_SPE		(1 << 1)	/* SPI system enable */
84#define	 CR_LOOP	(1 << 0)	/* Local loopback mode */
85#define	SPI_SR		0x64		/* Status register */
86#define	 SR_TX_FULL	(1 << 3)	/* Transmit full */
87#define	 SR_TX_EMPTY	(1 << 2)	/* Transmit empty */
88#define	 SR_RX_FULL	(1 << 1)	/* Receive full */
89#define	 SR_RX_EMPTY	(1 << 0)	/* Receive empty */
90#define	SPI_DTR		0x68		/* Data transmit register */
91#define	SPI_DRR		0x6C		/* Data receive register */
92#define	SPI_SSR		0x70		/* Slave select register */
93#define	SPI_TFOR	0x74		/* Transmit FIFO Occupancy Register */
94#define	SPI_RFOR	0x78		/* Receive FIFO Occupancy Register */
95#define	SPI_DGIER	0x1C		/* Device global interrupt enable register */
96#define	SPI_IPISR	0x20		/* IP interrupt status register */
97#define	SPI_IPIER	0x28		/* IP interrupt enable register */
98
99struct spi_softc {
100	struct resource		*res[1];
101	bus_space_tag_t		bst;
102	bus_space_handle_t	bsh;
103	void			*ih;
104};
105
106static struct resource_spec spi_spec[] = {
107	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
108	{ -1, 0 }
109};
110
111static int
112spi_probe(device_t dev)
113{
114
115	if (!ofw_bus_status_okay(dev))
116		return (ENXIO);
117
118	if (!ofw_bus_is_compatible(dev, "xlnx,xps-spi-3.2"))
119		return (ENXIO);
120
121	device_set_desc(dev, "Xilinx Quad SPI");
122	return (BUS_PROBE_DEFAULT);
123}
124
125static int
126spi_attach(device_t dev)
127{
128	struct spi_softc *sc;
129	uint32_t reg;
130
131	sc = device_get_softc(dev);
132
133	if (bus_alloc_resources(dev, spi_spec, sc->res)) {
134		device_printf(dev, "could not allocate resources\n");
135		return (ENXIO);
136	}
137
138	/* Memory interface */
139	sc->bst = rman_get_bustag(sc->res[0]);
140	sc->bsh = rman_get_bushandle(sc->res[0]);
141
142	/* Reset */
143	WRITE4(sc, SPI_SRR, SRR_RESET);
144
145	DELAY(1000);
146
147	reg = (CR_MASTER | CR_MSS | CR_RST_RX | CR_RST_TX);
148	WRITE4(sc, SPI_CR, reg);
149	WRITE4(sc, SPI_DGIER, 0);	/* Disable interrupts */
150
151	reg = (CR_MASTER | CR_MSS | CR_SPE);
152	WRITE4(sc, SPI_CR, reg);
153
154	device_add_child(dev, "spibus", 0);
155	return (bus_generic_attach(dev));
156}
157
158static int
159spi_txrx(struct spi_softc *sc, uint8_t *out_buf,
160    uint8_t *in_buf, int bufsz, int cs)
161{
162	uint32_t data;
163	uint32_t i;
164
165	for (i = 0; i < bufsz; i++) {
166		WRITE4(sc, SPI_DTR, out_buf[i]);
167
168		while(!(READ4(sc, SPI_SR) & SR_TX_EMPTY))
169			continue;
170
171		data = READ4(sc, SPI_DRR);
172		if (in_buf)
173			in_buf[i] = (data & 0xff);
174	}
175
176	return (0);
177}
178
179static int
180spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
181{
182	struct spi_softc *sc;
183	uint32_t reg;
184	uint32_t cs;
185
186	sc = device_get_softc(dev);
187
188	KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
189	    ("%s: TX/RX command sizes should be equal", __func__));
190	KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
191	    ("%s: TX/RX data sizes should be equal", __func__));
192
193	/* get the proper chip select */
194	spibus_get_cs(child, &cs);
195
196	cs &= ~SPIBUS_CS_HIGH;
197
198	/* Assert CS */
199	reg = READ4(sc, SPI_SSR);
200	reg &= ~(1 << cs);
201	WRITE4(sc, SPI_SSR, reg);
202
203	/* Command */
204	spi_txrx(sc, cmd->tx_cmd, cmd->rx_cmd, cmd->tx_cmd_sz, cs);
205
206	/* Data */
207	spi_txrx(sc, cmd->tx_data, cmd->rx_data, cmd->tx_data_sz, cs);
208
209	/* Deassert CS */
210	reg = READ4(sc, SPI_SSR);
211	reg |= (1 << cs);
212	WRITE4(sc, SPI_SSR, reg);
213
214	return (0);
215}
216
217static device_method_t spi_methods[] = {
218	/* Device interface */
219	DEVMETHOD(device_probe,		spi_probe),
220	DEVMETHOD(device_attach,	spi_attach),
221
222	/* SPI interface */
223	DEVMETHOD(spibus_transfer,	spi_transfer),
224	DEVMETHOD_END
225};
226
227static driver_t spi_driver = {
228	"spi",
229	spi_methods,
230	sizeof(struct spi_softc),
231};
232
233static devclass_t spi_devclass;
234
235DRIVER_MODULE(spi, simplebus, spi_driver, spi_devclass, 0, 0);
236