310883 |
31-Dec-2016 |
loos |
MFC r309461:
Allow simultaneous access to switch device, there is no reason to prevent it.
Remove bogus wrappers and use the kernel defaults.
While here, use DEVMETHOD_END.
Obtained from: pfSense Sponsored by: Rubicon Communications, LLC (Netgate) |
299910 |
16-May-2016 |
sgalabov |
Introduce basic etherswitch support for Ralink SoCs
This revision introduces basic support for the internal ESW switch found Ralink/Mediatek SoCs such as RT3050, RT3352, RT5350, MT7628; and GSW found in MT7620 and MT7621.
It only supports 802.1q VLANs and doesn't support external PHYs at the moment (only the ones that are built into the switch itself).
Approved by: adrian (mentor) Sponsored by: Smartcom - Bulgaria AD Differential Revision: https://reviews.freebsd.org/D6348
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289947 |
25-Oct-2015 |
zbb |
Introduce e6000sw etherswitch support
Add e6000sw driver supporting Marvell 88E6352, 88E6172, 88E6176 switches. It needs to be attached to mdio interface, exporting SMI access functionality. e6000sw supports port-based VLAN configuration, per-port media changing, accessing PHY and switch registers.
e6000sw attaches miibuses and PHY drivers as children. Instead of typical tick as callout, kthread-based tick is used. This combined with SX locks allows MDIO read/write calls to sleep. It is expected, because this hardware requires long delays in SMI read/write procedures, which can not be handled by busy-waiting.
Reviewed by: adrian Obtained from: Semihalf Submitted by: Bartosz Szczepanek <bsz@semihalf.com> Differential revision: https://reviews.freebsd.org/D3902
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289665 |
20-Oct-2015 |
adrian |
AR8327: Fix up the ability to configure the vlangroup configuration for the CPU port
I messed up when doing the reset_vlans method - setting vid[0] = 1 here was making it 'hidden' from configuration (as it needed ETHERSWITCH_VID_VALID as well) and so there was no way to configure vlangroup0.
In per-port VLAN mode, vlangroup0 is for the CPU port (port0). Now, it normally wouldn't really matter - the CPU port thus sees all other ports. However there are two CPU ports on the AR8327 and so port0 (arge0) was seeing all traffic on port6 (arge1). If you thus tried to use arge1/port6 for anything (eg a WAN port) in a bridge group then things would very upset very quickly.
Whilst here, add a comment to remind myself that yes, it'd be nice if we could specify a boot-time switch config.
Tested:
* AP135 reference platform w/ AR8327N switch
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279943 |
13-Mar-2015 |
adrian |
Commit 802.1q configuration support for the AR8327.
This is slightly different to the other switches - the VLAN table (VTU) programs in the vlan port mapping /and/ the port config (tagged, untagged, passthrough, any.)
So:
* Add VTU operations to program the VTU (vlan table) * abstract out the mirror-disable function so it's .. well, a function. * setup the port to have a dot1q configuration for dot1q - the port security is VLAN (not per-port VLAN) and requires an entry in the VLAN table; * add set_dot1q / get_dot1q to program the VLAN table; * since the tagged/untagged ports are now programmed into the VTU, rather than global - plumb the ports /and/ untagged ports bitmaps through the arswitch API.
Tested:
* AP135 - QCA9558 SoC + AR8327N switch
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279790 |
08-Mar-2015 |
adrian |
Add per-port vlan support for the AR8327.
All the per-port support is really doing is applying a port visibility mask to each of the switchports. Everything still look like a single portgroup (vlan id 1), but the per-port visibility mask is modified.
Whilst I'm here, also add some initial dot1q support - the pvid stuff is doing the right thing, but it's not useful without the rest of the VLAN table programming.
It's enough for me to be able to use the LAN/WAN port distinction on the AP135, where there isn't (for now!) a dedicated PHY for the "WAN" port.
Tested:
* AP135, QCA9558 SoC + AR8327 switch
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279767 |
08-Mar-2015 |
adrian |
Fix up support for the AR8327.
* Even though I got the registers around "right", it seems I'm not tickling the MDIO access correctly for the internal PHY bus. Some of the switches are fine poking at the external PHY registers; others aren't. So, enable direct PHY bus access for the AR8327, and leave the existing code in place for the others.
* Go and shuffle the register access around. Whilst here, restore the 2ms delay if changing page.
* Comment out some of the stub printf()s; there's some upcoming work to add port VLAN support.
Tested:
* AP135 development board * Carambola2 - AR9331 SoC
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279490 |
01-Mar-2015 |
adrian |
Bump the port mask on the AR8327 ethernet switch from 0x3f to 0x7f.
So, it turns out that the AR8327 has 7 ports internally:
* GMAC0 / external (CPU) MAC0 * GMAC1 / port1 -> GMAC5 / port5: external switch port PHYs * GMAC6 / external (CPU) MAC1
Now, depending upon how things are wired up, the second CPU port (MAC1) can be wired to either the switch (port6), or through port5's PHY, bypassing the GMAC+switch entirely. Ie, it can pretend to be a boring PHY, saving system designers from having to include a separate PHY for a "WAN" port.
Here's the rub - the AP135 board (QCA955x SoC) hooks up arge0 to the second CPU port on the AR8327, but it's hooked up as RGMII. So, in order to hook it up to the rest of the switch, it isn't configured as a separate PHY - OpenWRT has it setup as connected via RGMII to GMAC6 and (I'm guessing) it's set to be a WAN port by configuring up port-based VLANs or something.
Thus, with a port mask of 0x3f, GMAC6 was never allowed to receive traffic from any other port. It could transmit fine, but not receive anything.
So, now it works enough for me to continue doing board bootstrapping. Note, this isn't enough to make the QCA955x + AR8327 work - there's a bunch of uncommitted work to both the platform SoC (interrupt handling, ethernet, etc) and the ethernet switch (register access space, setup, etc) that needs to happen. However, this particular change is also relevant to other SoCs, like the AR934x and AR7161, both of which can be glued to this switch.
Tested:
* AP135 development board
TODO:
* Figure out whether I can somehow abuse another port mode to have this be a pass-through PHY, or whether I should just create some more boot time hints to explicitly set up port-based isolation so this works in a more useful way by default.
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268233 |
03-Jul-2014 |
loos |
Initialize the switch vlan table at attachment.
Update some comments on code, specifying the correct vlans used on switch setup.
Advertise the proper switch operation mode (the rtl8366rb only support dot1q vlans).
This fixes the breakage that i introduced on r249752 and make the rtl8366rb switch works again with etherswitchcfg(8).
Tested on TP-Link 1043ND.
Tested by: me, Harm Weites (harm at weites.com)
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262683 |
02-Mar-2014 |
adrian |
Set all of the ports into the same vlangroup; there's only one vlangroup (pvid=1) and we already configure them to send to other ports.
Setting pvid=portnum would mean that there were separate vlangroups for each ports, but 'leaking' into other ports. The result? All port traffic flooded to all other port traffic.
Tested:
* DB120, AR9344 + AR8327 switch
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262681 |
02-Mar-2014 |
adrian |
Add ATU flush support.
The OpenWRT AR8xxx switch support flushes the ATU (address translation unit) after each port link 'up' status change. I've modified this to just flush on any port transition.
Whilst here, bump the number of ports on the AR8327 to 6, rather than the default of 5. It's DB120 specific; I'll go and make this configurable later.
There's some debugging code in here still; I am still debugging whether this is or isn't working fully.
Tested:
* DB120, AR9344 + AR8327 switch
Obtained from: OpenWRT
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262653 |
01-Mar-2014 |
adrian |
(I think!) make the AR8327 switch correctly handle traffic.
This patch does four things:
* it globally disables mirroring; * it globally sets the mirroring on each port to be disabled; * the initial port setup now programs a portmask for the port to allow transmission (forwarding) to all other ports bar itself; * the vlan setup path now programs the portmask for the port to allow transmission (forwarding) to all other ports bar itself.
Before this, I hard-coded the portmask to 0x3f which would mean all ports (bar port 6, which currently isn't hooked up to anything.) This means that traffic would be duplicated back out the port it received it. I bet this wasn't .. optimal.
In any case, this _seems_ to make DHCP from my macosx laptop work through this access point. I'll do some further testing to ensure it's actually working correctly on all my devices.
Tested:
* DB120, AR8327 switch
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262433 |
24-Feb-2014 |
adrian |
Add in port0/port6 configuration as part of the platform data code path.
It's still hardcoded (for db120) but it is now hardcoded in all the same place (ie, the pdata path.) The port config/status code now checks port0/port6 as appropriate to configure things.
Tested:
* Qualcomm Atheros DB120, AR8327 switch.
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262430 |
24-Feb-2014 |
adrian |
Add initial AR8327 support.
This is (almost!) enough to actually probe, attach, configure a default port group and do some basic work. It's also totally hard-coded for the Qualcomm Atheros DB120 board - it doesn't yet have any of the code from OpenWRT which parses extra configuration data to know how to program the switch. The LED stuff is also missing.
But, it's enough to facilitate board, PHY, switch and VLAN bringup, so I am committing it now.
Tested:
* Qualcomm Atheros DB120
Obtained from: OpenWRT
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258780 |
30-Nov-2013 |
eadler |
Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this shifts into the sign bit. Instead use (1U << 31) which gets the expected result.
This fix is not ideal as it assumes a 32 bit int, but does fix the issue for most cases.
A similar change was made in OpenBSD.
Discussed with: -arch, rdivacky Reviewed by: cperciva
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250381 |
08-May-2013 |
adrian |
Add the ability to change the vlan operation mode.
This adds a vlan capability field to etherswitch_info structure and some definitions of ports flags.
It adds the support to global config parameters which right now is used only to switch between the vlan modes, but it is intended to be extended to support the setup of others parameters (STP, mirror, etc.).
Submitted by: Luiz Otavio O Souza <loos.br@gmail.com> Reviewed by: ray
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249752 |
22-Apr-2013 |
adrian |
Convert over the etherswitch framework to use VLAN IDs per port, rather than VLAN groups.
Some chips (eg this rtl8366rb) has a VLAN group per port - you first define a set of VLANs in a vlan group, then you assign a VLAN group to a port.
Other chips (eg the AR8xxx switch chips) have a VLAN ID array per port - there's no group per se, just a list of vlans that can be configured.
So for now, the switch API will use the latter and rely on drivers doing the heavy lifting if one wishes to use the VLAN group method. Maybe later on both can be supported.
PR: kern/177878 PR: kern/177873 Submitted by: Luiz Otavio O Souza <loos.br@gmail.com> Reviewed by: ray
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235377 |
12-May-2012 |
adrian |
Setup the CPU port and broadcast map on the AR7240, rather than depending upon the bootloader initialising it.
The aim is to eventually support a full switch set and reinitialisation rather than relying on a consistent bootloader setup.
Remove the port flood config from arswitch.c, it's not yet used and it's totally incorrect.
Whilst I'm here, also add in a comment describing why the full switch reset is disabled.
Obtained from: Linux (OpenWRT) - Values
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235367 |
12-May-2012 |
adrian |
* Add in the AR7240 global control field for setting the maximum frame size for the AR7240.
* Include SM/MS macros, thanks to ath_hal(4).
* This field is for normal packets, VLAN and other headers are added to this by the switch device.
* Set the MTU to 1536, to match what is done in Linux. Use the SM macro to write this field.
Obtained from: Atheros (AR7240 datasheet), Linux OpenWRT (MTU default)
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235323 |
12-May-2012 |
adrian |
Further arswitch work:
* Add in the AR724x support. It probes the same as an AR8216/AR8316, so just add in a hint to force the probe success rather than auto-detecting it.
* Add in the missing entries from conf/files, lacking in the previous commit.
The register values and CPU port / mirror port initialisation value was obtained from Linux OpenWRT ag71xx_ar7240.c.
The DELAY(1000) to let things settle is my local workaround. For some reason, PHY4 doesn't seem to probe very reliably without it. It's quite possible that we're missing some MDIO bus initialisation code in if_arge for the AR724x case. As I dislike DELAY() workarounds in general, it's definitely worth trying to figure out why this is the case.
Tested on: AP93 (AR7240) reference design
Obtained from: Linux OpenWRT
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235288 |
11-May-2012 |
adrian |
Commit the first pass of the etherswitch support.
This is designed to support the very basic ethernet switch chip behaviour, specifically:
* accessing switch register space; * accessing per-PHY registers (for switches that actually expose PHYs); * basic vlan group support, which applies for the rtl8366 driver but not for the atheros switches.
This also includes initial support for:
* rtl8366rb support - which is a 10/100/1000 switch which supports vlan groups; * Initial Atheros AR8316 switch support - which is a 10/100/1000 switch which supports an alternate vlan configuration (so the vlan group methods are stubbed.)
The general idea here is that the switch driver may speak to a variety of backend busses (mdio, i2c, spi, whatever) and expose:
* If applicable, one or more MDIO busses which ethernet interfaces can then attach PHYs to via miiproxy/mdioproxy;
* exposes miibusses, one for each port at the moment, so ..
* .. a PHY can be exposed on each miibus, for each switch port, with all of the existing MII/ifnet framework.
However:
* The ifnet is manually created for now, and it isn't linked into the interface list, nor can you (currently) send/receive frames on this ifnet. At some point in the future there may be _some_ support for this, for switches with a multi-port, isolated mode.
* I'm still in the process of sorting out correct(er) locking.
TODO:
* ray's switch code in zrouter (zrouter.org) includes a much more developed newbus API that covers the various switch methods, as well as a capability API so drivers, the switch layer and the userland utility can properly control the subset of supported features.
The plan is to sort that out later, once the rest of ray's switch drivers are brought over and extended to export MII busses and PHYs.
Submitted by: Stefan Bethke <stb@lassitu.de> Reviewed by: ray
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234861 |
01-May-2012 |
adrian |
Bring over the first part of the etherswitch framework - an MDIO bus and MDIO/MII rendezvous proxy.
* Add an 'mdio' bus, which is the "IO" side of an MII bus (but by design can be anything which implements the underlying register access API.) * Add 'miiproxy' and 'mdioproxy', which provides a rendezvous mechanism for MII busses to appear hanging off arbitrary busses (ie, that aren't necessarily a traditional looking MII bus.)
MII busses can now hang off anything that implements an mdiobus.
For the AR71xx SoC, there's one MDIO bus but two MII busses. So to properly support two or more real PHYs, this can be done:
# arge0 MDIO bus - there's no arge1 MDIO bus for AR71xx hint.argemdio.0.at="nexus0" hint.argemdio.0.maddr=0x19000000 hint.argemdio.0.msize=0x1000 hint.argemdio.0.order=0
# Create two mdioproxy instances hint.mdioproxy.0.at="mdio0" hint.mdioproxy.1.at="mdio0"
# .. and with a follow-up patch hint.arge.0.mdio=mdioproxy0 hint.arge.1.mdio=mdioproxy0
TODO:
* Do a sweep or two and add appropriate locking in mdio/mdioproxy/miiproxy.
Submitted by: Stefan Bethke <stb@lassitu.de> Reviewed by: ray
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