258780 |
30-Nov-2013 |
eadler |
Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this shifts into the sign bit. Instead use (1U << 31) which gets the expected result.
This fix is not ideal as it assumes a 32 bit int, but does fix the issue for most cases.
A similar change was made in OpenBSD.
Discussed with: -arch, rdivacky Reviewed by: cperciva
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205397 |
20-Mar-2010 |
marius |
- While SPARC V9 allows tininess to be detected either before or after rounding (impl. dep. #55), the SPARC JPS1 responsible for SPARC64 and UltraSPARC processors defines that in all cases tinyness is detected before rounding, therefore rounding up to the smallest normalised number should set the underflow flag. - If an infinite result is rounded down, the result should have an exponent 1 less than the value for infinity.
PR: 144900 Submitted by: Peter Jeremy MFC after: 3 days
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204974 |
10-Mar-2010 |
marius |
- The OPSZ macro actually only does the right thing for int32 and int64 operands but not for double and extended double ones. Instead of trying to fix the macro just nuke it and unroll the loops in the correct way though as extended double operands turn out to be the only special case. - For FxTO{s,d,q} the source operand is int64 so rs2 has to be re-decoded after setting type accordingly as it's generally decoded using the low 2 bits as the type, which are 0 for these three instructions. - Similarly, in case of F{s,d,q}TOx the target is int64 so rd has to be re-decoded using not only the operand mask appropriate for int64 but also the correct register number encoding. - Use const where appropriate. - Wrap long lines.
Submitted by: Peter Jeremy (partly) MFC after: 3 days
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157791 |
16-Apr-2006 |
marius |
For _Qp_{fge,fgt,fle,flt}() the SCD states that "Exceptions mimic fcmpeq", this means they should set the cmpe flag when calling __fpu_compare().
Submitted by: stefanf MFC after: 2 weeks
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146673 |
27-May-2005 |
stefanf |
Fix long (and long long) to long double, unsigned to long double and unsigned long (and unsigned long long) to long double conversions. - Add a parameter that specifies the position of the sign bit to the _QP_TTOQ macro, previously it always looked at bit 31. Pass a negative number to disable sign inspection for unsigned types. This fixes _Qp_xtoq(), _Qp_uitoq() and _Qp_uxtoq(). - In the functions __fpu_itof() and __fpu_xtof(), look at the sign bit to decide whether we're doing a conversion from an unsigned type. If so, don't negate the mantissa if the integer exceeds the biggest signed number.
PR: 55773 Patch by: Stephen Paskaluk (based upon) MFC after: 2 weeks
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96422 |
11-May-2002 |
jake |
Add a support macro to convert the 5-bit packed register field of a floating point instruction into a 6-bit register number for double and quad arguments. Make use of the new INSFPdq_RN macro where apporpriate; this is required for correctly handling the "high" fp registers (>= %f32). Fix a number of bugs related to the handling of the high registers which were caused by using __fpu_[gs]etreg() where __fpu_[gs]etreg64() should be used (the former can only access the low, single-precision, registers).
Submitted by: tmm
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95604 |
28-Apr-2002 |
jake |
Add code to emulate arithmetic, comparison and conversion operations on long double, which are not implemented in hardware on any UltraSPARC chip that I know of. This just calls into the existing floating point emulator, which is still needed to emulate other floating point operations in certain conditions. Without this gcc has to generate the quad floating point instructions directly, which sometimes causes internal compiler errors.
Reviewed by: tmm
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92055 |
11-Mar-2002 |
tmm |
Fix some bugs that would prevent %fsr to be set correctly, and add support for fcmp and fcmpe instructions with a condition code specification other than %fcc0. This (primarily the first part) seems to fix a lot of problems that people were seeing, e.g. perl and gawk failures.
Reported and analyzed by: wollman
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