Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, as nothing has been merged
here.

Additional commits post-branch will follow.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Add support for a generic AHCI attachment. This allows us to attach to a
typically memory mapped bus, for example on the AMD Opteron A1100 the AHCI
device is mapped in the CPUs address space, and not through a PCI
controller.

Further work is needed for this to work with ACPI as this is expected to be
common on ARMv8 servers.

Reviewed by: mav, mmel
Obtained from: mmel, ABT Systems Ltd
Relnotes: yes
Sponsored by: SoftIron Inc
Differential Revision: https://reviews.freebsd.org/D4269

Allow AHCI driver attach to all known chips reporting RAID class.

Reported by: Michael BlackHeart <amdmiek@gmail.com>
MFC after: 1 week

Introduce support for MSI-X interrupts in AHCI

- Allocate resources for MSI-X table and PBA if necessary
- Add function ahci_free_mem() to free all resources

Reviewed by: jhb, mav
Obtained from: Semihalf
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D3009

Disable port multiplier support on Marvell 88SE61xx chips.

According to report, some recent unrelated changes in the driver triggered
timeouts when testing for absent port multiplier. Cause of this behavior
channge is unclear, but since these chips are old, rare and buggy, it is
easier to just disable port multiplier support, same as done in Linux.

Reported by: bar
MFC after: 3 days

Reduce priority of ATA/SATA drivers.

Legacy ata(4) -> BUS_PROBE_LOW_PRIORITY; more functional ahci(4), siis(4),
mvs(4) -> BUS_PROBE_DEFAULT; BUS_PROBE_VENDOR leave for vendor drivers.

MFC after: 2 weeks

Introduce Annapurna Labs AHCI support

Overview:
* implemented quirk for forcing SATA interface enable
* restore value to status register - this enables link autonegotiation

Modifications:
* devid:vendorid field
* quirk for forcing PI setting (BIOS is doing that on PC-like systems)
* write to capabilites field to enable phy link initialization

Submitted by: Wojciech Macek <wma@semihalf.com>
Reviewed by: imp, mav
Obtained from: Semihalf

Update ThunderX SATA quirk

Add quirk to ThunderX AHCI forcing only 1 MSI-X interrupt.
Shorten Thunder quirk description to avoid printing 'SATA' twice.

Obtained from: Semihalf
Sponsored by: The FreeBSD Foundation

Add a quirk to limit AHCI MSI vectors to one

In 10.1-RELEASE the default number of MSI vectors used was changed from one
to as many vectors as the HW supports.

This change resulted in an ahci timeouts regression when running on AMD
SB7x0/SB8x0/SB9x0 hardware, so its now limited to 1 MSI by default using
this new quirk.

MFC after: 2 weeks
Sponsored by: Multiplay

Add quirk to override default BAR(5) rid for AHCI.
Use it for Cavium AHCI.

Submitted by: Michaе┌ Stanek
Reviewed by: imp (previous version)
MFC after: 1 week

- Const'ify the ahci_ids table.
- Use DEVMETHOD_END.
- Use NULL instead of 0 for pointers.

MFC after: 3 days

Add bunch of PCI IDs of Intel Wildcat Point (9 Series) chipsets.

MFC after: 1 week

Add PCI ID for Promise TX8660 8-port 3Gbps HBA.

This device reports RAID subclass, but appears to be AHCI compatible.

Submitted by: Yuri Perejilin <yuri@rivera.ru>
MFC after: 1 week

Restore order of interrupt setup. Minor problems can result by
setting up the interrupts too early:

Reviewed by: mav@
Sponsored by: Netflix

Invert AHCI_Q_NOBSYRES quirk meaning, waiting for readiness by default.

I gave up to update list of Marvell chips that require this quirk.
The final nail was growing number of PCIe/M.2 SSDs where Marvell chips
have PCI IDs of different vendors.

MFC after: 1 week
H/W donated by: I/O Switch

Separate out PCI attachment from the main AHCI driver. Move checks of
PCI IDs into quirks, which mostly fit (though you'd get no argument
from me that AHCI_Q_SATA1_UNIT0 is oddly specific). Set these quirks
in the PCI attachment. Make some shared functions public so that PCI
and possibly other bus attachments can use them.

The split isn't perfect yet, but it is functional. The split will be
perfected as other bus attachments for AHCI are written.

Sponsored by: Netflix
Reviewed by: kan, mav
Differential Revision: https://reviews.freebsd.org/D699

We were returning 20 bytes as the FIS size to send, but only
initializing 16. Initialize all 20 so we don't send garbage in the
Auxiliary register. The SATA standard mandates a 5 dword length for
the Host to Device FIS.

Sponsored by: Netflix

Don't bother clearing maps for static DMA allocations to NULL. Instead,
leave them as purely opaque values that are only set by bus_dmamem_alloc().

Correct AMD chipsets identification.

Submitted by: Dmitry Luhtionov <dmitryluhtionov@gmail.com>
MFC after: 2 weeks

Add ID for one more ASMedia AHCI-compatible controller.

Reported by: ignace.peeters@gmail.com
MFC after: 2 weeks

Revert r260165: Proper configuration of unmapped_buf_allowed should be used

To avoid failures in bus_dmamap_sync() on ARM unmapped_buf_allowed should
be set to 0. Hence, ARM-specific changes in AHCI should not be applied.

Use only mapped BIOs on ARM

Using unmapped BIOs causes failure inside bus_dmamap_sync, since
this function requires valid MVA address, which is not present
if mapping is not set up.

Submitted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf

Do not attach to PCI bridges in AHCI driver

Some vendors use the same VID:PID combination in AHCI and PCI bridge cards

Submitted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf

Add few more minor parts of DevSleep support from AHCI 1.3.1 proposal.

Add some more IDs for Intel ATA, AHCI and USB controllers.

Merge CAM locking changes from the projects/camlock branch to radically
reduce lock congestion and improve SMP scalability of the SCSI/ATA stack,
preparing the ground for the coming next GEOM direct dispatch support.

Replace big per-SIM locks with bunch of smaller ones:
- per-LUN locks to protect device and peripheral drivers state;
- per-target locks to protect list of LUNs on target;
- per-bus locks to protect reference counting;
- per-send queue locks to protect queue of CCBs to be sent;
- per-done queue locks to protect queue of completed CCBs;
- remaining per-SIM locks now protect only HBA driver internals.

While holding LUN lock it is allowed (while not recommended for performance
reasons) to take SIM lock. The opposite acquisition order is forbidden.
All the other locks are leaf locks, that can be taken anywhere, but should
not be cascaded. Many functions, such as: xpt_action(), xpt_done(),
xpt_async(), xpt_create_path(), etc. are no longer require (but allow) SIM
lock to be held.

To keep compatibility and solve cases where SIM lock can't be dropped, all
xpt_async() calls in addition to xpt_done() calls are queued to completion
threads for async processing in clean environment without SIM lock held.

Instead of single CAM SWI thread, used for commands completion processing
before, use multiple (depending on number of CPUs) threads. Load balanced
between them using "hash" of the device B:T:L address.

HBA drivers that can drop SIM lock during completion processing and have
sufficient number of completion threads to efficiently scale to multiple
CPUs can use new function xpt_done_direct() to avoid extra context switch.
Make ahci(4) driver to use this mechanism depending on hardware setup.

Sponsored by: iXsystems, Inc.
MFC after: 2 months

Support the PCI-Express SSD in the new MacBook Air (model A1465)

Submitted by: Johannes Lundberg <johannes brilliantservice.co.jp>
MFC after: 3 days

Decode some bits defined in AHCI 1.3.1 Device Sleep Technical Proposal.
For now this is only conmetics to report HBA capabilities (Haswell?).

Submitted by: Dmitry Luhtionov <dmitryluhtionov@gmail.com>

Add new Coleto Creek device support: SATA, SMBus, and Watchdog devices.

MFC after: 1 week

Add ID for Marvell 88SE9215 AHCI SATA controller.

MFC after: 3 days

Add one more ID of Marvell SATA controller.

Submitted by: marck
MFC after: 3 days

Added output of device QUIRKS for CAM and AHCI devices during boot.

Reviewed by: mav
Approved by: pjd (mentor)
MFC after: 2 weeks

Add IDs for HighPoint RocketRAID 640L/642L/644L -- new series of 4-port
6Gbps PCIe 2.0 x2 SATA controllers, based on Marvell 88SE9235 chips.

MFC after: 1 week

Create controller-level DMA tag, handling range of supported addresses.
That simplifies logic for channels and gives the bus information about what
device actually allocated the tag.

Submitted by: jhb@

Read Asynchronous Notification statuses only if Port Multiplier or ATAPI
device are connected. ATA disks are not using ANs, while the extra register
read operation is quite expensive.

Depending on combination of running commands (NCQ/non-NCQ) try to avoid
extra read from PxCI/PxSACT registers. If only NCQ commands are running, we
don't really need PxCI. If only non-NCQ commands are running we don't need
PxSACT. Mixed set may happen only on controllers with FIS-based switching
when port multiplier is attached, and then we have to read both registers.

MFC after: 1 month

No need to erase all 64 bytes of CFIS area if we never use more then 16.

ahci(4) and siis(4) are ready to process the unmapped i/o requests

Sponsored by: The FreeBSD Foundation
Tested by: pho
Submitted by: bf (siis patch)

Reform the busdma API so that new types may be added without modifying
every architecture's busdma_machdep.c. It is done by unifying the
bus_dmamap_load_buffer() routines so that they may be called from MI
code. The MD busdma is then given a chance to do any final processing
in the complete() callback.

The cam changes unify the bus_dmamap_load* handling in cam drivers.

The arm and mips implementations are updated to track virtual
addresses for sync(). Previously this was done in a type specific
way. Now it is done in a generic way by recording the list of
virtuals in the map.

Submitted by: jeff (sponsored by EMC/Isilon)
Reviewed by: kan (previous version), scottl,
mjacob (isp(4), no objections for target mode changes)
Discussed with: ian (arm changes)
Tested by: marius (sparc64), mips (jmallet), isci(4) on x86 (jharris),
amd64 (Fabian Keil <freebsd-listen@fabiankeil.de>)

Disable MSI interrupts for SB600 chipset. According to the report they are
not functional.

PR: kern/174880, kern/174985, kern/175002
MFC after: 1 week

Add Intel Lynx Point PCH SATA Controller Device IDs

Add IDs for SATA controllers on AMD Hudson-2 series chipsets.
I am not exactly sure about the naming due to lack of specs on AMD site,
but it is better to have some identification then none at all.

MFC after: 1 month

Switch some PCI register reads from using magic numbers to using the names
defined in pcireg.h

MFC after: 1 week

Fix AHCI 1.2 version checks. This should be mostly cosmetic.

Submitted by: Dmitry Luhtionov <dmitryluhtionov@gmail.com>
MFC after: 1 week

Add IDs for JMicron JMB360/JMB362 AHCI SATA controllers.

MFC after: 1 week

Refactor enclosure manegement support in ahci(4). Move it out into separate
subdevice ahciem. Emulate SEMB SES device from AHCI LED interface to expose
it to users in form of ses(4) CAM device. If we ever see AHCI controllers
supporting SES of SAF-TE over I2C as described by specification, they should
fit well into this new picture.

Sponsored by: iXsystems, Inc.

Partially revert r236666:
Return PROTO_ATA protocol in response to XPT_PATH_INQ.

smartmontools uses it to identify ATA devices and I don't know any other
place now where it is important. It could probably use XPT_GDEV_TYPE
instead for more accurate protocol information, but let it live for now.

Reported by: matthew
MFC after: 3 days

Add IDs for Marvell 88SE9220/9230/9235 PCIe 2.0 x2 6Gbps SATA controllers.
Marvell 88SE9230 was confirmed to work, the rest two are just guessed.

MFC after: 1 week

ATA/SATA controllers have no idea about protocol of the connected device
until transport will do some probe actions (at least soft reset).
Make ATA/SATA SIMs to not report bogus and confusing PROTO_ATA protocol.
Make ATA/SATA transport to fill that gap by reporting protocol to SIM with
XPT_SET_TRAN_SETTINGS and patching XPT_GET_TRAN_SETTINGS results if needed.

Add quirk for Marvell based AHCI controller.

MFC after: 3 days
Suggested by: mav @

Add two functions xpt_batch_start() and xpt_batch_done() to the CAM SIM KPI
to allow drivers to handle request completion directly without passing
them to the CAM SWI thread removing extra context switch.
Modify all ATA/SATA drivers to use them.

Reviewed by: gibbs, ken
MFC after: 2 weeks

Fix names of some Marvell SATA chips. It looks like chips with proprietary
interface supported by mvs(4) are 88SX, while AHCI-like chips are 88SE.

PR: kern/165271
Submitted by: Jia-Shiun Li <jiashiun@gmail.com>
MFC after: 1 week

Add 0x2826 device ID for C600 (Patsburg) SATA controller in RAID mode.

Reviewed by: mav
Approved by: scottl

Add hw.ahci.force tunable to control whether AHCI drivers should attach
to known AHCI-capable chips (AMD/NVIDIA), configured for legacy emulation.

Enabled by default to get additional performance and functionality of AHCI
when it can't be enabled by BIOS. Can be disabled to honor BIOS settings if
needed for some reason.

MFC after: 1 month

Rename device_delete_all_children() into device_delete_children().

Suggested by: jhb @ and marius @
MFC after: 1 week

Move the device_delete_all_children() function from usb_util.c
to kern/subr_bus.c. Simplify this function so that it no longer
depends on malloc() to execute. Identify a few other places where
it makes sense to use device_delete_all_children().

MFC after: 1 week

Change the way how "not implemented" AHCI channels handled. Instead of
completely skipping them, create ahcich devices for them to allocate unit
numbers, but mark them as disabled to prevent driver probe and attach.

Last time some BIOSes tend to report unused channels as "not implemented".
This change makes ahcichX devices numbering consistent, independently of
connected disks. It makes per-channel driver hints usable and CAM devices
wiring possible on such systems.

Mark MALLOC_DEFINEs static that have no corresponding MALLOC_DECLAREs.

This means that their use is restricted to a single C file.

Add one more ID for the Marvell 88SE9128 6Gbps SATA controller.

MFC after: 3 days

Add ID for ASMedia ASM1061 2-port PCIe 2.0 x1 6Gb/s SATA controller.

Approved by: re (blackend)
MFC after: 1 week

Do not force AHCI mode on NVIDIA MCP89 SATA controllers. Recent Apple
Mac with this chipset does not initialize AHCI mode unless it is started
from EFI loader. However, legacy ATA mode works.

Submitted by: jkim@ (original version)
Approved by: re (kib)
MFC after: 1 week

In some cases, at least on Marvell 88SE912x controllers, Current Command
Slot field of the PxCMD register may point to an empty command slot.
That breaks command timeout detection logic, making impossible to find
what command actually caused timeout, and leading to infinite wait.
Workaround that by checking whether pointed command slot is really used
and can timeout in its time. And if not, fallback to the dumb algorithm
used with FBS -- let all commands to time out and then fail all of them.

Approved by: re (kib)
MFC after: 1 week

Add ID for Marvell 88SE9125 SATA controller.

PR: kern/157843
MFC after: 1 week

Add Marvell 88SE9172 chip PCI ID.

Marvell 88SE91xx controllers are known to report soft-reset completion
without waiting for device readiness (or at least not updating FIS receive
area in time). To workaround that, special quirk was added earlier to wait
for the FIS receive area update. But it was found that under same PCI ID
0x91231b4b and revision 0x11 there are two completely different chip
versions (firmware?): HBA and RAID. The problem is that RAID version in
some cases, such as hot-plug, does not update FIS receive area at all!

To workaround that, differentiate the chip versions by their capabilities,
and, if RAID version found, skip FIS receive area update waiting and read
device signature from the PxSIG register instead. This method doesn't work
for HBA version when PMP attached, so keep using previous workaround there.

According to SATA specification, when Serial ATA Enclosure Management Bridge
(SEMB) is unable to communicate to Storage Enclosure Processor (SEP), in
response to hard and soft resets it should among other things return value
0x7F in Status register. The weird side is that it means DRQ bit set, which
tells that reset request is not completed. It would be fine if SEMB was the
only device on port. But if SEMB connected to PMP or built into it, it may
block access to other devices sharing same SATA port.

Make some tunings/fixes to soft-reset handling to workaround the issue:
- ahci(4): request CLO on the port after soft reset to ignore DRQ bit;
- siis(4): gracefully reinitialize port after soft reset timeout (hardware
doesn't detect reset request completion in this case);
- mvs(4): if PMP is used, send dummy soft-reset to the PMP port to make it
clear DRQ bit for us.

For now this makes quirks in ata_pmp.c, hiding SEMB ports of SiI3726/SiI4726
PMPs, less important. Further, if hardware permit, I hope to implement real
SEMB support.

Add support for "LED" enclosure management messages, defined by the AHCI.

When supported by hardware, this allows to control per-port activity, locate
and fault LEDs via the led(4) API for localization and status reporting
purposes. Supporting AHCI controllers may transmit that information to the
backplane controllers via SGPIO interface. Backplane controllers interpret
received statuses in some way (IBPI standard) to report them using present
indicators.

Chipset support for the new Intel Panther Point PCH, thanks
to Seth Heasley for preparing the changes.

Add PCI ID for Marvell 88SE9182 -- PCIe 2.x x2 relative of the 88SE912x.

Submitted by: dchagin
MFC after: 1 week

Fix some English grammar.

According to specification. device should respond to COMRESET with COMINIT
in no more then 10ms. If we detected no device presence within that time,
there is no reason to wait longer.

Properly handle memory allocation errors during error recovery.

Handle ready timeout during polled operation same as done in mvs(4) before.

- Tune different wait loops to cut some more milliseconds from reset time.
- Do not call ahci_start() before device signature received. It is required
by the specification and caused non-fatal reset timeouts on AMD chipsets.

Some changes around hot-plug and interface power-management:
- use ATA_SE_EXCHANGED (SError.DIAG.X) bit to detect hot-plug events when
power-management enabled and ATA_SE_PHY_CHANGED (SError.DIAG.N) can't be
trusted;
- on controllers supporting staggered spin-up (SS) put unused channels
into Listen state instead of Off. It should still save some power, but
allow plug-in events to be detected;
- on controllers supporting cold presence detection (CPD), when power
management enabled, use CPD events to detect hot-plug in addition to PHY
events.

Improve SATA Asynchronous Notification feature support in CAM:
- make SATA SIMs announce capabilities to handle SDB with Notification bit;
- make PMP driver honor this SIMs capability;
- make SATA XPT to negotiate and enable this feature for ATAPI devices.

This feature allows supporting SATA ATAPI devices to inform system about
some events happened, that may require attention. In my case this allows
LG GH22LS50 SATA DVR-RW drive to report tray open/close events. Events
reported to CAM in form of AC_SCSI_AEN async. Further they could be used
as a hints for checking device status and reporting media change to upper
layers, for example, via spoiling mechanism of GEOM.

Refactor hard-reset implementation in ahci(4).

Instead of spinning in a tight loop for up to 15 seconds, polling for device
readiness while it spins up, return reset completion just after PHY reports
"connect well" or 100ms connection timeout. If device was found, use callout
for checking device readiness with 100ms period up to full 31 second timeout.

This fixes system freeze for 5-10 seconds on drives hot plug-in.

Implement automatic SCSI sense fetching for ahci(4).

Add one more ID for Marvell 88SE912x chip found on Asus U3S6 card.

Submitted by: Jonas Jonsson <fatbrain@gmail.com>

Add some more IDs of HighPoint RocketRAID 64x.

Restore DH89xxCC/Patsburg chip IDs accentally dropped at r218596.

Disable NCQ for multiport Marvell 88SX61XX SATA controllers. Simultaneous
active I/O to several disks (copying large file on ZFS) causes timeout after
just a few seconds of run. Single port 88SX6111 seems like not affected.

Skip reading transferred bytes count for these controllers. It works for
88SX6111, but 88SX6145 always returns zero there. Haven't tested others,
but better to be safe.

Support for the new Patsburg PCH chipset:
- SMBus Controller
- SATA Controller
- HD Audio Controller
- Watchdog Controller

Thanks to Seth Heasley (seth.heasley@intel.com) for providing us code.

MFC after 3 days

Support for the new DH89xxCC PCH chipset including:
- SATA controller
- Watchdog timer
- SMBus controller

Add IDs for HighPoint RocketRAID 64x controllers.

These controllers consist of two Marvell 88SE9128 6Gbps SATA chips and
PLX PCIe bridge. As result, they seem to be agree to work with ahci(4)
as usual HBAs. The only noticed issue is that RAID BIOS disables all
drive caches during boot, though `camcontrol cmd ...` is able to fix that.

Those who wants RAID functionality can still use closed proprietary driver
from HighPoint site.

MFC after: 1 week

Add IDs of HighPoint RocketRAID 62x cards (Marvell 88SE9128 chips).

PR: kern/152926
Submitted by: Mike Tancsa <mike@sentex.net>
MFC after: 1 week

Fix small typo.

Submitted by: Artem Belevich

Teach ahci(4), siis(4) and ATA_CAM ata(4) wrapper report to CAM residual
I/O length on underruns, that often happens for some SCSI commands.

Add missing mtx_destroy() on channel attach failure.

Fix panic, when due to some kind of congestion on FIS-based switching
port multiplier some command triggers false positive timeout, but then
completes normally.

MFC after: 2 weeks

MFata(4):
Add Intel Cougar Point PCH SATA Controller DeviceIDs. Correct some existing
entries for Intel Ibex Peak (5 Series/3400 Series) PCH SATA controllers.

Export PCI IDs of ATA/SATA controllers through CAM and ata(4) layers to
GEOM. This information needed for proper soft-RAID's on-disk metadata
reading and writing.

Disable NCQ and PMP support for VIA VT8251 AHCI. It was reported to be
unreliable under load. Linux does the same.

Plug memory leak to silent Coverity. Error is still not really handled.

Found with: Coverity Prevent(tm)
CID: 4130

Fix attach errors handling.

Found with: Coverity Prevent(tm)
CID: 3424

Fill rman range start/end values. It makes devinfo output more readable.

Report ATA/SATA channel number to NewBus at location string.

Improve suspend/resume support. Make sure controller is idle on suspend
and reset it on resume.

Enable PCI busmastering explicitly to be sure.

Make SATA XPT negotiate and enable some additional SATA features, such as:
- device initiated power management (some devices support only this way);
- Automatic Partial to Slumber Transition (more power saving);
- DMA auto-activation (expected to slightly improve performance).
More features could be added later, when hardware supports.

Add Target/LUN ID checks and deny access to targets 1-14 when PMP absent.
Enforce PMA bit clearing when PMP detached to avoid further scan timeouts.

Revert r206755. It causes some laptops to stop booting.

Add another ICH7M chipset that works.

MFC after: 1 week

- Spec tells that CCC interrupt is edge triggered. Acknowledge it as such.
- Do not try to enable CCC if it is not supported.

MFp4:
With FBS enabled, we have no idea what command caused timeout.
Implement same logic as in siis(4) - wait for other commands
complete or timeout and then give some more time.

Disable PHY of unconnected ports when interface power management enabled.
It allows to save a bit more power (about 0.5W on 2 unused ports of ICH8M).

- Give ATA/SATA SIMs info about ATAPI packet size, supported by device.
- Make ATA XPT to reject longer SCSI CDBs then supported by device, or
any SCSI CDBs, if device doesn't support ATAPI.

Reset port on disconnect event, to abort any running requests.

Add FIS-based switching support. If controller supports FBS, it allows
several devices beyond Port Multiplier to work simultaneously, substantially
increasing performance.

MFp4: Large set of CAM inprovements.

- Unify bus reset/probe sequence. Whenever bus attached at boot or later,
CAM will automatically reset and scan it. It allows to remove duplicate
code from many drivers.
- Any bus, attached before CAM completed it's boot-time initialization,
will equally join to the process, delaying boot if needed.
- New kern.cam.boot_delay loader tunable should help controllers that
are still unable to register their buses in time (such as slow USB/
PCCard/ CardBus devices), by adding one more event to wait on boot.
- To allow synchronization between different CAM levels, concept of
requests priorities was extended. Priorities now split between several
"run levels". Device can be freezed at specified level, allowing higher
priority requests to pass. For example, no payload requests allowed,
until PMP driver enable port. ATA XPT negotiate transfer parameters,
periph driver configure caching and so on.
- Frozen requests are no more counted by request allocation scheduler.
It fixes deadlocks, when frozen low priority payload requests occupying
slots, required by higher levels to manage theit execution.
- Two last changes were holding proper ATA reinitialization and error
recovery implementation. Now it is done: SATA controllers and Port
Multipliers now implement automatic hot-plug and should correctly
recover from timeouts and bus resets.
- Improve SCSI error recovery for devices on buses without automatic sense
reporting, such as ATAPI or USB. For example, it allows CAM to wait, while
CD drive loads disk, instead of immediately return error status.
- Decapitalize diagnostic messages and make them more readable and sensible.
- Teach PMP driver to limit maximum speed on fan-out ports.
- Make boot wait for PMP scan completes, and make rescan more reliable.
- Fix pass driver, to return CCB to user level in case of error.
- Increase number of retries in cd driver, as device may return several UAs.

Add support for SATA part of Marvell 88SE912x controllers to ahci(4).
Limit early revisions from 6Gb/s to 3Gb/s by default, or they negotiate
only 1.5Gbps, when 3Gb/s devices connected.

Add dummy driver for PATA part of these controllers, preventing generic
driver attach them. It causes system freeze when SATA controller used after
PATA was touched.

While AHCI specification tells that multi-vector MSI doesn't use global IS
register, nVidia chipsets have different oppinion, requiring every interrupt
to be acknowledged there.

While there, add interrupt descriptions in multi-vector MSI mode.

Avoid false positive probe on ICH6 chipsets.

Clear all ports interrupt status bits in single write. Clearing one by one
causes additional MSIs messages sent if several ports asked for attention
same time. Time window before clearing is not important, as these interrupts
are level triggered by interrupt source.

Add Asynchronous Notification support for controllers without SNTF
capability by snooping SDB FIS receive area. It should be even faster
then regular way, but less reliable.

MFp4:
Improve ATA mode/SATA revision control.

MFp4:
- Extend XPT-SIM transfer settings control API. Now it allows to report to
SATA SIM number of tags supported by each device, implement ATA mode and
SATA revision negotiation for both SATA and PATA SIMs.
- Make ahci(4) and siis(4) to use submitted maximum tag number, when
scheduling requests. It allows to support NCQ on devices with lower tags
count then controller supports.
- Make PMP driver to report attached devices connection speeds.
- Implement ATA mode negotiation between user settings, device and
controller capabilities.

Do not attach JMicrons with single PCI function. They are not working as
AHCI for some reason, even when declaring so. Let atajmicron configure
them for us and provide PATA support.

Change the way in which AHCI+PATA combined controllers, such as JMicron
and Marvell handled. Instead of trying to attach two different drivers to
single device, wrapping each call, make one of them (atajmicron, atamarvell)
attach do device solely, but create child device for AHCI driver,
passing it all required resources. It is quite easy, as none of
resources are shared, except IRQ.

As result, it:
- makes drivers operation more independent and straitforward,
- allows to use new ahci(4) driver with such devices, adding support for
new features, such as PMP and NCQ, same time keeping legacy PATA support,
- will allow to just drop old ataahci driver, when it's time come.

MFp4:
Check SNCQ HBA capability bit when reporting NCQ support to CAM.

MFp4:
- Move tagged queueing control from ADA to ATA XPT. It allows to control
device command queue length correctly. First step to support < 32 tags.
- Limit queue for non-tagged devices by 2 slots for ahci(4) and siis(4).
- Implement quirk matching for ATA devices.
- Move xpt_schedule_dev_sendq() from header to source file.
- Move delayed queue shrinking to the more expected place - element freeing.
- Remove some SCSIsms in ATA.

MFp4:
Add set of chip IDs, known to support AHCI.

MFp4:
- Handle timeouts and fatal errors with port hard-reset. The rest of
recovery will be done by XPT on receiving async event. More gracefull
per-device soft-reset recovery can be implemented later.
- Add workaround for ATI SB600/SB700 PMP probe related bug, to speedup boot.

Revert interrupt reason check order back.
ATAPI errors may set IF bit together with TFE.

MFp4:
Report real max_target = 15. SIM doesn't need to know that target 15 is PMP.
It is XPT business.

MFp4:
On error, freeze device queue, to allow periph driver to do proper recovery.
Freeze SIM queue only in some cases, when it is needed to protect SIM.

Implement better command timeout detection logic for non-queued commands.
This fixes false positives when command with short timeout waiting for the
long one. For example, when hald tastes CD during burning process.

Read and clear SERR register on interrupt.

On command timeout handle frozen command first, to not run it inside
XXX_end_transaction().

Submitted by: avg

To save small bit of CPU time, hide part of SNTF register read latency
behind other reads.

Round maxio for ATI SB600 to 64K.

Submitted by: scottl@

ATI SB600 can't handle 256 sectors transfers with FPDMA (NCQ).

MFC after: 3 days

Fix build with INVARIANTS.

MFp4:
- Add Command Completion Coalescing support.
- Add SNTF support.
- Add two more power management modes (4, 5), implemented on driver level.
- Fix interface mode setting.
- Reduce interface reset time.
- Do not report meaningless protocol/transport versions.
- Report CAP2 register content.
- Some performance optimizations.

Separate the parallel scsi knowledge out of the core of the XPT, and
modularize it so that new transports can be created.

Add a transport for SATA

Add a periph+protocol layer for ATA

Add a driver for AHCI-compliant hardware.

Add a maxio field to CAM so that drivers can advertise their max
I/O capability. Modify various drivers so that they are insulated
from the value of MAXPHYS.

The new ATA/SATA code supports AHCI-compliant hardware, and will override
the classic ATA driver if it is loaded as a module at boot time or compiled
into the kernel. The stack now support NCQ (tagged queueing) for increased
performance on modern SATA drives. It also supports port multipliers.

ATA drives are accessed via 'ada' device nodes. ATAPI drives are
accessed via 'cd' device nodes. They can all be enumerated and manipulated
via camcontrol, just like SCSI drives. SCSI commands are not translated to
their ATA equivalents; ATA native commands are used throughout the entire
stack, including camcontrol. See the camcontrol manpage for further
details. Testing this code may require that you update your fstab, and
possibly modify your BIOS to enable AHCI functionality, if available.

This code is very experimental at the moment. The userland ABI/API has
changed, so applications will need to be recompiled. It may change
further in the near future. The 'ada' device name may also change as
more infrastructure is completed in this project. The goal is to
eventually put all CAM busses and devices until newbus, allowing for
interesting topology and management options.

Few functional changes will be seen with existing SCSI/SAS/FC drivers,
though the userland ABI has still changed. In the future, transports
specific modules for SAS and FC may appear in order to better support
the topologies and capabilities of these technologies.

The modularization of CAM and the addition of the ATA/SATA modules is
meant to break CAM out of the mold of being specific to SCSI, letting it
grow to be a framework for arbitrary transports and protocols. It also
allows drivers to be written to support discrete hardware without
jeopardizing the stability of non-related hardware. While only an AHCI
driver is provided now, a Silicon Image driver is also in the works.
Drivers for ICH1-4, ICH5-6, PIIX, classic IDE, and any other hardware
is possible and encouraged. Help with new transports is also encouraged.

Submitted by: scottl, mav
Approved by: re