ahci_generic.c revision 218149
1/*- 2 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ahci/ahci.c 218149 2011-02-01 01:05:11Z jfv $"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/ata.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/malloc.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <sys/sema.h> 41#include <sys/taskqueue.h> 42#include <vm/uma.h> 43#include <machine/stdarg.h> 44#include <machine/resource.h> 45#include <machine/bus.h> 46#include <sys/rman.h> 47#include <dev/pci/pcivar.h> 48#include <dev/pci/pcireg.h> 49#include "ahci.h" 50 51#include <cam/cam.h> 52#include <cam/cam_ccb.h> 53#include <cam/cam_sim.h> 54#include <cam/cam_xpt_sim.h> 55#include <cam/cam_debug.h> 56 57/* local prototypes */ 58static int ahci_setup_interrupt(device_t dev); 59static void ahci_intr(void *data); 60static void ahci_intr_one(void *data); 61static int ahci_suspend(device_t dev); 62static int ahci_resume(device_t dev); 63static int ahci_ch_init(device_t dev); 64static int ahci_ch_deinit(device_t dev); 65static int ahci_ch_suspend(device_t dev); 66static int ahci_ch_resume(device_t dev); 67static void ahci_ch_pm(void *arg); 68static void ahci_ch_intr_locked(void *data); 69static void ahci_ch_intr(void *data); 70static int ahci_ctlr_reset(device_t dev); 71static int ahci_ctlr_setup(device_t dev); 72static void ahci_begin_transaction(device_t dev, union ccb *ccb); 73static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 74static void ahci_execute_transaction(struct ahci_slot *slot); 75static void ahci_timeout(struct ahci_slot *slot); 76static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 77static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 78static void ahci_dmainit(device_t dev); 79static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 80static void ahci_dmafini(device_t dev); 81static void ahci_slotsalloc(device_t dev); 82static void ahci_slotsfree(device_t dev); 83static void ahci_reset(device_t dev); 84static void ahci_start(device_t dev, int fbs); 85static void ahci_stop(device_t dev); 86static void ahci_clo(device_t dev); 87static void ahci_start_fr(device_t dev); 88static void ahci_stop_fr(device_t dev); 89 90static int ahci_sata_connect(struct ahci_channel *ch); 91static int ahci_sata_phy_reset(device_t dev); 92static int ahci_wait_ready(device_t dev, int t); 93 94static void ahci_issue_read_log(device_t dev); 95static void ahci_process_read_log(device_t dev, union ccb *ccb); 96 97static void ahciaction(struct cam_sim *sim, union ccb *ccb); 98static void ahcipoll(struct cam_sim *sim); 99 100MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 101 102static struct { 103 uint32_t id; 104 uint8_t rev; 105 const char *name; 106 int quirks; 107#define AHCI_Q_NOFORCE 1 108#define AHCI_Q_NOPMP 2 109#define AHCI_Q_NONCQ 4 110#define AHCI_Q_1CH 8 111#define AHCI_Q_2CH 16 112#define AHCI_Q_4CH 32 113#define AHCI_Q_EDGEIS 64 114#define AHCI_Q_SATA2 128 115#define AHCI_Q_NOBSYRES 256 116#define AHCI_Q_NOAA 512 117} ahci_ids[] = { 118 {0x43801002, 0x00, "ATI IXP600", 0}, 119 {0x43901002, 0x00, "ATI IXP700", 0}, 120 {0x43911002, 0x00, "ATI IXP700", 0}, 121 {0x43921002, 0x00, "ATI IXP700", 0}, 122 {0x43931002, 0x00, "ATI IXP700", 0}, 123 {0x43941002, 0x00, "ATI IXP800", 0}, 124 {0x43951002, 0x00, "ATI IXP800", 0}, 125 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE}, 126 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE}, 127 {0x26818086, 0x00, "Intel ESB2", 0}, 128 {0x26828086, 0x00, "Intel ESB2", 0}, 129 {0x26838086, 0x00, "Intel ESB2", 0}, 130 {0x27c18086, 0x00, "Intel ICH7", 0}, 131 {0x27c38086, 0x00, "Intel ICH7", 0}, 132 {0x27c58086, 0x00, "Intel ICH7M", 0}, 133 {0x27c68086, 0x00, "Intel ICH7M", 0}, 134 {0x28218086, 0x00, "Intel ICH8", 0}, 135 {0x28228086, 0x00, "Intel ICH8", 0}, 136 {0x28248086, 0x00, "Intel ICH8", 0}, 137 {0x28298086, 0x00, "Intel ICH8M", 0}, 138 {0x282a8086, 0x00, "Intel ICH8M", 0}, 139 {0x29228086, 0x00, "Intel ICH9", 0}, 140 {0x29238086, 0x00, "Intel ICH9", 0}, 141 {0x29248086, 0x00, "Intel ICH9", 0}, 142 {0x29258086, 0x00, "Intel ICH9", 0}, 143 {0x29278086, 0x00, "Intel ICH9", 0}, 144 {0x29298086, 0x00, "Intel ICH9M", 0}, 145 {0x292a8086, 0x00, "Intel ICH9M", 0}, 146 {0x292b8086, 0x00, "Intel ICH9M", 0}, 147 {0x292c8086, 0x00, "Intel ICH9M", 0}, 148 {0x292f8086, 0x00, "Intel ICH9M", 0}, 149 {0x294d8086, 0x00, "Intel ICH9", 0}, 150 {0x294e8086, 0x00, "Intel ICH9M", 0}, 151 {0x3a058086, 0x00, "Intel ICH10", 0}, 152 {0x3a228086, 0x00, "Intel ICH10", 0}, 153 {0x3a258086, 0x00, "Intel ICH10", 0}, 154 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0}, 155 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0}, 156 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0}, 157 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0}, 158 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0}, 159 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0}, 160 {0x1c028086, 0x00, "Intel Cougar Point", 0}, 161 {0x1c038086, 0x00, "Intel Cougar Point", 0}, 162 {0x1c048086, 0x00, "Intel Cougar Point", 0}, 163 {0x1c058086, 0x00, "Intel Cougar Point", 0}, 164 {0x23238086, 0x00, "Intel DH89xxCC", 0}, 165 {0x1d028086, 0x00, "Intel Patsburg", 0}, 166 {0x1d048086, 0x00, "Intel Patsburg", 0}, 167 {0x1d068086, 0x00, "Intel Patsburg", 0}, 168 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE}, 169 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE}, 170 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE}, 171 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE}, 172 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE}, 173 {0x611111ab, 0x00, "Marvell 88SX6111", AHCI_Q_NOFORCE|AHCI_Q_1CH|AHCI_Q_EDGEIS}, 174 {0x612111ab, 0x00, "Marvell 88SX6121", AHCI_Q_NOFORCE|AHCI_Q_2CH|AHCI_Q_EDGEIS}, 175 {0x614111ab, 0x00, "Marvell 88SX6141", AHCI_Q_NOFORCE|AHCI_Q_4CH|AHCI_Q_EDGEIS}, 176 {0x614511ab, 0x00, "Marvell 88SX6145", AHCI_Q_NOFORCE|AHCI_Q_4CH|AHCI_Q_EDGEIS}, 177 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES}, 178 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES}, 179 {0x06201103, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 180 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 181 {0x06221103, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 182 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 183 {0x06401103, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 184 {0x06441103, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 185 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 186 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 187 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 188 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 189 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 190 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 191 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 192 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 193 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 194 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 195 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 196 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 197 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 198 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 199 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 200 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 201 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 202 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 203 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 204 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 205 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 206 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 207 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 208 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 209 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 210 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 211 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 212 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 213 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 214 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 215 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 216 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 217 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 218 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 219 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 220 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 221 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 222 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 223 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 224 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 225 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 226 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 227 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 228 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 229 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 230 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 231 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 232 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 233 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 234 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 235 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 236 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 237 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 238 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 239 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 240 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 241 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 242 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 243 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 244 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 245 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 246 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 247 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 248 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 249 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 250 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 251 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 252 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 253 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 254 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 255 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 256 {0x11841039, 0x00, "SiS 966", 0}, 257 {0x11851039, 0x00, "SiS 968", 0}, 258 {0x01861039, 0x00, "SiS 968", 0}, 259 {0x00000000, 0x00, NULL, 0} 260}; 261 262static int 263ahci_probe(device_t dev) 264{ 265 char buf[64]; 266 int i, valid = 0; 267 uint32_t devid = pci_get_devid(dev); 268 uint8_t revid = pci_get_revid(dev); 269 270 /* Is this a possible AHCI candidate? */ 271 if (pci_get_class(dev) == PCIC_STORAGE && 272 pci_get_subclass(dev) == PCIS_STORAGE_SATA && 273 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0) 274 valid = 1; 275 /* Is this a known AHCI chip? */ 276 for (i = 0; ahci_ids[i].id != 0; i++) { 277 if (ahci_ids[i].id == devid && 278 ahci_ids[i].rev <= revid && 279 (valid || !(ahci_ids[i].quirks & AHCI_Q_NOFORCE))) { 280 /* Do not attach JMicrons with single PCI function. */ 281 if (pci_get_vendor(dev) == 0x197b && 282 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0) 283 return (ENXIO); 284 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 285 ahci_ids[i].name); 286 device_set_desc_copy(dev, buf); 287 return (BUS_PROBE_VENDOR); 288 } 289 } 290 if (!valid) 291 return (ENXIO); 292 device_set_desc_copy(dev, "AHCI SATA controller"); 293 return (BUS_PROBE_VENDOR); 294} 295 296static int 297ahci_ata_probe(device_t dev) 298{ 299 char buf[64]; 300 int i; 301 uint32_t devid = pci_get_devid(dev); 302 uint8_t revid = pci_get_revid(dev); 303 304 if ((intptr_t)device_get_ivars(dev) >= 0) 305 return (ENXIO); 306 /* Is this a known AHCI chip? */ 307 for (i = 0; ahci_ids[i].id != 0; i++) { 308 if (ahci_ids[i].id == devid && 309 ahci_ids[i].rev <= revid) { 310 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 311 ahci_ids[i].name); 312 device_set_desc_copy(dev, buf); 313 return (BUS_PROBE_VENDOR); 314 } 315 } 316 device_set_desc_copy(dev, "AHCI SATA controller"); 317 return (BUS_PROBE_VENDOR); 318} 319 320static int 321ahci_attach(device_t dev) 322{ 323 struct ahci_controller *ctlr = device_get_softc(dev); 324 device_t child; 325 int error, unit, speed, i; 326 uint32_t devid = pci_get_devid(dev); 327 uint8_t revid = pci_get_revid(dev); 328 u_int32_t version; 329 330 ctlr->dev = dev; 331 i = 0; 332 while (ahci_ids[i].id != 0 && 333 (ahci_ids[i].id != devid || 334 ahci_ids[i].rev > revid)) 335 i++; 336 ctlr->quirks = ahci_ids[i].quirks; 337 resource_int_value(device_get_name(dev), 338 device_get_unit(dev), "ccc", &ctlr->ccc); 339 /* if we have a memory BAR(5) we are likely on an AHCI part */ 340 ctlr->r_rid = PCIR_BAR(5); 341 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 342 &ctlr->r_rid, RF_ACTIVE))) 343 return ENXIO; 344 /* Setup our own memory management for channels. */ 345 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 346 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 347 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 348 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 349 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 350 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 351 return (error); 352 } 353 if ((error = rman_manage_region(&ctlr->sc_iomem, 354 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 355 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 356 rman_fini(&ctlr->sc_iomem); 357 return (error); 358 } 359 pci_enable_busmaster(dev); 360 /* Reset controller */ 361 if ((error = ahci_ctlr_reset(dev)) != 0) { 362 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 363 rman_fini(&ctlr->sc_iomem); 364 return (error); 365 }; 366 /* Get the HW capabilities */ 367 version = ATA_INL(ctlr->r_mem, AHCI_VS); 368 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 369 if (version >= 0x00010020) 370 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 371 if (ctlr->caps & AHCI_CAP_EMS) 372 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 373 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 374 if (ctlr->quirks & AHCI_Q_1CH) { 375 ctlr->caps &= ~AHCI_CAP_NPMASK; 376 ctlr->ichannels &= 0x01; 377 } 378 if (ctlr->quirks & AHCI_Q_2CH) { 379 ctlr->caps &= ~AHCI_CAP_NPMASK; 380 ctlr->caps |= 1; 381 ctlr->ichannels &= 0x03; 382 } 383 if (ctlr->quirks & AHCI_Q_4CH) { 384 ctlr->caps &= ~AHCI_CAP_NPMASK; 385 ctlr->caps |= 3; 386 ctlr->ichannels &= 0x0f; 387 } 388 ctlr->channels = MAX(flsl(ctlr->ichannels), 389 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 390 if (ctlr->quirks & AHCI_Q_NOPMP) 391 ctlr->caps &= ~AHCI_CAP_SPM; 392 if (ctlr->quirks & AHCI_Q_NONCQ) 393 ctlr->caps &= ~AHCI_CAP_SNCQ; 394 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 395 ctlr->ccc = 0; 396 ahci_ctlr_setup(dev); 397 /* Setup interrupts. */ 398 if (ahci_setup_interrupt(dev)) { 399 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 400 rman_fini(&ctlr->sc_iomem); 401 return ENXIO; 402 } 403 /* Announce HW capabilities. */ 404 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 405 device_printf(dev, 406 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 407 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 408 ((version >> 4) & 0xf0) + (version & 0x0f), 409 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 410 ((speed == 1) ? "1.5":((speed == 2) ? "3": 411 ((speed == 3) ? "6":"?"))), 412 (ctlr->caps & AHCI_CAP_SPM) ? 413 "supported" : "not supported", 414 (ctlr->caps & AHCI_CAP_FBSS) ? 415 " with FBS" : ""); 416 if (bootverbose) { 417 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 418 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 419 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 420 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 421 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 422 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 423 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 424 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 425 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 426 ((speed == 1) ? "1.5":((speed == 2) ? "3": 427 ((speed == 3) ? "6":"?")))); 428 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 429 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 430 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 431 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 432 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 433 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 434 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 435 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 436 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 437 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 438 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 439 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 440 } 441 if (bootverbose && version >= 0x00010020) { 442 device_printf(dev, "Caps2:%s%s%s\n", 443 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 444 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 445 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 446 } 447 if (bootverbose && (ctlr->caps & AHCI_CAP_EMS)) { 448 device_printf(dev, "EM Caps:%s%s%s%s%s%s%s%s\n", 449 (ctlr->capsem & AHCI_EM_PM) ? " PM":"", 450 (ctlr->capsem & AHCI_EM_ALHD) ? " ALHD":"", 451 (ctlr->capsem & AHCI_EM_XMT) ? " XMT":"", 452 (ctlr->capsem & AHCI_EM_SMB) ? " SMB":"", 453 (ctlr->capsem & AHCI_EM_SGPIO) ? " SGPIO":"", 454 (ctlr->capsem & AHCI_EM_SES2) ? " SES-2":"", 455 (ctlr->capsem & AHCI_EM_SAFTE) ? " SAF-TE":"", 456 (ctlr->capsem & AHCI_EM_LED) ? " LED":""); 457 } 458 /* Attach all channels on this controller */ 459 for (unit = 0; unit < ctlr->channels; unit++) { 460 if ((ctlr->ichannels & (1 << unit)) == 0) 461 continue; 462 child = device_add_child(dev, "ahcich", -1); 463 if (child == NULL) 464 device_printf(dev, "failed to add channel device\n"); 465 else 466 device_set_ivars(child, (void *)(intptr_t)unit); 467 } 468 bus_generic_attach(dev); 469 return 0; 470} 471 472static int 473ahci_detach(device_t dev) 474{ 475 struct ahci_controller *ctlr = device_get_softc(dev); 476 device_t *children; 477 int nchildren, i; 478 479 /* Detach & delete all children */ 480 if (!device_get_children(dev, &children, &nchildren)) { 481 for (i = 0; i < nchildren; i++) 482 device_delete_child(dev, children[i]); 483 free(children, M_TEMP); 484 } 485 /* Free interrupts. */ 486 for (i = 0; i < ctlr->numirqs; i++) { 487 if (ctlr->irqs[i].r_irq) { 488 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 489 ctlr->irqs[i].handle); 490 bus_release_resource(dev, SYS_RES_IRQ, 491 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 492 } 493 } 494 pci_release_msi(dev); 495 /* Free memory. */ 496 rman_fini(&ctlr->sc_iomem); 497 if (ctlr->r_mem) 498 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 499 return (0); 500} 501 502static int 503ahci_ctlr_reset(device_t dev) 504{ 505 struct ahci_controller *ctlr = device_get_softc(dev); 506 int timeout; 507 508 if (pci_read_config(dev, 0x00, 4) == 0x28298086 && 509 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 510 pci_write_config(dev, 0x92, 0x01, 1); 511 /* Enable AHCI mode */ 512 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 513 /* Reset AHCI controller */ 514 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 515 for (timeout = 1000; timeout > 0; timeout--) { 516 DELAY(1000); 517 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 518 break; 519 } 520 if (timeout == 0) { 521 device_printf(dev, "AHCI controller reset failure\n"); 522 return ENXIO; 523 } 524 /* Reenable AHCI mode */ 525 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 526 return (0); 527} 528 529static int 530ahci_ctlr_setup(device_t dev) 531{ 532 struct ahci_controller *ctlr = device_get_softc(dev); 533 /* Clear interrupts */ 534 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 535 /* Configure CCC */ 536 if (ctlr->ccc) { 537 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 538 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 539 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 540 (4 << AHCI_CCCC_CC_SHIFT) | 541 AHCI_CCCC_EN); 542 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 543 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 544 if (bootverbose) { 545 device_printf(dev, 546 "CCC with %dms/4cmd enabled on vector %d\n", 547 ctlr->ccc, ctlr->cccv); 548 } 549 } 550 /* Enable AHCI interrupts */ 551 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 552 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 553 return (0); 554} 555 556static int 557ahci_suspend(device_t dev) 558{ 559 struct ahci_controller *ctlr = device_get_softc(dev); 560 561 bus_generic_suspend(dev); 562 /* Disable interupts, so the state change(s) doesn't trigger */ 563 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 564 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 565 return 0; 566} 567 568static int 569ahci_resume(device_t dev) 570{ 571 int res; 572 573 if ((res = ahci_ctlr_reset(dev)) != 0) 574 return (res); 575 ahci_ctlr_setup(dev); 576 return (bus_generic_resume(dev)); 577} 578 579static int 580ahci_setup_interrupt(device_t dev) 581{ 582 struct ahci_controller *ctlr = device_get_softc(dev); 583 int i, msi = 1; 584 585 /* Process hints. */ 586 resource_int_value(device_get_name(dev), 587 device_get_unit(dev), "msi", &msi); 588 if (msi < 0) 589 msi = 0; 590 else if (msi == 1) 591 msi = min(1, pci_msi_count(dev)); 592 else if (msi > 1) 593 msi = pci_msi_count(dev); 594 /* Allocate MSI if needed/present. */ 595 if (msi && pci_alloc_msi(dev, &msi) == 0) { 596 ctlr->numirqs = msi; 597 } else { 598 msi = 0; 599 ctlr->numirqs = 1; 600 } 601 /* Check for single MSI vector fallback. */ 602 if (ctlr->numirqs > 1 && 603 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 604 device_printf(dev, "Falling back to one MSI\n"); 605 ctlr->numirqs = 1; 606 } 607 /* Allocate all IRQs. */ 608 for (i = 0; i < ctlr->numirqs; i++) { 609 ctlr->irqs[i].ctlr = ctlr; 610 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0); 611 if (ctlr->numirqs == 1 || i >= ctlr->channels || 612 (ctlr->ccc && i == ctlr->cccv)) 613 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 614 else if (i == ctlr->numirqs - 1) 615 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 616 else 617 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 618 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 619 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 620 device_printf(dev, "unable to map interrupt\n"); 621 return ENXIO; 622 } 623 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 624 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr, 625 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 626 /* SOS XXX release r_irq */ 627 device_printf(dev, "unable to setup interrupt\n"); 628 return ENXIO; 629 } 630 if (ctlr->numirqs > 1) { 631 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 632 ctlr->irqs[i].handle, 633 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 634 "ch%d" : "%d", i); 635 } 636 } 637 return (0); 638} 639 640/* 641 * Common case interrupt handler. 642 */ 643static void 644ahci_intr(void *data) 645{ 646 struct ahci_controller_irq *irq = data; 647 struct ahci_controller *ctlr = irq->ctlr; 648 u_int32_t is, ise = 0; 649 void *arg; 650 int unit; 651 652 if (irq->mode == AHCI_IRQ_MODE_ALL) { 653 unit = 0; 654 if (ctlr->ccc) 655 is = ctlr->ichannels; 656 else 657 is = ATA_INL(ctlr->r_mem, AHCI_IS); 658 } else { /* AHCI_IRQ_MODE_AFTER */ 659 unit = irq->r_irq_rid - 1; 660 is = ATA_INL(ctlr->r_mem, AHCI_IS); 661 } 662 /* CCC interrupt is edge triggered. */ 663 if (ctlr->ccc) 664 ise = 1 << ctlr->cccv; 665 /* Some controllers have edge triggered IS. */ 666 if (ctlr->quirks & AHCI_Q_EDGEIS) 667 ise |= is; 668 if (ise != 0) 669 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 670 for (; unit < ctlr->channels; unit++) { 671 if ((is & (1 << unit)) != 0 && 672 (arg = ctlr->interrupt[unit].argument)) { 673 ctlr->interrupt[unit].function(arg); 674 } 675 } 676 /* AHCI declares level triggered IS. */ 677 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 678 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 679} 680 681/* 682 * Simplified interrupt handler for multivector MSI mode. 683 */ 684static void 685ahci_intr_one(void *data) 686{ 687 struct ahci_controller_irq *irq = data; 688 struct ahci_controller *ctlr = irq->ctlr; 689 void *arg; 690 int unit; 691 692 unit = irq->r_irq_rid - 1; 693 /* Some controllers have edge triggered IS. */ 694 if (ctlr->quirks & AHCI_Q_EDGEIS) 695 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 696 if ((arg = ctlr->interrupt[unit].argument)) 697 ctlr->interrupt[unit].function(arg); 698 /* AHCI declares level triggered IS. */ 699 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 700 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 701} 702 703static struct resource * 704ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 705 u_long start, u_long end, u_long count, u_int flags) 706{ 707 struct ahci_controller *ctlr = device_get_softc(dev); 708 int unit = ((struct ahci_channel *)device_get_softc(child))->unit; 709 struct resource *res = NULL; 710 int offset = AHCI_OFFSET + (unit << 7); 711 long st; 712 713 switch (type) { 714 case SYS_RES_MEMORY: 715 st = rman_get_start(ctlr->r_mem); 716 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 717 st + offset + 127, 128, RF_ACTIVE, child); 718 if (res) { 719 bus_space_handle_t bsh; 720 bus_space_tag_t bst; 721 bsh = rman_get_bushandle(ctlr->r_mem); 722 bst = rman_get_bustag(ctlr->r_mem); 723 bus_space_subregion(bst, bsh, offset, 128, &bsh); 724 rman_set_bushandle(res, bsh); 725 rman_set_bustag(res, bst); 726 } 727 break; 728 case SYS_RES_IRQ: 729 if (*rid == ATA_IRQ_RID) 730 res = ctlr->irqs[0].r_irq; 731 break; 732 } 733 return (res); 734} 735 736static int 737ahci_release_resource(device_t dev, device_t child, int type, int rid, 738 struct resource *r) 739{ 740 741 switch (type) { 742 case SYS_RES_MEMORY: 743 rman_release_resource(r); 744 return (0); 745 case SYS_RES_IRQ: 746 if (rid != ATA_IRQ_RID) 747 return ENOENT; 748 return (0); 749 } 750 return (EINVAL); 751} 752 753static int 754ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 755 int flags, driver_filter_t *filter, driver_intr_t *function, 756 void *argument, void **cookiep) 757{ 758 struct ahci_controller *ctlr = device_get_softc(dev); 759 int unit = (intptr_t)device_get_ivars(child); 760 761 if (filter != NULL) { 762 printf("ahci.c: we cannot use a filter here\n"); 763 return (EINVAL); 764 } 765 ctlr->interrupt[unit].function = function; 766 ctlr->interrupt[unit].argument = argument; 767 return (0); 768} 769 770static int 771ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 772 void *cookie) 773{ 774 struct ahci_controller *ctlr = device_get_softc(dev); 775 int unit = (intptr_t)device_get_ivars(child); 776 777 ctlr->interrupt[unit].function = NULL; 778 ctlr->interrupt[unit].argument = NULL; 779 return (0); 780} 781 782static int 783ahci_print_child(device_t dev, device_t child) 784{ 785 int retval; 786 787 retval = bus_print_child_header(dev, child); 788 retval += printf(" at channel %d", 789 (int)(intptr_t)device_get_ivars(child)); 790 retval += bus_print_child_footer(dev, child); 791 792 return (retval); 793} 794 795static int 796ahci_child_location_str(device_t dev, device_t child, char *buf, 797 size_t buflen) 798{ 799 800 snprintf(buf, buflen, "channel=%d", 801 (int)(intptr_t)device_get_ivars(child)); 802 return (0); 803} 804 805devclass_t ahci_devclass; 806static device_method_t ahci_methods[] = { 807 DEVMETHOD(device_probe, ahci_probe), 808 DEVMETHOD(device_attach, ahci_attach), 809 DEVMETHOD(device_detach, ahci_detach), 810 DEVMETHOD(device_suspend, ahci_suspend), 811 DEVMETHOD(device_resume, ahci_resume), 812 DEVMETHOD(bus_print_child, ahci_print_child), 813 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 814 DEVMETHOD(bus_release_resource, ahci_release_resource), 815 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 816 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 817 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 818 { 0, 0 } 819}; 820static driver_t ahci_driver = { 821 "ahci", 822 ahci_methods, 823 sizeof(struct ahci_controller) 824}; 825DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 826static device_method_t ahci_ata_methods[] = { 827 DEVMETHOD(device_probe, ahci_ata_probe), 828 DEVMETHOD(device_attach, ahci_attach), 829 DEVMETHOD(device_detach, ahci_detach), 830 DEVMETHOD(device_suspend, ahci_suspend), 831 DEVMETHOD(device_resume, ahci_resume), 832 DEVMETHOD(bus_print_child, ahci_print_child), 833 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 834 DEVMETHOD(bus_release_resource, ahci_release_resource), 835 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 836 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 837 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 838 { 0, 0 } 839}; 840static driver_t ahci_ata_driver = { 841 "ahci", 842 ahci_ata_methods, 843 sizeof(struct ahci_controller) 844}; 845DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0); 846MODULE_VERSION(ahci, 1); 847MODULE_DEPEND(ahci, cam, 1, 1, 1); 848 849static int 850ahci_ch_probe(device_t dev) 851{ 852 853 device_set_desc_copy(dev, "AHCI channel"); 854 return (0); 855} 856 857static int 858ahci_ch_attach(device_t dev) 859{ 860 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 861 struct ahci_channel *ch = device_get_softc(dev); 862 struct cam_devq *devq; 863 int rid, error, i, sata_rev = 0; 864 u_int32_t version; 865 866 ch->dev = dev; 867 ch->unit = (intptr_t)device_get_ivars(dev); 868 ch->caps = ctlr->caps; 869 ch->caps2 = ctlr->caps2; 870 ch->quirks = ctlr->quirks; 871 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 872 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 873 resource_int_value(device_get_name(dev), 874 device_get_unit(dev), "pm_level", &ch->pm_level); 875 if (ch->pm_level > 3) 876 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 877 /* Limit speed for my onboard JMicron external port. 878 * It is not eSATA really. */ 879 if (pci_get_devid(ctlr->dev) == 0x2363197b && 880 pci_get_subvendor(ctlr->dev) == 0x1043 && 881 pci_get_subdevice(ctlr->dev) == 0x81e4 && 882 ch->unit == 0) 883 sata_rev = 1; 884 if (ch->quirks & AHCI_Q_SATA2) 885 sata_rev = 2; 886 resource_int_value(device_get_name(dev), 887 device_get_unit(dev), "sata_rev", &sata_rev); 888 for (i = 0; i < 16; i++) { 889 ch->user[i].revision = sata_rev; 890 ch->user[i].mode = 0; 891 ch->user[i].bytecount = 8192; 892 ch->user[i].tags = ch->numslots; 893 ch->user[i].caps = 0; 894 ch->curr[i] = ch->user[i]; 895 if (ch->pm_level) { 896 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 897 CTS_SATA_CAPS_H_APST | 898 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 899 } 900 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA; 901 } 902 rid = ch->unit; 903 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 904 &rid, RF_ACTIVE))) 905 return (ENXIO); 906 ahci_dmainit(dev); 907 ahci_slotsalloc(dev); 908 ahci_ch_init(dev); 909 mtx_lock(&ch->mtx); 910 rid = ATA_IRQ_RID; 911 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 912 &rid, RF_SHAREABLE | RF_ACTIVE))) { 913 device_printf(dev, "Unable to map interrupt\n"); 914 error = ENXIO; 915 goto err0; 916 } 917 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 918 ahci_ch_intr_locked, dev, &ch->ih))) { 919 device_printf(dev, "Unable to setup interrupt\n"); 920 error = ENXIO; 921 goto err1; 922 } 923 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 924 version = ATA_INL(ctlr->r_mem, AHCI_VS); 925 if (version < 0x00010020 && (ctlr->caps & AHCI_CAP_FBSS)) 926 ch->chcaps |= AHCI_P_CMD_FBSCP; 927 if (bootverbose) { 928 device_printf(dev, "Caps:%s%s%s%s%s\n", 929 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 930 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 931 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 932 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 933 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":""); 934 } 935 /* Create the device queue for our SIM. */ 936 devq = cam_simq_alloc(ch->numslots); 937 if (devq == NULL) { 938 device_printf(dev, "Unable to allocate simq\n"); 939 error = ENOMEM; 940 goto err1; 941 } 942 /* Construct SIM entry */ 943 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 944 device_get_unit(dev), &ch->mtx, 945 min(2, ch->numslots), 946 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 947 devq); 948 if (ch->sim == NULL) { 949 cam_simq_free(devq); 950 device_printf(dev, "unable to allocate sim\n"); 951 error = ENOMEM; 952 goto err1; 953 } 954 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 955 device_printf(dev, "unable to register xpt bus\n"); 956 error = ENXIO; 957 goto err2; 958 } 959 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 960 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 961 device_printf(dev, "unable to create path\n"); 962 error = ENXIO; 963 goto err3; 964 } 965 if (ch->pm_level > 3) { 966 callout_reset(&ch->pm_timer, 967 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 968 ahci_ch_pm, dev); 969 } 970 mtx_unlock(&ch->mtx); 971 return (0); 972 973err3: 974 xpt_bus_deregister(cam_sim_path(ch->sim)); 975err2: 976 cam_sim_free(ch->sim, /*free_devq*/TRUE); 977err1: 978 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 979err0: 980 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 981 mtx_unlock(&ch->mtx); 982 mtx_destroy(&ch->mtx); 983 return (error); 984} 985 986static int 987ahci_ch_detach(device_t dev) 988{ 989 struct ahci_channel *ch = device_get_softc(dev); 990 991 mtx_lock(&ch->mtx); 992 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 993 xpt_free_path(ch->path); 994 xpt_bus_deregister(cam_sim_path(ch->sim)); 995 cam_sim_free(ch->sim, /*free_devq*/TRUE); 996 mtx_unlock(&ch->mtx); 997 998 if (ch->pm_level > 3) 999 callout_drain(&ch->pm_timer); 1000 bus_teardown_intr(dev, ch->r_irq, ch->ih); 1001 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1002 1003 ahci_ch_deinit(dev); 1004 ahci_slotsfree(dev); 1005 ahci_dmafini(dev); 1006 1007 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1008 mtx_destroy(&ch->mtx); 1009 return (0); 1010} 1011 1012static int 1013ahci_ch_init(device_t dev) 1014{ 1015 struct ahci_channel *ch = device_get_softc(dev); 1016 uint64_t work; 1017 1018 /* Disable port interrupts */ 1019 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1020 /* Setup work areas */ 1021 work = ch->dma.work_bus + AHCI_CL_OFFSET; 1022 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 1023 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 1024 work = ch->dma.rfis_bus; 1025 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 1026 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 1027 /* Activate the channel and power/spin up device */ 1028 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 1029 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1030 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 1031 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 1032 ahci_start_fr(dev); 1033 ahci_start(dev, 1); 1034 return (0); 1035} 1036 1037static int 1038ahci_ch_deinit(device_t dev) 1039{ 1040 struct ahci_channel *ch = device_get_softc(dev); 1041 1042 /* Disable port interrupts. */ 1043 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1044 /* Reset command register. */ 1045 ahci_stop(dev); 1046 ahci_stop_fr(dev); 1047 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 1048 /* Allow everything, including partial and slumber modes. */ 1049 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 1050 /* Request slumber mode transition and give some time to get there. */ 1051 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 1052 DELAY(100); 1053 /* Disable PHY. */ 1054 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 1055 return (0); 1056} 1057 1058static int 1059ahci_ch_suspend(device_t dev) 1060{ 1061 struct ahci_channel *ch = device_get_softc(dev); 1062 1063 mtx_lock(&ch->mtx); 1064 xpt_freeze_simq(ch->sim, 1); 1065 while (ch->oslots) 1066 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 1067 ahci_ch_deinit(dev); 1068 mtx_unlock(&ch->mtx); 1069 return (0); 1070} 1071 1072static int 1073ahci_ch_resume(device_t dev) 1074{ 1075 struct ahci_channel *ch = device_get_softc(dev); 1076 1077 mtx_lock(&ch->mtx); 1078 ahci_ch_init(dev); 1079 ahci_reset(dev); 1080 xpt_release_simq(ch->sim, TRUE); 1081 mtx_unlock(&ch->mtx); 1082 return (0); 1083} 1084 1085devclass_t ahcich_devclass; 1086static device_method_t ahcich_methods[] = { 1087 DEVMETHOD(device_probe, ahci_ch_probe), 1088 DEVMETHOD(device_attach, ahci_ch_attach), 1089 DEVMETHOD(device_detach, ahci_ch_detach), 1090 DEVMETHOD(device_suspend, ahci_ch_suspend), 1091 DEVMETHOD(device_resume, ahci_ch_resume), 1092 { 0, 0 } 1093}; 1094static driver_t ahcich_driver = { 1095 "ahcich", 1096 ahcich_methods, 1097 sizeof(struct ahci_channel) 1098}; 1099DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0); 1100 1101struct ahci_dc_cb_args { 1102 bus_addr_t maddr; 1103 int error; 1104}; 1105 1106static void 1107ahci_dmainit(device_t dev) 1108{ 1109 struct ahci_channel *ch = device_get_softc(dev); 1110 struct ahci_dc_cb_args dcba; 1111 size_t rfsize; 1112 1113 if (ch->caps & AHCI_CAP_64BIT) 1114 ch->dma.max_address = BUS_SPACE_MAXADDR; 1115 else 1116 ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT; 1117 /* Command area. */ 1118 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1119 ch->dma.max_address, BUS_SPACE_MAXADDR, 1120 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1121 0, NULL, NULL, &ch->dma.work_tag)) 1122 goto error; 1123 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0, 1124 &ch->dma.work_map)) 1125 goto error; 1126 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1127 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1128 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1129 goto error; 1130 } 1131 ch->dma.work_bus = dcba.maddr; 1132 /* FIS receive area. */ 1133 if (ch->chcaps & AHCI_P_CMD_FBSCP) 1134 rfsize = 4096; 1135 else 1136 rfsize = 256; 1137 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 1138 ch->dma.max_address, BUS_SPACE_MAXADDR, 1139 NULL, NULL, rfsize, 1, rfsize, 1140 0, NULL, NULL, &ch->dma.rfis_tag)) 1141 goto error; 1142 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1143 &ch->dma.rfis_map)) 1144 goto error; 1145 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1146 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1147 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1148 goto error; 1149 } 1150 ch->dma.rfis_bus = dcba.maddr; 1151 /* Data area. */ 1152 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1153 ch->dma.max_address, BUS_SPACE_MAXADDR, 1154 NULL, NULL, 1155 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1156 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1157 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 1158 goto error; 1159 } 1160 return; 1161 1162error: 1163 device_printf(dev, "WARNING - DMA initialization failed\n"); 1164 ahci_dmafini(dev); 1165} 1166 1167static void 1168ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1169{ 1170 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1171 1172 if (!(dcba->error = error)) 1173 dcba->maddr = segs[0].ds_addr; 1174} 1175 1176static void 1177ahci_dmafini(device_t dev) 1178{ 1179 struct ahci_channel *ch = device_get_softc(dev); 1180 1181 if (ch->dma.data_tag) { 1182 bus_dma_tag_destroy(ch->dma.data_tag); 1183 ch->dma.data_tag = NULL; 1184 } 1185 if (ch->dma.rfis_bus) { 1186 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1187 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1188 ch->dma.rfis_bus = 0; 1189 ch->dma.rfis_map = NULL; 1190 ch->dma.rfis = NULL; 1191 } 1192 if (ch->dma.work_bus) { 1193 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1194 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1195 ch->dma.work_bus = 0; 1196 ch->dma.work_map = NULL; 1197 ch->dma.work = NULL; 1198 } 1199 if (ch->dma.work_tag) { 1200 bus_dma_tag_destroy(ch->dma.work_tag); 1201 ch->dma.work_tag = NULL; 1202 } 1203} 1204 1205static void 1206ahci_slotsalloc(device_t dev) 1207{ 1208 struct ahci_channel *ch = device_get_softc(dev); 1209 int i; 1210 1211 /* Alloc and setup command/dma slots */ 1212 bzero(ch->slot, sizeof(ch->slot)); 1213 for (i = 0; i < ch->numslots; i++) { 1214 struct ahci_slot *slot = &ch->slot[i]; 1215 1216 slot->dev = dev; 1217 slot->slot = i; 1218 slot->state = AHCI_SLOT_EMPTY; 1219 slot->ccb = NULL; 1220 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1221 1222 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1223 device_printf(ch->dev, "FAILURE - create data_map\n"); 1224 } 1225} 1226 1227static void 1228ahci_slotsfree(device_t dev) 1229{ 1230 struct ahci_channel *ch = device_get_softc(dev); 1231 int i; 1232 1233 /* Free all dma slots */ 1234 for (i = 0; i < ch->numslots; i++) { 1235 struct ahci_slot *slot = &ch->slot[i]; 1236 1237 callout_drain(&slot->timeout); 1238 if (slot->dma.data_map) { 1239 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1240 slot->dma.data_map = NULL; 1241 } 1242 } 1243} 1244 1245static void 1246ahci_phy_check_events(device_t dev, u_int32_t serr) 1247{ 1248 struct ahci_channel *ch = device_get_softc(dev); 1249 1250 if ((serr & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) { 1251 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1252 union ccb *ccb; 1253 1254 if (bootverbose) { 1255 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 1256 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 1257 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) { 1258 device_printf(dev, "CONNECT requested\n"); 1259 } else 1260 device_printf(dev, "DISCONNECT requested\n"); 1261 } 1262 ahci_reset(dev); 1263 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1264 return; 1265 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1266 cam_sim_path(ch->sim), 1267 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1268 xpt_free_ccb(ccb); 1269 return; 1270 } 1271 xpt_rescan(ccb); 1272 } 1273} 1274 1275static void 1276ahci_notify_events(device_t dev, u_int32_t status) 1277{ 1278 struct ahci_channel *ch = device_get_softc(dev); 1279 struct cam_path *dpath; 1280 int i; 1281 1282 if (ch->caps & AHCI_CAP_SSNTF) 1283 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1284 if (bootverbose) 1285 device_printf(dev, "SNTF 0x%04x\n", status); 1286 for (i = 0; i < 16; i++) { 1287 if ((status & (1 << i)) == 0) 1288 continue; 1289 if (xpt_create_path(&dpath, NULL, 1290 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1291 xpt_async(AC_SCSI_AEN, dpath, NULL); 1292 xpt_free_path(dpath); 1293 } 1294 } 1295} 1296 1297static void 1298ahci_ch_intr_locked(void *data) 1299{ 1300 device_t dev = (device_t)data; 1301 struct ahci_channel *ch = device_get_softc(dev); 1302 1303 mtx_lock(&ch->mtx); 1304 ahci_ch_intr(data); 1305 mtx_unlock(&ch->mtx); 1306} 1307 1308static void 1309ahci_ch_pm(void *arg) 1310{ 1311 device_t dev = (device_t)arg; 1312 struct ahci_channel *ch = device_get_softc(dev); 1313 uint32_t work; 1314 1315 if (ch->numrslots != 0) 1316 return; 1317 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1318 if (ch->pm_level == 4) 1319 work |= AHCI_P_CMD_PARTIAL; 1320 else 1321 work |= AHCI_P_CMD_SLUMBER; 1322 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1323} 1324 1325static void 1326ahci_ch_intr(void *data) 1327{ 1328 device_t dev = (device_t)data; 1329 struct ahci_channel *ch = device_get_softc(dev); 1330 uint32_t istatus, sstatus, cstatus, serr = 0, sntf = 0, ok, err; 1331 enum ahci_err_type et; 1332 int i, ccs, port; 1333 1334 /* Read and clear interrupt statuses. */ 1335 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1336 if (istatus == 0) 1337 return; 1338 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1339 /* Read command statuses. */ 1340 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1341 cstatus = ATA_INL(ch->r_mem, AHCI_P_CI); 1342 if (istatus & AHCI_P_IX_SDB) { 1343 if (ch->caps & AHCI_CAP_SSNTF) 1344 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1345 else if (ch->fbs_enabled) { 1346 u_int8_t *fis = ch->dma.rfis + 0x58; 1347 1348 for (i = 0; i < 16; i++) { 1349 if (fis[1] & 0x80) { 1350 fis[1] &= 0x7f; 1351 sntf |= 1 << i; 1352 } 1353 fis += 256; 1354 } 1355 } else { 1356 u_int8_t *fis = ch->dma.rfis + 0x58; 1357 1358 if (fis[1] & 0x80) 1359 sntf = (1 << (fis[1] & 0x0f)); 1360 } 1361 } 1362 /* Process PHY events */ 1363 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1364 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1365 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1366 if (serr) { 1367 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1368 ahci_phy_check_events(dev, serr); 1369 } 1370 } 1371 /* Process command errors */ 1372 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1373 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1374 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1375 >> AHCI_P_CMD_CCS_SHIFT; 1376//device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1377// __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1378// serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1379 port = -1; 1380 if (ch->fbs_enabled) { 1381 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1382 if (fbs & AHCI_P_FBS_SDE) { 1383 port = (fbs & AHCI_P_FBS_DWE) 1384 >> AHCI_P_FBS_DWE_SHIFT; 1385 } else { 1386 for (i = 0; i < 16; i++) { 1387 if (ch->numrslotspd[i] == 0) 1388 continue; 1389 if (port == -1) 1390 port = i; 1391 else if (port != i) { 1392 port = -2; 1393 break; 1394 } 1395 } 1396 } 1397 } 1398 err = ch->rslots & (cstatus | sstatus); 1399 } else { 1400 ccs = 0; 1401 err = 0; 1402 port = -1; 1403 } 1404 /* Complete all successfull commands. */ 1405 ok = ch->rslots & ~(cstatus | sstatus); 1406 for (i = 0; i < ch->numslots; i++) { 1407 if ((ok >> i) & 1) 1408 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1409 } 1410 /* On error, complete the rest of commands with error statuses. */ 1411 if (err) { 1412 if (ch->frozen) { 1413 union ccb *fccb = ch->frozen; 1414 ch->frozen = NULL; 1415 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1416 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1417 xpt_freeze_devq(fccb->ccb_h.path, 1); 1418 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1419 } 1420 xpt_done(fccb); 1421 } 1422 for (i = 0; i < ch->numslots; i++) { 1423 /* XXX: reqests in loading state. */ 1424 if (((err >> i) & 1) == 0) 1425 continue; 1426 if (port >= 0 && 1427 ch->slot[i].ccb->ccb_h.target_id != port) 1428 continue; 1429 if (istatus & AHCI_P_IX_TFE) { 1430 if (port != -2) { 1431 /* Task File Error */ 1432 if (ch->numtslotspd[ 1433 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1434 /* Untagged operation. */ 1435 if (i == ccs) 1436 et = AHCI_ERR_TFE; 1437 else 1438 et = AHCI_ERR_INNOCENT; 1439 } else { 1440 /* Tagged operation. */ 1441 et = AHCI_ERR_NCQ; 1442 } 1443 } else { 1444 et = AHCI_ERR_TFE; 1445 ch->fatalerr = 1; 1446 } 1447 } else if (istatus & AHCI_P_IX_IF) { 1448 if (ch->numtslots == 0 && i != ccs && port != -2) 1449 et = AHCI_ERR_INNOCENT; 1450 else 1451 et = AHCI_ERR_SATA; 1452 } else 1453 et = AHCI_ERR_INVALID; 1454 ahci_end_transaction(&ch->slot[i], et); 1455 } 1456 /* 1457 * We can't reinit port if there are some other 1458 * commands active, use resume to complete them. 1459 */ 1460 if (ch->rslots != 0) 1461 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1462 } 1463 /* Process NOTIFY events */ 1464 if (sntf) 1465 ahci_notify_events(dev, sntf); 1466} 1467 1468/* Must be called with channel locked. */ 1469static int 1470ahci_check_collision(device_t dev, union ccb *ccb) 1471{ 1472 struct ahci_channel *ch = device_get_softc(dev); 1473 int t = ccb->ccb_h.target_id; 1474 1475 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1476 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1477 /* Tagged command while we have no supported tag free. */ 1478 if (((~ch->oslots) & (0xffffffff >> (32 - 1479 ch->curr[t].tags))) == 0) 1480 return (1); 1481 /* If we have FBS */ 1482 if (ch->fbs_enabled) { 1483 /* Tagged command while untagged are active. */ 1484 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1485 return (1); 1486 } else { 1487 /* Tagged command while untagged are active. */ 1488 if (ch->numrslots != 0 && ch->numtslots == 0) 1489 return (1); 1490 /* Tagged command while tagged to other target is active. */ 1491 if (ch->numtslots != 0 && 1492 ch->taggedtarget != ccb->ccb_h.target_id) 1493 return (1); 1494 } 1495 } else { 1496 /* If we have FBS */ 1497 if (ch->fbs_enabled) { 1498 /* Untagged command while tagged are active. */ 1499 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1500 return (1); 1501 } else { 1502 /* Untagged command while tagged are active. */ 1503 if (ch->numrslots != 0 && ch->numtslots != 0) 1504 return (1); 1505 } 1506 } 1507 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1508 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1509 /* Atomic command while anything active. */ 1510 if (ch->numrslots != 0) 1511 return (1); 1512 } 1513 /* We have some atomic command running. */ 1514 if (ch->aslots != 0) 1515 return (1); 1516 return (0); 1517} 1518 1519/* Must be called with channel locked. */ 1520static void 1521ahci_begin_transaction(device_t dev, union ccb *ccb) 1522{ 1523 struct ahci_channel *ch = device_get_softc(dev); 1524 struct ahci_slot *slot; 1525 int tag, tags; 1526 1527 /* Choose empty slot. */ 1528 tags = ch->numslots; 1529 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1530 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1531 tags = ch->curr[ccb->ccb_h.target_id].tags; 1532 tag = ch->lastslot; 1533 while (1) { 1534 if (tag >= tags) 1535 tag = 0; 1536 if (ch->slot[tag].state == AHCI_SLOT_EMPTY) 1537 break; 1538 tag++; 1539 }; 1540 ch->lastslot = tag; 1541 /* Occupy chosen slot. */ 1542 slot = &ch->slot[tag]; 1543 slot->ccb = ccb; 1544 /* Stop PM timer. */ 1545 if (ch->numrslots == 0 && ch->pm_level > 3) 1546 callout_stop(&ch->pm_timer); 1547 /* Update channel stats. */ 1548 ch->oslots |= (1 << slot->slot); 1549 ch->numrslots++; 1550 ch->numrslotspd[ccb->ccb_h.target_id]++; 1551 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1552 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1553 ch->numtslots++; 1554 ch->numtslotspd[ccb->ccb_h.target_id]++; 1555 ch->taggedtarget = ccb->ccb_h.target_id; 1556 } 1557 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1558 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1559 ch->aslots |= (1 << slot->slot); 1560 slot->dma.nsegs = 0; 1561 /* If request moves data, setup and load SG list */ 1562 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1563 void *buf; 1564 bus_size_t size; 1565 1566 slot->state = AHCI_SLOT_LOADING; 1567 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1568 buf = ccb->ataio.data_ptr; 1569 size = ccb->ataio.dxfer_len; 1570 } else { 1571 buf = ccb->csio.data_ptr; 1572 size = ccb->csio.dxfer_len; 1573 } 1574 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1575 buf, size, ahci_dmasetprd, slot, 0); 1576 } else 1577 ahci_execute_transaction(slot); 1578} 1579 1580/* Locked by busdma engine. */ 1581static void 1582ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1583{ 1584 struct ahci_slot *slot = arg; 1585 struct ahci_channel *ch = device_get_softc(slot->dev); 1586 struct ahci_cmd_tab *ctp; 1587 struct ahci_dma_prd *prd; 1588 int i; 1589 1590 if (error) { 1591 device_printf(slot->dev, "DMA load error\n"); 1592 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1593 return; 1594 } 1595 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1596 /* Get a piece of the workspace for this request */ 1597 ctp = (struct ahci_cmd_tab *) 1598 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1599 /* Fill S/G table */ 1600 prd = &ctp->prd_tab[0]; 1601 for (i = 0; i < nsegs; i++) { 1602 prd[i].dba = htole64(segs[i].ds_addr); 1603 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1604 } 1605 slot->dma.nsegs = nsegs; 1606 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1607 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1608 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1609 ahci_execute_transaction(slot); 1610} 1611 1612/* Must be called with channel locked. */ 1613static void 1614ahci_execute_transaction(struct ahci_slot *slot) 1615{ 1616 device_t dev = slot->dev; 1617 struct ahci_channel *ch = device_get_softc(dev); 1618 struct ahci_cmd_tab *ctp; 1619 struct ahci_cmd_list *clp; 1620 union ccb *ccb = slot->ccb; 1621 int port = ccb->ccb_h.target_id & 0x0f; 1622 int fis_size, i; 1623 uint8_t *fis = ch->dma.rfis + 0x40; 1624 uint8_t val; 1625 1626 /* Get a piece of the workspace for this request */ 1627 ctp = (struct ahci_cmd_tab *) 1628 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1629 /* Setup the FIS for this request */ 1630 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) { 1631 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1632 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1633 return; 1634 } 1635 /* Setup the command list entry */ 1636 clp = (struct ahci_cmd_list *) 1637 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1638 clp->cmd_flags = htole16( 1639 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1640 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1641 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1642 (fis_size / sizeof(u_int32_t)) | 1643 (port << 12)); 1644 clp->prd_length = htole16(slot->dma.nsegs); 1645 /* Special handling for Soft Reset command. */ 1646 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1647 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1648 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1649 /* Kick controller into sane state */ 1650 ahci_stop(dev); 1651 ahci_clo(dev); 1652 ahci_start(dev, 0); 1653 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1654 } else { 1655 /* Prepare FIS receive area for check. */ 1656 for (i = 0; i < 20; i++) 1657 fis[i] = 0xff; 1658 } 1659 } 1660 clp->bytecount = 0; 1661 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1662 (AHCI_CT_SIZE * slot->slot)); 1663 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1664 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1665 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1666 BUS_DMASYNC_PREREAD); 1667 /* Set ACTIVE bit for NCQ commands. */ 1668 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1669 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1670 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1671 } 1672 /* If FBS is enabled, set PMP port. */ 1673 if (ch->fbs_enabled) { 1674 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1675 (port << AHCI_P_FBS_DEV_SHIFT)); 1676 } 1677 /* Issue command to the controller. */ 1678 slot->state = AHCI_SLOT_RUNNING; 1679 ch->rslots |= (1 << slot->slot); 1680 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1681 /* Device reset commands doesn't interrupt. Poll them. */ 1682 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1683 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || 1684 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL))) { 1685 int count, timeout = ccb->ccb_h.timeout; 1686 enum ahci_err_type et = AHCI_ERR_NONE; 1687 1688 for (count = 0; count < timeout; count++) { 1689 DELAY(1000); 1690 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1691 break; 1692 if (ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) { 1693 device_printf(ch->dev, 1694 "Poll error on slot %d, TFD: %04x\n", 1695 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1696 et = AHCI_ERR_TFE; 1697 break; 1698 } 1699 /* Workaround for ATI SB600/SB700 chipsets. */ 1700 if (ccb->ccb_h.target_id == 15 && 1701 pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1702 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1703 et = AHCI_ERR_TIMEOUT; 1704 break; 1705 } 1706 } 1707 if (timeout && (count >= timeout)) { 1708 device_printf(ch->dev, 1709 "Poll timeout on slot %d\n", slot->slot); 1710 device_printf(dev, "is %08x cs %08x ss %08x " 1711 "rs %08x tfd %02x serr %08x\n", 1712 ATA_INL(ch->r_mem, AHCI_P_IS), 1713 ATA_INL(ch->r_mem, AHCI_P_CI), 1714 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1715 ATA_INL(ch->r_mem, AHCI_P_TFD), 1716 ATA_INL(ch->r_mem, AHCI_P_SERR)); 1717 et = AHCI_ERR_TIMEOUT; 1718 } 1719 /* Marvell controllers do not wait for readyness. */ 1720 if ((ch->quirks & AHCI_Q_NOBSYRES) && 1721 (ccb->ccb_h.func_code == XPT_ATA_IO) && 1722 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1723 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 1724 while ((val = fis[2]) & (ATA_S_BUSY | ATA_S_DRQ)) { 1725 DELAY(1000); 1726 if (count++ >= timeout) { 1727 device_printf(dev, "device is not " 1728 "ready after soft-reset: " 1729 "tfd = %08x\n", val); 1730 et = AHCI_ERR_TIMEOUT; 1731 break; 1732 } 1733 } 1734 } 1735 ahci_end_transaction(slot, et); 1736 /* Kick controller into sane state and enable FBS. */ 1737 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1738 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1739 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 1740 ahci_stop(ch->dev); 1741 ahci_start(ch->dev, 1); 1742 } 1743 return; 1744 } 1745 /* Start command execution timeout */ 1746 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 1747 (timeout_t*)ahci_timeout, slot); 1748 return; 1749} 1750 1751/* Must be called with channel locked. */ 1752static void 1753ahci_process_timeout(device_t dev) 1754{ 1755 struct ahci_channel *ch = device_get_softc(dev); 1756 int i; 1757 1758 mtx_assert(&ch->mtx, MA_OWNED); 1759 /* Handle the rest of commands. */ 1760 for (i = 0; i < ch->numslots; i++) { 1761 /* Do we have a running request on slot? */ 1762 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1763 continue; 1764 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 1765 } 1766} 1767 1768/* Must be called with channel locked. */ 1769static void 1770ahci_rearm_timeout(device_t dev) 1771{ 1772 struct ahci_channel *ch = device_get_softc(dev); 1773 int i; 1774 1775 mtx_assert(&ch->mtx, MA_OWNED); 1776 for (i = 0; i < ch->numslots; i++) { 1777 struct ahci_slot *slot = &ch->slot[i]; 1778 1779 /* Do we have a running request on slot? */ 1780 if (slot->state < AHCI_SLOT_RUNNING) 1781 continue; 1782 if ((ch->toslots & (1 << i)) == 0) 1783 continue; 1784 callout_reset(&slot->timeout, 1785 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1786 (timeout_t*)ahci_timeout, slot); 1787 } 1788} 1789 1790/* Locked by callout mechanism. */ 1791static void 1792ahci_timeout(struct ahci_slot *slot) 1793{ 1794 device_t dev = slot->dev; 1795 struct ahci_channel *ch = device_get_softc(dev); 1796 uint32_t sstatus; 1797 int ccs; 1798 int i; 1799 1800 /* Check for stale timeout. */ 1801 if (slot->state < AHCI_SLOT_RUNNING) 1802 return; 1803 1804 /* Check if slot was not being executed last time we checked. */ 1805 if (slot->state < AHCI_SLOT_EXECUTING) { 1806 /* Check if slot started executing. */ 1807 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1808 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1809 >> AHCI_P_CMD_CCS_SHIFT; 1810 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 1811 ch->fbs_enabled) 1812 slot->state = AHCI_SLOT_EXECUTING; 1813 1814 callout_reset(&slot->timeout, 1815 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1816 (timeout_t*)ahci_timeout, slot); 1817 return; 1818 } 1819 1820 device_printf(dev, "Timeout on slot %d\n", slot->slot); 1821 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x\n", 1822 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1823 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1824 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR)); 1825 1826 /* Handle frozen command. */ 1827 if (ch->frozen) { 1828 union ccb *fccb = ch->frozen; 1829 ch->frozen = NULL; 1830 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1831 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1832 xpt_freeze_devq(fccb->ccb_h.path, 1); 1833 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1834 } 1835 xpt_done(fccb); 1836 } 1837 if (!ch->fbs_enabled) { 1838 /* Without FBS we know real timeout source. */ 1839 ch->fatalerr = 1; 1840 /* Handle command with timeout. */ 1841 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 1842 /* Handle the rest of commands. */ 1843 for (i = 0; i < ch->numslots; i++) { 1844 /* Do we have a running request on slot? */ 1845 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1846 continue; 1847 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1848 } 1849 } else { 1850 /* With FBS we wait for other commands timeout and pray. */ 1851 if (ch->toslots == 0) 1852 xpt_freeze_simq(ch->sim, 1); 1853 ch->toslots |= (1 << slot->slot); 1854 if ((ch->rslots & ~ch->toslots) == 0) 1855 ahci_process_timeout(dev); 1856 else 1857 device_printf(dev, " ... waiting for slots %08x\n", 1858 ch->rslots & ~ch->toslots); 1859 } 1860} 1861 1862/* Must be called with channel locked. */ 1863static void 1864ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 1865{ 1866 device_t dev = slot->dev; 1867 struct ahci_channel *ch = device_get_softc(dev); 1868 union ccb *ccb = slot->ccb; 1869 struct ahci_cmd_list *clp; 1870 int lastto; 1871 1872 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1873 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1874 clp = (struct ahci_cmd_list *) 1875 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1876 /* Read result registers to the result struct 1877 * May be incorrect if several commands finished same time, 1878 * so read only when sure or have to. 1879 */ 1880 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1881 struct ata_res *res = &ccb->ataio.res; 1882 1883 if ((et == AHCI_ERR_TFE) || 1884 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1885 u_int8_t *fis = ch->dma.rfis + 0x40; 1886 1887 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1888 BUS_DMASYNC_POSTREAD); 1889 if (ch->fbs_enabled) { 1890 fis += ccb->ccb_h.target_id * 256; 1891 res->status = fis[2]; 1892 res->error = fis[3]; 1893 } else { 1894 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 1895 1896 res->status = tfd; 1897 res->error = tfd >> 8; 1898 } 1899 res->lba_low = fis[4]; 1900 res->lba_mid = fis[5]; 1901 res->lba_high = fis[6]; 1902 res->device = fis[7]; 1903 res->lba_low_exp = fis[8]; 1904 res->lba_mid_exp = fis[9]; 1905 res->lba_high_exp = fis[10]; 1906 res->sector_count = fis[12]; 1907 res->sector_count_exp = fis[13]; 1908 } else 1909 bzero(res, sizeof(*res)); 1910 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 1911 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1912 ccb->ataio.resid = 1913 ccb->ataio.dxfer_len - le32toh(clp->bytecount); 1914 } 1915 } else { 1916 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1917 ccb->csio.resid = 1918 ccb->csio.dxfer_len - le32toh(clp->bytecount); 1919 } 1920 } 1921 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1922 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1923 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1924 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1925 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1926 } 1927 if (et != AHCI_ERR_NONE) 1928 ch->eslots |= (1 << slot->slot); 1929 /* In case of error, freeze device for proper recovery. */ 1930 if ((et != AHCI_ERR_NONE) && (!ch->readlog) && 1931 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 1932 xpt_freeze_devq(ccb->ccb_h.path, 1); 1933 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1934 } 1935 /* Set proper result status. */ 1936 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1937 switch (et) { 1938 case AHCI_ERR_NONE: 1939 ccb->ccb_h.status |= CAM_REQ_CMP; 1940 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1941 ccb->csio.scsi_status = SCSI_STATUS_OK; 1942 break; 1943 case AHCI_ERR_INVALID: 1944 ch->fatalerr = 1; 1945 ccb->ccb_h.status |= CAM_REQ_INVALID; 1946 break; 1947 case AHCI_ERR_INNOCENT: 1948 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1949 break; 1950 case AHCI_ERR_TFE: 1951 case AHCI_ERR_NCQ: 1952 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1953 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1954 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1955 } else { 1956 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1957 } 1958 break; 1959 case AHCI_ERR_SATA: 1960 ch->fatalerr = 1; 1961 if (!ch->readlog) { 1962 xpt_freeze_simq(ch->sim, 1); 1963 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1964 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1965 } 1966 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1967 break; 1968 case AHCI_ERR_TIMEOUT: 1969 if (!ch->readlog) { 1970 xpt_freeze_simq(ch->sim, 1); 1971 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1972 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1973 } 1974 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1975 break; 1976 default: 1977 ch->fatalerr = 1; 1978 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1979 } 1980 /* Free slot. */ 1981 ch->oslots &= ~(1 << slot->slot); 1982 ch->rslots &= ~(1 << slot->slot); 1983 ch->aslots &= ~(1 << slot->slot); 1984 slot->state = AHCI_SLOT_EMPTY; 1985 slot->ccb = NULL; 1986 /* Update channel stats. */ 1987 ch->numrslots--; 1988 ch->numrslotspd[ccb->ccb_h.target_id]--; 1989 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1990 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1991 ch->numtslots--; 1992 ch->numtslotspd[ccb->ccb_h.target_id]--; 1993 } 1994 /* Cancel timeout state if request completed normally. */ 1995 if (et != AHCI_ERR_TIMEOUT) { 1996 lastto = (ch->toslots == (1 << slot->slot)); 1997 ch->toslots &= ~(1 << slot->slot); 1998 if (lastto) 1999 xpt_release_simq(ch->sim, TRUE); 2000 } 2001 /* If it was first request of reset sequence and there is no error, 2002 * proceed to second request. */ 2003 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2004 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2005 (ccb->ataio.cmd.control & ATA_A_RESET) && 2006 et == AHCI_ERR_NONE) { 2007 ccb->ataio.cmd.control &= ~ATA_A_RESET; 2008 ahci_begin_transaction(dev, ccb); 2009 return; 2010 } 2011 /* If it was our READ LOG command - process it. */ 2012 if (ch->readlog) { 2013 ahci_process_read_log(dev, ccb); 2014 /* If it was NCQ command error, put result on hold. */ 2015 } else if (et == AHCI_ERR_NCQ) { 2016 ch->hold[slot->slot] = ccb; 2017 ch->numhslots++; 2018 } else 2019 xpt_done(ccb); 2020 /* Unfreeze frozen command. */ 2021 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) { 2022 union ccb *fccb = ch->frozen; 2023 ch->frozen = NULL; 2024 ahci_begin_transaction(dev, fccb); 2025 xpt_release_simq(ch->sim, TRUE); 2026 } 2027 /* If we have no other active commands, ... */ 2028 if (ch->rslots == 0) { 2029 /* if there was fatal error - reset port. */ 2030 if (ch->toslots != 0 || ch->fatalerr) { 2031 ahci_reset(dev); 2032 } else { 2033 /* if we have slots in error, we can reinit port. */ 2034 if (ch->eslots != 0) { 2035 ahci_stop(dev); 2036 ahci_start(dev, 1); 2037 } 2038 /* if there commands on hold, we can do READ LOG. */ 2039 if (!ch->readlog && ch->numhslots) 2040 ahci_issue_read_log(dev); 2041 } 2042 /* If all the rest of commands are in timeout - give them chance. */ 2043 } else if ((ch->rslots & ~ch->toslots) == 0 && 2044 et != AHCI_ERR_TIMEOUT) 2045 ahci_rearm_timeout(dev); 2046 /* Start PM timer. */ 2047 if (ch->numrslots == 0 && ch->pm_level > 3 && 2048 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 2049 callout_schedule(&ch->pm_timer, 2050 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 2051 } 2052} 2053 2054static void 2055ahci_issue_read_log(device_t dev) 2056{ 2057 struct ahci_channel *ch = device_get_softc(dev); 2058 union ccb *ccb; 2059 struct ccb_ataio *ataio; 2060 int i; 2061 2062 ch->readlog = 1; 2063 /* Find some holden command. */ 2064 for (i = 0; i < ch->numslots; i++) { 2065 if (ch->hold[i]) 2066 break; 2067 } 2068 ccb = xpt_alloc_ccb_nowait(); 2069 if (ccb == NULL) { 2070 device_printf(dev, "Unable allocate READ LOG command"); 2071 return; /* XXX */ 2072 } 2073 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 2074 ccb->ccb_h.func_code = XPT_ATA_IO; 2075 ccb->ccb_h.flags = CAM_DIR_IN; 2076 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2077 ataio = &ccb->ataio; 2078 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 2079 if (ataio->data_ptr == NULL) { 2080 xpt_free_ccb(ccb); 2081 device_printf(dev, "Unable allocate memory for READ LOG command"); 2082 return; /* XXX */ 2083 } 2084 ataio->dxfer_len = 512; 2085 bzero(&ataio->cmd, sizeof(ataio->cmd)); 2086 ataio->cmd.flags = CAM_ATAIO_48BIT; 2087 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2088 ataio->cmd.sector_count = 1; 2089 ataio->cmd.sector_count_exp = 0; 2090 ataio->cmd.lba_low = 0x10; 2091 ataio->cmd.lba_mid = 0; 2092 ataio->cmd.lba_mid_exp = 0; 2093 /* Freeze SIM while doing READ LOG EXT. */ 2094 xpt_freeze_simq(ch->sim, 1); 2095 ahci_begin_transaction(dev, ccb); 2096} 2097 2098static void 2099ahci_process_read_log(device_t dev, union ccb *ccb) 2100{ 2101 struct ahci_channel *ch = device_get_softc(dev); 2102 uint8_t *data; 2103 struct ata_res *res; 2104 int i; 2105 2106 ch->readlog = 0; 2107 2108 data = ccb->ataio.data_ptr; 2109 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2110 (data[0] & 0x80) == 0) { 2111 for (i = 0; i < ch->numslots; i++) { 2112 if (!ch->hold[i]) 2113 continue; 2114 if ((data[0] & 0x1F) == i) { 2115 res = &ch->hold[i]->ataio.res; 2116 res->status = data[2]; 2117 res->error = data[3]; 2118 res->lba_low = data[4]; 2119 res->lba_mid = data[5]; 2120 res->lba_high = data[6]; 2121 res->device = data[7]; 2122 res->lba_low_exp = data[8]; 2123 res->lba_mid_exp = data[9]; 2124 res->lba_high_exp = data[10]; 2125 res->sector_count = data[12]; 2126 res->sector_count_exp = data[13]; 2127 } else { 2128 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2129 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2130 } 2131 xpt_done(ch->hold[i]); 2132 ch->hold[i] = NULL; 2133 ch->numhslots--; 2134 } 2135 } else { 2136 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2137 device_printf(dev, "Error while READ LOG EXT\n"); 2138 else if ((data[0] & 0x80) == 0) { 2139 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 2140 } 2141 for (i = 0; i < ch->numslots; i++) { 2142 if (!ch->hold[i]) 2143 continue; 2144 xpt_done(ch->hold[i]); 2145 ch->hold[i] = NULL; 2146 ch->numhslots--; 2147 } 2148 } 2149 free(ccb->ataio.data_ptr, M_AHCI); 2150 xpt_free_ccb(ccb); 2151 xpt_release_simq(ch->sim, TRUE); 2152} 2153 2154static void 2155ahci_start(device_t dev, int fbs) 2156{ 2157 struct ahci_channel *ch = device_get_softc(dev); 2158 u_int32_t cmd; 2159 2160 /* Clear SATA error register */ 2161 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2162 /* Clear any interrupts pending on this channel */ 2163 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2164 /* Configure FIS-based switching if supported. */ 2165 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2166 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2167 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2168 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2169 } 2170 /* Start operations on this channel */ 2171 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2172 cmd &= ~AHCI_P_CMD_PMA; 2173 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2174 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2175} 2176 2177static void 2178ahci_stop(device_t dev) 2179{ 2180 struct ahci_channel *ch = device_get_softc(dev); 2181 u_int32_t cmd; 2182 int timeout; 2183 2184 /* Kill all activity on this channel */ 2185 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2186 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2187 /* Wait for activity stop. */ 2188 timeout = 0; 2189 do { 2190 DELAY(1000); 2191 if (timeout++ > 1000) { 2192 device_printf(dev, "stopping AHCI engine failed\n"); 2193 break; 2194 } 2195 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2196 ch->eslots = 0; 2197} 2198 2199static void 2200ahci_clo(device_t dev) 2201{ 2202 struct ahci_channel *ch = device_get_softc(dev); 2203 u_int32_t cmd; 2204 int timeout; 2205 2206 /* Issue Command List Override if supported */ 2207 if (ch->caps & AHCI_CAP_SCLO) { 2208 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2209 cmd |= AHCI_P_CMD_CLO; 2210 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2211 timeout = 0; 2212 do { 2213 DELAY(1000); 2214 if (timeout++ > 1000) { 2215 device_printf(dev, "executing CLO failed\n"); 2216 break; 2217 } 2218 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2219 } 2220} 2221 2222static void 2223ahci_stop_fr(device_t dev) 2224{ 2225 struct ahci_channel *ch = device_get_softc(dev); 2226 u_int32_t cmd; 2227 int timeout; 2228 2229 /* Kill all FIS reception on this channel */ 2230 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2231 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2232 /* Wait for FIS reception stop. */ 2233 timeout = 0; 2234 do { 2235 DELAY(1000); 2236 if (timeout++ > 1000) { 2237 device_printf(dev, "stopping AHCI FR engine failed\n"); 2238 break; 2239 } 2240 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2241} 2242 2243static void 2244ahci_start_fr(device_t dev) 2245{ 2246 struct ahci_channel *ch = device_get_softc(dev); 2247 u_int32_t cmd; 2248 2249 /* Start FIS reception on this channel */ 2250 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2251 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2252} 2253 2254static int 2255ahci_wait_ready(device_t dev, int t) 2256{ 2257 struct ahci_channel *ch = device_get_softc(dev); 2258 int timeout = 0; 2259 uint32_t val; 2260 2261 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2262 (ATA_S_BUSY | ATA_S_DRQ)) { 2263 DELAY(1000); 2264 if (timeout++ > t) { 2265 device_printf(dev, "device is not ready (timeout %dms) " 2266 "tfd = %08x\n", t, val); 2267 return (EBUSY); 2268 } 2269 } 2270 if (bootverbose) 2271 device_printf(dev, "ready wait time=%dms\n", timeout); 2272 return (0); 2273} 2274 2275static void 2276ahci_reset(device_t dev) 2277{ 2278 struct ahci_channel *ch = device_get_softc(dev); 2279 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2280 int i; 2281 2282 xpt_freeze_simq(ch->sim, 1); 2283 if (bootverbose) 2284 device_printf(dev, "AHCI reset...\n"); 2285 /* Requeue freezed command. */ 2286 if (ch->frozen) { 2287 union ccb *fccb = ch->frozen; 2288 ch->frozen = NULL; 2289 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2290 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2291 xpt_freeze_devq(fccb->ccb_h.path, 1); 2292 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2293 } 2294 xpt_done(fccb); 2295 } 2296 /* Kill the engine and requeue all running commands. */ 2297 ahci_stop(dev); 2298 for (i = 0; i < ch->numslots; i++) { 2299 /* Do we have a running request on slot? */ 2300 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2301 continue; 2302 /* XXX; Commands in loading state. */ 2303 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2304 } 2305 for (i = 0; i < ch->numslots; i++) { 2306 if (!ch->hold[i]) 2307 continue; 2308 xpt_done(ch->hold[i]); 2309 ch->hold[i] = NULL; 2310 ch->numhslots--; 2311 } 2312 if (ch->toslots != 0) 2313 xpt_release_simq(ch->sim, TRUE); 2314 ch->eslots = 0; 2315 ch->toslots = 0; 2316 ch->fatalerr = 0; 2317 /* Tell the XPT about the event */ 2318 xpt_async(AC_BUS_RESET, ch->path, NULL); 2319 /* Disable port interrupts */ 2320 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2321 /* Reset and reconnect PHY, */ 2322 if (!ahci_sata_phy_reset(dev)) { 2323 if (bootverbose) 2324 device_printf(dev, 2325 "AHCI reset done: phy reset found no device\n"); 2326 ch->devices = 0; 2327 /* Enable wanted port interrupts */ 2328 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2329 (AHCI_P_IX_CPD | AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2330 xpt_release_simq(ch->sim, TRUE); 2331 return; 2332 } 2333 /* Wait for clearing busy status. */ 2334 if (ahci_wait_ready(dev, 15000)) 2335 ahci_clo(dev); 2336 ahci_start(dev, 1); 2337 ch->devices = 1; 2338 /* Enable wanted port interrupts */ 2339 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2340 (AHCI_P_IX_CPD | AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2341 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2342 ((ch->pm_level == 0) ? AHCI_P_IX_PRC | AHCI_P_IX_PC : 0) | 2343 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2344 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2345 if (bootverbose) 2346 device_printf(dev, "AHCI reset done: device found\n"); 2347 xpt_release_simq(ch->sim, TRUE); 2348} 2349 2350static int 2351ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2352{ 2353 struct ahci_channel *ch = device_get_softc(dev); 2354 u_int8_t *fis = &ctp->cfis[0]; 2355 2356 bzero(ctp->cfis, 64); 2357 fis[0] = 0x27; /* host to device */ 2358 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2359 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2360 fis[1] |= 0x80; 2361 fis[2] = ATA_PACKET_CMD; 2362 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2363 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2364 fis[3] = ATA_F_DMA; 2365 else { 2366 fis[5] = ccb->csio.dxfer_len; 2367 fis[6] = ccb->csio.dxfer_len >> 8; 2368 } 2369 fis[7] = ATA_D_LBA; 2370 fis[15] = ATA_A_4BIT; 2371 bzero(ctp->acmd, 32); 2372 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2373 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2374 ctp->acmd, ccb->csio.cdb_len); 2375 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2376 fis[1] |= 0x80; 2377 fis[2] = ccb->ataio.cmd.command; 2378 fis[3] = ccb->ataio.cmd.features; 2379 fis[4] = ccb->ataio.cmd.lba_low; 2380 fis[5] = ccb->ataio.cmd.lba_mid; 2381 fis[6] = ccb->ataio.cmd.lba_high; 2382 fis[7] = ccb->ataio.cmd.device; 2383 fis[8] = ccb->ataio.cmd.lba_low_exp; 2384 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2385 fis[10] = ccb->ataio.cmd.lba_high_exp; 2386 fis[11] = ccb->ataio.cmd.features_exp; 2387 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2388 fis[12] = tag << 3; 2389 fis[13] = 0; 2390 } else { 2391 fis[12] = ccb->ataio.cmd.sector_count; 2392 fis[13] = ccb->ataio.cmd.sector_count_exp; 2393 } 2394 fis[15] = ATA_A_4BIT; 2395 } else { 2396 fis[15] = ccb->ataio.cmd.control; 2397 } 2398 return (20); 2399} 2400 2401static int 2402ahci_sata_connect(struct ahci_channel *ch) 2403{ 2404 u_int32_t status; 2405 int timeout; 2406 2407 /* Wait up to 100ms for "connect well" */ 2408 for (timeout = 0; timeout < 100 ; timeout++) { 2409 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2410 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2411 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2412 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2413 break; 2414 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2415 if (bootverbose) { 2416 device_printf(ch->dev, "SATA offline status=%08x\n", 2417 status); 2418 } 2419 return (0); 2420 } 2421 DELAY(1000); 2422 } 2423 if (timeout >= 100) { 2424 if (bootverbose) { 2425 device_printf(ch->dev, "SATA connect timeout status=%08x\n", 2426 status); 2427 } 2428 return (0); 2429 } 2430 if (bootverbose) { 2431 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n", 2432 timeout, status); 2433 } 2434 /* Clear SATA error register */ 2435 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2436 return (1); 2437} 2438 2439static int 2440ahci_sata_phy_reset(device_t dev) 2441{ 2442 struct ahci_channel *ch = device_get_softc(dev); 2443 int sata_rev; 2444 uint32_t val; 2445 2446 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2447 if (sata_rev == 1) 2448 val = ATA_SC_SPD_SPEED_GEN1; 2449 else if (sata_rev == 2) 2450 val = ATA_SC_SPD_SPEED_GEN2; 2451 else if (sata_rev == 3) 2452 val = ATA_SC_SPD_SPEED_GEN3; 2453 else 2454 val = 0; 2455 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2456 ATA_SC_DET_RESET | val | 2457 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2458 DELAY(5000); 2459 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2460 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2461 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2462 DELAY(5000); 2463 if (!ahci_sata_connect(ch)) { 2464 if (ch->pm_level > 0) 2465 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2466 return (0); 2467 } 2468 return (1); 2469} 2470 2471static int 2472ahci_check_ids(device_t dev, union ccb *ccb) 2473{ 2474 struct ahci_channel *ch = device_get_softc(dev); 2475 2476 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2477 ccb->ccb_h.status = CAM_TID_INVALID; 2478 xpt_done(ccb); 2479 return (-1); 2480 } 2481 if (ccb->ccb_h.target_lun != 0) { 2482 ccb->ccb_h.status = CAM_LUN_INVALID; 2483 xpt_done(ccb); 2484 return (-1); 2485 } 2486 return (0); 2487} 2488 2489static void 2490ahciaction(struct cam_sim *sim, union ccb *ccb) 2491{ 2492 device_t dev, parent; 2493 struct ahci_channel *ch; 2494 2495 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2496 ccb->ccb_h.func_code)); 2497 2498 ch = (struct ahci_channel *)cam_sim_softc(sim); 2499 dev = ch->dev; 2500 switch (ccb->ccb_h.func_code) { 2501 /* Common cases first */ 2502 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2503 case XPT_SCSI_IO: 2504 if (ahci_check_ids(dev, ccb)) 2505 return; 2506 if (ch->devices == 0 || 2507 (ch->pm_present == 0 && 2508 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2509 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2510 break; 2511 } 2512 /* Check for command collision. */ 2513 if (ahci_check_collision(dev, ccb)) { 2514 /* Freeze command. */ 2515 ch->frozen = ccb; 2516 /* We have only one frozen slot, so freeze simq also. */ 2517 xpt_freeze_simq(ch->sim, 1); 2518 return; 2519 } 2520 ahci_begin_transaction(dev, ccb); 2521 return; 2522 case XPT_EN_LUN: /* Enable LUN as a target */ 2523 case XPT_TARGET_IO: /* Execute target I/O request */ 2524 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2525 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2526 case XPT_ABORT: /* Abort the specified CCB */ 2527 /* XXX Implement */ 2528 ccb->ccb_h.status = CAM_REQ_INVALID; 2529 break; 2530 case XPT_SET_TRAN_SETTINGS: 2531 { 2532 struct ccb_trans_settings *cts = &ccb->cts; 2533 struct ahci_device *d; 2534 2535 if (ahci_check_ids(dev, ccb)) 2536 return; 2537 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2538 d = &ch->curr[ccb->ccb_h.target_id]; 2539 else 2540 d = &ch->user[ccb->ccb_h.target_id]; 2541 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2542 d->revision = cts->xport_specific.sata.revision; 2543 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2544 d->mode = cts->xport_specific.sata.mode; 2545 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2546 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2547 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2548 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2549 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2550 ch->pm_present = cts->xport_specific.sata.pm_present; 2551 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2552 d->atapi = cts->xport_specific.sata.atapi; 2553 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2554 d->caps = cts->xport_specific.sata.caps; 2555 ccb->ccb_h.status = CAM_REQ_CMP; 2556 break; 2557 } 2558 case XPT_GET_TRAN_SETTINGS: 2559 /* Get default/user set transfer settings for the target */ 2560 { 2561 struct ccb_trans_settings *cts = &ccb->cts; 2562 struct ahci_device *d; 2563 uint32_t status; 2564 2565 if (ahci_check_ids(dev, ccb)) 2566 return; 2567 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2568 d = &ch->curr[ccb->ccb_h.target_id]; 2569 else 2570 d = &ch->user[ccb->ccb_h.target_id]; 2571 cts->protocol = PROTO_ATA; 2572 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2573 cts->transport = XPORT_SATA; 2574 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2575 cts->proto_specific.valid = 0; 2576 cts->xport_specific.sata.valid = 0; 2577 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2578 (ccb->ccb_h.target_id == 15 || 2579 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2580 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2581 if (status & 0x0f0) { 2582 cts->xport_specific.sata.revision = 2583 (status & 0x0f0) >> 4; 2584 cts->xport_specific.sata.valid |= 2585 CTS_SATA_VALID_REVISION; 2586 } 2587 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2588 if (ch->pm_level) { 2589 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 2590 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2591 if (ch->caps2 & AHCI_CAP2_APST) 2592 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 2593 } 2594 if ((ch->caps & AHCI_CAP_SNCQ) && 2595 (ch->quirks & AHCI_Q_NOAA) == 0) 2596 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 2597 cts->xport_specific.sata.caps &= 2598 ch->user[ccb->ccb_h.target_id].caps; 2599 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2600 } else { 2601 cts->xport_specific.sata.revision = d->revision; 2602 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2603 cts->xport_specific.sata.caps = d->caps; 2604 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2605 } 2606 cts->xport_specific.sata.mode = d->mode; 2607 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2608 cts->xport_specific.sata.bytecount = d->bytecount; 2609 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2610 cts->xport_specific.sata.pm_present = ch->pm_present; 2611 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2612 cts->xport_specific.sata.tags = d->tags; 2613 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2614 cts->xport_specific.sata.atapi = d->atapi; 2615 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2616 ccb->ccb_h.status = CAM_REQ_CMP; 2617 break; 2618 } 2619 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2620 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2621 ahci_reset(dev); 2622 ccb->ccb_h.status = CAM_REQ_CMP; 2623 break; 2624 case XPT_TERM_IO: /* Terminate the I/O process */ 2625 /* XXX Implement */ 2626 ccb->ccb_h.status = CAM_REQ_INVALID; 2627 break; 2628 case XPT_PATH_INQ: /* Path routing inquiry */ 2629 { 2630 struct ccb_pathinq *cpi = &ccb->cpi; 2631 2632 parent = device_get_parent(dev); 2633 cpi->version_num = 1; /* XXX??? */ 2634 cpi->hba_inquiry = PI_SDTR_ABLE; 2635 if (ch->caps & AHCI_CAP_SNCQ) 2636 cpi->hba_inquiry |= PI_TAG_ABLE; 2637 if (ch->caps & AHCI_CAP_SPM) 2638 cpi->hba_inquiry |= PI_SATAPM; 2639 cpi->target_sprt = 0; 2640 cpi->hba_misc = PIM_SEQSCAN; 2641 cpi->hba_eng_cnt = 0; 2642 if (ch->caps & AHCI_CAP_SPM) 2643 cpi->max_target = 15; 2644 else 2645 cpi->max_target = 0; 2646 cpi->max_lun = 0; 2647 cpi->initiator_id = 0; 2648 cpi->bus_id = cam_sim_bus(sim); 2649 cpi->base_transfer_speed = 150000; 2650 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2651 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2652 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2653 cpi->unit_number = cam_sim_unit(sim); 2654 cpi->transport = XPORT_SATA; 2655 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2656 cpi->protocol = PROTO_ATA; 2657 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2658 cpi->maxio = MAXPHYS; 2659 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2660 if (pci_get_devid(parent) == 0x43801002) 2661 cpi->maxio = min(cpi->maxio, 128 * 512); 2662 cpi->hba_vendor = pci_get_vendor(parent); 2663 cpi->hba_device = pci_get_device(parent); 2664 cpi->hba_subvendor = pci_get_subvendor(parent); 2665 cpi->hba_subdevice = pci_get_subdevice(parent); 2666 cpi->ccb_h.status = CAM_REQ_CMP; 2667 break; 2668 } 2669 default: 2670 ccb->ccb_h.status = CAM_REQ_INVALID; 2671 break; 2672 } 2673 xpt_done(ccb); 2674} 2675 2676static void 2677ahcipoll(struct cam_sim *sim) 2678{ 2679 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2680 2681 ahci_ch_intr(ch->dev); 2682} 2683