ahci_generic.c revision 239907
1/*- 2 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ahci/ahci.c 239907 2012-08-30 15:23:59Z mav $"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/bus.h> 35#include <sys/conf.h> 36#include <sys/endian.h> 37#include <sys/malloc.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <machine/stdarg.h> 41#include <machine/resource.h> 42#include <machine/bus.h> 43#include <sys/rman.h> 44#include <dev/pci/pcivar.h> 45#include <dev/pci/pcireg.h> 46#include "ahci.h" 47 48#include <cam/cam.h> 49#include <cam/cam_ccb.h> 50#include <cam/cam_sim.h> 51#include <cam/cam_xpt_sim.h> 52#include <cam/cam_debug.h> 53 54/* local prototypes */ 55static int ahci_setup_interrupt(device_t dev); 56static void ahci_intr(void *data); 57static void ahci_intr_one(void *data); 58static int ahci_suspend(device_t dev); 59static int ahci_resume(device_t dev); 60static int ahci_ch_init(device_t dev); 61static int ahci_ch_deinit(device_t dev); 62static int ahci_ch_suspend(device_t dev); 63static int ahci_ch_resume(device_t dev); 64static void ahci_ch_pm(void *arg); 65static void ahci_ch_intr_locked(void *data); 66static void ahci_ch_intr(void *data); 67static int ahci_ctlr_reset(device_t dev); 68static int ahci_ctlr_setup(device_t dev); 69static void ahci_begin_transaction(device_t dev, union ccb *ccb); 70static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 71static void ahci_execute_transaction(struct ahci_slot *slot); 72static void ahci_timeout(struct ahci_slot *slot); 73static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 74static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 75static void ahci_dmainit(device_t dev); 76static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 77static void ahci_dmafini(device_t dev); 78static void ahci_slotsalloc(device_t dev); 79static void ahci_slotsfree(device_t dev); 80static void ahci_reset(device_t dev); 81static void ahci_start(device_t dev, int fbs); 82static void ahci_stop(device_t dev); 83static void ahci_clo(device_t dev); 84static void ahci_start_fr(device_t dev); 85static void ahci_stop_fr(device_t dev); 86 87static int ahci_sata_connect(struct ahci_channel *ch); 88static int ahci_sata_phy_reset(device_t dev); 89static int ahci_wait_ready(device_t dev, int t, int t0); 90 91static void ahci_issue_recovery(device_t dev); 92static void ahci_process_read_log(device_t dev, union ccb *ccb); 93static void ahci_process_request_sense(device_t dev, union ccb *ccb); 94 95static void ahciaction(struct cam_sim *sim, union ccb *ccb); 96static void ahcipoll(struct cam_sim *sim); 97 98static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 99 100static struct { 101 uint32_t id; 102 uint8_t rev; 103 const char *name; 104 int quirks; 105#define AHCI_Q_NOFORCE 1 106#define AHCI_Q_NOPMP 2 107#define AHCI_Q_NONCQ 4 108#define AHCI_Q_1CH 8 109#define AHCI_Q_2CH 16 110#define AHCI_Q_4CH 32 111#define AHCI_Q_EDGEIS 64 112#define AHCI_Q_SATA2 128 113#define AHCI_Q_NOBSYRES 256 114#define AHCI_Q_NOAA 512 115#define AHCI_Q_NOCOUNT 1024 116#define AHCI_Q_ALTSIG 2048 117} ahci_ids[] = { 118 {0x43801002, 0x00, "ATI IXP600", 0}, 119 {0x43901002, 0x00, "ATI IXP700", 0}, 120 {0x43911002, 0x00, "ATI IXP700", 0}, 121 {0x43921002, 0x00, "ATI IXP700", 0}, 122 {0x43931002, 0x00, "ATI IXP700", 0}, 123 {0x43941002, 0x00, "ATI IXP800", 0}, 124 {0x43951002, 0x00, "ATI IXP800", 0}, 125 {0x06121b21, 0x00, "ASMedia ASM1061", 0}, 126 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE}, 127 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE}, 128 {0x26818086, 0x00, "Intel ESB2", 0}, 129 {0x26828086, 0x00, "Intel ESB2", 0}, 130 {0x26838086, 0x00, "Intel ESB2", 0}, 131 {0x27c18086, 0x00, "Intel ICH7", 0}, 132 {0x27c38086, 0x00, "Intel ICH7", 0}, 133 {0x27c58086, 0x00, "Intel ICH7M", 0}, 134 {0x27c68086, 0x00, "Intel ICH7M", 0}, 135 {0x28218086, 0x00, "Intel ICH8", 0}, 136 {0x28228086, 0x00, "Intel ICH8", 0}, 137 {0x28248086, 0x00, "Intel ICH8", 0}, 138 {0x28298086, 0x00, "Intel ICH8M", 0}, 139 {0x282a8086, 0x00, "Intel ICH8M", 0}, 140 {0x29228086, 0x00, "Intel ICH9", 0}, 141 {0x29238086, 0x00, "Intel ICH9", 0}, 142 {0x29248086, 0x00, "Intel ICH9", 0}, 143 {0x29258086, 0x00, "Intel ICH9", 0}, 144 {0x29278086, 0x00, "Intel ICH9", 0}, 145 {0x29298086, 0x00, "Intel ICH9M", 0}, 146 {0x292a8086, 0x00, "Intel ICH9M", 0}, 147 {0x292b8086, 0x00, "Intel ICH9M", 0}, 148 {0x292c8086, 0x00, "Intel ICH9M", 0}, 149 {0x292f8086, 0x00, "Intel ICH9M", 0}, 150 {0x294d8086, 0x00, "Intel ICH9", 0}, 151 {0x294e8086, 0x00, "Intel ICH9M", 0}, 152 {0x3a058086, 0x00, "Intel ICH10", 0}, 153 {0x3a228086, 0x00, "Intel ICH10", 0}, 154 {0x3a258086, 0x00, "Intel ICH10", 0}, 155 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0}, 156 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0}, 157 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0}, 158 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0}, 159 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0}, 160 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0}, 161 {0x1c028086, 0x00, "Intel Cougar Point", 0}, 162 {0x1c038086, 0x00, "Intel Cougar Point", 0}, 163 {0x1c048086, 0x00, "Intel Cougar Point", 0}, 164 {0x1c058086, 0x00, "Intel Cougar Point", 0}, 165 {0x1d028086, 0x00, "Intel Patsburg", 0}, 166 {0x1d048086, 0x00, "Intel Patsburg", 0}, 167 {0x1d068086, 0x00, "Intel Patsburg", 0}, 168 {0x28268086, 0x00, "Intel Patsburg (RAID)", 0}, 169 {0x1e028086, 0x00, "Intel Panther Point", 0}, 170 {0x1e038086, 0x00, "Intel Panther Point", 0}, 171 {0x1e048086, 0x00, "Intel Panther Point", 0}, 172 {0x1e058086, 0x00, "Intel Panther Point", 0}, 173 {0x1e068086, 0x00, "Intel Panther Point", 0}, 174 {0x1e078086, 0x00, "Intel Panther Point", 0}, 175 {0x1e0e8086, 0x00, "Intel Panther Point", 0}, 176 {0x1e0f8086, 0x00, "Intel Panther Point", 0}, 177 {0x23238086, 0x00, "Intel DH89xxCC", 0}, 178 {0x2360197b, 0x00, "JMicron JMB360", 0}, 179 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE}, 180 {0x2362197b, 0x00, "JMicron JMB362", 0}, 181 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE}, 182 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE}, 183 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE}, 184 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE}, 185 {0x611111ab, 0x00, "Marvell 88SE6111", AHCI_Q_NOFORCE | AHCI_Q_1CH | 186 AHCI_Q_EDGEIS}, 187 {0x612111ab, 0x00, "Marvell 88SE6121", AHCI_Q_NOFORCE | AHCI_Q_2CH | 188 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 189 {0x614111ab, 0x00, "Marvell 88SE6141", AHCI_Q_NOFORCE | AHCI_Q_4CH | 190 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 191 {0x614511ab, 0x00, "Marvell 88SE6145", AHCI_Q_NOFORCE | AHCI_Q_4CH | 192 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 193 {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_NOBSYRES}, 194 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 195 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES}, 196 {0x91251b4b, 0x00, "Marvell 88SE9125", AHCI_Q_NOBSYRES}, 197 {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 198 {0x91301b4b, 0x00, "Marvell 88SE9130", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 199 {0x91721b4b, 0x00, "Marvell 88SE9172", AHCI_Q_NOBSYRES}, 200 {0x91821b4b, 0x00, "Marvell 88SE9182", AHCI_Q_NOBSYRES}, 201 {0x92201b4b, 0x00, "Marvell 88SE9220", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 202 {0x92301b4b, 0x00, "Marvell 88SE9230", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 203 {0x92351b4b, 0x00, "Marvell 88SE9235", AHCI_Q_NOBSYRES}, 204 {0x06201103, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 205 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 206 {0x06221103, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 207 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 208 {0x06401103, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 209 {0x06401b4b, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 210 {0x06441103, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 211 {0x06441b4b, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 212 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 213 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 214 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 215 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 216 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 217 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 218 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 219 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 220 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 221 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 222 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 223 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 224 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 225 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 226 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 227 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 228 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 229 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 230 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 231 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 232 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 233 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 234 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 235 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 236 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 237 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 238 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 239 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 240 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 241 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 242 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 243 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 244 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 245 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 246 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 247 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 248 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 249 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 250 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 251 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 252 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 253 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 254 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 255 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 256 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 257 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 258 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 259 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 260 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 261 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 262 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 263 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 264 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 265 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 266 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 267 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 268 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 269 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 270 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA}, 271 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 272 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 273 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 274 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 275 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 276 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 277 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 278 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 279 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 280 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 281 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 282 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 283 {0x11841039, 0x00, "SiS 966", 0}, 284 {0x11851039, 0x00, "SiS 968", 0}, 285 {0x01861039, 0x00, "SiS 968", 0}, 286 {0x00000000, 0x00, NULL, 0} 287}; 288 289#define recovery_type spriv_field0 290#define RECOVERY_NONE 0 291#define RECOVERY_READ_LOG 1 292#define RECOVERY_REQUEST_SENSE 2 293#define recovery_slot spriv_field1 294 295static int force_ahci = 1; 296TUNABLE_INT("hw.ahci.force", &force_ahci); 297 298static int 299ahci_probe(device_t dev) 300{ 301 char buf[64]; 302 int i, valid = 0; 303 uint32_t devid = pci_get_devid(dev); 304 uint8_t revid = pci_get_revid(dev); 305 306 /* Is this a possible AHCI candidate? */ 307 if (pci_get_class(dev) == PCIC_STORAGE && 308 pci_get_subclass(dev) == PCIS_STORAGE_SATA && 309 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0) 310 valid = 1; 311 /* Is this a known AHCI chip? */ 312 for (i = 0; ahci_ids[i].id != 0; i++) { 313 if (ahci_ids[i].id == devid && 314 ahci_ids[i].rev <= revid && 315 (valid || (force_ahci == 1 && 316 !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) { 317 /* Do not attach JMicrons with single PCI function. */ 318 if (pci_get_vendor(dev) == 0x197b && 319 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0) 320 return (ENXIO); 321 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 322 ahci_ids[i].name); 323 device_set_desc_copy(dev, buf); 324 return (BUS_PROBE_VENDOR); 325 } 326 } 327 if (!valid) 328 return (ENXIO); 329 device_set_desc_copy(dev, "AHCI SATA controller"); 330 return (BUS_PROBE_VENDOR); 331} 332 333static int 334ahci_ata_probe(device_t dev) 335{ 336 char buf[64]; 337 int i; 338 uint32_t devid = pci_get_devid(dev); 339 uint8_t revid = pci_get_revid(dev); 340 341 if ((intptr_t)device_get_ivars(dev) >= 0) 342 return (ENXIO); 343 /* Is this a known AHCI chip? */ 344 for (i = 0; ahci_ids[i].id != 0; i++) { 345 if (ahci_ids[i].id == devid && 346 ahci_ids[i].rev <= revid) { 347 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 348 ahci_ids[i].name); 349 device_set_desc_copy(dev, buf); 350 return (BUS_PROBE_VENDOR); 351 } 352 } 353 device_set_desc_copy(dev, "AHCI SATA controller"); 354 return (BUS_PROBE_VENDOR); 355} 356 357static int 358ahci_attach(device_t dev) 359{ 360 struct ahci_controller *ctlr = device_get_softc(dev); 361 device_t child; 362 int error, unit, speed, i; 363 uint32_t devid = pci_get_devid(dev); 364 uint8_t revid = pci_get_revid(dev); 365 u_int32_t version; 366 367 ctlr->dev = dev; 368 i = 0; 369 while (ahci_ids[i].id != 0 && 370 (ahci_ids[i].id != devid || 371 ahci_ids[i].rev > revid)) 372 i++; 373 ctlr->quirks = ahci_ids[i].quirks; 374 resource_int_value(device_get_name(dev), 375 device_get_unit(dev), "ccc", &ctlr->ccc); 376 /* if we have a memory BAR(5) we are likely on an AHCI part */ 377 ctlr->r_rid = PCIR_BAR(5); 378 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 379 &ctlr->r_rid, RF_ACTIVE))) 380 return ENXIO; 381 /* Setup our own memory management for channels. */ 382 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 383 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 384 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 385 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 386 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 387 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 388 return (error); 389 } 390 if ((error = rman_manage_region(&ctlr->sc_iomem, 391 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 392 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 393 rman_fini(&ctlr->sc_iomem); 394 return (error); 395 } 396 pci_enable_busmaster(dev); 397 /* Reset controller */ 398 if ((error = ahci_ctlr_reset(dev)) != 0) { 399 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 400 rman_fini(&ctlr->sc_iomem); 401 return (error); 402 }; 403 /* Get the HW capabilities */ 404 version = ATA_INL(ctlr->r_mem, AHCI_VS); 405 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 406 if (version >= 0x00010020) 407 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 408 if (ctlr->caps & AHCI_CAP_EMS) 409 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 410 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 411 412 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */ 413 if ((ctlr->quirks & AHCI_Q_NOBSYRES) && 414 (ctlr->quirks & AHCI_Q_ALTSIG) && 415 (ctlr->caps & AHCI_CAP_SPM) == 0) 416 ctlr->quirks &= ~AHCI_Q_NOBSYRES; 417 418 if (ctlr->quirks & AHCI_Q_1CH) { 419 ctlr->caps &= ~AHCI_CAP_NPMASK; 420 ctlr->ichannels &= 0x01; 421 } 422 if (ctlr->quirks & AHCI_Q_2CH) { 423 ctlr->caps &= ~AHCI_CAP_NPMASK; 424 ctlr->caps |= 1; 425 ctlr->ichannels &= 0x03; 426 } 427 if (ctlr->quirks & AHCI_Q_4CH) { 428 ctlr->caps &= ~AHCI_CAP_NPMASK; 429 ctlr->caps |= 3; 430 ctlr->ichannels &= 0x0f; 431 } 432 ctlr->channels = MAX(flsl(ctlr->ichannels), 433 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 434 if (ctlr->quirks & AHCI_Q_NOPMP) 435 ctlr->caps &= ~AHCI_CAP_SPM; 436 if (ctlr->quirks & AHCI_Q_NONCQ) 437 ctlr->caps &= ~AHCI_CAP_SNCQ; 438 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 439 ctlr->ccc = 0; 440 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC); 441 ahci_ctlr_setup(dev); 442 /* Setup interrupts. */ 443 if (ahci_setup_interrupt(dev)) { 444 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 445 rman_fini(&ctlr->sc_iomem); 446 return ENXIO; 447 } 448 /* Announce HW capabilities. */ 449 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 450 device_printf(dev, 451 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 452 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 453 ((version >> 4) & 0xf0) + (version & 0x0f), 454 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 455 ((speed == 1) ? "1.5":((speed == 2) ? "3": 456 ((speed == 3) ? "6":"?"))), 457 (ctlr->caps & AHCI_CAP_SPM) ? 458 "supported" : "not supported", 459 (ctlr->caps & AHCI_CAP_FBSS) ? 460 " with FBS" : ""); 461 if (bootverbose) { 462 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 463 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 464 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 465 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 466 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 467 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 468 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 469 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 470 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 471 ((speed == 1) ? "1.5":((speed == 2) ? "3": 472 ((speed == 3) ? "6":"?")))); 473 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 474 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 475 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 476 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 477 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 478 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 479 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 480 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 481 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 482 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 483 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 484 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 485 } 486 if (bootverbose && version >= 0x00010020) { 487 device_printf(dev, "Caps2:%s%s%s\n", 488 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 489 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 490 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 491 } 492 /* Attach all channels on this controller */ 493 for (unit = 0; unit < ctlr->channels; unit++) { 494 child = device_add_child(dev, "ahcich", -1); 495 if (child == NULL) { 496 device_printf(dev, "failed to add channel device\n"); 497 continue; 498 } 499 device_set_ivars(child, (void *)(intptr_t)unit); 500 if ((ctlr->ichannels & (1 << unit)) == 0) 501 device_disable(child); 502 } 503 if (ctlr->caps & AHCI_CAP_EMS) { 504 child = device_add_child(dev, "ahciem", -1); 505 if (child == NULL) 506 device_printf(dev, "failed to add enclosure device\n"); 507 else 508 device_set_ivars(child, (void *)(intptr_t)-1); 509 } 510 bus_generic_attach(dev); 511 return 0; 512} 513 514static int 515ahci_detach(device_t dev) 516{ 517 struct ahci_controller *ctlr = device_get_softc(dev); 518 int i; 519 520 /* Detach & delete all children */ 521 device_delete_children(dev); 522 523 /* Free interrupts. */ 524 for (i = 0; i < ctlr->numirqs; i++) { 525 if (ctlr->irqs[i].r_irq) { 526 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 527 ctlr->irqs[i].handle); 528 bus_release_resource(dev, SYS_RES_IRQ, 529 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 530 } 531 } 532 pci_release_msi(dev); 533 /* Free memory. */ 534 rman_fini(&ctlr->sc_iomem); 535 if (ctlr->r_mem) 536 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 537 return (0); 538} 539 540static int 541ahci_ctlr_reset(device_t dev) 542{ 543 struct ahci_controller *ctlr = device_get_softc(dev); 544 int timeout; 545 546 if (pci_read_config(dev, 0x00, 4) == 0x28298086 && 547 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 548 pci_write_config(dev, 0x92, 0x01, 1); 549 /* Enable AHCI mode */ 550 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 551 /* Reset AHCI controller */ 552 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 553 for (timeout = 1000; timeout > 0; timeout--) { 554 DELAY(1000); 555 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 556 break; 557 } 558 if (timeout == 0) { 559 device_printf(dev, "AHCI controller reset failure\n"); 560 return ENXIO; 561 } 562 /* Reenable AHCI mode */ 563 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 564 return (0); 565} 566 567static int 568ahci_ctlr_setup(device_t dev) 569{ 570 struct ahci_controller *ctlr = device_get_softc(dev); 571 /* Clear interrupts */ 572 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 573 /* Configure CCC */ 574 if (ctlr->ccc) { 575 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 576 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 577 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 578 (4 << AHCI_CCCC_CC_SHIFT) | 579 AHCI_CCCC_EN); 580 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 581 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 582 if (bootverbose) { 583 device_printf(dev, 584 "CCC with %dms/4cmd enabled on vector %d\n", 585 ctlr->ccc, ctlr->cccv); 586 } 587 } 588 /* Enable AHCI interrupts */ 589 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 590 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 591 return (0); 592} 593 594static int 595ahci_suspend(device_t dev) 596{ 597 struct ahci_controller *ctlr = device_get_softc(dev); 598 599 bus_generic_suspend(dev); 600 /* Disable interupts, so the state change(s) doesn't trigger */ 601 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 602 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 603 return 0; 604} 605 606static int 607ahci_resume(device_t dev) 608{ 609 int res; 610 611 if ((res = ahci_ctlr_reset(dev)) != 0) 612 return (res); 613 ahci_ctlr_setup(dev); 614 return (bus_generic_resume(dev)); 615} 616 617static int 618ahci_setup_interrupt(device_t dev) 619{ 620 struct ahci_controller *ctlr = device_get_softc(dev); 621 int i, msi = 1; 622 623 /* Process hints. */ 624 resource_int_value(device_get_name(dev), 625 device_get_unit(dev), "msi", &msi); 626 if (msi < 0) 627 msi = 0; 628 else if (msi == 1) 629 msi = min(1, pci_msi_count(dev)); 630 else if (msi > 1) 631 msi = pci_msi_count(dev); 632 /* Allocate MSI if needed/present. */ 633 if (msi && pci_alloc_msi(dev, &msi) == 0) { 634 ctlr->numirqs = msi; 635 } else { 636 msi = 0; 637 ctlr->numirqs = 1; 638 } 639 /* Check for single MSI vector fallback. */ 640 if (ctlr->numirqs > 1 && 641 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 642 device_printf(dev, "Falling back to one MSI\n"); 643 ctlr->numirqs = 1; 644 } 645 /* Allocate all IRQs. */ 646 for (i = 0; i < ctlr->numirqs; i++) { 647 ctlr->irqs[i].ctlr = ctlr; 648 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0); 649 if (ctlr->numirqs == 1 || i >= ctlr->channels || 650 (ctlr->ccc && i == ctlr->cccv)) 651 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 652 else if (i == ctlr->numirqs - 1) 653 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 654 else 655 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 656 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 657 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 658 device_printf(dev, "unable to map interrupt\n"); 659 return ENXIO; 660 } 661 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 662 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr, 663 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 664 /* SOS XXX release r_irq */ 665 device_printf(dev, "unable to setup interrupt\n"); 666 return ENXIO; 667 } 668 if (ctlr->numirqs > 1) { 669 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 670 ctlr->irqs[i].handle, 671 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 672 "ch%d" : "%d", i); 673 } 674 } 675 return (0); 676} 677 678/* 679 * Common case interrupt handler. 680 */ 681static void 682ahci_intr(void *data) 683{ 684 struct ahci_controller_irq *irq = data; 685 struct ahci_controller *ctlr = irq->ctlr; 686 u_int32_t is, ise = 0; 687 void *arg; 688 int unit; 689 690 if (irq->mode == AHCI_IRQ_MODE_ALL) { 691 unit = 0; 692 if (ctlr->ccc) 693 is = ctlr->ichannels; 694 else 695 is = ATA_INL(ctlr->r_mem, AHCI_IS); 696 } else { /* AHCI_IRQ_MODE_AFTER */ 697 unit = irq->r_irq_rid - 1; 698 is = ATA_INL(ctlr->r_mem, AHCI_IS); 699 } 700 /* CCC interrupt is edge triggered. */ 701 if (ctlr->ccc) 702 ise = 1 << ctlr->cccv; 703 /* Some controllers have edge triggered IS. */ 704 if (ctlr->quirks & AHCI_Q_EDGEIS) 705 ise |= is; 706 if (ise != 0) 707 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 708 for (; unit < ctlr->channels; unit++) { 709 if ((is & (1 << unit)) != 0 && 710 (arg = ctlr->interrupt[unit].argument)) { 711 ctlr->interrupt[unit].function(arg); 712 } 713 } 714 /* AHCI declares level triggered IS. */ 715 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 716 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 717} 718 719/* 720 * Simplified interrupt handler for multivector MSI mode. 721 */ 722static void 723ahci_intr_one(void *data) 724{ 725 struct ahci_controller_irq *irq = data; 726 struct ahci_controller *ctlr = irq->ctlr; 727 void *arg; 728 int unit; 729 730 unit = irq->r_irq_rid - 1; 731 /* Some controllers have edge triggered IS. */ 732 if (ctlr->quirks & AHCI_Q_EDGEIS) 733 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 734 if ((arg = ctlr->interrupt[unit].argument)) 735 ctlr->interrupt[unit].function(arg); 736 /* AHCI declares level triggered IS. */ 737 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 738 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 739} 740 741static struct resource * 742ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 743 u_long start, u_long end, u_long count, u_int flags) 744{ 745 struct ahci_controller *ctlr = device_get_softc(dev); 746 struct resource *res; 747 long st; 748 int offset, size, unit; 749 750 unit = (intptr_t)device_get_ivars(child); 751 res = NULL; 752 switch (type) { 753 case SYS_RES_MEMORY: 754 if (unit >= 0) { 755 offset = AHCI_OFFSET + (unit << 7); 756 size = 128; 757 } else if (*rid == 0) { 758 offset = AHCI_EM_CTL; 759 size = 4; 760 } else { 761 offset = (ctlr->emloc & 0xffff0000) >> 14; 762 size = (ctlr->emloc & 0x0000ffff) << 2; 763 if (*rid != 1) { 764 if (*rid == 2 && (ctlr->capsem & 765 (AHCI_EM_XMT | AHCI_EM_SMB)) == 0) 766 offset += size; 767 else 768 break; 769 } 770 } 771 st = rman_get_start(ctlr->r_mem); 772 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 773 st + offset + size - 1, size, RF_ACTIVE, child); 774 if (res) { 775 bus_space_handle_t bsh; 776 bus_space_tag_t bst; 777 bsh = rman_get_bushandle(ctlr->r_mem); 778 bst = rman_get_bustag(ctlr->r_mem); 779 bus_space_subregion(bst, bsh, offset, 128, &bsh); 780 rman_set_bushandle(res, bsh); 781 rman_set_bustag(res, bst); 782 } 783 break; 784 case SYS_RES_IRQ: 785 if (*rid == ATA_IRQ_RID) 786 res = ctlr->irqs[0].r_irq; 787 break; 788 } 789 return (res); 790} 791 792static int 793ahci_release_resource(device_t dev, device_t child, int type, int rid, 794 struct resource *r) 795{ 796 797 switch (type) { 798 case SYS_RES_MEMORY: 799 rman_release_resource(r); 800 return (0); 801 case SYS_RES_IRQ: 802 if (rid != ATA_IRQ_RID) 803 return ENOENT; 804 return (0); 805 } 806 return (EINVAL); 807} 808 809static int 810ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 811 int flags, driver_filter_t *filter, driver_intr_t *function, 812 void *argument, void **cookiep) 813{ 814 struct ahci_controller *ctlr = device_get_softc(dev); 815 int unit = (intptr_t)device_get_ivars(child); 816 817 if (filter != NULL) { 818 printf("ahci.c: we cannot use a filter here\n"); 819 return (EINVAL); 820 } 821 ctlr->interrupt[unit].function = function; 822 ctlr->interrupt[unit].argument = argument; 823 return (0); 824} 825 826static int 827ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 828 void *cookie) 829{ 830 struct ahci_controller *ctlr = device_get_softc(dev); 831 int unit = (intptr_t)device_get_ivars(child); 832 833 ctlr->interrupt[unit].function = NULL; 834 ctlr->interrupt[unit].argument = NULL; 835 return (0); 836} 837 838static int 839ahci_print_child(device_t dev, device_t child) 840{ 841 int retval, channel; 842 843 retval = bus_print_child_header(dev, child); 844 channel = (int)(intptr_t)device_get_ivars(child); 845 if (channel >= 0) 846 retval += printf(" at channel %d", channel); 847 retval += bus_print_child_footer(dev, child); 848 return (retval); 849} 850 851static int 852ahci_child_location_str(device_t dev, device_t child, char *buf, 853 size_t buflen) 854{ 855 int channel; 856 857 channel = (int)(intptr_t)device_get_ivars(child); 858 if (channel >= 0) 859 snprintf(buf, buflen, "channel=%d", channel); 860 return (0); 861} 862 863devclass_t ahci_devclass; 864static device_method_t ahci_methods[] = { 865 DEVMETHOD(device_probe, ahci_probe), 866 DEVMETHOD(device_attach, ahci_attach), 867 DEVMETHOD(device_detach, ahci_detach), 868 DEVMETHOD(device_suspend, ahci_suspend), 869 DEVMETHOD(device_resume, ahci_resume), 870 DEVMETHOD(bus_print_child, ahci_print_child), 871 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 872 DEVMETHOD(bus_release_resource, ahci_release_resource), 873 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 874 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 875 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 876 { 0, 0 } 877}; 878static driver_t ahci_driver = { 879 "ahci", 880 ahci_methods, 881 sizeof(struct ahci_controller) 882}; 883DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 884static device_method_t ahci_ata_methods[] = { 885 DEVMETHOD(device_probe, ahci_ata_probe), 886 DEVMETHOD(device_attach, ahci_attach), 887 DEVMETHOD(device_detach, ahci_detach), 888 DEVMETHOD(device_suspend, ahci_suspend), 889 DEVMETHOD(device_resume, ahci_resume), 890 DEVMETHOD(bus_print_child, ahci_print_child), 891 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 892 DEVMETHOD(bus_release_resource, ahci_release_resource), 893 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 894 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 895 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 896 { 0, 0 } 897}; 898static driver_t ahci_ata_driver = { 899 "ahci", 900 ahci_ata_methods, 901 sizeof(struct ahci_controller) 902}; 903DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0); 904MODULE_VERSION(ahci, 1); 905MODULE_DEPEND(ahci, cam, 1, 1, 1); 906 907static int 908ahci_ch_probe(device_t dev) 909{ 910 911 device_set_desc_copy(dev, "AHCI channel"); 912 return (0); 913} 914 915static int 916ahci_ch_attach(device_t dev) 917{ 918 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 919 struct ahci_channel *ch = device_get_softc(dev); 920 struct cam_devq *devq; 921 int rid, error, i, sata_rev = 0; 922 u_int32_t version; 923 924 ch->dev = dev; 925 ch->unit = (intptr_t)device_get_ivars(dev); 926 ch->caps = ctlr->caps; 927 ch->caps2 = ctlr->caps2; 928 ch->quirks = ctlr->quirks; 929 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 930 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 931 resource_int_value(device_get_name(dev), 932 device_get_unit(dev), "pm_level", &ch->pm_level); 933 if (ch->pm_level > 3) 934 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 935 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 936 /* Limit speed for my onboard JMicron external port. 937 * It is not eSATA really. */ 938 if (pci_get_devid(ctlr->dev) == 0x2363197b && 939 pci_get_subvendor(ctlr->dev) == 0x1043 && 940 pci_get_subdevice(ctlr->dev) == 0x81e4 && 941 ch->unit == 0) 942 sata_rev = 1; 943 if (ch->quirks & AHCI_Q_SATA2) 944 sata_rev = 2; 945 resource_int_value(device_get_name(dev), 946 device_get_unit(dev), "sata_rev", &sata_rev); 947 for (i = 0; i < 16; i++) { 948 ch->user[i].revision = sata_rev; 949 ch->user[i].mode = 0; 950 ch->user[i].bytecount = 8192; 951 ch->user[i].tags = ch->numslots; 952 ch->user[i].caps = 0; 953 ch->curr[i] = ch->user[i]; 954 if (ch->pm_level) { 955 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 956 CTS_SATA_CAPS_H_APST | 957 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 958 } 959 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA | 960 CTS_SATA_CAPS_H_AN; 961 } 962 rid = 0; 963 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 964 &rid, RF_ACTIVE))) 965 return (ENXIO); 966 ahci_dmainit(dev); 967 ahci_slotsalloc(dev); 968 ahci_ch_init(dev); 969 mtx_lock(&ch->mtx); 970 rid = ATA_IRQ_RID; 971 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 972 &rid, RF_SHAREABLE | RF_ACTIVE))) { 973 device_printf(dev, "Unable to map interrupt\n"); 974 error = ENXIO; 975 goto err0; 976 } 977 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 978 ahci_ch_intr_locked, dev, &ch->ih))) { 979 device_printf(dev, "Unable to setup interrupt\n"); 980 error = ENXIO; 981 goto err1; 982 } 983 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 984 version = ATA_INL(ctlr->r_mem, AHCI_VS); 985 if (version < 0x00010020 && (ctlr->caps & AHCI_CAP_FBSS)) 986 ch->chcaps |= AHCI_P_CMD_FBSCP; 987 if (bootverbose) { 988 device_printf(dev, "Caps:%s%s%s%s%s\n", 989 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 990 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 991 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 992 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 993 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":""); 994 } 995 /* Create the device queue for our SIM. */ 996 devq = cam_simq_alloc(ch->numslots); 997 if (devq == NULL) { 998 device_printf(dev, "Unable to allocate simq\n"); 999 error = ENOMEM; 1000 goto err1; 1001 } 1002 /* Construct SIM entry */ 1003 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 1004 device_get_unit(dev), &ch->mtx, 1005 min(2, ch->numslots), 1006 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 1007 devq); 1008 if (ch->sim == NULL) { 1009 cam_simq_free(devq); 1010 device_printf(dev, "unable to allocate sim\n"); 1011 error = ENOMEM; 1012 goto err1; 1013 } 1014 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 1015 device_printf(dev, "unable to register xpt bus\n"); 1016 error = ENXIO; 1017 goto err2; 1018 } 1019 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 1020 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1021 device_printf(dev, "unable to create path\n"); 1022 error = ENXIO; 1023 goto err3; 1024 } 1025 if (ch->pm_level > 3) { 1026 callout_reset(&ch->pm_timer, 1027 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 1028 ahci_ch_pm, dev); 1029 } 1030 mtx_unlock(&ch->mtx); 1031 return (0); 1032 1033err3: 1034 xpt_bus_deregister(cam_sim_path(ch->sim)); 1035err2: 1036 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1037err1: 1038 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1039err0: 1040 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1041 mtx_unlock(&ch->mtx); 1042 mtx_destroy(&ch->mtx); 1043 return (error); 1044} 1045 1046static int 1047ahci_ch_detach(device_t dev) 1048{ 1049 struct ahci_channel *ch = device_get_softc(dev); 1050 1051 mtx_lock(&ch->mtx); 1052 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 1053 /* Forget about reset. */ 1054 if (ch->resetting) { 1055 ch->resetting = 0; 1056 xpt_release_simq(ch->sim, TRUE); 1057 } 1058 xpt_free_path(ch->path); 1059 xpt_bus_deregister(cam_sim_path(ch->sim)); 1060 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1061 mtx_unlock(&ch->mtx); 1062 1063 if (ch->pm_level > 3) 1064 callout_drain(&ch->pm_timer); 1065 callout_drain(&ch->reset_timer); 1066 bus_teardown_intr(dev, ch->r_irq, ch->ih); 1067 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1068 1069 ahci_ch_deinit(dev); 1070 ahci_slotsfree(dev); 1071 ahci_dmafini(dev); 1072 1073 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1074 mtx_destroy(&ch->mtx); 1075 return (0); 1076} 1077 1078static int 1079ahci_ch_init(device_t dev) 1080{ 1081 struct ahci_channel *ch = device_get_softc(dev); 1082 uint64_t work; 1083 1084 /* Disable port interrupts */ 1085 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1086 /* Setup work areas */ 1087 work = ch->dma.work_bus + AHCI_CL_OFFSET; 1088 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 1089 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 1090 work = ch->dma.rfis_bus; 1091 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 1092 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 1093 /* Activate the channel and power/spin up device */ 1094 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 1095 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1096 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 1097 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 1098 ahci_start_fr(dev); 1099 ahci_start(dev, 1); 1100 return (0); 1101} 1102 1103static int 1104ahci_ch_deinit(device_t dev) 1105{ 1106 struct ahci_channel *ch = device_get_softc(dev); 1107 1108 /* Disable port interrupts. */ 1109 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1110 /* Reset command register. */ 1111 ahci_stop(dev); 1112 ahci_stop_fr(dev); 1113 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 1114 /* Allow everything, including partial and slumber modes. */ 1115 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 1116 /* Request slumber mode transition and give some time to get there. */ 1117 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 1118 DELAY(100); 1119 /* Disable PHY. */ 1120 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 1121 return (0); 1122} 1123 1124static int 1125ahci_ch_suspend(device_t dev) 1126{ 1127 struct ahci_channel *ch = device_get_softc(dev); 1128 1129 mtx_lock(&ch->mtx); 1130 xpt_freeze_simq(ch->sim, 1); 1131 /* Forget about reset. */ 1132 if (ch->resetting) { 1133 ch->resetting = 0; 1134 callout_stop(&ch->reset_timer); 1135 xpt_release_simq(ch->sim, TRUE); 1136 } 1137 while (ch->oslots) 1138 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 1139 ahci_ch_deinit(dev); 1140 mtx_unlock(&ch->mtx); 1141 return (0); 1142} 1143 1144static int 1145ahci_ch_resume(device_t dev) 1146{ 1147 struct ahci_channel *ch = device_get_softc(dev); 1148 1149 mtx_lock(&ch->mtx); 1150 ahci_ch_init(dev); 1151 ahci_reset(dev); 1152 xpt_release_simq(ch->sim, TRUE); 1153 mtx_unlock(&ch->mtx); 1154 return (0); 1155} 1156 1157devclass_t ahcich_devclass; 1158static device_method_t ahcich_methods[] = { 1159 DEVMETHOD(device_probe, ahci_ch_probe), 1160 DEVMETHOD(device_attach, ahci_ch_attach), 1161 DEVMETHOD(device_detach, ahci_ch_detach), 1162 DEVMETHOD(device_suspend, ahci_ch_suspend), 1163 DEVMETHOD(device_resume, ahci_ch_resume), 1164 { 0, 0 } 1165}; 1166static driver_t ahcich_driver = { 1167 "ahcich", 1168 ahcich_methods, 1169 sizeof(struct ahci_channel) 1170}; 1171DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0); 1172 1173struct ahci_dc_cb_args { 1174 bus_addr_t maddr; 1175 int error; 1176}; 1177 1178static void 1179ahci_dmainit(device_t dev) 1180{ 1181 struct ahci_channel *ch = device_get_softc(dev); 1182 struct ahci_dc_cb_args dcba; 1183 size_t rfsize; 1184 1185 if (ch->caps & AHCI_CAP_64BIT) 1186 ch->dma.max_address = BUS_SPACE_MAXADDR; 1187 else 1188 ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT; 1189 /* Command area. */ 1190 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1191 ch->dma.max_address, BUS_SPACE_MAXADDR, 1192 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1193 0, NULL, NULL, &ch->dma.work_tag)) 1194 goto error; 1195 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0, 1196 &ch->dma.work_map)) 1197 goto error; 1198 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1199 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1200 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1201 goto error; 1202 } 1203 ch->dma.work_bus = dcba.maddr; 1204 /* FIS receive area. */ 1205 if (ch->chcaps & AHCI_P_CMD_FBSCP) 1206 rfsize = 4096; 1207 else 1208 rfsize = 256; 1209 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 1210 ch->dma.max_address, BUS_SPACE_MAXADDR, 1211 NULL, NULL, rfsize, 1, rfsize, 1212 0, NULL, NULL, &ch->dma.rfis_tag)) 1213 goto error; 1214 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1215 &ch->dma.rfis_map)) 1216 goto error; 1217 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1218 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1219 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1220 goto error; 1221 } 1222 ch->dma.rfis_bus = dcba.maddr; 1223 /* Data area. */ 1224 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1225 ch->dma.max_address, BUS_SPACE_MAXADDR, 1226 NULL, NULL, 1227 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1228 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1229 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 1230 goto error; 1231 } 1232 return; 1233 1234error: 1235 device_printf(dev, "WARNING - DMA initialization failed\n"); 1236 ahci_dmafini(dev); 1237} 1238 1239static void 1240ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1241{ 1242 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1243 1244 if (!(dcba->error = error)) 1245 dcba->maddr = segs[0].ds_addr; 1246} 1247 1248static void 1249ahci_dmafini(device_t dev) 1250{ 1251 struct ahci_channel *ch = device_get_softc(dev); 1252 1253 if (ch->dma.data_tag) { 1254 bus_dma_tag_destroy(ch->dma.data_tag); 1255 ch->dma.data_tag = NULL; 1256 } 1257 if (ch->dma.rfis_bus) { 1258 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1259 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1260 ch->dma.rfis_bus = 0; 1261 ch->dma.rfis_map = NULL; 1262 ch->dma.rfis = NULL; 1263 } 1264 if (ch->dma.work_bus) { 1265 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1266 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1267 ch->dma.work_bus = 0; 1268 ch->dma.work_map = NULL; 1269 ch->dma.work = NULL; 1270 } 1271 if (ch->dma.work_tag) { 1272 bus_dma_tag_destroy(ch->dma.work_tag); 1273 ch->dma.work_tag = NULL; 1274 } 1275} 1276 1277static void 1278ahci_slotsalloc(device_t dev) 1279{ 1280 struct ahci_channel *ch = device_get_softc(dev); 1281 int i; 1282 1283 /* Alloc and setup command/dma slots */ 1284 bzero(ch->slot, sizeof(ch->slot)); 1285 for (i = 0; i < ch->numslots; i++) { 1286 struct ahci_slot *slot = &ch->slot[i]; 1287 1288 slot->dev = dev; 1289 slot->slot = i; 1290 slot->state = AHCI_SLOT_EMPTY; 1291 slot->ccb = NULL; 1292 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1293 1294 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1295 device_printf(ch->dev, "FAILURE - create data_map\n"); 1296 } 1297} 1298 1299static void 1300ahci_slotsfree(device_t dev) 1301{ 1302 struct ahci_channel *ch = device_get_softc(dev); 1303 int i; 1304 1305 /* Free all dma slots */ 1306 for (i = 0; i < ch->numslots; i++) { 1307 struct ahci_slot *slot = &ch->slot[i]; 1308 1309 callout_drain(&slot->timeout); 1310 if (slot->dma.data_map) { 1311 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1312 slot->dma.data_map = NULL; 1313 } 1314 } 1315} 1316 1317static int 1318ahci_phy_check_events(device_t dev, u_int32_t serr) 1319{ 1320 struct ahci_channel *ch = device_get_softc(dev); 1321 1322 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 1323 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) { 1324 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1325 union ccb *ccb; 1326 1327 if (bootverbose) { 1328 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 1329 device_printf(dev, "CONNECT requested\n"); 1330 else 1331 device_printf(dev, "DISCONNECT requested\n"); 1332 } 1333 ahci_reset(dev); 1334 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1335 return (0); 1336 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1337 cam_sim_path(ch->sim), 1338 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1339 xpt_free_ccb(ccb); 1340 return (0); 1341 } 1342 xpt_rescan(ccb); 1343 return (1); 1344 } 1345 return (0); 1346} 1347 1348static void 1349ahci_cpd_check_events(device_t dev) 1350{ 1351 struct ahci_channel *ch = device_get_softc(dev); 1352 u_int32_t status; 1353 union ccb *ccb; 1354 1355 if (ch->pm_level == 0) 1356 return; 1357 1358 status = ATA_INL(ch->r_mem, AHCI_P_CMD); 1359 if ((status & AHCI_P_CMD_CPD) == 0) 1360 return; 1361 1362 if (bootverbose) { 1363 if (status & AHCI_P_CMD_CPS) { 1364 device_printf(dev, "COLD CONNECT requested\n"); 1365 } else 1366 device_printf(dev, "COLD DISCONNECT requested\n"); 1367 } 1368 ahci_reset(dev); 1369 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1370 return; 1371 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim), 1372 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1373 xpt_free_ccb(ccb); 1374 return; 1375 } 1376 xpt_rescan(ccb); 1377} 1378 1379static void 1380ahci_notify_events(device_t dev, u_int32_t status) 1381{ 1382 struct ahci_channel *ch = device_get_softc(dev); 1383 struct cam_path *dpath; 1384 int i; 1385 1386 if (ch->caps & AHCI_CAP_SSNTF) 1387 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1388 if (bootverbose) 1389 device_printf(dev, "SNTF 0x%04x\n", status); 1390 for (i = 0; i < 16; i++) { 1391 if ((status & (1 << i)) == 0) 1392 continue; 1393 if (xpt_create_path(&dpath, NULL, 1394 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1395 xpt_async(AC_SCSI_AEN, dpath, NULL); 1396 xpt_free_path(dpath); 1397 } 1398 } 1399} 1400 1401static void 1402ahci_ch_intr_locked(void *data) 1403{ 1404 device_t dev = (device_t)data; 1405 struct ahci_channel *ch = device_get_softc(dev); 1406 1407 mtx_lock(&ch->mtx); 1408 xpt_batch_start(ch->sim); 1409 ahci_ch_intr(data); 1410 xpt_batch_done(ch->sim); 1411 mtx_unlock(&ch->mtx); 1412} 1413 1414static void 1415ahci_ch_pm(void *arg) 1416{ 1417 device_t dev = (device_t)arg; 1418 struct ahci_channel *ch = device_get_softc(dev); 1419 uint32_t work; 1420 1421 if (ch->numrslots != 0) 1422 return; 1423 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1424 if (ch->pm_level == 4) 1425 work |= AHCI_P_CMD_PARTIAL; 1426 else 1427 work |= AHCI_P_CMD_SLUMBER; 1428 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1429} 1430 1431static void 1432ahci_ch_intr(void *data) 1433{ 1434 device_t dev = (device_t)data; 1435 struct ahci_channel *ch = device_get_softc(dev); 1436 uint32_t istatus, sstatus, cstatus, serr = 0, sntf = 0, ok, err; 1437 enum ahci_err_type et; 1438 int i, ccs, port, reset = 0; 1439 1440 /* Read and clear interrupt statuses. */ 1441 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1442 if (istatus == 0) 1443 return; 1444 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1445 /* Read command statuses. */ 1446 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1447 cstatus = ATA_INL(ch->r_mem, AHCI_P_CI); 1448 if (istatus & AHCI_P_IX_SDB) { 1449 if (ch->caps & AHCI_CAP_SSNTF) 1450 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1451 else if (ch->fbs_enabled) { 1452 u_int8_t *fis = ch->dma.rfis + 0x58; 1453 1454 for (i = 0; i < 16; i++) { 1455 if (fis[1] & 0x80) { 1456 fis[1] &= 0x7f; 1457 sntf |= 1 << i; 1458 } 1459 fis += 256; 1460 } 1461 } else { 1462 u_int8_t *fis = ch->dma.rfis + 0x58; 1463 1464 if (fis[1] & 0x80) 1465 sntf = (1 << (fis[1] & 0x0f)); 1466 } 1467 } 1468 /* Process PHY events */ 1469 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1470 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1471 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1472 if (serr) { 1473 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1474 reset = ahci_phy_check_events(dev, serr); 1475 } 1476 } 1477 /* Process cold presence detection events */ 1478 if ((istatus & AHCI_P_IX_CPD) && !reset) 1479 ahci_cpd_check_events(dev); 1480 /* Process command errors */ 1481 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1482 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1483 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1484 >> AHCI_P_CMD_CCS_SHIFT; 1485//device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1486// __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1487// serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1488 port = -1; 1489 if (ch->fbs_enabled) { 1490 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1491 if (fbs & AHCI_P_FBS_SDE) { 1492 port = (fbs & AHCI_P_FBS_DWE) 1493 >> AHCI_P_FBS_DWE_SHIFT; 1494 } else { 1495 for (i = 0; i < 16; i++) { 1496 if (ch->numrslotspd[i] == 0) 1497 continue; 1498 if (port == -1) 1499 port = i; 1500 else if (port != i) { 1501 port = -2; 1502 break; 1503 } 1504 } 1505 } 1506 } 1507 err = ch->rslots & (cstatus | sstatus); 1508 } else { 1509 ccs = 0; 1510 err = 0; 1511 port = -1; 1512 } 1513 /* Complete all successfull commands. */ 1514 ok = ch->rslots & ~(cstatus | sstatus); 1515 for (i = 0; i < ch->numslots; i++) { 1516 if ((ok >> i) & 1) 1517 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1518 } 1519 /* On error, complete the rest of commands with error statuses. */ 1520 if (err) { 1521 if (ch->frozen) { 1522 union ccb *fccb = ch->frozen; 1523 ch->frozen = NULL; 1524 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1525 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1526 xpt_freeze_devq(fccb->ccb_h.path, 1); 1527 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1528 } 1529 xpt_done(fccb); 1530 } 1531 for (i = 0; i < ch->numslots; i++) { 1532 /* XXX: reqests in loading state. */ 1533 if (((err >> i) & 1) == 0) 1534 continue; 1535 if (port >= 0 && 1536 ch->slot[i].ccb->ccb_h.target_id != port) 1537 continue; 1538 if (istatus & AHCI_P_IX_TFE) { 1539 if (port != -2) { 1540 /* Task File Error */ 1541 if (ch->numtslotspd[ 1542 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1543 /* Untagged operation. */ 1544 if (i == ccs) 1545 et = AHCI_ERR_TFE; 1546 else 1547 et = AHCI_ERR_INNOCENT; 1548 } else { 1549 /* Tagged operation. */ 1550 et = AHCI_ERR_NCQ; 1551 } 1552 } else { 1553 et = AHCI_ERR_TFE; 1554 ch->fatalerr = 1; 1555 } 1556 } else if (istatus & AHCI_P_IX_IF) { 1557 if (ch->numtslots == 0 && i != ccs && port != -2) 1558 et = AHCI_ERR_INNOCENT; 1559 else 1560 et = AHCI_ERR_SATA; 1561 } else 1562 et = AHCI_ERR_INVALID; 1563 ahci_end_transaction(&ch->slot[i], et); 1564 } 1565 /* 1566 * We can't reinit port if there are some other 1567 * commands active, use resume to complete them. 1568 */ 1569 if (ch->rslots != 0 && !ch->recoverycmd) 1570 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1571 } 1572 /* Process NOTIFY events */ 1573 if (sntf) 1574 ahci_notify_events(dev, sntf); 1575} 1576 1577/* Must be called with channel locked. */ 1578static int 1579ahci_check_collision(device_t dev, union ccb *ccb) 1580{ 1581 struct ahci_channel *ch = device_get_softc(dev); 1582 int t = ccb->ccb_h.target_id; 1583 1584 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1585 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1586 /* Tagged command while we have no supported tag free. */ 1587 if (((~ch->oslots) & (0xffffffff >> (32 - 1588 ch->curr[t].tags))) == 0) 1589 return (1); 1590 /* If we have FBS */ 1591 if (ch->fbs_enabled) { 1592 /* Tagged command while untagged are active. */ 1593 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1594 return (1); 1595 } else { 1596 /* Tagged command while untagged are active. */ 1597 if (ch->numrslots != 0 && ch->numtslots == 0) 1598 return (1); 1599 /* Tagged command while tagged to other target is active. */ 1600 if (ch->numtslots != 0 && 1601 ch->taggedtarget != ccb->ccb_h.target_id) 1602 return (1); 1603 } 1604 } else { 1605 /* If we have FBS */ 1606 if (ch->fbs_enabled) { 1607 /* Untagged command while tagged are active. */ 1608 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1609 return (1); 1610 } else { 1611 /* Untagged command while tagged are active. */ 1612 if (ch->numrslots != 0 && ch->numtslots != 0) 1613 return (1); 1614 } 1615 } 1616 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1617 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1618 /* Atomic command while anything active. */ 1619 if (ch->numrslots != 0) 1620 return (1); 1621 } 1622 /* We have some atomic command running. */ 1623 if (ch->aslots != 0) 1624 return (1); 1625 return (0); 1626} 1627 1628/* Must be called with channel locked. */ 1629static void 1630ahci_begin_transaction(device_t dev, union ccb *ccb) 1631{ 1632 struct ahci_channel *ch = device_get_softc(dev); 1633 struct ahci_slot *slot; 1634 int tag, tags; 1635 1636 /* Choose empty slot. */ 1637 tags = ch->numslots; 1638 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1639 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1640 tags = ch->curr[ccb->ccb_h.target_id].tags; 1641 tag = ch->lastslot; 1642 while (1) { 1643 if (tag >= tags) 1644 tag = 0; 1645 if (ch->slot[tag].state == AHCI_SLOT_EMPTY) 1646 break; 1647 tag++; 1648 }; 1649 ch->lastslot = tag; 1650 /* Occupy chosen slot. */ 1651 slot = &ch->slot[tag]; 1652 slot->ccb = ccb; 1653 /* Stop PM timer. */ 1654 if (ch->numrslots == 0 && ch->pm_level > 3) 1655 callout_stop(&ch->pm_timer); 1656 /* Update channel stats. */ 1657 ch->oslots |= (1 << slot->slot); 1658 ch->numrslots++; 1659 ch->numrslotspd[ccb->ccb_h.target_id]++; 1660 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1661 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1662 ch->numtslots++; 1663 ch->numtslotspd[ccb->ccb_h.target_id]++; 1664 ch->taggedtarget = ccb->ccb_h.target_id; 1665 } 1666 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1667 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1668 ch->aslots |= (1 << slot->slot); 1669 slot->dma.nsegs = 0; 1670 /* If request moves data, setup and load SG list */ 1671 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1672 void *buf; 1673 bus_size_t size; 1674 1675 slot->state = AHCI_SLOT_LOADING; 1676 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1677 buf = ccb->ataio.data_ptr; 1678 size = ccb->ataio.dxfer_len; 1679 } else { 1680 buf = ccb->csio.data_ptr; 1681 size = ccb->csio.dxfer_len; 1682 } 1683 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1684 buf, size, ahci_dmasetprd, slot, 0); 1685 } else 1686 ahci_execute_transaction(slot); 1687} 1688 1689/* Locked by busdma engine. */ 1690static void 1691ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1692{ 1693 struct ahci_slot *slot = arg; 1694 struct ahci_channel *ch = device_get_softc(slot->dev); 1695 struct ahci_cmd_tab *ctp; 1696 struct ahci_dma_prd *prd; 1697 int i; 1698 1699 if (error) { 1700 device_printf(slot->dev, "DMA load error\n"); 1701 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1702 return; 1703 } 1704 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1705 /* Get a piece of the workspace for this request */ 1706 ctp = (struct ahci_cmd_tab *) 1707 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1708 /* Fill S/G table */ 1709 prd = &ctp->prd_tab[0]; 1710 for (i = 0; i < nsegs; i++) { 1711 prd[i].dba = htole64(segs[i].ds_addr); 1712 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1713 } 1714 slot->dma.nsegs = nsegs; 1715 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1716 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1717 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1718 ahci_execute_transaction(slot); 1719} 1720 1721/* Must be called with channel locked. */ 1722static void 1723ahci_execute_transaction(struct ahci_slot *slot) 1724{ 1725 device_t dev = slot->dev; 1726 struct ahci_channel *ch = device_get_softc(dev); 1727 struct ahci_cmd_tab *ctp; 1728 struct ahci_cmd_list *clp; 1729 union ccb *ccb = slot->ccb; 1730 int port = ccb->ccb_h.target_id & 0x0f; 1731 int fis_size, i, softreset; 1732 uint8_t *fis = ch->dma.rfis + 0x40; 1733 uint8_t val; 1734 1735 /* Get a piece of the workspace for this request */ 1736 ctp = (struct ahci_cmd_tab *) 1737 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1738 /* Setup the FIS for this request */ 1739 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) { 1740 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1741 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1742 return; 1743 } 1744 /* Setup the command list entry */ 1745 clp = (struct ahci_cmd_list *) 1746 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1747 clp->cmd_flags = htole16( 1748 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1749 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1750 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1751 (fis_size / sizeof(u_int32_t)) | 1752 (port << 12)); 1753 clp->prd_length = htole16(slot->dma.nsegs); 1754 /* Special handling for Soft Reset command. */ 1755 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1756 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1757 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1758 softreset = 1; 1759 /* Kick controller into sane state */ 1760 ahci_stop(dev); 1761 ahci_clo(dev); 1762 ahci_start(dev, 0); 1763 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1764 } else { 1765 softreset = 2; 1766 /* Prepare FIS receive area for check. */ 1767 for (i = 0; i < 20; i++) 1768 fis[i] = 0xff; 1769 } 1770 } else 1771 softreset = 0; 1772 clp->bytecount = 0; 1773 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1774 (AHCI_CT_SIZE * slot->slot)); 1775 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1776 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1777 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1778 BUS_DMASYNC_PREREAD); 1779 /* Set ACTIVE bit for NCQ commands. */ 1780 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1781 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1782 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1783 } 1784 /* If FBS is enabled, set PMP port. */ 1785 if (ch->fbs_enabled) { 1786 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1787 (port << AHCI_P_FBS_DEV_SHIFT)); 1788 } 1789 /* Issue command to the controller. */ 1790 slot->state = AHCI_SLOT_RUNNING; 1791 ch->rslots |= (1 << slot->slot); 1792 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1793 /* Device reset commands doesn't interrupt. Poll them. */ 1794 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1795 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) { 1796 int count, timeout = ccb->ccb_h.timeout * 100; 1797 enum ahci_err_type et = AHCI_ERR_NONE; 1798 1799 for (count = 0; count < timeout; count++) { 1800 DELAY(10); 1801 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1802 break; 1803 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) && 1804 softreset != 1) { 1805#if 0 1806 device_printf(ch->dev, 1807 "Poll error on slot %d, TFD: %04x\n", 1808 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1809#endif 1810 et = AHCI_ERR_TFE; 1811 break; 1812 } 1813 /* Workaround for ATI SB600/SB700 chipsets. */ 1814 if (ccb->ccb_h.target_id == 15 && 1815 pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1816 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1817 et = AHCI_ERR_TIMEOUT; 1818 break; 1819 } 1820 } 1821 1822 /* Marvell controllers do not wait for readyness. */ 1823 if ((ch->quirks & AHCI_Q_NOBSYRES) && softreset == 2 && 1824 et == AHCI_ERR_NONE) { 1825 while ((val = fis[2]) & ATA_S_BUSY) { 1826 DELAY(10); 1827 if (count++ >= timeout) 1828 break; 1829 } 1830 } 1831 1832 if (timeout && (count >= timeout)) { 1833 device_printf(dev, "Poll timeout on slot %d port %d\n", 1834 slot->slot, port); 1835 device_printf(dev, "is %08x cs %08x ss %08x " 1836 "rs %08x tfd %02x serr %08x cmd %08x\n", 1837 ATA_INL(ch->r_mem, AHCI_P_IS), 1838 ATA_INL(ch->r_mem, AHCI_P_CI), 1839 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1840 ATA_INL(ch->r_mem, AHCI_P_TFD), 1841 ATA_INL(ch->r_mem, AHCI_P_SERR), 1842 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1843 et = AHCI_ERR_TIMEOUT; 1844 } 1845 1846 /* Kick controller into sane state and enable FBS. */ 1847 if (softreset == 2) 1848 ch->eslots |= (1 << slot->slot); 1849 ahci_end_transaction(slot, et); 1850 return; 1851 } 1852 /* Start command execution timeout */ 1853 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 1854 (timeout_t*)ahci_timeout, slot); 1855 return; 1856} 1857 1858/* Must be called with channel locked. */ 1859static void 1860ahci_process_timeout(device_t dev) 1861{ 1862 struct ahci_channel *ch = device_get_softc(dev); 1863 int i; 1864 1865 mtx_assert(&ch->mtx, MA_OWNED); 1866 /* Handle the rest of commands. */ 1867 for (i = 0; i < ch->numslots; i++) { 1868 /* Do we have a running request on slot? */ 1869 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1870 continue; 1871 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 1872 } 1873} 1874 1875/* Must be called with channel locked. */ 1876static void 1877ahci_rearm_timeout(device_t dev) 1878{ 1879 struct ahci_channel *ch = device_get_softc(dev); 1880 int i; 1881 1882 mtx_assert(&ch->mtx, MA_OWNED); 1883 for (i = 0; i < ch->numslots; i++) { 1884 struct ahci_slot *slot = &ch->slot[i]; 1885 1886 /* Do we have a running request on slot? */ 1887 if (slot->state < AHCI_SLOT_RUNNING) 1888 continue; 1889 if ((ch->toslots & (1 << i)) == 0) 1890 continue; 1891 callout_reset(&slot->timeout, 1892 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1893 (timeout_t*)ahci_timeout, slot); 1894 } 1895} 1896 1897/* Locked by callout mechanism. */ 1898static void 1899ahci_timeout(struct ahci_slot *slot) 1900{ 1901 device_t dev = slot->dev; 1902 struct ahci_channel *ch = device_get_softc(dev); 1903 uint32_t sstatus; 1904 int ccs; 1905 int i; 1906 1907 /* Check for stale timeout. */ 1908 if (slot->state < AHCI_SLOT_RUNNING) 1909 return; 1910 1911 /* Check if slot was not being executed last time we checked. */ 1912 if (slot->state < AHCI_SLOT_EXECUTING) { 1913 /* Check if slot started executing. */ 1914 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1915 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1916 >> AHCI_P_CMD_CCS_SHIFT; 1917 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 1918 ch->fbs_enabled || ch->wrongccs) 1919 slot->state = AHCI_SLOT_EXECUTING; 1920 else if ((ch->rslots & (1 << ccs)) == 0) { 1921 ch->wrongccs = 1; 1922 slot->state = AHCI_SLOT_EXECUTING; 1923 } 1924 1925 callout_reset(&slot->timeout, 1926 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1927 (timeout_t*)ahci_timeout, slot); 1928 return; 1929 } 1930 1931 device_printf(dev, "Timeout on slot %d port %d\n", 1932 slot->slot, slot->ccb->ccb_h.target_id & 0x0f); 1933 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x " 1934 "serr %08x cmd %08x\n", 1935 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1936 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1937 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR), 1938 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1939 1940 /* Handle frozen command. */ 1941 if (ch->frozen) { 1942 union ccb *fccb = ch->frozen; 1943 ch->frozen = NULL; 1944 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1945 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1946 xpt_freeze_devq(fccb->ccb_h.path, 1); 1947 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1948 } 1949 xpt_done(fccb); 1950 } 1951 if (!ch->fbs_enabled && !ch->wrongccs) { 1952 /* Without FBS we know real timeout source. */ 1953 ch->fatalerr = 1; 1954 /* Handle command with timeout. */ 1955 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 1956 /* Handle the rest of commands. */ 1957 for (i = 0; i < ch->numslots; i++) { 1958 /* Do we have a running request on slot? */ 1959 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1960 continue; 1961 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1962 } 1963 } else { 1964 /* With FBS we wait for other commands timeout and pray. */ 1965 if (ch->toslots == 0) 1966 xpt_freeze_simq(ch->sim, 1); 1967 ch->toslots |= (1 << slot->slot); 1968 if ((ch->rslots & ~ch->toslots) == 0) 1969 ahci_process_timeout(dev); 1970 else 1971 device_printf(dev, " ... waiting for slots %08x\n", 1972 ch->rslots & ~ch->toslots); 1973 } 1974} 1975 1976/* Must be called with channel locked. */ 1977static void 1978ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 1979{ 1980 device_t dev = slot->dev; 1981 struct ahci_channel *ch = device_get_softc(dev); 1982 union ccb *ccb = slot->ccb; 1983 struct ahci_cmd_list *clp; 1984 int lastto; 1985 uint32_t sig; 1986 1987 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1988 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1989 clp = (struct ahci_cmd_list *) 1990 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1991 /* Read result registers to the result struct 1992 * May be incorrect if several commands finished same time, 1993 * so read only when sure or have to. 1994 */ 1995 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1996 struct ata_res *res = &ccb->ataio.res; 1997 1998 if ((et == AHCI_ERR_TFE) || 1999 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 2000 u_int8_t *fis = ch->dma.rfis + 0x40; 2001 2002 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 2003 BUS_DMASYNC_POSTREAD); 2004 if (ch->fbs_enabled) { 2005 fis += ccb->ccb_h.target_id * 256; 2006 res->status = fis[2]; 2007 res->error = fis[3]; 2008 } else { 2009 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 2010 2011 res->status = tfd; 2012 res->error = tfd >> 8; 2013 } 2014 res->lba_low = fis[4]; 2015 res->lba_mid = fis[5]; 2016 res->lba_high = fis[6]; 2017 res->device = fis[7]; 2018 res->lba_low_exp = fis[8]; 2019 res->lba_mid_exp = fis[9]; 2020 res->lba_high_exp = fis[10]; 2021 res->sector_count = fis[12]; 2022 res->sector_count_exp = fis[13]; 2023 2024 /* 2025 * Some weird controllers do not return signature in 2026 * FIS receive area. Read it from PxSIG register. 2027 */ 2028 if ((ch->quirks & AHCI_Q_ALTSIG) && 2029 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2030 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 2031 sig = ATA_INL(ch->r_mem, AHCI_P_SIG); 2032 res->lba_high = sig >> 24; 2033 res->lba_mid = sig >> 16; 2034 res->lba_low = sig >> 8; 2035 res->sector_count = sig; 2036 } 2037 } else 2038 bzero(res, sizeof(*res)); 2039 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 2040 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2041 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2042 ccb->ataio.resid = 2043 ccb->ataio.dxfer_len - le32toh(clp->bytecount); 2044 } 2045 } else { 2046 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2047 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2048 ccb->csio.resid = 2049 ccb->csio.dxfer_len - le32toh(clp->bytecount); 2050 } 2051 } 2052 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2053 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 2054 (ccb->ccb_h.flags & CAM_DIR_IN) ? 2055 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2056 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 2057 } 2058 if (et != AHCI_ERR_NONE) 2059 ch->eslots |= (1 << slot->slot); 2060 /* In case of error, freeze device for proper recovery. */ 2061 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) && 2062 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 2063 xpt_freeze_devq(ccb->ccb_h.path, 1); 2064 ccb->ccb_h.status |= CAM_DEV_QFRZN; 2065 } 2066 /* Set proper result status. */ 2067 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2068 switch (et) { 2069 case AHCI_ERR_NONE: 2070 ccb->ccb_h.status |= CAM_REQ_CMP; 2071 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 2072 ccb->csio.scsi_status = SCSI_STATUS_OK; 2073 break; 2074 case AHCI_ERR_INVALID: 2075 ch->fatalerr = 1; 2076 ccb->ccb_h.status |= CAM_REQ_INVALID; 2077 break; 2078 case AHCI_ERR_INNOCENT: 2079 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 2080 break; 2081 case AHCI_ERR_TFE: 2082 case AHCI_ERR_NCQ: 2083 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2084 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2085 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2086 } else { 2087 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 2088 } 2089 break; 2090 case AHCI_ERR_SATA: 2091 ch->fatalerr = 1; 2092 if (!ch->recoverycmd) { 2093 xpt_freeze_simq(ch->sim, 1); 2094 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2095 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2096 } 2097 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 2098 break; 2099 case AHCI_ERR_TIMEOUT: 2100 if (!ch->recoverycmd) { 2101 xpt_freeze_simq(ch->sim, 1); 2102 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2103 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2104 } 2105 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 2106 break; 2107 default: 2108 ch->fatalerr = 1; 2109 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 2110 } 2111 /* Free slot. */ 2112 ch->oslots &= ~(1 << slot->slot); 2113 ch->rslots &= ~(1 << slot->slot); 2114 ch->aslots &= ~(1 << slot->slot); 2115 slot->state = AHCI_SLOT_EMPTY; 2116 slot->ccb = NULL; 2117 /* Update channel stats. */ 2118 ch->numrslots--; 2119 ch->numrslotspd[ccb->ccb_h.target_id]--; 2120 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2121 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 2122 ch->numtslots--; 2123 ch->numtslotspd[ccb->ccb_h.target_id]--; 2124 } 2125 /* Cancel timeout state if request completed normally. */ 2126 if (et != AHCI_ERR_TIMEOUT) { 2127 lastto = (ch->toslots == (1 << slot->slot)); 2128 ch->toslots &= ~(1 << slot->slot); 2129 if (lastto) 2130 xpt_release_simq(ch->sim, TRUE); 2131 } 2132 /* If it was first request of reset sequence and there is no error, 2133 * proceed to second request. */ 2134 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2135 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2136 (ccb->ataio.cmd.control & ATA_A_RESET) && 2137 et == AHCI_ERR_NONE) { 2138 ccb->ataio.cmd.control &= ~ATA_A_RESET; 2139 ahci_begin_transaction(dev, ccb); 2140 return; 2141 } 2142 /* If it was our READ LOG command - process it. */ 2143 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 2144 ahci_process_read_log(dev, ccb); 2145 /* If it was our REQUEST SENSE command - process it. */ 2146 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 2147 ahci_process_request_sense(dev, ccb); 2148 /* If it was NCQ or ATAPI command error, put result on hold. */ 2149 } else if (et == AHCI_ERR_NCQ || 2150 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 2151 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 2152 ch->hold[slot->slot] = ccb; 2153 ch->numhslots++; 2154 } else 2155 xpt_done(ccb); 2156 /* If we have no other active commands, ... */ 2157 if (ch->rslots == 0) { 2158 /* if there was fatal error - reset port. */ 2159 if (ch->toslots != 0 || ch->fatalerr) { 2160 ahci_reset(dev); 2161 } else { 2162 /* if we have slots in error, we can reinit port. */ 2163 if (ch->eslots != 0) { 2164 ahci_stop(dev); 2165 ahci_clo(dev); 2166 ahci_start(dev, 1); 2167 } 2168 /* if there commands on hold, we can do READ LOG. */ 2169 if (!ch->recoverycmd && ch->numhslots) 2170 ahci_issue_recovery(dev); 2171 } 2172 /* If all the rest of commands are in timeout - give them chance. */ 2173 } else if ((ch->rslots & ~ch->toslots) == 0 && 2174 et != AHCI_ERR_TIMEOUT) 2175 ahci_rearm_timeout(dev); 2176 /* Unfreeze frozen command. */ 2177 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) { 2178 union ccb *fccb = ch->frozen; 2179 ch->frozen = NULL; 2180 ahci_begin_transaction(dev, fccb); 2181 xpt_release_simq(ch->sim, TRUE); 2182 } 2183 /* Start PM timer. */ 2184 if (ch->numrslots == 0 && ch->pm_level > 3 && 2185 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 2186 callout_schedule(&ch->pm_timer, 2187 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 2188 } 2189} 2190 2191static void 2192ahci_issue_recovery(device_t dev) 2193{ 2194 struct ahci_channel *ch = device_get_softc(dev); 2195 union ccb *ccb; 2196 struct ccb_ataio *ataio; 2197 struct ccb_scsiio *csio; 2198 int i; 2199 2200 /* Find some held command. */ 2201 for (i = 0; i < ch->numslots; i++) { 2202 if (ch->hold[i]) 2203 break; 2204 } 2205 ccb = xpt_alloc_ccb_nowait(); 2206 if (ccb == NULL) { 2207 device_printf(dev, "Unable to allocate recovery command\n"); 2208completeall: 2209 /* We can't do anything -- complete held commands. */ 2210 for (i = 0; i < ch->numslots; i++) { 2211 if (ch->hold[i] == NULL) 2212 continue; 2213 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2214 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 2215 xpt_done(ch->hold[i]); 2216 ch->hold[i] = NULL; 2217 ch->numhslots--; 2218 } 2219 ahci_reset(dev); 2220 return; 2221 } 2222 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 2223 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2224 /* READ LOG */ 2225 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 2226 ccb->ccb_h.func_code = XPT_ATA_IO; 2227 ccb->ccb_h.flags = CAM_DIR_IN; 2228 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2229 ataio = &ccb->ataio; 2230 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 2231 if (ataio->data_ptr == NULL) { 2232 xpt_free_ccb(ccb); 2233 device_printf(dev, 2234 "Unable to allocate memory for READ LOG command\n"); 2235 goto completeall; 2236 } 2237 ataio->dxfer_len = 512; 2238 bzero(&ataio->cmd, sizeof(ataio->cmd)); 2239 ataio->cmd.flags = CAM_ATAIO_48BIT; 2240 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2241 ataio->cmd.sector_count = 1; 2242 ataio->cmd.sector_count_exp = 0; 2243 ataio->cmd.lba_low = 0x10; 2244 ataio->cmd.lba_mid = 0; 2245 ataio->cmd.lba_mid_exp = 0; 2246 } else { 2247 /* REQUEST SENSE */ 2248 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 2249 ccb->ccb_h.recovery_slot = i; 2250 ccb->ccb_h.func_code = XPT_SCSI_IO; 2251 ccb->ccb_h.flags = CAM_DIR_IN; 2252 ccb->ccb_h.status = 0; 2253 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2254 csio = &ccb->csio; 2255 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 2256 csio->dxfer_len = ch->hold[i]->csio.sense_len; 2257 csio->cdb_len = 6; 2258 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 2259 csio->cdb_io.cdb_bytes[0] = 0x03; 2260 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 2261 } 2262 /* Freeze SIM while doing recovery. */ 2263 ch->recoverycmd = 1; 2264 xpt_freeze_simq(ch->sim, 1); 2265 ahci_begin_transaction(dev, ccb); 2266} 2267 2268static void 2269ahci_process_read_log(device_t dev, union ccb *ccb) 2270{ 2271 struct ahci_channel *ch = device_get_softc(dev); 2272 uint8_t *data; 2273 struct ata_res *res; 2274 int i; 2275 2276 ch->recoverycmd = 0; 2277 2278 data = ccb->ataio.data_ptr; 2279 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2280 (data[0] & 0x80) == 0) { 2281 for (i = 0; i < ch->numslots; i++) { 2282 if (!ch->hold[i]) 2283 continue; 2284 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2285 continue; 2286 if ((data[0] & 0x1F) == i) { 2287 res = &ch->hold[i]->ataio.res; 2288 res->status = data[2]; 2289 res->error = data[3]; 2290 res->lba_low = data[4]; 2291 res->lba_mid = data[5]; 2292 res->lba_high = data[6]; 2293 res->device = data[7]; 2294 res->lba_low_exp = data[8]; 2295 res->lba_mid_exp = data[9]; 2296 res->lba_high_exp = data[10]; 2297 res->sector_count = data[12]; 2298 res->sector_count_exp = data[13]; 2299 } else { 2300 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2301 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2302 } 2303 xpt_done(ch->hold[i]); 2304 ch->hold[i] = NULL; 2305 ch->numhslots--; 2306 } 2307 } else { 2308 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2309 device_printf(dev, "Error while READ LOG EXT\n"); 2310 else if ((data[0] & 0x80) == 0) { 2311 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 2312 } 2313 for (i = 0; i < ch->numslots; i++) { 2314 if (!ch->hold[i]) 2315 continue; 2316 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2317 continue; 2318 xpt_done(ch->hold[i]); 2319 ch->hold[i] = NULL; 2320 ch->numhslots--; 2321 } 2322 } 2323 free(ccb->ataio.data_ptr, M_AHCI); 2324 xpt_free_ccb(ccb); 2325 xpt_release_simq(ch->sim, TRUE); 2326} 2327 2328static void 2329ahci_process_request_sense(device_t dev, union ccb *ccb) 2330{ 2331 struct ahci_channel *ch = device_get_softc(dev); 2332 int i; 2333 2334 ch->recoverycmd = 0; 2335 2336 i = ccb->ccb_h.recovery_slot; 2337 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 2338 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 2339 } else { 2340 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2341 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 2342 } 2343 xpt_done(ch->hold[i]); 2344 ch->hold[i] = NULL; 2345 ch->numhslots--; 2346 xpt_free_ccb(ccb); 2347 xpt_release_simq(ch->sim, TRUE); 2348} 2349 2350static void 2351ahci_start(device_t dev, int fbs) 2352{ 2353 struct ahci_channel *ch = device_get_softc(dev); 2354 u_int32_t cmd; 2355 2356 /* Clear SATA error register */ 2357 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2358 /* Clear any interrupts pending on this channel */ 2359 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2360 /* Configure FIS-based switching if supported. */ 2361 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2362 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2363 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2364 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2365 } 2366 /* Start operations on this channel */ 2367 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2368 cmd &= ~AHCI_P_CMD_PMA; 2369 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2370 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2371} 2372 2373static void 2374ahci_stop(device_t dev) 2375{ 2376 struct ahci_channel *ch = device_get_softc(dev); 2377 u_int32_t cmd; 2378 int timeout; 2379 2380 /* Kill all activity on this channel */ 2381 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2382 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2383 /* Wait for activity stop. */ 2384 timeout = 0; 2385 do { 2386 DELAY(10); 2387 if (timeout++ > 50000) { 2388 device_printf(dev, "stopping AHCI engine failed\n"); 2389 break; 2390 } 2391 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2392 ch->eslots = 0; 2393} 2394 2395static void 2396ahci_clo(device_t dev) 2397{ 2398 struct ahci_channel *ch = device_get_softc(dev); 2399 u_int32_t cmd; 2400 int timeout; 2401 2402 /* Issue Command List Override if supported */ 2403 if (ch->caps & AHCI_CAP_SCLO) { 2404 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2405 cmd |= AHCI_P_CMD_CLO; 2406 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2407 timeout = 0; 2408 do { 2409 DELAY(10); 2410 if (timeout++ > 50000) { 2411 device_printf(dev, "executing CLO failed\n"); 2412 break; 2413 } 2414 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2415 } 2416} 2417 2418static void 2419ahci_stop_fr(device_t dev) 2420{ 2421 struct ahci_channel *ch = device_get_softc(dev); 2422 u_int32_t cmd; 2423 int timeout; 2424 2425 /* Kill all FIS reception on this channel */ 2426 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2427 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2428 /* Wait for FIS reception stop. */ 2429 timeout = 0; 2430 do { 2431 DELAY(10); 2432 if (timeout++ > 50000) { 2433 device_printf(dev, "stopping AHCI FR engine failed\n"); 2434 break; 2435 } 2436 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2437} 2438 2439static void 2440ahci_start_fr(device_t dev) 2441{ 2442 struct ahci_channel *ch = device_get_softc(dev); 2443 u_int32_t cmd; 2444 2445 /* Start FIS reception on this channel */ 2446 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2447 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2448} 2449 2450static int 2451ahci_wait_ready(device_t dev, int t, int t0) 2452{ 2453 struct ahci_channel *ch = device_get_softc(dev); 2454 int timeout = 0; 2455 uint32_t val; 2456 2457 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2458 (ATA_S_BUSY | ATA_S_DRQ)) { 2459 if (timeout > t) { 2460 if (t != 0) { 2461 device_printf(dev, 2462 "AHCI reset: device not ready after %dms " 2463 "(tfd = %08x)\n", 2464 MAX(t, 0) + t0, val); 2465 } 2466 return (EBUSY); 2467 } 2468 DELAY(1000); 2469 timeout++; 2470 } 2471 if (bootverbose) 2472 device_printf(dev, "AHCI reset: device ready after %dms\n", 2473 timeout + t0); 2474 return (0); 2475} 2476 2477static void 2478ahci_reset_to(void *arg) 2479{ 2480 device_t dev = arg; 2481 struct ahci_channel *ch = device_get_softc(dev); 2482 2483 if (ch->resetting == 0) 2484 return; 2485 ch->resetting--; 2486 if (ahci_wait_ready(dev, ch->resetting == 0 ? -1 : 0, 2487 (310 - ch->resetting) * 100) == 0) { 2488 ch->resetting = 0; 2489 ahci_start(dev, 1); 2490 xpt_release_simq(ch->sim, TRUE); 2491 return; 2492 } 2493 if (ch->resetting == 0) { 2494 ahci_clo(dev); 2495 ahci_start(dev, 1); 2496 xpt_release_simq(ch->sim, TRUE); 2497 return; 2498 } 2499 callout_schedule(&ch->reset_timer, hz / 10); 2500} 2501 2502static void 2503ahci_reset(device_t dev) 2504{ 2505 struct ahci_channel *ch = device_get_softc(dev); 2506 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2507 int i; 2508 2509 xpt_freeze_simq(ch->sim, 1); 2510 if (bootverbose) 2511 device_printf(dev, "AHCI reset...\n"); 2512 /* Forget about previous reset. */ 2513 if (ch->resetting) { 2514 ch->resetting = 0; 2515 callout_stop(&ch->reset_timer); 2516 xpt_release_simq(ch->sim, TRUE); 2517 } 2518 /* Requeue freezed command. */ 2519 if (ch->frozen) { 2520 union ccb *fccb = ch->frozen; 2521 ch->frozen = NULL; 2522 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2523 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2524 xpt_freeze_devq(fccb->ccb_h.path, 1); 2525 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2526 } 2527 xpt_done(fccb); 2528 } 2529 /* Kill the engine and requeue all running commands. */ 2530 ahci_stop(dev); 2531 for (i = 0; i < ch->numslots; i++) { 2532 /* Do we have a running request on slot? */ 2533 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2534 continue; 2535 /* XXX; Commands in loading state. */ 2536 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2537 } 2538 for (i = 0; i < ch->numslots; i++) { 2539 if (!ch->hold[i]) 2540 continue; 2541 xpt_done(ch->hold[i]); 2542 ch->hold[i] = NULL; 2543 ch->numhslots--; 2544 } 2545 if (ch->toslots != 0) 2546 xpt_release_simq(ch->sim, TRUE); 2547 ch->eslots = 0; 2548 ch->toslots = 0; 2549 ch->wrongccs = 0; 2550 ch->fatalerr = 0; 2551 /* Tell the XPT about the event */ 2552 xpt_async(AC_BUS_RESET, ch->path, NULL); 2553 /* Disable port interrupts */ 2554 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2555 /* Reset and reconnect PHY, */ 2556 if (!ahci_sata_phy_reset(dev)) { 2557 if (bootverbose) 2558 device_printf(dev, 2559 "AHCI reset: device not found\n"); 2560 ch->devices = 0; 2561 /* Enable wanted port interrupts */ 2562 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2563 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2564 AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2565 xpt_release_simq(ch->sim, TRUE); 2566 return; 2567 } 2568 if (bootverbose) 2569 device_printf(dev, "AHCI reset: device found\n"); 2570 /* Wait for clearing busy status. */ 2571 if (ahci_wait_ready(dev, dumping ? 31000 : 0, 0)) { 2572 if (dumping) 2573 ahci_clo(dev); 2574 else 2575 ch->resetting = 310; 2576 } 2577 ch->devices = 1; 2578 /* Enable wanted port interrupts */ 2579 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2580 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2581 AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2582 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2583 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC | 2584 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2585 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2586 if (ch->resetting) 2587 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, dev); 2588 else { 2589 ahci_start(dev, 1); 2590 xpt_release_simq(ch->sim, TRUE); 2591 } 2592} 2593 2594static int 2595ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2596{ 2597 struct ahci_channel *ch = device_get_softc(dev); 2598 u_int8_t *fis = &ctp->cfis[0]; 2599 2600 bzero(ctp->cfis, 64); 2601 fis[0] = 0x27; /* host to device */ 2602 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2603 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2604 fis[1] |= 0x80; 2605 fis[2] = ATA_PACKET_CMD; 2606 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2607 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2608 fis[3] = ATA_F_DMA; 2609 else { 2610 fis[5] = ccb->csio.dxfer_len; 2611 fis[6] = ccb->csio.dxfer_len >> 8; 2612 } 2613 fis[7] = ATA_D_LBA; 2614 fis[15] = ATA_A_4BIT; 2615 bzero(ctp->acmd, 32); 2616 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2617 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2618 ctp->acmd, ccb->csio.cdb_len); 2619 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2620 fis[1] |= 0x80; 2621 fis[2] = ccb->ataio.cmd.command; 2622 fis[3] = ccb->ataio.cmd.features; 2623 fis[4] = ccb->ataio.cmd.lba_low; 2624 fis[5] = ccb->ataio.cmd.lba_mid; 2625 fis[6] = ccb->ataio.cmd.lba_high; 2626 fis[7] = ccb->ataio.cmd.device; 2627 fis[8] = ccb->ataio.cmd.lba_low_exp; 2628 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2629 fis[10] = ccb->ataio.cmd.lba_high_exp; 2630 fis[11] = ccb->ataio.cmd.features_exp; 2631 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2632 fis[12] = tag << 3; 2633 fis[13] = 0; 2634 } else { 2635 fis[12] = ccb->ataio.cmd.sector_count; 2636 fis[13] = ccb->ataio.cmd.sector_count_exp; 2637 } 2638 fis[15] = ATA_A_4BIT; 2639 } else { 2640 fis[15] = ccb->ataio.cmd.control; 2641 } 2642 return (20); 2643} 2644 2645static int 2646ahci_sata_connect(struct ahci_channel *ch) 2647{ 2648 u_int32_t status; 2649 int timeout, found = 0; 2650 2651 /* Wait up to 100ms for "connect well" */ 2652 for (timeout = 0; timeout < 1000 ; timeout++) { 2653 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2654 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 2655 found = 1; 2656 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2657 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2658 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2659 break; 2660 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2661 if (bootverbose) { 2662 device_printf(ch->dev, "SATA offline status=%08x\n", 2663 status); 2664 } 2665 return (0); 2666 } 2667 if (found == 0 && timeout >= 100) 2668 break; 2669 DELAY(100); 2670 } 2671 if (timeout >= 1000 || !found) { 2672 if (bootverbose) { 2673 device_printf(ch->dev, 2674 "SATA connect timeout time=%dus status=%08x\n", 2675 timeout * 100, status); 2676 } 2677 return (0); 2678 } 2679 if (bootverbose) { 2680 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2681 timeout * 100, status); 2682 } 2683 /* Clear SATA error register */ 2684 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2685 return (1); 2686} 2687 2688static int 2689ahci_sata_phy_reset(device_t dev) 2690{ 2691 struct ahci_channel *ch = device_get_softc(dev); 2692 int sata_rev; 2693 uint32_t val; 2694 2695 if (ch->listening) { 2696 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2697 val |= AHCI_P_CMD_SUD; 2698 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2699 ch->listening = 0; 2700 } 2701 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2702 if (sata_rev == 1) 2703 val = ATA_SC_SPD_SPEED_GEN1; 2704 else if (sata_rev == 2) 2705 val = ATA_SC_SPD_SPEED_GEN2; 2706 else if (sata_rev == 3) 2707 val = ATA_SC_SPD_SPEED_GEN3; 2708 else 2709 val = 0; 2710 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2711 ATA_SC_DET_RESET | val | 2712 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2713 DELAY(1000); 2714 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2715 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2716 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2717 if (!ahci_sata_connect(ch)) { 2718 if (ch->caps & AHCI_CAP_SSS) { 2719 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2720 val &= ~AHCI_P_CMD_SUD; 2721 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2722 ch->listening = 1; 2723 } else if (ch->pm_level > 0) 2724 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2725 return (0); 2726 } 2727 return (1); 2728} 2729 2730static int 2731ahci_check_ids(device_t dev, union ccb *ccb) 2732{ 2733 struct ahci_channel *ch = device_get_softc(dev); 2734 2735 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2736 ccb->ccb_h.status = CAM_TID_INVALID; 2737 xpt_done(ccb); 2738 return (-1); 2739 } 2740 if (ccb->ccb_h.target_lun != 0) { 2741 ccb->ccb_h.status = CAM_LUN_INVALID; 2742 xpt_done(ccb); 2743 return (-1); 2744 } 2745 return (0); 2746} 2747 2748static void 2749ahciaction(struct cam_sim *sim, union ccb *ccb) 2750{ 2751 device_t dev, parent; 2752 struct ahci_channel *ch; 2753 2754 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2755 ccb->ccb_h.func_code)); 2756 2757 ch = (struct ahci_channel *)cam_sim_softc(sim); 2758 dev = ch->dev; 2759 switch (ccb->ccb_h.func_code) { 2760 /* Common cases first */ 2761 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2762 case XPT_SCSI_IO: 2763 if (ahci_check_ids(dev, ccb)) 2764 return; 2765 if (ch->devices == 0 || 2766 (ch->pm_present == 0 && 2767 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2768 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2769 break; 2770 } 2771 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2772 /* Check for command collision. */ 2773 if (ahci_check_collision(dev, ccb)) { 2774 /* Freeze command. */ 2775 ch->frozen = ccb; 2776 /* We have only one frozen slot, so freeze simq also. */ 2777 xpt_freeze_simq(ch->sim, 1); 2778 return; 2779 } 2780 ahci_begin_transaction(dev, ccb); 2781 return; 2782 case XPT_EN_LUN: /* Enable LUN as a target */ 2783 case XPT_TARGET_IO: /* Execute target I/O request */ 2784 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2785 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2786 case XPT_ABORT: /* Abort the specified CCB */ 2787 /* XXX Implement */ 2788 ccb->ccb_h.status = CAM_REQ_INVALID; 2789 break; 2790 case XPT_SET_TRAN_SETTINGS: 2791 { 2792 struct ccb_trans_settings *cts = &ccb->cts; 2793 struct ahci_device *d; 2794 2795 if (ahci_check_ids(dev, ccb)) 2796 return; 2797 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2798 d = &ch->curr[ccb->ccb_h.target_id]; 2799 else 2800 d = &ch->user[ccb->ccb_h.target_id]; 2801 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2802 d->revision = cts->xport_specific.sata.revision; 2803 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2804 d->mode = cts->xport_specific.sata.mode; 2805 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2806 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2807 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2808 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2809 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2810 ch->pm_present = cts->xport_specific.sata.pm_present; 2811 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2812 d->atapi = cts->xport_specific.sata.atapi; 2813 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2814 d->caps = cts->xport_specific.sata.caps; 2815 ccb->ccb_h.status = CAM_REQ_CMP; 2816 break; 2817 } 2818 case XPT_GET_TRAN_SETTINGS: 2819 /* Get default/user set transfer settings for the target */ 2820 { 2821 struct ccb_trans_settings *cts = &ccb->cts; 2822 struct ahci_device *d; 2823 uint32_t status; 2824 2825 if (ahci_check_ids(dev, ccb)) 2826 return; 2827 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2828 d = &ch->curr[ccb->ccb_h.target_id]; 2829 else 2830 d = &ch->user[ccb->ccb_h.target_id]; 2831 cts->protocol = PROTO_UNSPECIFIED; 2832 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2833 cts->transport = XPORT_SATA; 2834 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2835 cts->proto_specific.valid = 0; 2836 cts->xport_specific.sata.valid = 0; 2837 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2838 (ccb->ccb_h.target_id == 15 || 2839 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2840 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2841 if (status & 0x0f0) { 2842 cts->xport_specific.sata.revision = 2843 (status & 0x0f0) >> 4; 2844 cts->xport_specific.sata.valid |= 2845 CTS_SATA_VALID_REVISION; 2846 } 2847 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2848 if (ch->pm_level) { 2849 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 2850 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2851 if (ch->caps2 & AHCI_CAP2_APST) 2852 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 2853 } 2854 if ((ch->caps & AHCI_CAP_SNCQ) && 2855 (ch->quirks & AHCI_Q_NOAA) == 0) 2856 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 2857 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 2858 cts->xport_specific.sata.caps &= 2859 ch->user[ccb->ccb_h.target_id].caps; 2860 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2861 } else { 2862 cts->xport_specific.sata.revision = d->revision; 2863 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2864 cts->xport_specific.sata.caps = d->caps; 2865 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2866 } 2867 cts->xport_specific.sata.mode = d->mode; 2868 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2869 cts->xport_specific.sata.bytecount = d->bytecount; 2870 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2871 cts->xport_specific.sata.pm_present = ch->pm_present; 2872 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2873 cts->xport_specific.sata.tags = d->tags; 2874 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2875 cts->xport_specific.sata.atapi = d->atapi; 2876 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2877 ccb->ccb_h.status = CAM_REQ_CMP; 2878 break; 2879 } 2880 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2881 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2882 ahci_reset(dev); 2883 ccb->ccb_h.status = CAM_REQ_CMP; 2884 break; 2885 case XPT_TERM_IO: /* Terminate the I/O process */ 2886 /* XXX Implement */ 2887 ccb->ccb_h.status = CAM_REQ_INVALID; 2888 break; 2889 case XPT_PATH_INQ: /* Path routing inquiry */ 2890 { 2891 struct ccb_pathinq *cpi = &ccb->cpi; 2892 2893 parent = device_get_parent(dev); 2894 cpi->version_num = 1; /* XXX??? */ 2895 cpi->hba_inquiry = PI_SDTR_ABLE; 2896 if (ch->caps & AHCI_CAP_SNCQ) 2897 cpi->hba_inquiry |= PI_TAG_ABLE; 2898 if (ch->caps & AHCI_CAP_SPM) 2899 cpi->hba_inquiry |= PI_SATAPM; 2900 cpi->target_sprt = 0; 2901 cpi->hba_misc = PIM_SEQSCAN; 2902 cpi->hba_eng_cnt = 0; 2903 if (ch->caps & AHCI_CAP_SPM) 2904 cpi->max_target = 15; 2905 else 2906 cpi->max_target = 0; 2907 cpi->max_lun = 0; 2908 cpi->initiator_id = 0; 2909 cpi->bus_id = cam_sim_bus(sim); 2910 cpi->base_transfer_speed = 150000; 2911 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2912 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2913 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2914 cpi->unit_number = cam_sim_unit(sim); 2915 cpi->transport = XPORT_SATA; 2916 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2917 cpi->protocol = PROTO_ATA; 2918 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2919 cpi->maxio = MAXPHYS; 2920 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2921 if (pci_get_devid(parent) == 0x43801002) 2922 cpi->maxio = min(cpi->maxio, 128 * 512); 2923 cpi->hba_vendor = pci_get_vendor(parent); 2924 cpi->hba_device = pci_get_device(parent); 2925 cpi->hba_subvendor = pci_get_subvendor(parent); 2926 cpi->hba_subdevice = pci_get_subdevice(parent); 2927 cpi->ccb_h.status = CAM_REQ_CMP; 2928 break; 2929 } 2930 default: 2931 ccb->ccb_h.status = CAM_REQ_INVALID; 2932 break; 2933 } 2934 xpt_done(ccb); 2935} 2936 2937static void 2938ahcipoll(struct cam_sim *sim) 2939{ 2940 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2941 2942 ahci_ch_intr(ch->dev); 2943 if (ch->resetting != 0 && 2944 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 2945 ch->resetpolldiv = 1000; 2946 ahci_reset_to(ch->dev); 2947 } 2948} 2949