ahci_generic.c revision 199176
1/*- 2 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ahci/ahci.c 199176 2009-11-11 10:44:09Z mav $"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/ata.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/malloc.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <sys/sema.h> 41#include <sys/taskqueue.h> 42#include <vm/uma.h> 43#include <machine/stdarg.h> 44#include <machine/resource.h> 45#include <machine/bus.h> 46#include <sys/rman.h> 47#include <dev/pci/pcivar.h> 48#include <dev/pci/pcireg.h> 49#include "ahci.h" 50 51#include <cam/cam.h> 52#include <cam/cam_ccb.h> 53#include <cam/cam_sim.h> 54#include <cam/cam_xpt_sim.h> 55#include <cam/cam_xpt_periph.h> 56#include <cam/cam_debug.h> 57 58/* local prototypes */ 59static int ahci_setup_interrupt(device_t dev); 60static void ahci_intr(void *data); 61static void ahci_intr_one(void *data); 62static int ahci_suspend(device_t dev); 63static int ahci_resume(device_t dev); 64static int ahci_ch_suspend(device_t dev); 65static int ahci_ch_resume(device_t dev); 66static void ahci_ch_pm(void *arg); 67static void ahci_ch_intr_locked(void *data); 68static void ahci_ch_intr(void *data); 69static int ahci_ctlr_reset(device_t dev); 70static void ahci_begin_transaction(device_t dev, union ccb *ccb); 71static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 72static void ahci_execute_transaction(struct ahci_slot *slot); 73static void ahci_timeout(struct ahci_slot *slot); 74static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 75static int ahci_setup_fis(struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 76static void ahci_dmainit(device_t dev); 77static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 78static void ahci_dmafini(device_t dev); 79static void ahci_slotsalloc(device_t dev); 80static void ahci_slotsfree(device_t dev); 81static void ahci_reset(device_t dev); 82static void ahci_start(device_t dev); 83static void ahci_stop(device_t dev); 84static void ahci_clo(device_t dev); 85static void ahci_start_fr(device_t dev); 86static void ahci_stop_fr(device_t dev); 87 88static int ahci_sata_connect(struct ahci_channel *ch); 89static int ahci_sata_phy_reset(device_t dev, int quick); 90 91static void ahci_issue_read_log(device_t dev); 92static void ahci_process_read_log(device_t dev, union ccb *ccb); 93 94static void ahciaction(struct cam_sim *sim, union ccb *ccb); 95static void ahcipoll(struct cam_sim *sim); 96 97MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 98 99static struct { 100 uint32_t id; 101 const char *name; 102 int flags; 103} ahci_ids[] = { 104 {0x43801002, "ATI IXP600", 0}, 105 {0x43901002, "ATI IXP700", 0}, 106 {0x43911002, "ATI IXP700", 0}, 107 {0x43921002, "ATI IXP700", 0}, 108 {0x43931002, "ATI IXP700", 0}, 109 {0x43941002, "ATI IXP800", 0}, 110 {0x43951002, "ATI IXP800", 0}, 111 {0x26528086, "Intel ICH6", 0}, 112 {0x26538086, "Intel ICH6M", 0}, 113 {0x26818086, "Intel ESB2", 0}, 114 {0x26828086, "Intel ESB2", 0}, 115 {0x26838086, "Intel ESB2", 0}, 116 {0x27c18086, "Intel ICH7", 0}, 117 {0x27c38086, "Intel ICH7", 0}, 118 {0x27c58086, "Intel ICH7M", 0}, 119 {0x27c68086, "Intel ICH7M", 0}, 120 {0x28218086, "Intel ICH8", 0}, 121 {0x28228086, "Intel ICH8", 0}, 122 {0x28248086, "Intel ICH8", 0}, 123 {0x28298086, "Intel ICH8M", 0}, 124 {0x282a8086, "Intel ICH8M", 0}, 125 {0x29228086, "Intel ICH9", 0}, 126 {0x29238086, "Intel ICH9", 0}, 127 {0x29248086, "Intel ICH9", 0}, 128 {0x29258086, "Intel ICH9", 0}, 129 {0x29278086, "Intel ICH9", 0}, 130 {0x29298086, "Intel ICH9M", 0}, 131 {0x292a8086, "Intel ICH9M", 0}, 132 {0x292b8086, "Intel ICH9M", 0}, 133 {0x292c8086, "Intel ICH9M", 0}, 134 {0x292f8086, "Intel ICH9M", 0}, 135 {0x294d8086, "Intel ICH9", 0}, 136 {0x294e8086, "Intel ICH9M", 0}, 137 {0x3a058086, "Intel ICH10", 0}, 138 {0x3a228086, "Intel ICH10", 0}, 139 {0x3a258086, "Intel ICH10", 0}, 140 {0x3b228086, "Intel PCH", 0}, 141 {0x3b238086, "Intel PCH", 0}, 142 {0x3b248086, "Intel PCH", 0}, 143 {0x3b258086, "Intel PCH", 0}, 144 {0x3b298086, "Intel PCH", 0}, 145 {0x3b2b8086, "Intel PCH", 0}, 146 {0x3b2c8086, "Intel PCH", 0}, 147 {0x3b2f8086, "Intel PCH", 0}, 148 {0x044c10de, "NVIDIA MCP65", 0}, 149 {0x044d10de, "NVIDIA MCP65", 0}, 150 {0x044e10de, "NVIDIA MCP65", 0}, 151 {0x044f10de, "NVIDIA MCP65", 0}, 152 {0x045c10de, "NVIDIA MCP65", 0}, 153 {0x045d10de, "NVIDIA MCP65", 0}, 154 {0x045e10de, "NVIDIA MCP65", 0}, 155 {0x045f10de, "NVIDIA MCP65", 0}, 156 {0x055010de, "NVIDIA MCP67", 0}, 157 {0x055110de, "NVIDIA MCP67", 0}, 158 {0x055210de, "NVIDIA MCP67", 0}, 159 {0x055310de, "NVIDIA MCP67", 0}, 160 {0x055410de, "NVIDIA MCP67", 0}, 161 {0x055510de, "NVIDIA MCP67", 0}, 162 {0x055610de, "NVIDIA MCP67", 0}, 163 {0x055710de, "NVIDIA MCP67", 0}, 164 {0x055810de, "NVIDIA MCP67", 0}, 165 {0x055910de, "NVIDIA MCP67", 0}, 166 {0x055A10de, "NVIDIA MCP67", 0}, 167 {0x055B10de, "NVIDIA MCP67", 0}, 168 {0x058410de, "NVIDIA MCP67", 0}, 169 {0x07f010de, "NVIDIA MCP73", 0}, 170 {0x07f110de, "NVIDIA MCP73", 0}, 171 {0x07f210de, "NVIDIA MCP73", 0}, 172 {0x07f310de, "NVIDIA MCP73", 0}, 173 {0x07f410de, "NVIDIA MCP73", 0}, 174 {0x07f510de, "NVIDIA MCP73", 0}, 175 {0x07f610de, "NVIDIA MCP73", 0}, 176 {0x07f710de, "NVIDIA MCP73", 0}, 177 {0x07f810de, "NVIDIA MCP73", 0}, 178 {0x07f910de, "NVIDIA MCP73", 0}, 179 {0x07fa10de, "NVIDIA MCP73", 0}, 180 {0x07fb10de, "NVIDIA MCP73", 0}, 181 {0x0ad010de, "NVIDIA MCP77", 0}, 182 {0x0ad110de, "NVIDIA MCP77", 0}, 183 {0x0ad210de, "NVIDIA MCP77", 0}, 184 {0x0ad310de, "NVIDIA MCP77", 0}, 185 {0x0ad410de, "NVIDIA MCP77", 0}, 186 {0x0ad510de, "NVIDIA MCP77", 0}, 187 {0x0ad610de, "NVIDIA MCP77", 0}, 188 {0x0ad710de, "NVIDIA MCP77", 0}, 189 {0x0ad810de, "NVIDIA MCP77", 0}, 190 {0x0ad910de, "NVIDIA MCP77", 0}, 191 {0x0ada10de, "NVIDIA MCP77", 0}, 192 {0x0adb10de, "NVIDIA MCP77", 0}, 193 {0x0ab410de, "NVIDIA MCP79", 0}, 194 {0x0ab510de, "NVIDIA MCP79", 0}, 195 {0x0ab610de, "NVIDIA MCP79", 0}, 196 {0x0ab710de, "NVIDIA MCP79", 0}, 197 {0x0ab810de, "NVIDIA MCP79", 0}, 198 {0x0ab910de, "NVIDIA MCP79", 0}, 199 {0x0aba10de, "NVIDIA MCP79", 0}, 200 {0x0abb10de, "NVIDIA MCP79", 0}, 201 {0x0abc10de, "NVIDIA MCP79", 0}, 202 {0x0abd10de, "NVIDIA MCP79", 0}, 203 {0x0abe10de, "NVIDIA MCP79", 0}, 204 {0x0abf10de, "NVIDIA MCP79", 0}, 205 {0x0d8410de, "NVIDIA MCP89", 0}, 206 {0x0d8510de, "NVIDIA MCP89", 0}, 207 {0x0d8610de, "NVIDIA MCP89", 0}, 208 {0x0d8710de, "NVIDIA MCP89", 0}, 209 {0x0d8810de, "NVIDIA MCP89", 0}, 210 {0x0d8910de, "NVIDIA MCP89", 0}, 211 {0x0d8a10de, "NVIDIA MCP89", 0}, 212 {0x0d8b10de, "NVIDIA MCP89", 0}, 213 {0x0d8c10de, "NVIDIA MCP89", 0}, 214 {0x0d8d10de, "NVIDIA MCP89", 0}, 215 {0x0d8e10de, "NVIDIA MCP89", 0}, 216 {0x0d8f10de, "NVIDIA MCP89", 0}, 217 {0x33491106, "VIA VT8251", 0}, 218 {0x62871106, "VIA VT8251", 0}, 219 {0x11841039, "SiS 966", 0}, 220 {0x11851039, "SiS 968", 0}, 221 {0x01861039, "SiS 968", 0}, 222 {0, NULL, 0} 223}; 224 225static int 226ahci_probe(device_t dev) 227{ 228 char buf[64]; 229 int i; 230 uint32_t devid = pci_get_devid(dev); 231 232 /* Is this a known AHCI chip? */ 233 for (i = 0; ahci_ids[i].id != 0; i++) { 234 if (ahci_ids[i].id == devid) { 235 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 236 ahci_ids[i].name); 237 device_set_desc_copy(dev, buf); 238 return (BUS_PROBE_VENDOR); 239 } 240 } 241 /* Is this a possible AHCI candidate? */ 242 if (pci_get_class(dev) != PCIC_STORAGE || 243 pci_get_subclass(dev) != PCIS_STORAGE_SATA || 244 pci_get_progif(dev) != PCIP_STORAGE_SATA_AHCI_1_0) 245 return (ENXIO); 246 device_set_desc_copy(dev, "AHCI SATA controller"); 247 return (BUS_PROBE_VENDOR); 248} 249 250static int 251ahci_attach(device_t dev) 252{ 253 struct ahci_controller *ctlr = device_get_softc(dev); 254 device_t child; 255 int error, unit, speed; 256 u_int32_t version; 257 258 ctlr->dev = dev; 259 resource_int_value(device_get_name(dev), 260 device_get_unit(dev), "ccc", &ctlr->ccc); 261 /* if we have a memory BAR(5) we are likely on an AHCI part */ 262 ctlr->r_rid = PCIR_BAR(5); 263 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 264 &ctlr->r_rid, RF_ACTIVE))) 265 return ENXIO; 266 /* Setup our own memory management for channels. */ 267 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 268 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 269 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 270 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 271 return (error); 272 } 273 if ((error = rman_manage_region(&ctlr->sc_iomem, 274 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 275 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 276 rman_fini(&ctlr->sc_iomem); 277 return (error); 278 } 279 /* Reset controller */ 280 if ((error = ahci_ctlr_reset(dev)) != 0) { 281 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 282 rman_fini(&ctlr->sc_iomem); 283 return (error); 284 }; 285 /* Get the number of HW channels */ 286 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 287 ctlr->channels = MAX(flsl(ctlr->ichannels), 288 (ATA_INL(ctlr->r_mem, AHCI_CAP) & AHCI_CAP_NPMASK) + 1); 289 /* Setup interrupts. */ 290 if (ahci_setup_interrupt(dev)) { 291 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 292 rman_fini(&ctlr->sc_iomem); 293 return ENXIO; 294 } 295 /* Announce HW capabilities. */ 296 version = ATA_INL(ctlr->r_mem, AHCI_VS); 297 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 298 if (version >= 0x00010020) 299 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 300 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 301 device_printf(dev, 302 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s\n", 303 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 304 ((version >> 4) & 0xf0) + (version & 0x0f), 305 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 306 ((speed == 1) ? "1.5":((speed == 2) ? "3": 307 ((speed == 3) ? "6":"?"))), 308 (ctlr->caps & AHCI_CAP_SPM) ? 309 "supported" : "not supported"); 310 if (bootverbose) { 311 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 312 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 313 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 314 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 315 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 316 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 317 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 318 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 319 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 320 ((speed == 1) ? "1.5":((speed == 2) ? "3": 321 ((speed == 3) ? "6":"?")))); 322 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 323 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 324 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 325 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 326 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 327 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 328 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 329 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 330 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 331 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 332 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 333 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 334 } 335 if (bootverbose && version >= 0x00010020) { 336 device_printf(dev, "Caps2:%s%s%s\n", 337 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 338 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 339 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 340 } 341 /* Attach all channels on this controller */ 342 for (unit = 0; unit < ctlr->channels; unit++) { 343 if ((ctlr->ichannels & (1 << unit)) == 0) 344 continue; 345 child = device_add_child(dev, "ahcich", -1); 346 if (child == NULL) 347 device_printf(dev, "failed to add channel device\n"); 348 else 349 device_set_ivars(child, (void *)(intptr_t)unit); 350 } 351 bus_generic_attach(dev); 352 return 0; 353} 354 355static int 356ahci_detach(device_t dev) 357{ 358 struct ahci_controller *ctlr = device_get_softc(dev); 359 device_t *children; 360 int nchildren, i; 361 362 /* Detach & delete all children */ 363 if (!device_get_children(dev, &children, &nchildren)) { 364 for (i = 0; i < nchildren; i++) 365 device_delete_child(dev, children[i]); 366 free(children, M_TEMP); 367 } 368 /* Free interrupts. */ 369 for (i = 0; i < ctlr->numirqs; i++) { 370 if (ctlr->irqs[i].r_irq) { 371 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 372 ctlr->irqs[i].handle); 373 bus_release_resource(dev, SYS_RES_IRQ, 374 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 375 } 376 } 377 pci_release_msi(dev); 378 /* Free memory. */ 379 rman_fini(&ctlr->sc_iomem); 380 if (ctlr->r_mem) 381 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 382 return (0); 383} 384 385static int 386ahci_ctlr_reset(device_t dev) 387{ 388 struct ahci_controller *ctlr = device_get_softc(dev); 389 int timeout; 390 391 if (pci_read_config(dev, 0x00, 4) == 0x28298086 && 392 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 393 pci_write_config(dev, 0x92, 0x01, 1); 394 /* Enable AHCI mode */ 395 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 396 /* Reset AHCI controller */ 397 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 398 for (timeout = 1000; timeout > 0; timeout--) { 399 DELAY(1000); 400 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 401 break; 402 } 403 if (timeout == 0) { 404 device_printf(dev, "AHCI controller reset failure\n"); 405 return ENXIO; 406 } 407 /* Reenable AHCI mode */ 408 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 409 /* Clear interrupts */ 410 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 411 /* Configure CCC */ 412 if (ctlr->ccc) { 413 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 414 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 415 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 416 (4 << AHCI_CCCC_CC_SHIFT) | 417 AHCI_CCCC_EN); 418 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 419 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 420 if (bootverbose) { 421 device_printf(dev, 422 "CCC with %dms/4cmd enabled on vector %d\n", 423 ctlr->ccc, ctlr->cccv); 424 } 425 } 426 /* Enable AHCI interrupts */ 427 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 428 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 429 return (0); 430} 431 432static int 433ahci_suspend(device_t dev) 434{ 435 struct ahci_controller *ctlr = device_get_softc(dev); 436 437 bus_generic_suspend(dev); 438 /* Disable interupts, so the state change(s) doesn't trigger */ 439 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 440 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 441 return 0; 442} 443 444static int 445ahci_resume(device_t dev) 446{ 447 int res; 448 449 if ((res = ahci_ctlr_reset(dev)) != 0) 450 return (res); 451 return (bus_generic_resume(dev)); 452} 453 454static int 455ahci_setup_interrupt(device_t dev) 456{ 457 struct ahci_controller *ctlr = device_get_softc(dev); 458 int i, msi = 1; 459 460 /* Process hints. */ 461 resource_int_value(device_get_name(dev), 462 device_get_unit(dev), "msi", &msi); 463 if (msi < 0) 464 msi = 0; 465 else if (msi == 1) 466 msi = min(1, pci_msi_count(dev)); 467 else if (msi > 1) 468 msi = pci_msi_count(dev); 469 /* Allocate MSI if needed/present. */ 470 if (msi && pci_alloc_msi(dev, &msi) == 0) { 471 ctlr->numirqs = msi; 472 } else { 473 msi = 0; 474 ctlr->numirqs = 1; 475 } 476 /* Check for single MSI vector fallback. */ 477 if (ctlr->numirqs > 1 && 478 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 479 device_printf(dev, "Falling back to one MSI\n"); 480 ctlr->numirqs = 1; 481 } 482 /* Allocate all IRQs. */ 483 for (i = 0; i < ctlr->numirqs; i++) { 484 ctlr->irqs[i].ctlr = ctlr; 485 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0); 486 if (ctlr->numirqs == 1 || i >= ctlr->channels || 487 (ctlr->ccc && i == ctlr->cccv)) 488 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 489 else if (i == ctlr->numirqs - 1) 490 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 491 else 492 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 493 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 494 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 495 device_printf(dev, "unable to map interrupt\n"); 496 return ENXIO; 497 } 498 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 499 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr, 500 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 501 /* SOS XXX release r_irq */ 502 device_printf(dev, "unable to setup interrupt\n"); 503 return ENXIO; 504 } 505 } 506 return (0); 507} 508 509/* 510 * Common case interrupt handler. 511 */ 512static void 513ahci_intr(void *data) 514{ 515 struct ahci_controller_irq *irq = data; 516 struct ahci_controller *ctlr = irq->ctlr; 517 u_int32_t is; 518 void *arg; 519 int unit; 520 521 if (irq->mode == AHCI_IRQ_MODE_ALL) { 522 unit = 0; 523 if (ctlr->ccc) 524 is = ctlr->ichannels; 525 else 526 is = ATA_INL(ctlr->r_mem, AHCI_IS); 527 } else { /* AHCI_IRQ_MODE_AFTER */ 528 unit = irq->r_irq_rid - 1; 529 is = ATA_INL(ctlr->r_mem, AHCI_IS); 530 } 531 for (; unit < ctlr->channels; unit++) { 532 if ((is & (1 << unit)) != 0 && 533 (arg = ctlr->interrupt[unit].argument)) { 534 ctlr->interrupt[unit].function(arg); 535 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 536 } 537 } 538} 539 540/* 541 * Simplified interrupt handler for multivector MSI mode. 542 */ 543static void 544ahci_intr_one(void *data) 545{ 546 struct ahci_controller_irq *irq = data; 547 struct ahci_controller *ctlr = irq->ctlr; 548 void *arg; 549 int unit; 550 551 unit = irq->r_irq_rid - 1; 552 if ((arg = ctlr->interrupt[unit].argument)) 553 ctlr->interrupt[unit].function(arg); 554} 555 556static struct resource * 557ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 558 u_long start, u_long end, u_long count, u_int flags) 559{ 560 struct ahci_controller *ctlr = device_get_softc(dev); 561 int unit = ((struct ahci_channel *)device_get_softc(child))->unit; 562 struct resource *res = NULL; 563 int offset = AHCI_OFFSET + (unit << 7); 564 long st; 565 566 switch (type) { 567 case SYS_RES_MEMORY: 568 st = rman_get_start(ctlr->r_mem); 569 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 570 st + offset + 127, 128, RF_ACTIVE, child); 571 if (res) { 572 bus_space_handle_t bsh; 573 bus_space_tag_t bst; 574 bsh = rman_get_bushandle(ctlr->r_mem); 575 bst = rman_get_bustag(ctlr->r_mem); 576 bus_space_subregion(bst, bsh, offset, 128, &bsh); 577 rman_set_bushandle(res, bsh); 578 rman_set_bustag(res, bst); 579 } 580 break; 581 case SYS_RES_IRQ: 582 if (*rid == ATA_IRQ_RID) 583 res = ctlr->irqs[0].r_irq; 584 break; 585 } 586 return (res); 587} 588 589static int 590ahci_release_resource(device_t dev, device_t child, int type, int rid, 591 struct resource *r) 592{ 593 594 switch (type) { 595 case SYS_RES_MEMORY: 596 rman_release_resource(r); 597 return (0); 598 case SYS_RES_IRQ: 599 if (rid != ATA_IRQ_RID) 600 return ENOENT; 601 return (0); 602 } 603 return (EINVAL); 604} 605 606static int 607ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 608 int flags, driver_filter_t *filter, driver_intr_t *function, 609 void *argument, void **cookiep) 610{ 611 struct ahci_controller *ctlr = device_get_softc(dev); 612 int unit = (intptr_t)device_get_ivars(child); 613 614 if (filter != NULL) { 615 printf("ahci.c: we cannot use a filter here\n"); 616 return (EINVAL); 617 } 618 ctlr->interrupt[unit].function = function; 619 ctlr->interrupt[unit].argument = argument; 620 return (0); 621} 622 623static int 624ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 625 void *cookie) 626{ 627 struct ahci_controller *ctlr = device_get_softc(dev); 628 int unit = (intptr_t)device_get_ivars(child); 629 630 ctlr->interrupt[unit].function = NULL; 631 ctlr->interrupt[unit].argument = NULL; 632 return (0); 633} 634 635static int 636ahci_print_child(device_t dev, device_t child) 637{ 638 int retval; 639 640 retval = bus_print_child_header(dev, child); 641 retval += printf(" at channel %d", 642 (int)(intptr_t)device_get_ivars(child)); 643 retval += bus_print_child_footer(dev, child); 644 645 return (retval); 646} 647 648devclass_t ahci_devclass; 649static device_method_t ahci_methods[] = { 650 DEVMETHOD(device_probe, ahci_probe), 651 DEVMETHOD(device_attach, ahci_attach), 652 DEVMETHOD(device_detach, ahci_detach), 653 DEVMETHOD(device_suspend, ahci_suspend), 654 DEVMETHOD(device_resume, ahci_resume), 655 DEVMETHOD(bus_print_child, ahci_print_child), 656 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 657 DEVMETHOD(bus_release_resource, ahci_release_resource), 658 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 659 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 660 { 0, 0 } 661}; 662static driver_t ahci_driver = { 663 "ahci", 664 ahci_methods, 665 sizeof(struct ahci_controller) 666}; 667DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 668MODULE_VERSION(ahci, 1); 669MODULE_DEPEND(ahci, cam, 1, 1, 1); 670 671static int 672ahci_ch_probe(device_t dev) 673{ 674 675 device_set_desc_copy(dev, "AHCI channel"); 676 return (0); 677} 678 679static int 680ahci_ch_attach(device_t dev) 681{ 682 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 683 struct ahci_channel *ch = device_get_softc(dev); 684 struct cam_devq *devq; 685 int rid, error; 686 687 ch->dev = dev; 688 ch->unit = (intptr_t)device_get_ivars(dev); 689 ch->caps = ctlr->caps; 690 ch->caps2 = ctlr->caps2; 691 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 692 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 693 resource_int_value(device_get_name(dev), 694 device_get_unit(dev), "pm_level", &ch->pm_level); 695 if (ch->pm_level > 3) 696 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 697 /* Limit speed for my onboard JMicron external port. 698 * It is not eSATA really. */ 699 if (pci_get_devid(ctlr->dev) == 0x2363197b && 700 pci_get_subvendor(ctlr->dev) == 0x1043 && 701 pci_get_subdevice(ctlr->dev) == 0x81e4 && 702 ch->unit == 0) 703 ch->sata_rev = 1; 704 resource_int_value(device_get_name(dev), 705 device_get_unit(dev), "sata_rev", &ch->sata_rev); 706 rid = ch->unit; 707 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 708 &rid, RF_ACTIVE))) 709 return (ENXIO); 710 ahci_dmainit(dev); 711 ahci_slotsalloc(dev); 712 ahci_ch_resume(dev); 713 mtx_lock(&ch->mtx); 714 rid = ATA_IRQ_RID; 715 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 716 &rid, RF_SHAREABLE | RF_ACTIVE))) { 717 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 718 device_printf(dev, "Unable to map interrupt\n"); 719 return (ENXIO); 720 } 721 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 722 ahci_ch_intr_locked, dev, &ch->ih))) { 723 device_printf(dev, "Unable to setup interrupt\n"); 724 error = ENXIO; 725 goto err1; 726 } 727 /* Create the device queue for our SIM. */ 728 devq = cam_simq_alloc(ch->numslots); 729 if (devq == NULL) { 730 device_printf(dev, "Unable to allocate simq\n"); 731 error = ENOMEM; 732 goto err1; 733 } 734 /* Construct SIM entry */ 735 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 736 device_get_unit(dev), &ch->mtx, ch->numslots, 0, devq); 737 if (ch->sim == NULL) { 738 device_printf(dev, "unable to allocate sim\n"); 739 error = ENOMEM; 740 goto err2; 741 } 742 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 743 device_printf(dev, "unable to register xpt bus\n"); 744 error = ENXIO; 745 goto err2; 746 } 747 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 748 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 749 device_printf(dev, "unable to create path\n"); 750 error = ENXIO; 751 goto err3; 752 } 753 if (ch->pm_level > 3) { 754 callout_reset(&ch->pm_timer, 755 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 756 ahci_ch_pm, dev); 757 } 758 mtx_unlock(&ch->mtx); 759 return (0); 760 761err3: 762 xpt_bus_deregister(cam_sim_path(ch->sim)); 763err2: 764 cam_sim_free(ch->sim, /*free_devq*/TRUE); 765err1: 766 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 767 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 768 mtx_unlock(&ch->mtx); 769 return (error); 770} 771 772static int 773ahci_ch_detach(device_t dev) 774{ 775 struct ahci_channel *ch = device_get_softc(dev); 776 777 mtx_lock(&ch->mtx); 778 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 779 xpt_free_path(ch->path); 780 xpt_bus_deregister(cam_sim_path(ch->sim)); 781 cam_sim_free(ch->sim, /*free_devq*/TRUE); 782 mtx_unlock(&ch->mtx); 783 784 if (ch->pm_level > 3) 785 callout_drain(&ch->pm_timer); 786 bus_teardown_intr(dev, ch->r_irq, ch->ih); 787 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 788 789 ahci_ch_suspend(dev); 790 ahci_slotsfree(dev); 791 ahci_dmafini(dev); 792 793 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 794 mtx_destroy(&ch->mtx); 795 return (0); 796} 797 798static int 799ahci_ch_suspend(device_t dev) 800{ 801 struct ahci_channel *ch = device_get_softc(dev); 802 803 /* Disable port interrupts. */ 804 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 805 /* Reset command register. */ 806 ahci_stop(dev); 807 ahci_stop_fr(dev); 808 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 809 /* Allow everything, including partial and slumber modes. */ 810 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 811 /* Request slumber mode transition and give some time to get there. */ 812 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 813 DELAY(100); 814 /* Disable PHY. */ 815 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 816 return (0); 817} 818 819static int 820ahci_ch_resume(device_t dev) 821{ 822 struct ahci_channel *ch = device_get_softc(dev); 823 uint64_t work; 824 825 /* Disable port interrupts */ 826 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 827 /* Setup work areas */ 828 work = ch->dma.work_bus + AHCI_CL_OFFSET; 829 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 830 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 831 work = ch->dma.rfis_bus; 832 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 833 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 834 /* Activate the channel and power/spin up device */ 835 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 836 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 837 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 838 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 839 ahci_start_fr(dev); 840 ahci_start(dev); 841 return (0); 842} 843 844devclass_t ahcich_devclass; 845static device_method_t ahcich_methods[] = { 846 DEVMETHOD(device_probe, ahci_ch_probe), 847 DEVMETHOD(device_attach, ahci_ch_attach), 848 DEVMETHOD(device_detach, ahci_ch_detach), 849 DEVMETHOD(device_suspend, ahci_ch_suspend), 850 DEVMETHOD(device_resume, ahci_ch_resume), 851 { 0, 0 } 852}; 853static driver_t ahcich_driver = { 854 "ahcich", 855 ahcich_methods, 856 sizeof(struct ahci_channel) 857}; 858DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahci_devclass, 0, 0); 859 860struct ahci_dc_cb_args { 861 bus_addr_t maddr; 862 int error; 863}; 864 865static void 866ahci_dmainit(device_t dev) 867{ 868 struct ahci_channel *ch = device_get_softc(dev); 869 struct ahci_dc_cb_args dcba; 870 871 if (ch->caps & AHCI_CAP_64BIT) 872 ch->dma.max_address = BUS_SPACE_MAXADDR; 873 else 874 ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT; 875 /* Command area. */ 876 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 877 ch->dma.max_address, BUS_SPACE_MAXADDR, 878 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 879 0, NULL, NULL, &ch->dma.work_tag)) 880 goto error; 881 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0, 882 &ch->dma.work_map)) 883 goto error; 884 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 885 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 886 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 887 goto error; 888 } 889 ch->dma.work_bus = dcba.maddr; 890 /* FIS receive area. */ 891 if (bus_dma_tag_create(bus_get_dma_tag(dev), 4096, 0, 892 ch->dma.max_address, BUS_SPACE_MAXADDR, 893 NULL, NULL, 4096, 1, 4096, 894 0, NULL, NULL, &ch->dma.rfis_tag)) 895 goto error; 896 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 897 &ch->dma.rfis_map)) 898 goto error; 899 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 900 4096, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 901 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 902 goto error; 903 } 904 ch->dma.rfis_bus = dcba.maddr; 905 /* Data area. */ 906 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 907 ch->dma.max_address, BUS_SPACE_MAXADDR, 908 NULL, NULL, 909 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 910 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 911 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 912 goto error; 913 } 914 return; 915 916error: 917 device_printf(dev, "WARNING - DMA initialization failed\n"); 918 ahci_dmafini(dev); 919} 920 921static void 922ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 923{ 924 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 925 926 if (!(dcba->error = error)) 927 dcba->maddr = segs[0].ds_addr; 928} 929 930static void 931ahci_dmafini(device_t dev) 932{ 933 struct ahci_channel *ch = device_get_softc(dev); 934 935 if (ch->dma.data_tag) { 936 bus_dma_tag_destroy(ch->dma.data_tag); 937 ch->dma.data_tag = NULL; 938 } 939 if (ch->dma.rfis_bus) { 940 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 941 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 942 ch->dma.rfis_bus = 0; 943 ch->dma.rfis_map = NULL; 944 ch->dma.rfis = NULL; 945 } 946 if (ch->dma.work_bus) { 947 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 948 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 949 ch->dma.work_bus = 0; 950 ch->dma.work_map = NULL; 951 ch->dma.work = NULL; 952 } 953 if (ch->dma.work_tag) { 954 bus_dma_tag_destroy(ch->dma.work_tag); 955 ch->dma.work_tag = NULL; 956 } 957} 958 959static void 960ahci_slotsalloc(device_t dev) 961{ 962 struct ahci_channel *ch = device_get_softc(dev); 963 int i; 964 965 /* Alloc and setup command/dma slots */ 966 bzero(ch->slot, sizeof(ch->slot)); 967 for (i = 0; i < ch->numslots; i++) { 968 struct ahci_slot *slot = &ch->slot[i]; 969 970 slot->dev = dev; 971 slot->slot = i; 972 slot->state = AHCI_SLOT_EMPTY; 973 slot->ccb = NULL; 974 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 975 976 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 977 device_printf(ch->dev, "FAILURE - create data_map\n"); 978 } 979} 980 981static void 982ahci_slotsfree(device_t dev) 983{ 984 struct ahci_channel *ch = device_get_softc(dev); 985 int i; 986 987 /* Free all dma slots */ 988 for (i = 0; i < ch->numslots; i++) { 989 struct ahci_slot *slot = &ch->slot[i]; 990 991 callout_drain(&slot->timeout); 992 if (slot->dma.data_map) { 993 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 994 slot->dma.data_map = NULL; 995 } 996 } 997} 998 999static void 1000ahci_phy_check_events(device_t dev, u_int32_t serr) 1001{ 1002 struct ahci_channel *ch = device_get_softc(dev); 1003 1004 if ((serr & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) { 1005 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1006 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 1007 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 1008 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) { 1009 if (bootverbose) 1010 device_printf(dev, "CONNECT requested\n"); 1011 ahci_reset(dev); 1012 } else { 1013 if (bootverbose) 1014 device_printf(dev, "DISCONNECT requested\n"); 1015 ch->devices = 0; 1016 } 1017 } 1018} 1019 1020static void 1021ahci_notify_events(device_t dev, u_int32_t status) 1022{ 1023 struct ahci_channel *ch = device_get_softc(dev); 1024 struct cam_path *dpath; 1025 int i; 1026 1027 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1028 if (bootverbose) 1029 device_printf(dev, "SNTF 0x%04x\n", status); 1030 for (i = 0; i < 16; i++) { 1031 if ((status & (1 << i)) == 0) 1032 continue; 1033 if (xpt_create_path(&dpath, NULL, 1034 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1035 xpt_async(AC_SCSI_AEN, dpath, NULL); 1036 xpt_free_path(dpath); 1037 } 1038 } 1039} 1040 1041static void 1042ahci_ch_intr_locked(void *data) 1043{ 1044 device_t dev = (device_t)data; 1045 struct ahci_channel *ch = device_get_softc(dev); 1046 1047 mtx_lock(&ch->mtx); 1048 ahci_ch_intr(data); 1049 mtx_unlock(&ch->mtx); 1050} 1051 1052static void 1053ahci_ch_pm(void *arg) 1054{ 1055 device_t dev = (device_t)arg; 1056 struct ahci_channel *ch = device_get_softc(dev); 1057 uint32_t work; 1058 1059 if (ch->numrslots != 0) 1060 return; 1061 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1062 if (ch->pm_level == 4) 1063 work |= AHCI_P_CMD_PARTIAL; 1064 else 1065 work |= AHCI_P_CMD_SLUMBER; 1066 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1067} 1068 1069static void 1070ahci_ch_intr(void *data) 1071{ 1072 device_t dev = (device_t)data; 1073 struct ahci_channel *ch = device_get_softc(dev); 1074 uint32_t istatus, sstatus, cstatus, serr = 0, sntf = 0, ok, err; 1075 enum ahci_err_type et; 1076 int i, ccs, ncq_err = 0; 1077 1078 /* Read and clear interrupt statuses. */ 1079 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1080 if (istatus == 0) 1081 return; 1082 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1083 /* Read command statuses. */ 1084 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1085 cstatus = ATA_INL(ch->r_mem, AHCI_P_CI); 1086 if ((istatus & AHCI_P_IX_SDB) && (ch->caps & AHCI_CAP_SSNTF)) 1087 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1088 /* Process PHY events */ 1089 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1090 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1091 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1092 if (serr) { 1093 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1094 ahci_phy_check_events(dev, serr); 1095 } 1096 } 1097 /* Process command errors */ 1098 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1099 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1100//device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x\n", 1101// __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1102// serr); 1103 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1104 >> AHCI_P_CMD_CCS_SHIFT; 1105 err = ch->rslots & (cstatus | sstatus); 1106 /* Kick controller into sane state */ 1107 ahci_stop(dev); 1108 ahci_start(dev); 1109 } else { 1110 ccs = 0; 1111 err = 0; 1112 } 1113 /* Complete all successfull commands. */ 1114 ok = ch->rslots & ~(cstatus | sstatus); 1115 for (i = 0; i < ch->numslots; i++) { 1116 if ((ok >> i) & 1) 1117 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1118 } 1119 /* On error, complete the rest of commands with error statuses. */ 1120 if (err) { 1121 if (ch->frozen) { 1122 union ccb *fccb = ch->frozen; 1123 ch->frozen = NULL; 1124 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1125 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1126 xpt_freeze_devq(fccb->ccb_h.path, 1); 1127 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1128 } 1129 xpt_done(fccb); 1130 } 1131 for (i = 0; i < ch->numslots; i++) { 1132 /* XXX: reqests in loading state. */ 1133 if (((err >> i) & 1) == 0) 1134 continue; 1135 if (istatus & AHCI_P_IX_TFE) { 1136 /* Task File Error */ 1137 if (ch->numtslots == 0) { 1138 /* Untagged operation. */ 1139 if (i == ccs) 1140 et = AHCI_ERR_TFE; 1141 else 1142 et = AHCI_ERR_INNOCENT; 1143 } else { 1144 /* Tagged operation. */ 1145 et = AHCI_ERR_NCQ; 1146 ncq_err = 1; 1147 } 1148 } else if (istatus & AHCI_P_IX_IF) { 1149 if (ch->numtslots == 0 && i != ccs) 1150 et = AHCI_ERR_INNOCENT; 1151 else 1152 et = AHCI_ERR_SATA; 1153 } else 1154 et = AHCI_ERR_INVALID; 1155 ahci_end_transaction(&ch->slot[i], et); 1156 } 1157 if (ncq_err) 1158 ahci_issue_read_log(dev); 1159 } 1160 /* Process NOTIFY events */ 1161 if (sntf) 1162 ahci_notify_events(dev, sntf); 1163} 1164 1165/* Must be called with channel locked. */ 1166static int 1167ahci_check_collision(device_t dev, union ccb *ccb) 1168{ 1169 struct ahci_channel *ch = device_get_softc(dev); 1170 1171 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1172 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1173 /* Tagged command while untagged are active. */ 1174 if (ch->numrslots != 0 && ch->numtslots == 0) 1175 return (1); 1176 /* Tagged command while tagged to other target is active. */ 1177 if (ch->numtslots != 0 && 1178 ch->taggedtarget != ccb->ccb_h.target_id) 1179 return (1); 1180 } else { 1181 /* Untagged command while tagged are active. */ 1182 if (ch->numrslots != 0 && ch->numtslots != 0) 1183 return (1); 1184 } 1185 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1186 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1187 /* Atomic command while anything active. */ 1188 if (ch->numrslots != 0) 1189 return (1); 1190 } 1191 /* We have some atomic command running. */ 1192 if (ch->aslots != 0) 1193 return (1); 1194 return (0); 1195} 1196 1197/* Must be called with channel locked. */ 1198static void 1199ahci_begin_transaction(device_t dev, union ccb *ccb) 1200{ 1201 struct ahci_channel *ch = device_get_softc(dev); 1202 struct ahci_slot *slot; 1203 int tag; 1204 1205 /* Choose empty slot. */ 1206 tag = ch->lastslot; 1207 while (ch->slot[tag].state != AHCI_SLOT_EMPTY) { 1208 if (++tag >= ch->numslots) 1209 tag = 0; 1210 KASSERT(tag != ch->lastslot, ("ahci: ALL SLOTS BUSY!")); 1211 } 1212 ch->lastslot = tag; 1213 /* Occupy chosen slot. */ 1214 slot = &ch->slot[tag]; 1215 slot->ccb = ccb; 1216 /* Stop PM timer. */ 1217 if (ch->numrslots == 0 && ch->pm_level > 3) 1218 callout_stop(&ch->pm_timer); 1219 /* Update channel stats. */ 1220 ch->numrslots++; 1221 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1222 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1223 ch->numtslots++; 1224 ch->taggedtarget = ccb->ccb_h.target_id; 1225 } 1226 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1227 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1228 ch->aslots |= (1 << slot->slot); 1229 slot->dma.nsegs = 0; 1230 /* If request moves data, setup and load SG list */ 1231 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1232 void *buf; 1233 bus_size_t size; 1234 1235 slot->state = AHCI_SLOT_LOADING; 1236 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1237 buf = ccb->ataio.data_ptr; 1238 size = ccb->ataio.dxfer_len; 1239 } else { 1240 buf = ccb->csio.data_ptr; 1241 size = ccb->csio.dxfer_len; 1242 } 1243 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1244 buf, size, ahci_dmasetprd, slot, 0); 1245 } else 1246 ahci_execute_transaction(slot); 1247} 1248 1249/* Locked by busdma engine. */ 1250static void 1251ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1252{ 1253 struct ahci_slot *slot = arg; 1254 struct ahci_channel *ch = device_get_softc(slot->dev); 1255 struct ahci_cmd_tab *ctp; 1256 struct ahci_dma_prd *prd; 1257 int i; 1258 1259 if (error) { 1260 device_printf(slot->dev, "DMA load error\n"); 1261 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1262 return; 1263 } 1264 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1265 /* Get a piece of the workspace for this request */ 1266 ctp = (struct ahci_cmd_tab *) 1267 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1268 /* Fill S/G table */ 1269 prd = &ctp->prd_tab[0]; 1270 for (i = 0; i < nsegs; i++) { 1271 prd[i].dba = htole64(segs[i].ds_addr); 1272 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1273 } 1274 slot->dma.nsegs = nsegs; 1275 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1276 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1277 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1278 ahci_execute_transaction(slot); 1279} 1280 1281/* Must be called with channel locked. */ 1282static void 1283ahci_execute_transaction(struct ahci_slot *slot) 1284{ 1285 device_t dev = slot->dev; 1286 struct ahci_channel *ch = device_get_softc(dev); 1287 struct ahci_cmd_tab *ctp; 1288 struct ahci_cmd_list *clp; 1289 union ccb *ccb = slot->ccb; 1290 int port = ccb->ccb_h.target_id & 0x0f; 1291 int fis_size; 1292 1293 /* Get a piece of the workspace for this request */ 1294 ctp = (struct ahci_cmd_tab *) 1295 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1296 /* Setup the FIS for this request */ 1297 if (!(fis_size = ahci_setup_fis(ctp, ccb, slot->slot))) { 1298 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1299 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1300 return; 1301 } 1302 /* Setup the command list entry */ 1303 clp = (struct ahci_cmd_list *) 1304 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1305 clp->prd_length = slot->dma.nsegs; 1306 clp->cmd_flags = (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1307 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1308 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1309 (fis_size / sizeof(u_int32_t)) | 1310 (port << 12); 1311 /* Special handling for Soft Reset command. */ 1312 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1313 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1314 (ccb->ataio.cmd.control & ATA_A_RESET)) { 1315 /* Kick controller into sane state */ 1316 ahci_stop(dev); 1317 ahci_clo(dev); 1318 ahci_start(dev); 1319 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1320 } 1321 clp->bytecount = 0; 1322 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1323 (AHCI_CT_SIZE * slot->slot)); 1324 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1325 BUS_DMASYNC_PREWRITE); 1326 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1327 BUS_DMASYNC_PREREAD); 1328 /* Set ACTIVE bit for NCQ commands. */ 1329 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1330 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1331 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1332 } 1333 /* Issue command to the controller. */ 1334 slot->state = AHCI_SLOT_RUNNING; 1335 ch->rslots |= (1 << slot->slot); 1336 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1337 /* Device reset commands doesn't interrupt. Poll them. */ 1338 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1339 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || 1340 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL))) { 1341 int count, timeout = ccb->ccb_h.timeout; 1342 enum ahci_err_type et = AHCI_ERR_NONE; 1343 1344 for (count = 0; count < timeout; count++) { 1345 DELAY(1000); 1346 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1347 break; 1348 if (ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) { 1349 device_printf(ch->dev, 1350 "Poll error on slot %d, TFD: %04x\n", 1351 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1352 et = AHCI_ERR_TFE; 1353 break; 1354 } 1355 /* Workaround for ATI SB600/SB700 chipsets. */ 1356 if (ccb->ccb_h.target_id == 15 && 1357 pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1358 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1359 et = AHCI_ERR_TIMEOUT; 1360 break; 1361 } 1362 } 1363 if (timeout && (count >= timeout)) { 1364 device_printf(ch->dev, 1365 "Poll timeout on slot %d\n", slot->slot); 1366 et = AHCI_ERR_TIMEOUT; 1367 } 1368 if (et != AHCI_ERR_NONE) { 1369 /* Kick controller into sane state */ 1370 ahci_stop(ch->dev); 1371 ahci_start(ch->dev); 1372 } 1373 ahci_end_transaction(slot, et); 1374 return; 1375 } 1376 /* Start command execution timeout */ 1377 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 1378 (timeout_t*)ahci_timeout, slot); 1379 return; 1380} 1381 1382/* Locked by callout mechanism. */ 1383static void 1384ahci_timeout(struct ahci_slot *slot) 1385{ 1386 device_t dev = slot->dev; 1387 struct ahci_channel *ch = device_get_softc(dev); 1388 uint32_t sstatus; 1389 int ccs; 1390 int i; 1391 1392 /* Check for stale timeout. */ 1393 if (slot->state < AHCI_SLOT_RUNNING) 1394 return; 1395 1396 /* Check if slot was not being executed last time we checked. */ 1397 if (slot->state < AHCI_SLOT_EXECUTING) { 1398 /* Check if slot started executing. */ 1399 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1400 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1401 >> AHCI_P_CMD_CCS_SHIFT; 1402 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot) 1403 slot->state = AHCI_SLOT_EXECUTING; 1404 1405 callout_reset(&slot->timeout, 1406 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1407 (timeout_t*)ahci_timeout, slot); 1408 return; 1409 } 1410 1411 device_printf(dev, "Timeout on slot %d\n", slot->slot); 1412 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x\n", 1413 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1414 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1415 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR)); 1416 1417 ch->fatalerr = 1; 1418 /* Handle frozen command. */ 1419 if (ch->frozen) { 1420 union ccb *fccb = ch->frozen; 1421 ch->frozen = NULL; 1422 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1423 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1424 xpt_freeze_devq(fccb->ccb_h.path, 1); 1425 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1426 } 1427 xpt_done(fccb); 1428 } 1429 /* Handle command with timeout. */ 1430 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 1431 /* Handle the rest of commands. */ 1432 for (i = 0; i < ch->numslots; i++) { 1433 /* Do we have a running request on slot? */ 1434 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1435 continue; 1436 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1437 } 1438} 1439 1440/* Must be called with channel locked. */ 1441static void 1442ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 1443{ 1444 device_t dev = slot->dev; 1445 struct ahci_channel *ch = device_get_softc(dev); 1446 union ccb *ccb = slot->ccb; 1447 1448 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1449 BUS_DMASYNC_POSTWRITE); 1450 /* Read result registers to the result struct 1451 * May be incorrect if several commands finished same time, 1452 * so read only when sure or have to. 1453 */ 1454 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1455 struct ata_res *res = &ccb->ataio.res; 1456 1457 if ((et == AHCI_ERR_TFE) || 1458 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1459 u_int8_t *fis = ch->dma.rfis + 0x40; 1460 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 1461 1462 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1463 BUS_DMASYNC_POSTREAD); 1464 res->status = tfd; 1465 res->error = tfd >> 8; 1466 res->lba_low = fis[4]; 1467 res->lba_mid = fis[5]; 1468 res->lba_high = fis[6]; 1469 res->device = fis[7]; 1470 res->lba_low_exp = fis[8]; 1471 res->lba_mid_exp = fis[9]; 1472 res->lba_high_exp = fis[10]; 1473 res->sector_count = fis[12]; 1474 res->sector_count_exp = fis[13]; 1475 } else 1476 bzero(res, sizeof(*res)); 1477 } 1478 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1479 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1480 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1481 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1482 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1483 } 1484 /* In case of error, freeze device for proper recovery. */ 1485 if ((et != AHCI_ERR_NONE) && (!ch->readlog) && 1486 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 1487 xpt_freeze_devq(ccb->ccb_h.path, 1); 1488 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1489 } 1490 /* Set proper result status. */ 1491 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1492 switch (et) { 1493 case AHCI_ERR_NONE: 1494 ccb->ccb_h.status |= CAM_REQ_CMP; 1495 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1496 ccb->csio.scsi_status = SCSI_STATUS_OK; 1497 break; 1498 case AHCI_ERR_INVALID: 1499 ch->fatalerr = 1; 1500 ccb->ccb_h.status |= CAM_REQ_INVALID; 1501 break; 1502 case AHCI_ERR_INNOCENT: 1503 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1504 break; 1505 case AHCI_ERR_TFE: 1506 case AHCI_ERR_NCQ: 1507 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1508 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1509 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1510 } else { 1511 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1512 } 1513 break; 1514 case AHCI_ERR_SATA: 1515 ch->fatalerr = 1; 1516 if (!ch->readlog) { 1517 xpt_freeze_simq(ch->sim, 1); 1518 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1519 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1520 } 1521 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1522 break; 1523 case AHCI_ERR_TIMEOUT: 1524 /* Do no treat soft-reset timeout as fatal here. */ 1525 if (ccb->ccb_h.func_code != XPT_ATA_IO || 1526 !(ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) 1527 ch->fatalerr = 1; 1528 if (!ch->readlog) { 1529 xpt_freeze_simq(ch->sim, 1); 1530 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1531 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1532 } 1533 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1534 break; 1535 default: 1536 ch->fatalerr = 1; 1537 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1538 } 1539 /* Free slot. */ 1540 ch->rslots &= ~(1 << slot->slot); 1541 ch->aslots &= ~(1 << slot->slot); 1542 slot->state = AHCI_SLOT_EMPTY; 1543 slot->ccb = NULL; 1544 /* Update channel stats. */ 1545 ch->numrslots--; 1546 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1547 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1548 ch->numtslots--; 1549 } 1550 /* If it was first request of reset sequence and there is no error, 1551 * proceed to second request. */ 1552 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1553 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1554 (ccb->ataio.cmd.control & ATA_A_RESET) && 1555 et == AHCI_ERR_NONE) { 1556 ccb->ataio.cmd.control &= ~ATA_A_RESET; 1557 ahci_begin_transaction(dev, ccb); 1558 return; 1559 } 1560 /* If it was our READ LOG command - process it. */ 1561 if (ch->readlog) { 1562 ahci_process_read_log(dev, ccb); 1563 /* If it was NCQ command error, put result on hold. */ 1564 } else if (et == AHCI_ERR_NCQ) { 1565 ch->hold[slot->slot] = ccb; 1566 } else 1567 xpt_done(ccb); 1568 /* Unfreeze frozen command. */ 1569 if (ch->frozen && ch->numrslots == 0) { 1570 union ccb *fccb = ch->frozen; 1571 ch->frozen = NULL; 1572 ahci_begin_transaction(dev, fccb); 1573 xpt_release_simq(ch->sim, TRUE); 1574 } 1575 /* If we have no other active commands, ... */ 1576 if (ch->rslots == 0) { 1577 /* if there was fatal error - reset port. */ 1578 if (ch->fatalerr) { 1579 ahci_reset(dev); 1580 } 1581 } 1582 /* Start PM timer. */ 1583 if (ch->numrslots == 0 && ch->pm_level > 3) { 1584 callout_schedule(&ch->pm_timer, 1585 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 1586 } 1587} 1588 1589static void 1590ahci_issue_read_log(device_t dev) 1591{ 1592 struct ahci_channel *ch = device_get_softc(dev); 1593 union ccb *ccb; 1594 struct ccb_ataio *ataio; 1595 int i; 1596 1597 ch->readlog = 1; 1598 /* Find some holden command. */ 1599 for (i = 0; i < ch->numslots; i++) { 1600 if (ch->hold[i]) 1601 break; 1602 } 1603 ccb = xpt_alloc_ccb_nowait(); 1604 if (ccb == NULL) { 1605 device_printf(dev, "Unable allocate READ LOG command"); 1606 return; /* XXX */ 1607 } 1608 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 1609 ccb->ccb_h.func_code = XPT_ATA_IO; 1610 ccb->ccb_h.flags = CAM_DIR_IN; 1611 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1612 ataio = &ccb->ataio; 1613 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 1614 if (ataio->data_ptr == NULL) { 1615 device_printf(dev, "Unable allocate memory for READ LOG command"); 1616 return; /* XXX */ 1617 } 1618 ataio->dxfer_len = 512; 1619 bzero(&ataio->cmd, sizeof(ataio->cmd)); 1620 ataio->cmd.flags = CAM_ATAIO_48BIT; 1621 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 1622 ataio->cmd.sector_count = 1; 1623 ataio->cmd.sector_count_exp = 0; 1624 ataio->cmd.lba_low = 0x10; 1625 ataio->cmd.lba_mid = 0; 1626 ataio->cmd.lba_mid_exp = 0; 1627 /* Freeze SIM while doing READ LOG EXT. */ 1628 xpt_freeze_simq(ch->sim, 1); 1629 ahci_begin_transaction(dev, ccb); 1630} 1631 1632static void 1633ahci_process_read_log(device_t dev, union ccb *ccb) 1634{ 1635 struct ahci_channel *ch = device_get_softc(dev); 1636 uint8_t *data; 1637 struct ata_res *res; 1638 int i; 1639 1640 ch->readlog = 0; 1641 1642 data = ccb->ataio.data_ptr; 1643 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 1644 (data[0] & 0x80) == 0) { 1645 for (i = 0; i < ch->numslots; i++) { 1646 if (!ch->hold[i]) 1647 continue; 1648 if ((data[0] & 0x1F) == i) { 1649 res = &ch->hold[i]->ataio.res; 1650 res->status = data[2]; 1651 res->error = data[3]; 1652 res->lba_low = data[4]; 1653 res->lba_mid = data[5]; 1654 res->lba_high = data[6]; 1655 res->device = data[7]; 1656 res->lba_low_exp = data[8]; 1657 res->lba_mid_exp = data[9]; 1658 res->lba_high_exp = data[10]; 1659 res->sector_count = data[12]; 1660 res->sector_count_exp = data[13]; 1661 } else { 1662 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1663 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 1664 } 1665 xpt_done(ch->hold[i]); 1666 ch->hold[i] = NULL; 1667 } 1668 } else { 1669 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 1670 device_printf(dev, "Error while READ LOG EXT\n"); 1671 else if ((data[0] & 0x80) == 0) { 1672 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 1673 } 1674 for (i = 0; i < ch->numslots; i++) { 1675 if (!ch->hold[i]) 1676 continue; 1677 xpt_done(ch->hold[i]); 1678 ch->hold[i] = NULL; 1679 } 1680 } 1681 free(ccb->ataio.data_ptr, M_AHCI); 1682 xpt_free_ccb(ccb); 1683 xpt_release_simq(ch->sim, TRUE); 1684} 1685 1686static void 1687ahci_start(device_t dev) 1688{ 1689 struct ahci_channel *ch = device_get_softc(dev); 1690 u_int32_t cmd; 1691 1692 /* Clear SATA error register */ 1693 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 1694 /* Clear any interrupts pending on this channel */ 1695 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 1696 /* Start operations on this channel */ 1697 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1698 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 1699 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 1700} 1701 1702static void 1703ahci_stop(device_t dev) 1704{ 1705 struct ahci_channel *ch = device_get_softc(dev); 1706 u_int32_t cmd; 1707 int timeout; 1708 1709 /* Kill all activity on this channel */ 1710 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1711 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 1712 /* Wait for activity stop. */ 1713 timeout = 0; 1714 do { 1715 DELAY(1000); 1716 if (timeout++ > 1000) { 1717 device_printf(dev, "stopping AHCI engine failed\n"); 1718 break; 1719 } 1720 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 1721} 1722 1723static void 1724ahci_clo(device_t dev) 1725{ 1726 struct ahci_channel *ch = device_get_softc(dev); 1727 u_int32_t cmd; 1728 int timeout; 1729 1730 /* Issue Command List Override if supported */ 1731 if (ch->caps & AHCI_CAP_SCLO) { 1732 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1733 cmd |= AHCI_P_CMD_CLO; 1734 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 1735 timeout = 0; 1736 do { 1737 DELAY(1000); 1738 if (timeout++ > 1000) { 1739 device_printf(dev, "executing CLO failed\n"); 1740 break; 1741 } 1742 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 1743 } 1744} 1745 1746static void 1747ahci_stop_fr(device_t dev) 1748{ 1749 struct ahci_channel *ch = device_get_softc(dev); 1750 u_int32_t cmd; 1751 int timeout; 1752 1753 /* Kill all FIS reception on this channel */ 1754 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1755 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 1756 /* Wait for FIS reception stop. */ 1757 timeout = 0; 1758 do { 1759 DELAY(1000); 1760 if (timeout++ > 1000) { 1761 device_printf(dev, "stopping AHCI FR engine failed\n"); 1762 break; 1763 } 1764 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 1765} 1766 1767static void 1768ahci_start_fr(device_t dev) 1769{ 1770 struct ahci_channel *ch = device_get_softc(dev); 1771 u_int32_t cmd; 1772 1773 /* Start FIS reception on this channel */ 1774 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1775 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 1776} 1777 1778static int 1779ahci_wait_ready(device_t dev, int t) 1780{ 1781 struct ahci_channel *ch = device_get_softc(dev); 1782 int timeout = 0; 1783 uint32_t val; 1784 1785 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 1786 (ATA_S_BUSY | ATA_S_DRQ)) { 1787 DELAY(1000); 1788 if (timeout++ > t) { 1789 device_printf(dev, "port is not ready (timeout %dms) " 1790 "tfd = %08x\n", t, val); 1791 return (EBUSY); 1792 } 1793 } 1794 if (bootverbose) 1795 device_printf(dev, "ready wait time=%dms\n", timeout); 1796 return (0); 1797} 1798 1799static void 1800ahci_reset(device_t dev) 1801{ 1802 struct ahci_channel *ch = device_get_softc(dev); 1803 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1804 int i; 1805 1806 if (bootverbose) 1807 device_printf(dev, "AHCI reset...\n"); 1808 /* Requeue freezed command. */ 1809 if (ch->frozen) { 1810 union ccb *fccb = ch->frozen; 1811 ch->frozen = NULL; 1812 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1813 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1814 xpt_freeze_devq(fccb->ccb_h.path, 1); 1815 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1816 } 1817 xpt_done(fccb); 1818 } 1819 /* Kill the engine and requeue all running commands. */ 1820 ahci_stop(dev); 1821 for (i = 0; i < ch->numslots; i++) { 1822 /* Do we have a running request on slot? */ 1823 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1824 continue; 1825 /* XXX; Commands in loading state. */ 1826 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1827 } 1828 for (i = 0; i < ch->numslots; i++) { 1829 if (!ch->hold[i]) 1830 continue; 1831 xpt_done(ch->hold[i]); 1832 ch->hold[i] = NULL; 1833 } 1834 ch->fatalerr = 0; 1835 /* Tell the XPT about the event */ 1836 xpt_async(AC_BUS_RESET, ch->path, NULL); 1837 /* Disable port interrupts */ 1838 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1839 /* Reset and reconnect PHY, */ 1840 if (!ahci_sata_phy_reset(dev, 0)) { 1841 if (bootverbose) 1842 device_printf(dev, 1843 "AHCI reset done: phy reset found no device\n"); 1844 ch->devices = 0; 1845 /* Enable wanted port interrupts */ 1846 ATA_OUTL(ch->r_mem, AHCI_P_IE, 1847 (AHCI_P_IX_CPD | AHCI_P_IX_PRC | AHCI_P_IX_PC)); 1848 return; 1849 } 1850 /* Wait for clearing busy status. */ 1851 if (ahci_wait_ready(dev, 10000)) { 1852 device_printf(dev, "device ready timeout\n"); 1853 ahci_clo(dev); 1854 } 1855 ahci_start(dev); 1856 ch->devices = 1; 1857 /* Enable wanted port interrupts */ 1858 ATA_OUTL(ch->r_mem, AHCI_P_IE, 1859 (AHCI_P_IX_CPD | AHCI_P_IX_TFE | AHCI_P_IX_HBF | 1860 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 1861 ((ch->pm_level == 0) ? AHCI_P_IX_PRC | AHCI_P_IX_PC : 0) | 1862 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 1863 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 1864 if (bootverbose) 1865 device_printf(dev, "AHCI reset done: device found\n"); 1866} 1867 1868static int 1869ahci_setup_fis(struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 1870{ 1871 u_int8_t *fis = &ctp->cfis[0]; 1872 1873 bzero(ctp->cfis, 64); 1874 fis[0] = 0x27; /* host to device */ 1875 fis[1] = (ccb->ccb_h.target_id & 0x0f); 1876 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1877 fis[1] |= 0x80; 1878 fis[2] = ATA_PACKET_CMD; 1879 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) 1880 fis[3] = ATA_F_DMA; 1881 else { 1882 fis[5] = ccb->csio.dxfer_len; 1883 fis[6] = ccb->csio.dxfer_len >> 8; 1884 } 1885 fis[7] = ATA_D_LBA; 1886 fis[15] = ATA_A_4BIT; 1887 bzero(ctp->acmd, 32); 1888 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 1889 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 1890 ctp->acmd, ccb->csio.cdb_len); 1891 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 1892 fis[1] |= 0x80; 1893 fis[2] = ccb->ataio.cmd.command; 1894 fis[3] = ccb->ataio.cmd.features; 1895 fis[4] = ccb->ataio.cmd.lba_low; 1896 fis[5] = ccb->ataio.cmd.lba_mid; 1897 fis[6] = ccb->ataio.cmd.lba_high; 1898 fis[7] = ccb->ataio.cmd.device; 1899 fis[8] = ccb->ataio.cmd.lba_low_exp; 1900 fis[9] = ccb->ataio.cmd.lba_mid_exp; 1901 fis[10] = ccb->ataio.cmd.lba_high_exp; 1902 fis[11] = ccb->ataio.cmd.features_exp; 1903 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1904 fis[12] = tag << 3; 1905 fis[13] = 0; 1906 } else { 1907 fis[12] = ccb->ataio.cmd.sector_count; 1908 fis[13] = ccb->ataio.cmd.sector_count_exp; 1909 } 1910 fis[15] = ATA_A_4BIT; 1911 } else { 1912 fis[15] = ccb->ataio.cmd.control; 1913 } 1914 return (20); 1915} 1916 1917static int 1918ahci_sata_connect(struct ahci_channel *ch) 1919{ 1920 u_int32_t status; 1921 int timeout; 1922 1923 /* Wait up to 100ms for "connect well" */ 1924 for (timeout = 0; timeout < 100 ; timeout++) { 1925 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1926 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 1927 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 1928 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 1929 break; 1930 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 1931 if (bootverbose) { 1932 device_printf(ch->dev, "SATA offline status=%08x\n", 1933 status); 1934 } 1935 return (0); 1936 } 1937 DELAY(1000); 1938 } 1939 if (timeout >= 100) { 1940 if (bootverbose) { 1941 device_printf(ch->dev, "SATA connect timeout status=%08x\n", 1942 status); 1943 } 1944 return (0); 1945 } 1946 if (bootverbose) { 1947 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n", 1948 timeout, status); 1949 } 1950 /* Clear SATA error register */ 1951 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 1952 return (1); 1953} 1954 1955static int 1956ahci_sata_phy_reset(device_t dev, int quick) 1957{ 1958 struct ahci_channel *ch = device_get_softc(dev); 1959 uint32_t val; 1960 1961 if (quick) { 1962 val = ATA_INL(ch->r_mem, AHCI_P_SCTL); 1963 if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) 1964 return (ahci_sata_connect(ch)); 1965 } 1966 1967 if (bootverbose) 1968 device_printf(dev, "hardware reset ...\n"); 1969 if (ch->sata_rev == 1) 1970 val = ATA_SC_SPD_SPEED_GEN1; 1971 else if (ch->sata_rev == 2) 1972 val = ATA_SC_SPD_SPEED_GEN2; 1973 else if (ch->sata_rev == 3) 1974 val = ATA_SC_SPD_SPEED_GEN3; 1975 else 1976 val = 0; 1977 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 1978 ATA_SC_DET_RESET | val | 1979 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 1980 DELAY(5000); 1981 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 1982 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 1983 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 1984 DELAY(5000); 1985 return (ahci_sata_connect(ch)); 1986} 1987 1988static void 1989ahciaction(struct cam_sim *sim, union ccb *ccb) 1990{ 1991 device_t dev; 1992 struct ahci_channel *ch; 1993 1994 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 1995 ccb->ccb_h.func_code)); 1996 1997 ch = (struct ahci_channel *)cam_sim_softc(sim); 1998 dev = ch->dev; 1999 switch (ccb->ccb_h.func_code) { 2000 /* Common cases first */ 2001 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2002 case XPT_SCSI_IO: 2003 if (ch->devices == 0) { 2004 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2005 xpt_done(ccb); 2006 break; 2007 } 2008 /* Check for command collision. */ 2009 if (ahci_check_collision(dev, ccb)) { 2010 /* Freeze command. */ 2011 ch->frozen = ccb; 2012 /* We have only one frozen slot, so freeze simq also. */ 2013 xpt_freeze_simq(ch->sim, 1); 2014 return; 2015 } 2016 ahci_begin_transaction(dev, ccb); 2017 break; 2018 case XPT_EN_LUN: /* Enable LUN as a target */ 2019 case XPT_TARGET_IO: /* Execute target I/O request */ 2020 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2021 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2022 case XPT_ABORT: /* Abort the specified CCB */ 2023 /* XXX Implement */ 2024 ccb->ccb_h.status = CAM_REQ_INVALID; 2025 xpt_done(ccb); 2026 break; 2027 case XPT_SET_TRAN_SETTINGS: 2028 { 2029 struct ccb_trans_settings *cts = &ccb->cts; 2030 2031 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) { 2032 ch->pm_present = cts->xport_specific.sata.pm_present; 2033 } 2034 ccb->ccb_h.status = CAM_REQ_CMP; 2035 xpt_done(ccb); 2036 break; 2037 } 2038 case XPT_GET_TRAN_SETTINGS: 2039 /* Get default/user set transfer settings for the target */ 2040 { 2041 struct ccb_trans_settings *cts = &ccb->cts; 2042 uint32_t status; 2043 2044 cts->protocol = PROTO_ATA; 2045 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2046 cts->transport = XPORT_SATA; 2047 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2048 cts->proto_specific.valid = 0; 2049 cts->xport_specific.sata.valid = 0; 2050 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2051 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2052 else 2053 status = ATA_INL(ch->r_mem, AHCI_P_SCTL) & ATA_SC_SPD_MASK; 2054 if (status & ATA_SS_SPD_GEN3) { 2055 cts->xport_specific.sata.bitrate = 600000; 2056 cts->xport_specific.sata.valid |= CTS_SATA_VALID_SPEED; 2057 } else if (status & ATA_SS_SPD_GEN2) { 2058 cts->xport_specific.sata.bitrate = 300000; 2059 cts->xport_specific.sata.valid |= CTS_SATA_VALID_SPEED; 2060 } else if (status & ATA_SS_SPD_GEN1) { 2061 cts->xport_specific.sata.bitrate = 150000; 2062 cts->xport_specific.sata.valid |= CTS_SATA_VALID_SPEED; 2063 } 2064 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 2065 cts->xport_specific.sata.pm_present = 2066 (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_PMA) ? 2067 1 : 0; 2068 } else { 2069 cts->xport_specific.sata.pm_present = ch->pm_present; 2070 } 2071 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2072 ccb->ccb_h.status = CAM_REQ_CMP; 2073 xpt_done(ccb); 2074 break; 2075 } 2076#if 0 2077 case XPT_CALC_GEOMETRY: 2078 { 2079 struct ccb_calc_geometry *ccg; 2080 uint32_t size_mb; 2081 uint32_t secs_per_cylinder; 2082 2083 ccg = &ccb->ccg; 2084 size_mb = ccg->volume_size 2085 / ((1024L * 1024L) / ccg->block_size); 2086 if (size_mb >= 1024 && (aha->extended_trans != 0)) { 2087 if (size_mb >= 2048) { 2088 ccg->heads = 255; 2089 ccg->secs_per_track = 63; 2090 } else { 2091 ccg->heads = 128; 2092 ccg->secs_per_track = 32; 2093 } 2094 } else { 2095 ccg->heads = 64; 2096 ccg->secs_per_track = 32; 2097 } 2098 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 2099 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 2100 ccb->ccb_h.status = CAM_REQ_CMP; 2101 xpt_done(ccb); 2102 break; 2103 } 2104#endif 2105 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2106 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2107 ahci_reset(dev); 2108 ccb->ccb_h.status = CAM_REQ_CMP; 2109 xpt_done(ccb); 2110 break; 2111 case XPT_TERM_IO: /* Terminate the I/O process */ 2112 /* XXX Implement */ 2113 ccb->ccb_h.status = CAM_REQ_INVALID; 2114 xpt_done(ccb); 2115 break; 2116 case XPT_PATH_INQ: /* Path routing inquiry */ 2117 { 2118 struct ccb_pathinq *cpi = &ccb->cpi; 2119 2120 cpi->version_num = 1; /* XXX??? */ 2121 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE; 2122 if (ch->caps & AHCI_CAP_SPM) 2123 cpi->hba_inquiry |= PI_SATAPM; 2124 cpi->target_sprt = 0; 2125 cpi->hba_misc = PIM_SEQSCAN; 2126 cpi->hba_eng_cnt = 0; 2127 if (ch->caps & AHCI_CAP_SPM) 2128 cpi->max_target = 15; 2129 else 2130 cpi->max_target = 0; 2131 cpi->max_lun = 0; 2132 cpi->initiator_id = 0; 2133 cpi->bus_id = cam_sim_bus(sim); 2134 cpi->base_transfer_speed = 150000; 2135 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2136 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2137 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2138 cpi->unit_number = cam_sim_unit(sim); 2139 cpi->transport = XPORT_SATA; 2140 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2141 cpi->protocol = PROTO_ATA; 2142 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2143 cpi->maxio = MAXPHYS; 2144 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2145 if (pci_get_devid(device_get_parent(dev)) == 0x43801002) 2146 cpi->maxio = min(cpi->maxio, 128 * 512); 2147 cpi->ccb_h.status = CAM_REQ_CMP; 2148 xpt_done(ccb); 2149 break; 2150 } 2151 default: 2152 ccb->ccb_h.status = CAM_REQ_INVALID; 2153 xpt_done(ccb); 2154 break; 2155 } 2156} 2157 2158static void 2159ahcipoll(struct cam_sim *sim) 2160{ 2161 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2162 2163 ahci_ch_intr(ch->dev); 2164} 2165