ahci_generic.c revision 220565
1/*- 2 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ahci/ahci.c 220565 2011-04-12 11:24:59Z mav $"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/ata.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/malloc.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <sys/sema.h> 41#include <sys/taskqueue.h> 42#include <vm/uma.h> 43#include <machine/stdarg.h> 44#include <machine/resource.h> 45#include <machine/bus.h> 46#include <sys/rman.h> 47#include <dev/pci/pcivar.h> 48#include <dev/pci/pcireg.h> 49#include "ahci.h" 50 51#include <cam/cam.h> 52#include <cam/cam_ccb.h> 53#include <cam/cam_sim.h> 54#include <cam/cam_xpt_sim.h> 55#include <cam/cam_debug.h> 56 57/* local prototypes */ 58static int ahci_setup_interrupt(device_t dev); 59static void ahci_intr(void *data); 60static void ahci_intr_one(void *data); 61static int ahci_suspend(device_t dev); 62static int ahci_resume(device_t dev); 63static int ahci_ch_init(device_t dev); 64static int ahci_ch_deinit(device_t dev); 65static int ahci_ch_suspend(device_t dev); 66static int ahci_ch_resume(device_t dev); 67static void ahci_ch_pm(void *arg); 68static void ahci_ch_intr_locked(void *data); 69static void ahci_ch_intr(void *data); 70static int ahci_ctlr_reset(device_t dev); 71static int ahci_ctlr_setup(device_t dev); 72static void ahci_begin_transaction(device_t dev, union ccb *ccb); 73static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 74static void ahci_execute_transaction(struct ahci_slot *slot); 75static void ahci_timeout(struct ahci_slot *slot); 76static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 77static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 78static void ahci_dmainit(device_t dev); 79static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 80static void ahci_dmafini(device_t dev); 81static void ahci_slotsalloc(device_t dev); 82static void ahci_slotsfree(device_t dev); 83static void ahci_reset(device_t dev); 84static void ahci_start(device_t dev, int fbs); 85static void ahci_stop(device_t dev); 86static void ahci_clo(device_t dev); 87static void ahci_start_fr(device_t dev); 88static void ahci_stop_fr(device_t dev); 89 90static int ahci_sata_connect(struct ahci_channel *ch); 91static int ahci_sata_phy_reset(device_t dev); 92static int ahci_wait_ready(device_t dev, int t); 93 94static void ahci_issue_recovery(device_t dev); 95static void ahci_process_read_log(device_t dev, union ccb *ccb); 96static void ahci_process_request_sense(device_t dev, union ccb *ccb); 97 98static void ahciaction(struct cam_sim *sim, union ccb *ccb); 99static void ahcipoll(struct cam_sim *sim); 100 101MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 102 103static struct { 104 uint32_t id; 105 uint8_t rev; 106 const char *name; 107 int quirks; 108#define AHCI_Q_NOFORCE 1 109#define AHCI_Q_NOPMP 2 110#define AHCI_Q_NONCQ 4 111#define AHCI_Q_1CH 8 112#define AHCI_Q_2CH 16 113#define AHCI_Q_4CH 32 114#define AHCI_Q_EDGEIS 64 115#define AHCI_Q_SATA2 128 116#define AHCI_Q_NOBSYRES 256 117#define AHCI_Q_NOAA 512 118#define AHCI_Q_NOCOUNT 1024 119} ahci_ids[] = { 120 {0x43801002, 0x00, "ATI IXP600", 0}, 121 {0x43901002, 0x00, "ATI IXP700", 0}, 122 {0x43911002, 0x00, "ATI IXP700", 0}, 123 {0x43921002, 0x00, "ATI IXP700", 0}, 124 {0x43931002, 0x00, "ATI IXP700", 0}, 125 {0x43941002, 0x00, "ATI IXP800", 0}, 126 {0x43951002, 0x00, "ATI IXP800", 0}, 127 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE}, 128 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE}, 129 {0x26818086, 0x00, "Intel ESB2", 0}, 130 {0x26828086, 0x00, "Intel ESB2", 0}, 131 {0x26838086, 0x00, "Intel ESB2", 0}, 132 {0x27c18086, 0x00, "Intel ICH7", 0}, 133 {0x27c38086, 0x00, "Intel ICH7", 0}, 134 {0x27c58086, 0x00, "Intel ICH7M", 0}, 135 {0x27c68086, 0x00, "Intel ICH7M", 0}, 136 {0x28218086, 0x00, "Intel ICH8", 0}, 137 {0x28228086, 0x00, "Intel ICH8", 0}, 138 {0x28248086, 0x00, "Intel ICH8", 0}, 139 {0x28298086, 0x00, "Intel ICH8M", 0}, 140 {0x282a8086, 0x00, "Intel ICH8M", 0}, 141 {0x29228086, 0x00, "Intel ICH9", 0}, 142 {0x29238086, 0x00, "Intel ICH9", 0}, 143 {0x29248086, 0x00, "Intel ICH9", 0}, 144 {0x29258086, 0x00, "Intel ICH9", 0}, 145 {0x29278086, 0x00, "Intel ICH9", 0}, 146 {0x29298086, 0x00, "Intel ICH9M", 0}, 147 {0x292a8086, 0x00, "Intel ICH9M", 0}, 148 {0x292b8086, 0x00, "Intel ICH9M", 0}, 149 {0x292c8086, 0x00, "Intel ICH9M", 0}, 150 {0x292f8086, 0x00, "Intel ICH9M", 0}, 151 {0x294d8086, 0x00, "Intel ICH9", 0}, 152 {0x294e8086, 0x00, "Intel ICH9M", 0}, 153 {0x3a058086, 0x00, "Intel ICH10", 0}, 154 {0x3a228086, 0x00, "Intel ICH10", 0}, 155 {0x3a258086, 0x00, "Intel ICH10", 0}, 156 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0}, 157 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0}, 158 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0}, 159 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0}, 160 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0}, 161 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0}, 162 {0x1c028086, 0x00, "Intel Cougar Point", 0}, 163 {0x1c038086, 0x00, "Intel Cougar Point", 0}, 164 {0x1c048086, 0x00, "Intel Cougar Point", 0}, 165 {0x1c058086, 0x00, "Intel Cougar Point", 0}, 166 {0x23238086, 0x00, "Intel DH89xxCC", 0}, 167 {0x1d028086, 0x00, "Intel Patsburg", 0}, 168 {0x1d048086, 0x00, "Intel Patsburg", 0}, 169 {0x1d068086, 0x00, "Intel Patsburg", 0}, 170 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE}, 171 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE}, 172 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE}, 173 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE}, 174 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE}, 175 {0x611111ab, 0x00, "Marvell 88SX6111", AHCI_Q_NOFORCE | AHCI_Q_1CH | 176 AHCI_Q_EDGEIS}, 177 {0x612111ab, 0x00, "Marvell 88SX6121", AHCI_Q_NOFORCE | AHCI_Q_2CH | 178 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 179 {0x614111ab, 0x00, "Marvell 88SX6141", AHCI_Q_NOFORCE | AHCI_Q_4CH | 180 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 181 {0x614511ab, 0x00, "Marvell 88SX6145", AHCI_Q_NOFORCE | AHCI_Q_4CH | 182 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 183 {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_NOBSYRES}, 184 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES}, 185 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES}, 186 {0x06201103, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 187 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 188 {0x06221103, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 189 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 190 {0x06401103, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 191 {0x06401b4b, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 192 {0x06441103, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 193 {0x06441b4b, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 194 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 195 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 196 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 197 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 198 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 199 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 200 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 201 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 202 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 203 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 204 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 205 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 206 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 207 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 208 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 209 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 210 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 211 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 212 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 213 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 214 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 215 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 216 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 217 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 218 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 219 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 220 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 221 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 222 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 223 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 224 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 225 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 226 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 227 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 228 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 229 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 230 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 231 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 232 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 233 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 234 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 235 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 236 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 237 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 238 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 239 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 240 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 241 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 242 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 243 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 244 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 245 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 246 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 247 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 248 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 249 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 250 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 251 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 252 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 253 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 254 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 255 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 256 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 257 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 258 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 259 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 260 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 261 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 262 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 263 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 264 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 265 {0x11841039, 0x00, "SiS 966", 0}, 266 {0x11851039, 0x00, "SiS 968", 0}, 267 {0x01861039, 0x00, "SiS 968", 0}, 268 {0x00000000, 0x00, NULL, 0} 269}; 270 271#define recovery_type spriv_field0 272#define RECOVERY_NONE 0 273#define RECOVERY_READ_LOG 1 274#define RECOVERY_REQUEST_SENSE 2 275#define recovery_slot spriv_field1 276 277static int 278ahci_probe(device_t dev) 279{ 280 char buf[64]; 281 int i, valid = 0; 282 uint32_t devid = pci_get_devid(dev); 283 uint8_t revid = pci_get_revid(dev); 284 285 /* Is this a possible AHCI candidate? */ 286 if (pci_get_class(dev) == PCIC_STORAGE && 287 pci_get_subclass(dev) == PCIS_STORAGE_SATA && 288 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0) 289 valid = 1; 290 /* Is this a known AHCI chip? */ 291 for (i = 0; ahci_ids[i].id != 0; i++) { 292 if (ahci_ids[i].id == devid && 293 ahci_ids[i].rev <= revid && 294 (valid || !(ahci_ids[i].quirks & AHCI_Q_NOFORCE))) { 295 /* Do not attach JMicrons with single PCI function. */ 296 if (pci_get_vendor(dev) == 0x197b && 297 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0) 298 return (ENXIO); 299 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 300 ahci_ids[i].name); 301 device_set_desc_copy(dev, buf); 302 return (BUS_PROBE_VENDOR); 303 } 304 } 305 if (!valid) 306 return (ENXIO); 307 device_set_desc_copy(dev, "AHCI SATA controller"); 308 return (BUS_PROBE_VENDOR); 309} 310 311static int 312ahci_ata_probe(device_t dev) 313{ 314 char buf[64]; 315 int i; 316 uint32_t devid = pci_get_devid(dev); 317 uint8_t revid = pci_get_revid(dev); 318 319 if ((intptr_t)device_get_ivars(dev) >= 0) 320 return (ENXIO); 321 /* Is this a known AHCI chip? */ 322 for (i = 0; ahci_ids[i].id != 0; i++) { 323 if (ahci_ids[i].id == devid && 324 ahci_ids[i].rev <= revid) { 325 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 326 ahci_ids[i].name); 327 device_set_desc_copy(dev, buf); 328 return (BUS_PROBE_VENDOR); 329 } 330 } 331 device_set_desc_copy(dev, "AHCI SATA controller"); 332 return (BUS_PROBE_VENDOR); 333} 334 335static int 336ahci_attach(device_t dev) 337{ 338 struct ahci_controller *ctlr = device_get_softc(dev); 339 device_t child; 340 int error, unit, speed, i; 341 uint32_t devid = pci_get_devid(dev); 342 uint8_t revid = pci_get_revid(dev); 343 u_int32_t version; 344 345 ctlr->dev = dev; 346 i = 0; 347 while (ahci_ids[i].id != 0 && 348 (ahci_ids[i].id != devid || 349 ahci_ids[i].rev > revid)) 350 i++; 351 ctlr->quirks = ahci_ids[i].quirks; 352 resource_int_value(device_get_name(dev), 353 device_get_unit(dev), "ccc", &ctlr->ccc); 354 /* if we have a memory BAR(5) we are likely on an AHCI part */ 355 ctlr->r_rid = PCIR_BAR(5); 356 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 357 &ctlr->r_rid, RF_ACTIVE))) 358 return ENXIO; 359 /* Setup our own memory management for channels. */ 360 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 361 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 362 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 363 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 364 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 365 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 366 return (error); 367 } 368 if ((error = rman_manage_region(&ctlr->sc_iomem, 369 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 370 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 371 rman_fini(&ctlr->sc_iomem); 372 return (error); 373 } 374 pci_enable_busmaster(dev); 375 /* Reset controller */ 376 if ((error = ahci_ctlr_reset(dev)) != 0) { 377 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 378 rman_fini(&ctlr->sc_iomem); 379 return (error); 380 }; 381 /* Get the HW capabilities */ 382 version = ATA_INL(ctlr->r_mem, AHCI_VS); 383 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 384 if (version >= 0x00010020) 385 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 386 if (ctlr->caps & AHCI_CAP_EMS) 387 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 388 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 389 if (ctlr->quirks & AHCI_Q_1CH) { 390 ctlr->caps &= ~AHCI_CAP_NPMASK; 391 ctlr->ichannels &= 0x01; 392 } 393 if (ctlr->quirks & AHCI_Q_2CH) { 394 ctlr->caps &= ~AHCI_CAP_NPMASK; 395 ctlr->caps |= 1; 396 ctlr->ichannels &= 0x03; 397 } 398 if (ctlr->quirks & AHCI_Q_4CH) { 399 ctlr->caps &= ~AHCI_CAP_NPMASK; 400 ctlr->caps |= 3; 401 ctlr->ichannels &= 0x0f; 402 } 403 ctlr->channels = MAX(flsl(ctlr->ichannels), 404 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 405 if (ctlr->quirks & AHCI_Q_NOPMP) 406 ctlr->caps &= ~AHCI_CAP_SPM; 407 if (ctlr->quirks & AHCI_Q_NONCQ) 408 ctlr->caps &= ~AHCI_CAP_SNCQ; 409 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 410 ctlr->ccc = 0; 411 ahci_ctlr_setup(dev); 412 /* Setup interrupts. */ 413 if (ahci_setup_interrupt(dev)) { 414 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 415 rman_fini(&ctlr->sc_iomem); 416 return ENXIO; 417 } 418 /* Announce HW capabilities. */ 419 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 420 device_printf(dev, 421 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 422 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 423 ((version >> 4) & 0xf0) + (version & 0x0f), 424 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 425 ((speed == 1) ? "1.5":((speed == 2) ? "3": 426 ((speed == 3) ? "6":"?"))), 427 (ctlr->caps & AHCI_CAP_SPM) ? 428 "supported" : "not supported", 429 (ctlr->caps & AHCI_CAP_FBSS) ? 430 " with FBS" : ""); 431 if (bootverbose) { 432 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 433 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 434 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 435 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 436 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 437 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 438 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 439 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 440 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 441 ((speed == 1) ? "1.5":((speed == 2) ? "3": 442 ((speed == 3) ? "6":"?")))); 443 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 444 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 445 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 446 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 447 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 448 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 449 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 450 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 451 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 452 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 453 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 454 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 455 } 456 if (bootverbose && version >= 0x00010020) { 457 device_printf(dev, "Caps2:%s%s%s\n", 458 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 459 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 460 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 461 } 462 if (bootverbose && (ctlr->caps & AHCI_CAP_EMS)) { 463 device_printf(dev, "EM Caps:%s%s%s%s%s%s%s%s\n", 464 (ctlr->capsem & AHCI_EM_PM) ? " PM":"", 465 (ctlr->capsem & AHCI_EM_ALHD) ? " ALHD":"", 466 (ctlr->capsem & AHCI_EM_XMT) ? " XMT":"", 467 (ctlr->capsem & AHCI_EM_SMB) ? " SMB":"", 468 (ctlr->capsem & AHCI_EM_SGPIO) ? " SGPIO":"", 469 (ctlr->capsem & AHCI_EM_SES2) ? " SES-2":"", 470 (ctlr->capsem & AHCI_EM_SAFTE) ? " SAF-TE":"", 471 (ctlr->capsem & AHCI_EM_LED) ? " LED":""); 472 } 473 /* Attach all channels on this controller */ 474 for (unit = 0; unit < ctlr->channels; unit++) { 475 if ((ctlr->ichannels & (1 << unit)) == 0) 476 continue; 477 child = device_add_child(dev, "ahcich", -1); 478 if (child == NULL) 479 device_printf(dev, "failed to add channel device\n"); 480 else 481 device_set_ivars(child, (void *)(intptr_t)unit); 482 } 483 bus_generic_attach(dev); 484 return 0; 485} 486 487static int 488ahci_detach(device_t dev) 489{ 490 struct ahci_controller *ctlr = device_get_softc(dev); 491 device_t *children; 492 int nchildren, i; 493 494 /* Detach & delete all children */ 495 if (!device_get_children(dev, &children, &nchildren)) { 496 for (i = 0; i < nchildren; i++) 497 device_delete_child(dev, children[i]); 498 free(children, M_TEMP); 499 } 500 /* Free interrupts. */ 501 for (i = 0; i < ctlr->numirqs; i++) { 502 if (ctlr->irqs[i].r_irq) { 503 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 504 ctlr->irqs[i].handle); 505 bus_release_resource(dev, SYS_RES_IRQ, 506 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 507 } 508 } 509 pci_release_msi(dev); 510 /* Free memory. */ 511 rman_fini(&ctlr->sc_iomem); 512 if (ctlr->r_mem) 513 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 514 return (0); 515} 516 517static int 518ahci_ctlr_reset(device_t dev) 519{ 520 struct ahci_controller *ctlr = device_get_softc(dev); 521 int timeout; 522 523 if (pci_read_config(dev, 0x00, 4) == 0x28298086 && 524 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 525 pci_write_config(dev, 0x92, 0x01, 1); 526 /* Enable AHCI mode */ 527 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 528 /* Reset AHCI controller */ 529 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 530 for (timeout = 1000; timeout > 0; timeout--) { 531 DELAY(1000); 532 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 533 break; 534 } 535 if (timeout == 0) { 536 device_printf(dev, "AHCI controller reset failure\n"); 537 return ENXIO; 538 } 539 /* Reenable AHCI mode */ 540 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 541 return (0); 542} 543 544static int 545ahci_ctlr_setup(device_t dev) 546{ 547 struct ahci_controller *ctlr = device_get_softc(dev); 548 /* Clear interrupts */ 549 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 550 /* Configure CCC */ 551 if (ctlr->ccc) { 552 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 553 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 554 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 555 (4 << AHCI_CCCC_CC_SHIFT) | 556 AHCI_CCCC_EN); 557 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 558 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 559 if (bootverbose) { 560 device_printf(dev, 561 "CCC with %dms/4cmd enabled on vector %d\n", 562 ctlr->ccc, ctlr->cccv); 563 } 564 } 565 /* Enable AHCI interrupts */ 566 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 567 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 568 return (0); 569} 570 571static int 572ahci_suspend(device_t dev) 573{ 574 struct ahci_controller *ctlr = device_get_softc(dev); 575 576 bus_generic_suspend(dev); 577 /* Disable interupts, so the state change(s) doesn't trigger */ 578 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 579 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 580 return 0; 581} 582 583static int 584ahci_resume(device_t dev) 585{ 586 int res; 587 588 if ((res = ahci_ctlr_reset(dev)) != 0) 589 return (res); 590 ahci_ctlr_setup(dev); 591 return (bus_generic_resume(dev)); 592} 593 594static int 595ahci_setup_interrupt(device_t dev) 596{ 597 struct ahci_controller *ctlr = device_get_softc(dev); 598 int i, msi = 1; 599 600 /* Process hints. */ 601 resource_int_value(device_get_name(dev), 602 device_get_unit(dev), "msi", &msi); 603 if (msi < 0) 604 msi = 0; 605 else if (msi == 1) 606 msi = min(1, pci_msi_count(dev)); 607 else if (msi > 1) 608 msi = pci_msi_count(dev); 609 /* Allocate MSI if needed/present. */ 610 if (msi && pci_alloc_msi(dev, &msi) == 0) { 611 ctlr->numirqs = msi; 612 } else { 613 msi = 0; 614 ctlr->numirqs = 1; 615 } 616 /* Check for single MSI vector fallback. */ 617 if (ctlr->numirqs > 1 && 618 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 619 device_printf(dev, "Falling back to one MSI\n"); 620 ctlr->numirqs = 1; 621 } 622 /* Allocate all IRQs. */ 623 for (i = 0; i < ctlr->numirqs; i++) { 624 ctlr->irqs[i].ctlr = ctlr; 625 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0); 626 if (ctlr->numirqs == 1 || i >= ctlr->channels || 627 (ctlr->ccc && i == ctlr->cccv)) 628 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 629 else if (i == ctlr->numirqs - 1) 630 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 631 else 632 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 633 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 634 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 635 device_printf(dev, "unable to map interrupt\n"); 636 return ENXIO; 637 } 638 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 639 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr, 640 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 641 /* SOS XXX release r_irq */ 642 device_printf(dev, "unable to setup interrupt\n"); 643 return ENXIO; 644 } 645 if (ctlr->numirqs > 1) { 646 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 647 ctlr->irqs[i].handle, 648 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 649 "ch%d" : "%d", i); 650 } 651 } 652 return (0); 653} 654 655/* 656 * Common case interrupt handler. 657 */ 658static void 659ahci_intr(void *data) 660{ 661 struct ahci_controller_irq *irq = data; 662 struct ahci_controller *ctlr = irq->ctlr; 663 u_int32_t is, ise = 0; 664 void *arg; 665 int unit; 666 667 if (irq->mode == AHCI_IRQ_MODE_ALL) { 668 unit = 0; 669 if (ctlr->ccc) 670 is = ctlr->ichannels; 671 else 672 is = ATA_INL(ctlr->r_mem, AHCI_IS); 673 } else { /* AHCI_IRQ_MODE_AFTER */ 674 unit = irq->r_irq_rid - 1; 675 is = ATA_INL(ctlr->r_mem, AHCI_IS); 676 } 677 /* CCC interrupt is edge triggered. */ 678 if (ctlr->ccc) 679 ise = 1 << ctlr->cccv; 680 /* Some controllers have edge triggered IS. */ 681 if (ctlr->quirks & AHCI_Q_EDGEIS) 682 ise |= is; 683 if (ise != 0) 684 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 685 for (; unit < ctlr->channels; unit++) { 686 if ((is & (1 << unit)) != 0 && 687 (arg = ctlr->interrupt[unit].argument)) { 688 ctlr->interrupt[unit].function(arg); 689 } 690 } 691 /* AHCI declares level triggered IS. */ 692 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 693 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 694} 695 696/* 697 * Simplified interrupt handler for multivector MSI mode. 698 */ 699static void 700ahci_intr_one(void *data) 701{ 702 struct ahci_controller_irq *irq = data; 703 struct ahci_controller *ctlr = irq->ctlr; 704 void *arg; 705 int unit; 706 707 unit = irq->r_irq_rid - 1; 708 /* Some controllers have edge triggered IS. */ 709 if (ctlr->quirks & AHCI_Q_EDGEIS) 710 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 711 if ((arg = ctlr->interrupt[unit].argument)) 712 ctlr->interrupt[unit].function(arg); 713 /* AHCI declares level triggered IS. */ 714 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 715 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 716} 717 718static struct resource * 719ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 720 u_long start, u_long end, u_long count, u_int flags) 721{ 722 struct ahci_controller *ctlr = device_get_softc(dev); 723 int unit = ((struct ahci_channel *)device_get_softc(child))->unit; 724 struct resource *res = NULL; 725 int offset = AHCI_OFFSET + (unit << 7); 726 long st; 727 728 switch (type) { 729 case SYS_RES_MEMORY: 730 st = rman_get_start(ctlr->r_mem); 731 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 732 st + offset + 127, 128, RF_ACTIVE, child); 733 if (res) { 734 bus_space_handle_t bsh; 735 bus_space_tag_t bst; 736 bsh = rman_get_bushandle(ctlr->r_mem); 737 bst = rman_get_bustag(ctlr->r_mem); 738 bus_space_subregion(bst, bsh, offset, 128, &bsh); 739 rman_set_bushandle(res, bsh); 740 rman_set_bustag(res, bst); 741 } 742 break; 743 case SYS_RES_IRQ: 744 if (*rid == ATA_IRQ_RID) 745 res = ctlr->irqs[0].r_irq; 746 break; 747 } 748 return (res); 749} 750 751static int 752ahci_release_resource(device_t dev, device_t child, int type, int rid, 753 struct resource *r) 754{ 755 756 switch (type) { 757 case SYS_RES_MEMORY: 758 rman_release_resource(r); 759 return (0); 760 case SYS_RES_IRQ: 761 if (rid != ATA_IRQ_RID) 762 return ENOENT; 763 return (0); 764 } 765 return (EINVAL); 766} 767 768static int 769ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 770 int flags, driver_filter_t *filter, driver_intr_t *function, 771 void *argument, void **cookiep) 772{ 773 struct ahci_controller *ctlr = device_get_softc(dev); 774 int unit = (intptr_t)device_get_ivars(child); 775 776 if (filter != NULL) { 777 printf("ahci.c: we cannot use a filter here\n"); 778 return (EINVAL); 779 } 780 ctlr->interrupt[unit].function = function; 781 ctlr->interrupt[unit].argument = argument; 782 return (0); 783} 784 785static int 786ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 787 void *cookie) 788{ 789 struct ahci_controller *ctlr = device_get_softc(dev); 790 int unit = (intptr_t)device_get_ivars(child); 791 792 ctlr->interrupt[unit].function = NULL; 793 ctlr->interrupt[unit].argument = NULL; 794 return (0); 795} 796 797static int 798ahci_print_child(device_t dev, device_t child) 799{ 800 int retval; 801 802 retval = bus_print_child_header(dev, child); 803 retval += printf(" at channel %d", 804 (int)(intptr_t)device_get_ivars(child)); 805 retval += bus_print_child_footer(dev, child); 806 807 return (retval); 808} 809 810static int 811ahci_child_location_str(device_t dev, device_t child, char *buf, 812 size_t buflen) 813{ 814 815 snprintf(buf, buflen, "channel=%d", 816 (int)(intptr_t)device_get_ivars(child)); 817 return (0); 818} 819 820devclass_t ahci_devclass; 821static device_method_t ahci_methods[] = { 822 DEVMETHOD(device_probe, ahci_probe), 823 DEVMETHOD(device_attach, ahci_attach), 824 DEVMETHOD(device_detach, ahci_detach), 825 DEVMETHOD(device_suspend, ahci_suspend), 826 DEVMETHOD(device_resume, ahci_resume), 827 DEVMETHOD(bus_print_child, ahci_print_child), 828 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 829 DEVMETHOD(bus_release_resource, ahci_release_resource), 830 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 831 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 832 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 833 { 0, 0 } 834}; 835static driver_t ahci_driver = { 836 "ahci", 837 ahci_methods, 838 sizeof(struct ahci_controller) 839}; 840DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 841static device_method_t ahci_ata_methods[] = { 842 DEVMETHOD(device_probe, ahci_ata_probe), 843 DEVMETHOD(device_attach, ahci_attach), 844 DEVMETHOD(device_detach, ahci_detach), 845 DEVMETHOD(device_suspend, ahci_suspend), 846 DEVMETHOD(device_resume, ahci_resume), 847 DEVMETHOD(bus_print_child, ahci_print_child), 848 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 849 DEVMETHOD(bus_release_resource, ahci_release_resource), 850 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 851 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 852 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 853 { 0, 0 } 854}; 855static driver_t ahci_ata_driver = { 856 "ahci", 857 ahci_ata_methods, 858 sizeof(struct ahci_controller) 859}; 860DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0); 861MODULE_VERSION(ahci, 1); 862MODULE_DEPEND(ahci, cam, 1, 1, 1); 863 864static int 865ahci_ch_probe(device_t dev) 866{ 867 868 device_set_desc_copy(dev, "AHCI channel"); 869 return (0); 870} 871 872static int 873ahci_ch_attach(device_t dev) 874{ 875 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 876 struct ahci_channel *ch = device_get_softc(dev); 877 struct cam_devq *devq; 878 int rid, error, i, sata_rev = 0; 879 u_int32_t version; 880 881 ch->dev = dev; 882 ch->unit = (intptr_t)device_get_ivars(dev); 883 ch->caps = ctlr->caps; 884 ch->caps2 = ctlr->caps2; 885 ch->quirks = ctlr->quirks; 886 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 887 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 888 resource_int_value(device_get_name(dev), 889 device_get_unit(dev), "pm_level", &ch->pm_level); 890 if (ch->pm_level > 3) 891 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 892 /* Limit speed for my onboard JMicron external port. 893 * It is not eSATA really. */ 894 if (pci_get_devid(ctlr->dev) == 0x2363197b && 895 pci_get_subvendor(ctlr->dev) == 0x1043 && 896 pci_get_subdevice(ctlr->dev) == 0x81e4 && 897 ch->unit == 0) 898 sata_rev = 1; 899 if (ch->quirks & AHCI_Q_SATA2) 900 sata_rev = 2; 901 resource_int_value(device_get_name(dev), 902 device_get_unit(dev), "sata_rev", &sata_rev); 903 for (i = 0; i < 16; i++) { 904 ch->user[i].revision = sata_rev; 905 ch->user[i].mode = 0; 906 ch->user[i].bytecount = 8192; 907 ch->user[i].tags = ch->numslots; 908 ch->user[i].caps = 0; 909 ch->curr[i] = ch->user[i]; 910 if (ch->pm_level) { 911 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 912 CTS_SATA_CAPS_H_APST | 913 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 914 } 915 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA; 916 } 917 rid = ch->unit; 918 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 919 &rid, RF_ACTIVE))) 920 return (ENXIO); 921 ahci_dmainit(dev); 922 ahci_slotsalloc(dev); 923 ahci_ch_init(dev); 924 mtx_lock(&ch->mtx); 925 rid = ATA_IRQ_RID; 926 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 927 &rid, RF_SHAREABLE | RF_ACTIVE))) { 928 device_printf(dev, "Unable to map interrupt\n"); 929 error = ENXIO; 930 goto err0; 931 } 932 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 933 ahci_ch_intr_locked, dev, &ch->ih))) { 934 device_printf(dev, "Unable to setup interrupt\n"); 935 error = ENXIO; 936 goto err1; 937 } 938 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 939 version = ATA_INL(ctlr->r_mem, AHCI_VS); 940 if (version < 0x00010020 && (ctlr->caps & AHCI_CAP_FBSS)) 941 ch->chcaps |= AHCI_P_CMD_FBSCP; 942 if (bootverbose) { 943 device_printf(dev, "Caps:%s%s%s%s%s\n", 944 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 945 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 946 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 947 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 948 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":""); 949 } 950 /* Create the device queue for our SIM. */ 951 devq = cam_simq_alloc(ch->numslots); 952 if (devq == NULL) { 953 device_printf(dev, "Unable to allocate simq\n"); 954 error = ENOMEM; 955 goto err1; 956 } 957 /* Construct SIM entry */ 958 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 959 device_get_unit(dev), &ch->mtx, 960 min(2, ch->numslots), 961 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 962 devq); 963 if (ch->sim == NULL) { 964 cam_simq_free(devq); 965 device_printf(dev, "unable to allocate sim\n"); 966 error = ENOMEM; 967 goto err1; 968 } 969 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 970 device_printf(dev, "unable to register xpt bus\n"); 971 error = ENXIO; 972 goto err2; 973 } 974 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 975 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 976 device_printf(dev, "unable to create path\n"); 977 error = ENXIO; 978 goto err3; 979 } 980 if (ch->pm_level > 3) { 981 callout_reset(&ch->pm_timer, 982 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 983 ahci_ch_pm, dev); 984 } 985 mtx_unlock(&ch->mtx); 986 return (0); 987 988err3: 989 xpt_bus_deregister(cam_sim_path(ch->sim)); 990err2: 991 cam_sim_free(ch->sim, /*free_devq*/TRUE); 992err1: 993 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 994err0: 995 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 996 mtx_unlock(&ch->mtx); 997 mtx_destroy(&ch->mtx); 998 return (error); 999} 1000 1001static int 1002ahci_ch_detach(device_t dev) 1003{ 1004 struct ahci_channel *ch = device_get_softc(dev); 1005 1006 mtx_lock(&ch->mtx); 1007 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 1008 xpt_free_path(ch->path); 1009 xpt_bus_deregister(cam_sim_path(ch->sim)); 1010 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1011 mtx_unlock(&ch->mtx); 1012 1013 if (ch->pm_level > 3) 1014 callout_drain(&ch->pm_timer); 1015 bus_teardown_intr(dev, ch->r_irq, ch->ih); 1016 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1017 1018 ahci_ch_deinit(dev); 1019 ahci_slotsfree(dev); 1020 ahci_dmafini(dev); 1021 1022 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1023 mtx_destroy(&ch->mtx); 1024 return (0); 1025} 1026 1027static int 1028ahci_ch_init(device_t dev) 1029{ 1030 struct ahci_channel *ch = device_get_softc(dev); 1031 uint64_t work; 1032 1033 /* Disable port interrupts */ 1034 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1035 /* Setup work areas */ 1036 work = ch->dma.work_bus + AHCI_CL_OFFSET; 1037 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 1038 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 1039 work = ch->dma.rfis_bus; 1040 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 1041 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 1042 /* Activate the channel and power/spin up device */ 1043 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 1044 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1045 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 1046 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 1047 ahci_start_fr(dev); 1048 ahci_start(dev, 1); 1049 return (0); 1050} 1051 1052static int 1053ahci_ch_deinit(device_t dev) 1054{ 1055 struct ahci_channel *ch = device_get_softc(dev); 1056 1057 /* Disable port interrupts. */ 1058 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1059 /* Reset command register. */ 1060 ahci_stop(dev); 1061 ahci_stop_fr(dev); 1062 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 1063 /* Allow everything, including partial and slumber modes. */ 1064 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 1065 /* Request slumber mode transition and give some time to get there. */ 1066 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 1067 DELAY(100); 1068 /* Disable PHY. */ 1069 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 1070 return (0); 1071} 1072 1073static int 1074ahci_ch_suspend(device_t dev) 1075{ 1076 struct ahci_channel *ch = device_get_softc(dev); 1077 1078 mtx_lock(&ch->mtx); 1079 xpt_freeze_simq(ch->sim, 1); 1080 while (ch->oslots) 1081 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 1082 ahci_ch_deinit(dev); 1083 mtx_unlock(&ch->mtx); 1084 return (0); 1085} 1086 1087static int 1088ahci_ch_resume(device_t dev) 1089{ 1090 struct ahci_channel *ch = device_get_softc(dev); 1091 1092 mtx_lock(&ch->mtx); 1093 ahci_ch_init(dev); 1094 ahci_reset(dev); 1095 xpt_release_simq(ch->sim, TRUE); 1096 mtx_unlock(&ch->mtx); 1097 return (0); 1098} 1099 1100devclass_t ahcich_devclass; 1101static device_method_t ahcich_methods[] = { 1102 DEVMETHOD(device_probe, ahci_ch_probe), 1103 DEVMETHOD(device_attach, ahci_ch_attach), 1104 DEVMETHOD(device_detach, ahci_ch_detach), 1105 DEVMETHOD(device_suspend, ahci_ch_suspend), 1106 DEVMETHOD(device_resume, ahci_ch_resume), 1107 { 0, 0 } 1108}; 1109static driver_t ahcich_driver = { 1110 "ahcich", 1111 ahcich_methods, 1112 sizeof(struct ahci_channel) 1113}; 1114DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0); 1115 1116struct ahci_dc_cb_args { 1117 bus_addr_t maddr; 1118 int error; 1119}; 1120 1121static void 1122ahci_dmainit(device_t dev) 1123{ 1124 struct ahci_channel *ch = device_get_softc(dev); 1125 struct ahci_dc_cb_args dcba; 1126 size_t rfsize; 1127 1128 if (ch->caps & AHCI_CAP_64BIT) 1129 ch->dma.max_address = BUS_SPACE_MAXADDR; 1130 else 1131 ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT; 1132 /* Command area. */ 1133 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1134 ch->dma.max_address, BUS_SPACE_MAXADDR, 1135 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1136 0, NULL, NULL, &ch->dma.work_tag)) 1137 goto error; 1138 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0, 1139 &ch->dma.work_map)) 1140 goto error; 1141 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1142 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1143 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1144 goto error; 1145 } 1146 ch->dma.work_bus = dcba.maddr; 1147 /* FIS receive area. */ 1148 if (ch->chcaps & AHCI_P_CMD_FBSCP) 1149 rfsize = 4096; 1150 else 1151 rfsize = 256; 1152 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 1153 ch->dma.max_address, BUS_SPACE_MAXADDR, 1154 NULL, NULL, rfsize, 1, rfsize, 1155 0, NULL, NULL, &ch->dma.rfis_tag)) 1156 goto error; 1157 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1158 &ch->dma.rfis_map)) 1159 goto error; 1160 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1161 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1162 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1163 goto error; 1164 } 1165 ch->dma.rfis_bus = dcba.maddr; 1166 /* Data area. */ 1167 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1168 ch->dma.max_address, BUS_SPACE_MAXADDR, 1169 NULL, NULL, 1170 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1171 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1172 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 1173 goto error; 1174 } 1175 return; 1176 1177error: 1178 device_printf(dev, "WARNING - DMA initialization failed\n"); 1179 ahci_dmafini(dev); 1180} 1181 1182static void 1183ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1184{ 1185 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1186 1187 if (!(dcba->error = error)) 1188 dcba->maddr = segs[0].ds_addr; 1189} 1190 1191static void 1192ahci_dmafini(device_t dev) 1193{ 1194 struct ahci_channel *ch = device_get_softc(dev); 1195 1196 if (ch->dma.data_tag) { 1197 bus_dma_tag_destroy(ch->dma.data_tag); 1198 ch->dma.data_tag = NULL; 1199 } 1200 if (ch->dma.rfis_bus) { 1201 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1202 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1203 ch->dma.rfis_bus = 0; 1204 ch->dma.rfis_map = NULL; 1205 ch->dma.rfis = NULL; 1206 } 1207 if (ch->dma.work_bus) { 1208 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1209 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1210 ch->dma.work_bus = 0; 1211 ch->dma.work_map = NULL; 1212 ch->dma.work = NULL; 1213 } 1214 if (ch->dma.work_tag) { 1215 bus_dma_tag_destroy(ch->dma.work_tag); 1216 ch->dma.work_tag = NULL; 1217 } 1218} 1219 1220static void 1221ahci_slotsalloc(device_t dev) 1222{ 1223 struct ahci_channel *ch = device_get_softc(dev); 1224 int i; 1225 1226 /* Alloc and setup command/dma slots */ 1227 bzero(ch->slot, sizeof(ch->slot)); 1228 for (i = 0; i < ch->numslots; i++) { 1229 struct ahci_slot *slot = &ch->slot[i]; 1230 1231 slot->dev = dev; 1232 slot->slot = i; 1233 slot->state = AHCI_SLOT_EMPTY; 1234 slot->ccb = NULL; 1235 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1236 1237 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1238 device_printf(ch->dev, "FAILURE - create data_map\n"); 1239 } 1240} 1241 1242static void 1243ahci_slotsfree(device_t dev) 1244{ 1245 struct ahci_channel *ch = device_get_softc(dev); 1246 int i; 1247 1248 /* Free all dma slots */ 1249 for (i = 0; i < ch->numslots; i++) { 1250 struct ahci_slot *slot = &ch->slot[i]; 1251 1252 callout_drain(&slot->timeout); 1253 if (slot->dma.data_map) { 1254 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1255 slot->dma.data_map = NULL; 1256 } 1257 } 1258} 1259 1260static void 1261ahci_phy_check_events(device_t dev, u_int32_t serr) 1262{ 1263 struct ahci_channel *ch = device_get_softc(dev); 1264 1265 if ((serr & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) { 1266 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1267 union ccb *ccb; 1268 1269 if (bootverbose) { 1270 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 1271 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 1272 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) { 1273 device_printf(dev, "CONNECT requested\n"); 1274 } else 1275 device_printf(dev, "DISCONNECT requested\n"); 1276 } 1277 ahci_reset(dev); 1278 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1279 return; 1280 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1281 cam_sim_path(ch->sim), 1282 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1283 xpt_free_ccb(ccb); 1284 return; 1285 } 1286 xpt_rescan(ccb); 1287 } 1288} 1289 1290static void 1291ahci_notify_events(device_t dev, u_int32_t status) 1292{ 1293 struct ahci_channel *ch = device_get_softc(dev); 1294 struct cam_path *dpath; 1295 int i; 1296 1297 if (ch->caps & AHCI_CAP_SSNTF) 1298 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1299 if (bootverbose) 1300 device_printf(dev, "SNTF 0x%04x\n", status); 1301 for (i = 0; i < 16; i++) { 1302 if ((status & (1 << i)) == 0) 1303 continue; 1304 if (xpt_create_path(&dpath, NULL, 1305 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1306 xpt_async(AC_SCSI_AEN, dpath, NULL); 1307 xpt_free_path(dpath); 1308 } 1309 } 1310} 1311 1312static void 1313ahci_ch_intr_locked(void *data) 1314{ 1315 device_t dev = (device_t)data; 1316 struct ahci_channel *ch = device_get_softc(dev); 1317 1318 mtx_lock(&ch->mtx); 1319 ahci_ch_intr(data); 1320 mtx_unlock(&ch->mtx); 1321} 1322 1323static void 1324ahci_ch_pm(void *arg) 1325{ 1326 device_t dev = (device_t)arg; 1327 struct ahci_channel *ch = device_get_softc(dev); 1328 uint32_t work; 1329 1330 if (ch->numrslots != 0) 1331 return; 1332 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1333 if (ch->pm_level == 4) 1334 work |= AHCI_P_CMD_PARTIAL; 1335 else 1336 work |= AHCI_P_CMD_SLUMBER; 1337 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1338} 1339 1340static void 1341ahci_ch_intr(void *data) 1342{ 1343 device_t dev = (device_t)data; 1344 struct ahci_channel *ch = device_get_softc(dev); 1345 uint32_t istatus, sstatus, cstatus, serr = 0, sntf = 0, ok, err; 1346 enum ahci_err_type et; 1347 int i, ccs, port; 1348 1349 /* Read and clear interrupt statuses. */ 1350 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1351 if (istatus == 0) 1352 return; 1353 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1354 /* Read command statuses. */ 1355 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1356 cstatus = ATA_INL(ch->r_mem, AHCI_P_CI); 1357 if (istatus & AHCI_P_IX_SDB) { 1358 if (ch->caps & AHCI_CAP_SSNTF) 1359 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1360 else if (ch->fbs_enabled) { 1361 u_int8_t *fis = ch->dma.rfis + 0x58; 1362 1363 for (i = 0; i < 16; i++) { 1364 if (fis[1] & 0x80) { 1365 fis[1] &= 0x7f; 1366 sntf |= 1 << i; 1367 } 1368 fis += 256; 1369 } 1370 } else { 1371 u_int8_t *fis = ch->dma.rfis + 0x58; 1372 1373 if (fis[1] & 0x80) 1374 sntf = (1 << (fis[1] & 0x0f)); 1375 } 1376 } 1377 /* Process PHY events */ 1378 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1379 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1380 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1381 if (serr) { 1382 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1383 ahci_phy_check_events(dev, serr); 1384 } 1385 } 1386 /* Process command errors */ 1387 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1388 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1389 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1390 >> AHCI_P_CMD_CCS_SHIFT; 1391//device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1392// __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1393// serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1394 port = -1; 1395 if (ch->fbs_enabled) { 1396 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1397 if (fbs & AHCI_P_FBS_SDE) { 1398 port = (fbs & AHCI_P_FBS_DWE) 1399 >> AHCI_P_FBS_DWE_SHIFT; 1400 } else { 1401 for (i = 0; i < 16; i++) { 1402 if (ch->numrslotspd[i] == 0) 1403 continue; 1404 if (port == -1) 1405 port = i; 1406 else if (port != i) { 1407 port = -2; 1408 break; 1409 } 1410 } 1411 } 1412 } 1413 err = ch->rslots & (cstatus | sstatus); 1414 } else { 1415 ccs = 0; 1416 err = 0; 1417 port = -1; 1418 } 1419 /* Complete all successfull commands. */ 1420 ok = ch->rslots & ~(cstatus | sstatus); 1421 for (i = 0; i < ch->numslots; i++) { 1422 if ((ok >> i) & 1) 1423 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1424 } 1425 /* On error, complete the rest of commands with error statuses. */ 1426 if (err) { 1427 if (ch->frozen) { 1428 union ccb *fccb = ch->frozen; 1429 ch->frozen = NULL; 1430 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1431 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1432 xpt_freeze_devq(fccb->ccb_h.path, 1); 1433 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1434 } 1435 xpt_done(fccb); 1436 } 1437 for (i = 0; i < ch->numslots; i++) { 1438 /* XXX: reqests in loading state. */ 1439 if (((err >> i) & 1) == 0) 1440 continue; 1441 if (port >= 0 && 1442 ch->slot[i].ccb->ccb_h.target_id != port) 1443 continue; 1444 if (istatus & AHCI_P_IX_TFE) { 1445 if (port != -2) { 1446 /* Task File Error */ 1447 if (ch->numtslotspd[ 1448 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1449 /* Untagged operation. */ 1450 if (i == ccs) 1451 et = AHCI_ERR_TFE; 1452 else 1453 et = AHCI_ERR_INNOCENT; 1454 } else { 1455 /* Tagged operation. */ 1456 et = AHCI_ERR_NCQ; 1457 } 1458 } else { 1459 et = AHCI_ERR_TFE; 1460 ch->fatalerr = 1; 1461 } 1462 } else if (istatus & AHCI_P_IX_IF) { 1463 if (ch->numtslots == 0 && i != ccs && port != -2) 1464 et = AHCI_ERR_INNOCENT; 1465 else 1466 et = AHCI_ERR_SATA; 1467 } else 1468 et = AHCI_ERR_INVALID; 1469 ahci_end_transaction(&ch->slot[i], et); 1470 } 1471 /* 1472 * We can't reinit port if there are some other 1473 * commands active, use resume to complete them. 1474 */ 1475 if (ch->rslots != 0 && !ch->recoverycmd) 1476 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1477 } 1478 /* Process NOTIFY events */ 1479 if (sntf) 1480 ahci_notify_events(dev, sntf); 1481} 1482 1483/* Must be called with channel locked. */ 1484static int 1485ahci_check_collision(device_t dev, union ccb *ccb) 1486{ 1487 struct ahci_channel *ch = device_get_softc(dev); 1488 int t = ccb->ccb_h.target_id; 1489 1490 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1491 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1492 /* Tagged command while we have no supported tag free. */ 1493 if (((~ch->oslots) & (0xffffffff >> (32 - 1494 ch->curr[t].tags))) == 0) 1495 return (1); 1496 /* If we have FBS */ 1497 if (ch->fbs_enabled) { 1498 /* Tagged command while untagged are active. */ 1499 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1500 return (1); 1501 } else { 1502 /* Tagged command while untagged are active. */ 1503 if (ch->numrslots != 0 && ch->numtslots == 0) 1504 return (1); 1505 /* Tagged command while tagged to other target is active. */ 1506 if (ch->numtslots != 0 && 1507 ch->taggedtarget != ccb->ccb_h.target_id) 1508 return (1); 1509 } 1510 } else { 1511 /* If we have FBS */ 1512 if (ch->fbs_enabled) { 1513 /* Untagged command while tagged are active. */ 1514 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1515 return (1); 1516 } else { 1517 /* Untagged command while tagged are active. */ 1518 if (ch->numrslots != 0 && ch->numtslots != 0) 1519 return (1); 1520 } 1521 } 1522 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1523 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1524 /* Atomic command while anything active. */ 1525 if (ch->numrslots != 0) 1526 return (1); 1527 } 1528 /* We have some atomic command running. */ 1529 if (ch->aslots != 0) 1530 return (1); 1531 return (0); 1532} 1533 1534/* Must be called with channel locked. */ 1535static void 1536ahci_begin_transaction(device_t dev, union ccb *ccb) 1537{ 1538 struct ahci_channel *ch = device_get_softc(dev); 1539 struct ahci_slot *slot; 1540 int tag, tags; 1541 1542 /* Choose empty slot. */ 1543 tags = ch->numslots; 1544 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1545 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1546 tags = ch->curr[ccb->ccb_h.target_id].tags; 1547 tag = ch->lastslot; 1548 while (1) { 1549 if (tag >= tags) 1550 tag = 0; 1551 if (ch->slot[tag].state == AHCI_SLOT_EMPTY) 1552 break; 1553 tag++; 1554 }; 1555 ch->lastslot = tag; 1556 /* Occupy chosen slot. */ 1557 slot = &ch->slot[tag]; 1558 slot->ccb = ccb; 1559 /* Stop PM timer. */ 1560 if (ch->numrslots == 0 && ch->pm_level > 3) 1561 callout_stop(&ch->pm_timer); 1562 /* Update channel stats. */ 1563 ch->oslots |= (1 << slot->slot); 1564 ch->numrslots++; 1565 ch->numrslotspd[ccb->ccb_h.target_id]++; 1566 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1567 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1568 ch->numtslots++; 1569 ch->numtslotspd[ccb->ccb_h.target_id]++; 1570 ch->taggedtarget = ccb->ccb_h.target_id; 1571 } 1572 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1573 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1574 ch->aslots |= (1 << slot->slot); 1575 slot->dma.nsegs = 0; 1576 /* If request moves data, setup and load SG list */ 1577 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1578 void *buf; 1579 bus_size_t size; 1580 1581 slot->state = AHCI_SLOT_LOADING; 1582 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1583 buf = ccb->ataio.data_ptr; 1584 size = ccb->ataio.dxfer_len; 1585 } else { 1586 buf = ccb->csio.data_ptr; 1587 size = ccb->csio.dxfer_len; 1588 } 1589 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1590 buf, size, ahci_dmasetprd, slot, 0); 1591 } else 1592 ahci_execute_transaction(slot); 1593} 1594 1595/* Locked by busdma engine. */ 1596static void 1597ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1598{ 1599 struct ahci_slot *slot = arg; 1600 struct ahci_channel *ch = device_get_softc(slot->dev); 1601 struct ahci_cmd_tab *ctp; 1602 struct ahci_dma_prd *prd; 1603 int i; 1604 1605 if (error) { 1606 device_printf(slot->dev, "DMA load error\n"); 1607 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1608 return; 1609 } 1610 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1611 /* Get a piece of the workspace for this request */ 1612 ctp = (struct ahci_cmd_tab *) 1613 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1614 /* Fill S/G table */ 1615 prd = &ctp->prd_tab[0]; 1616 for (i = 0; i < nsegs; i++) { 1617 prd[i].dba = htole64(segs[i].ds_addr); 1618 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1619 } 1620 slot->dma.nsegs = nsegs; 1621 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1622 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1623 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1624 ahci_execute_transaction(slot); 1625} 1626 1627/* Must be called with channel locked. */ 1628static void 1629ahci_execute_transaction(struct ahci_slot *slot) 1630{ 1631 device_t dev = slot->dev; 1632 struct ahci_channel *ch = device_get_softc(dev); 1633 struct ahci_cmd_tab *ctp; 1634 struct ahci_cmd_list *clp; 1635 union ccb *ccb = slot->ccb; 1636 int port = ccb->ccb_h.target_id & 0x0f; 1637 int fis_size, i; 1638 uint8_t *fis = ch->dma.rfis + 0x40; 1639 uint8_t val; 1640 1641 /* Get a piece of the workspace for this request */ 1642 ctp = (struct ahci_cmd_tab *) 1643 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1644 /* Setup the FIS for this request */ 1645 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) { 1646 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1647 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1648 return; 1649 } 1650 /* Setup the command list entry */ 1651 clp = (struct ahci_cmd_list *) 1652 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1653 clp->cmd_flags = htole16( 1654 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1655 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1656 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1657 (fis_size / sizeof(u_int32_t)) | 1658 (port << 12)); 1659 clp->prd_length = htole16(slot->dma.nsegs); 1660 /* Special handling for Soft Reset command. */ 1661 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1662 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1663 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1664 /* Kick controller into sane state */ 1665 ahci_stop(dev); 1666 ahci_clo(dev); 1667 ahci_start(dev, 0); 1668 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1669 } else { 1670 /* Prepare FIS receive area for check. */ 1671 for (i = 0; i < 20; i++) 1672 fis[i] = 0xff; 1673 } 1674 } 1675 clp->bytecount = 0; 1676 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1677 (AHCI_CT_SIZE * slot->slot)); 1678 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1679 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1680 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1681 BUS_DMASYNC_PREREAD); 1682 /* Set ACTIVE bit for NCQ commands. */ 1683 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1684 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1685 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1686 } 1687 /* If FBS is enabled, set PMP port. */ 1688 if (ch->fbs_enabled) { 1689 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1690 (port << AHCI_P_FBS_DEV_SHIFT)); 1691 } 1692 /* Issue command to the controller. */ 1693 slot->state = AHCI_SLOT_RUNNING; 1694 ch->rslots |= (1 << slot->slot); 1695 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1696 /* Device reset commands doesn't interrupt. Poll them. */ 1697 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1698 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || 1699 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL))) { 1700 int count, timeout = ccb->ccb_h.timeout; 1701 enum ahci_err_type et = AHCI_ERR_NONE; 1702 1703 for (count = 0; count < timeout; count++) { 1704 DELAY(1000); 1705 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1706 break; 1707 if (ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) { 1708 device_printf(ch->dev, 1709 "Poll error on slot %d, TFD: %04x\n", 1710 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1711 et = AHCI_ERR_TFE; 1712 break; 1713 } 1714 /* Workaround for ATI SB600/SB700 chipsets. */ 1715 if (ccb->ccb_h.target_id == 15 && 1716 pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1717 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1718 et = AHCI_ERR_TIMEOUT; 1719 break; 1720 } 1721 } 1722 if (timeout && (count >= timeout)) { 1723 device_printf(ch->dev, 1724 "Poll timeout on slot %d\n", slot->slot); 1725 device_printf(dev, "is %08x cs %08x ss %08x " 1726 "rs %08x tfd %02x serr %08x\n", 1727 ATA_INL(ch->r_mem, AHCI_P_IS), 1728 ATA_INL(ch->r_mem, AHCI_P_CI), 1729 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1730 ATA_INL(ch->r_mem, AHCI_P_TFD), 1731 ATA_INL(ch->r_mem, AHCI_P_SERR)); 1732 et = AHCI_ERR_TIMEOUT; 1733 } 1734 /* Marvell controllers do not wait for readyness. */ 1735 if ((ch->quirks & AHCI_Q_NOBSYRES) && 1736 (ccb->ccb_h.func_code == XPT_ATA_IO) && 1737 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1738 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 1739 while ((val = fis[2]) & (ATA_S_BUSY | ATA_S_DRQ)) { 1740 DELAY(1000); 1741 if (count++ >= timeout) { 1742 device_printf(dev, "device is not " 1743 "ready after soft-reset: " 1744 "tfd = %08x\n", val); 1745 et = AHCI_ERR_TIMEOUT; 1746 break; 1747 } 1748 } 1749 } 1750 ahci_end_transaction(slot, et); 1751 /* Kick controller into sane state and enable FBS. */ 1752 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1753 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1754 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 1755 ahci_stop(ch->dev); 1756 ahci_start(ch->dev, 1); 1757 } 1758 return; 1759 } 1760 /* Start command execution timeout */ 1761 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 1762 (timeout_t*)ahci_timeout, slot); 1763 return; 1764} 1765 1766/* Must be called with channel locked. */ 1767static void 1768ahci_process_timeout(device_t dev) 1769{ 1770 struct ahci_channel *ch = device_get_softc(dev); 1771 int i; 1772 1773 mtx_assert(&ch->mtx, MA_OWNED); 1774 /* Handle the rest of commands. */ 1775 for (i = 0; i < ch->numslots; i++) { 1776 /* Do we have a running request on slot? */ 1777 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1778 continue; 1779 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 1780 } 1781} 1782 1783/* Must be called with channel locked. */ 1784static void 1785ahci_rearm_timeout(device_t dev) 1786{ 1787 struct ahci_channel *ch = device_get_softc(dev); 1788 int i; 1789 1790 mtx_assert(&ch->mtx, MA_OWNED); 1791 for (i = 0; i < ch->numslots; i++) { 1792 struct ahci_slot *slot = &ch->slot[i]; 1793 1794 /* Do we have a running request on slot? */ 1795 if (slot->state < AHCI_SLOT_RUNNING) 1796 continue; 1797 if ((ch->toslots & (1 << i)) == 0) 1798 continue; 1799 callout_reset(&slot->timeout, 1800 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1801 (timeout_t*)ahci_timeout, slot); 1802 } 1803} 1804 1805/* Locked by callout mechanism. */ 1806static void 1807ahci_timeout(struct ahci_slot *slot) 1808{ 1809 device_t dev = slot->dev; 1810 struct ahci_channel *ch = device_get_softc(dev); 1811 uint32_t sstatus; 1812 int ccs; 1813 int i; 1814 1815 /* Check for stale timeout. */ 1816 if (slot->state < AHCI_SLOT_RUNNING) 1817 return; 1818 1819 /* Check if slot was not being executed last time we checked. */ 1820 if (slot->state < AHCI_SLOT_EXECUTING) { 1821 /* Check if slot started executing. */ 1822 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1823 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1824 >> AHCI_P_CMD_CCS_SHIFT; 1825 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 1826 ch->fbs_enabled) 1827 slot->state = AHCI_SLOT_EXECUTING; 1828 1829 callout_reset(&slot->timeout, 1830 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1831 (timeout_t*)ahci_timeout, slot); 1832 return; 1833 } 1834 1835 device_printf(dev, "Timeout on slot %d\n", slot->slot); 1836 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x\n", 1837 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1838 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1839 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR)); 1840 1841 /* Handle frozen command. */ 1842 if (ch->frozen) { 1843 union ccb *fccb = ch->frozen; 1844 ch->frozen = NULL; 1845 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1846 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1847 xpt_freeze_devq(fccb->ccb_h.path, 1); 1848 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1849 } 1850 xpt_done(fccb); 1851 } 1852 if (!ch->fbs_enabled) { 1853 /* Without FBS we know real timeout source. */ 1854 ch->fatalerr = 1; 1855 /* Handle command with timeout. */ 1856 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 1857 /* Handle the rest of commands. */ 1858 for (i = 0; i < ch->numslots; i++) { 1859 /* Do we have a running request on slot? */ 1860 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1861 continue; 1862 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1863 } 1864 } else { 1865 /* With FBS we wait for other commands timeout and pray. */ 1866 if (ch->toslots == 0) 1867 xpt_freeze_simq(ch->sim, 1); 1868 ch->toslots |= (1 << slot->slot); 1869 if ((ch->rslots & ~ch->toslots) == 0) 1870 ahci_process_timeout(dev); 1871 else 1872 device_printf(dev, " ... waiting for slots %08x\n", 1873 ch->rslots & ~ch->toslots); 1874 } 1875} 1876 1877/* Must be called with channel locked. */ 1878static void 1879ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 1880{ 1881 device_t dev = slot->dev; 1882 struct ahci_channel *ch = device_get_softc(dev); 1883 union ccb *ccb = slot->ccb; 1884 struct ahci_cmd_list *clp; 1885 int lastto; 1886 1887 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1888 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1889 clp = (struct ahci_cmd_list *) 1890 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1891 /* Read result registers to the result struct 1892 * May be incorrect if several commands finished same time, 1893 * so read only when sure or have to. 1894 */ 1895 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1896 struct ata_res *res = &ccb->ataio.res; 1897 1898 if ((et == AHCI_ERR_TFE) || 1899 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1900 u_int8_t *fis = ch->dma.rfis + 0x40; 1901 1902 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1903 BUS_DMASYNC_POSTREAD); 1904 if (ch->fbs_enabled) { 1905 fis += ccb->ccb_h.target_id * 256; 1906 res->status = fis[2]; 1907 res->error = fis[3]; 1908 } else { 1909 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 1910 1911 res->status = tfd; 1912 res->error = tfd >> 8; 1913 } 1914 res->lba_low = fis[4]; 1915 res->lba_mid = fis[5]; 1916 res->lba_high = fis[6]; 1917 res->device = fis[7]; 1918 res->lba_low_exp = fis[8]; 1919 res->lba_mid_exp = fis[9]; 1920 res->lba_high_exp = fis[10]; 1921 res->sector_count = fis[12]; 1922 res->sector_count_exp = fis[13]; 1923 } else 1924 bzero(res, sizeof(*res)); 1925 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 1926 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1927 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 1928 ccb->ataio.resid = 1929 ccb->ataio.dxfer_len - le32toh(clp->bytecount); 1930 } 1931 } else { 1932 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1933 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 1934 ccb->csio.resid = 1935 ccb->csio.dxfer_len - le32toh(clp->bytecount); 1936 } 1937 } 1938 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1939 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1940 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1941 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1942 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1943 } 1944 if (et != AHCI_ERR_NONE) 1945 ch->eslots |= (1 << slot->slot); 1946 /* In case of error, freeze device for proper recovery. */ 1947 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) && 1948 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 1949 xpt_freeze_devq(ccb->ccb_h.path, 1); 1950 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1951 } 1952 /* Set proper result status. */ 1953 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1954 switch (et) { 1955 case AHCI_ERR_NONE: 1956 ccb->ccb_h.status |= CAM_REQ_CMP; 1957 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1958 ccb->csio.scsi_status = SCSI_STATUS_OK; 1959 break; 1960 case AHCI_ERR_INVALID: 1961 ch->fatalerr = 1; 1962 ccb->ccb_h.status |= CAM_REQ_INVALID; 1963 break; 1964 case AHCI_ERR_INNOCENT: 1965 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1966 break; 1967 case AHCI_ERR_TFE: 1968 case AHCI_ERR_NCQ: 1969 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1970 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1971 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1972 } else { 1973 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1974 } 1975 break; 1976 case AHCI_ERR_SATA: 1977 ch->fatalerr = 1; 1978 if (!ch->recoverycmd) { 1979 xpt_freeze_simq(ch->sim, 1); 1980 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1981 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1982 } 1983 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1984 break; 1985 case AHCI_ERR_TIMEOUT: 1986 if (!ch->recoverycmd) { 1987 xpt_freeze_simq(ch->sim, 1); 1988 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1989 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1990 } 1991 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1992 break; 1993 default: 1994 ch->fatalerr = 1; 1995 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1996 } 1997 /* Free slot. */ 1998 ch->oslots &= ~(1 << slot->slot); 1999 ch->rslots &= ~(1 << slot->slot); 2000 ch->aslots &= ~(1 << slot->slot); 2001 slot->state = AHCI_SLOT_EMPTY; 2002 slot->ccb = NULL; 2003 /* Update channel stats. */ 2004 ch->numrslots--; 2005 ch->numrslotspd[ccb->ccb_h.target_id]--; 2006 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2007 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 2008 ch->numtslots--; 2009 ch->numtslotspd[ccb->ccb_h.target_id]--; 2010 } 2011 /* Cancel timeout state if request completed normally. */ 2012 if (et != AHCI_ERR_TIMEOUT) { 2013 lastto = (ch->toslots == (1 << slot->slot)); 2014 ch->toslots &= ~(1 << slot->slot); 2015 if (lastto) 2016 xpt_release_simq(ch->sim, TRUE); 2017 } 2018 /* If it was first request of reset sequence and there is no error, 2019 * proceed to second request. */ 2020 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2021 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2022 (ccb->ataio.cmd.control & ATA_A_RESET) && 2023 et == AHCI_ERR_NONE) { 2024 ccb->ataio.cmd.control &= ~ATA_A_RESET; 2025 ahci_begin_transaction(dev, ccb); 2026 return; 2027 } 2028 /* If it was our READ LOG command - process it. */ 2029 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 2030 ahci_process_read_log(dev, ccb); 2031 /* If it was our REQUEST SENSE command - process it. */ 2032 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 2033 ahci_process_request_sense(dev, ccb); 2034 /* If it was NCQ or ATAPI command error, put result on hold. */ 2035 } else if (et == AHCI_ERR_NCQ || 2036 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 2037 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 2038 ch->hold[slot->slot] = ccb; 2039 ch->numhslots++; 2040 } else 2041 xpt_done(ccb); 2042 /* Unfreeze frozen command. */ 2043 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) { 2044 union ccb *fccb = ch->frozen; 2045 ch->frozen = NULL; 2046 ahci_begin_transaction(dev, fccb); 2047 xpt_release_simq(ch->sim, TRUE); 2048 } 2049 /* If we have no other active commands, ... */ 2050 if (ch->rslots == 0) { 2051 /* if there was fatal error - reset port. */ 2052 if (ch->toslots != 0 || ch->fatalerr) { 2053 ahci_reset(dev); 2054 } else { 2055 /* if we have slots in error, we can reinit port. */ 2056 if (ch->eslots != 0) { 2057 ahci_stop(dev); 2058 ahci_start(dev, 1); 2059 } 2060 /* if there commands on hold, we can do READ LOG. */ 2061 if (!ch->recoverycmd && ch->numhslots) 2062 ahci_issue_recovery(dev); 2063 } 2064 /* If all the rest of commands are in timeout - give them chance. */ 2065 } else if ((ch->rslots & ~ch->toslots) == 0 && 2066 et != AHCI_ERR_TIMEOUT) 2067 ahci_rearm_timeout(dev); 2068 /* Start PM timer. */ 2069 if (ch->numrslots == 0 && ch->pm_level > 3 && 2070 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 2071 callout_schedule(&ch->pm_timer, 2072 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 2073 } 2074} 2075 2076static void 2077ahci_issue_recovery(device_t dev) 2078{ 2079 struct ahci_channel *ch = device_get_softc(dev); 2080 union ccb *ccb; 2081 struct ccb_ataio *ataio; 2082 struct ccb_scsiio *csio; 2083 int i; 2084 2085 ch->recoverycmd = 1; 2086 /* Find some holden command. */ 2087 for (i = 0; i < ch->numslots; i++) { 2088 if (ch->hold[i]) 2089 break; 2090 } 2091 ccb = xpt_alloc_ccb_nowait(); 2092 if (ccb == NULL) { 2093 device_printf(dev, "Unable allocate READ LOG command"); 2094 return; /* XXX */ 2095 } 2096 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 2097 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2098 /* READ LOG */ 2099 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 2100 ccb->ccb_h.func_code = XPT_ATA_IO; 2101 ccb->ccb_h.flags = CAM_DIR_IN; 2102 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2103 ataio = &ccb->ataio; 2104 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 2105 if (ataio->data_ptr == NULL) { 2106 xpt_free_ccb(ccb); 2107 device_printf(dev, "Unable allocate memory for READ LOG command"); 2108 return; /* XXX */ 2109 } 2110 ataio->dxfer_len = 512; 2111 bzero(&ataio->cmd, sizeof(ataio->cmd)); 2112 ataio->cmd.flags = CAM_ATAIO_48BIT; 2113 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2114 ataio->cmd.sector_count = 1; 2115 ataio->cmd.sector_count_exp = 0; 2116 ataio->cmd.lba_low = 0x10; 2117 ataio->cmd.lba_mid = 0; 2118 ataio->cmd.lba_mid_exp = 0; 2119 } else { 2120 /* REQUEST SENSE */ 2121 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 2122 ccb->ccb_h.recovery_slot = i; 2123 ccb->ccb_h.func_code = XPT_SCSI_IO; 2124 ccb->ccb_h.flags = CAM_DIR_IN; 2125 ccb->ccb_h.status = 0; 2126 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2127 csio = &ccb->csio; 2128 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 2129 csio->dxfer_len = ch->hold[i]->csio.sense_len; 2130 csio->cdb_len = 6; 2131 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 2132 csio->cdb_io.cdb_bytes[0] = 0x03; 2133 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 2134 } 2135 /* Freeze SIM while doing recovery. */ 2136 xpt_freeze_simq(ch->sim, 1); 2137 ahci_begin_transaction(dev, ccb); 2138} 2139 2140static void 2141ahci_process_read_log(device_t dev, union ccb *ccb) 2142{ 2143 struct ahci_channel *ch = device_get_softc(dev); 2144 uint8_t *data; 2145 struct ata_res *res; 2146 int i; 2147 2148 ch->recoverycmd = 0; 2149 2150 data = ccb->ataio.data_ptr; 2151 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2152 (data[0] & 0x80) == 0) { 2153 for (i = 0; i < ch->numslots; i++) { 2154 if (!ch->hold[i]) 2155 continue; 2156 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2157 continue; 2158 if ((data[0] & 0x1F) == i) { 2159 res = &ch->hold[i]->ataio.res; 2160 res->status = data[2]; 2161 res->error = data[3]; 2162 res->lba_low = data[4]; 2163 res->lba_mid = data[5]; 2164 res->lba_high = data[6]; 2165 res->device = data[7]; 2166 res->lba_low_exp = data[8]; 2167 res->lba_mid_exp = data[9]; 2168 res->lba_high_exp = data[10]; 2169 res->sector_count = data[12]; 2170 res->sector_count_exp = data[13]; 2171 } else { 2172 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2173 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2174 } 2175 xpt_done(ch->hold[i]); 2176 ch->hold[i] = NULL; 2177 ch->numhslots--; 2178 } 2179 } else { 2180 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2181 device_printf(dev, "Error while READ LOG EXT\n"); 2182 else if ((data[0] & 0x80) == 0) { 2183 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 2184 } 2185 for (i = 0; i < ch->numslots; i++) { 2186 if (!ch->hold[i]) 2187 continue; 2188 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2189 continue; 2190 xpt_done(ch->hold[i]); 2191 ch->hold[i] = NULL; 2192 ch->numhslots--; 2193 } 2194 } 2195 free(ccb->ataio.data_ptr, M_AHCI); 2196 xpt_free_ccb(ccb); 2197 xpt_release_simq(ch->sim, TRUE); 2198} 2199 2200static void 2201ahci_process_request_sense(device_t dev, union ccb *ccb) 2202{ 2203 struct ahci_channel *ch = device_get_softc(dev); 2204 int i; 2205 2206 ch->recoverycmd = 0; 2207 2208 i = ccb->ccb_h.recovery_slot; 2209 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 2210 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 2211 } else { 2212 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2213 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 2214 } 2215 xpt_done(ch->hold[i]); 2216 ch->hold[i] = NULL; 2217 ch->numhslots--; 2218 xpt_free_ccb(ccb); 2219 xpt_release_simq(ch->sim, TRUE); 2220} 2221 2222static void 2223ahci_start(device_t dev, int fbs) 2224{ 2225 struct ahci_channel *ch = device_get_softc(dev); 2226 u_int32_t cmd; 2227 2228 /* Clear SATA error register */ 2229 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2230 /* Clear any interrupts pending on this channel */ 2231 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2232 /* Configure FIS-based switching if supported. */ 2233 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2234 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2235 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2236 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2237 } 2238 /* Start operations on this channel */ 2239 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2240 cmd &= ~AHCI_P_CMD_PMA; 2241 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2242 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2243} 2244 2245static void 2246ahci_stop(device_t dev) 2247{ 2248 struct ahci_channel *ch = device_get_softc(dev); 2249 u_int32_t cmd; 2250 int timeout; 2251 2252 /* Kill all activity on this channel */ 2253 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2254 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2255 /* Wait for activity stop. */ 2256 timeout = 0; 2257 do { 2258 DELAY(1000); 2259 if (timeout++ > 1000) { 2260 device_printf(dev, "stopping AHCI engine failed\n"); 2261 break; 2262 } 2263 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2264 ch->eslots = 0; 2265} 2266 2267static void 2268ahci_clo(device_t dev) 2269{ 2270 struct ahci_channel *ch = device_get_softc(dev); 2271 u_int32_t cmd; 2272 int timeout; 2273 2274 /* Issue Command List Override if supported */ 2275 if (ch->caps & AHCI_CAP_SCLO) { 2276 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2277 cmd |= AHCI_P_CMD_CLO; 2278 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2279 timeout = 0; 2280 do { 2281 DELAY(1000); 2282 if (timeout++ > 1000) { 2283 device_printf(dev, "executing CLO failed\n"); 2284 break; 2285 } 2286 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2287 } 2288} 2289 2290static void 2291ahci_stop_fr(device_t dev) 2292{ 2293 struct ahci_channel *ch = device_get_softc(dev); 2294 u_int32_t cmd; 2295 int timeout; 2296 2297 /* Kill all FIS reception on this channel */ 2298 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2299 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2300 /* Wait for FIS reception stop. */ 2301 timeout = 0; 2302 do { 2303 DELAY(1000); 2304 if (timeout++ > 1000) { 2305 device_printf(dev, "stopping AHCI FR engine failed\n"); 2306 break; 2307 } 2308 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2309} 2310 2311static void 2312ahci_start_fr(device_t dev) 2313{ 2314 struct ahci_channel *ch = device_get_softc(dev); 2315 u_int32_t cmd; 2316 2317 /* Start FIS reception on this channel */ 2318 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2319 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2320} 2321 2322static int 2323ahci_wait_ready(device_t dev, int t) 2324{ 2325 struct ahci_channel *ch = device_get_softc(dev); 2326 int timeout = 0; 2327 uint32_t val; 2328 2329 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2330 (ATA_S_BUSY | ATA_S_DRQ)) { 2331 DELAY(1000); 2332 if (timeout++ > t) { 2333 device_printf(dev, "device is not ready (timeout %dms) " 2334 "tfd = %08x\n", t, val); 2335 return (EBUSY); 2336 } 2337 } 2338 if (bootverbose) 2339 device_printf(dev, "ready wait time=%dms\n", timeout); 2340 return (0); 2341} 2342 2343static void 2344ahci_reset(device_t dev) 2345{ 2346 struct ahci_channel *ch = device_get_softc(dev); 2347 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2348 int i; 2349 2350 xpt_freeze_simq(ch->sim, 1); 2351 if (bootverbose) 2352 device_printf(dev, "AHCI reset...\n"); 2353 /* Requeue freezed command. */ 2354 if (ch->frozen) { 2355 union ccb *fccb = ch->frozen; 2356 ch->frozen = NULL; 2357 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2358 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2359 xpt_freeze_devq(fccb->ccb_h.path, 1); 2360 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2361 } 2362 xpt_done(fccb); 2363 } 2364 /* Kill the engine and requeue all running commands. */ 2365 ahci_stop(dev); 2366 for (i = 0; i < ch->numslots; i++) { 2367 /* Do we have a running request on slot? */ 2368 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2369 continue; 2370 /* XXX; Commands in loading state. */ 2371 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2372 } 2373 for (i = 0; i < ch->numslots; i++) { 2374 if (!ch->hold[i]) 2375 continue; 2376 xpt_done(ch->hold[i]); 2377 ch->hold[i] = NULL; 2378 ch->numhslots--; 2379 } 2380 if (ch->toslots != 0) 2381 xpt_release_simq(ch->sim, TRUE); 2382 ch->eslots = 0; 2383 ch->toslots = 0; 2384 ch->fatalerr = 0; 2385 /* Tell the XPT about the event */ 2386 xpt_async(AC_BUS_RESET, ch->path, NULL); 2387 /* Disable port interrupts */ 2388 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2389 /* Reset and reconnect PHY, */ 2390 if (!ahci_sata_phy_reset(dev)) { 2391 if (bootverbose) 2392 device_printf(dev, 2393 "AHCI reset done: phy reset found no device\n"); 2394 ch->devices = 0; 2395 /* Enable wanted port interrupts */ 2396 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2397 (AHCI_P_IX_CPD | AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2398 xpt_release_simq(ch->sim, TRUE); 2399 return; 2400 } 2401 /* Wait for clearing busy status. */ 2402 if (ahci_wait_ready(dev, 15000)) 2403 ahci_clo(dev); 2404 ahci_start(dev, 1); 2405 ch->devices = 1; 2406 /* Enable wanted port interrupts */ 2407 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2408 (AHCI_P_IX_CPD | AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2409 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2410 ((ch->pm_level == 0) ? AHCI_P_IX_PRC | AHCI_P_IX_PC : 0) | 2411 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2412 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2413 if (bootverbose) 2414 device_printf(dev, "AHCI reset done: device found\n"); 2415 xpt_release_simq(ch->sim, TRUE); 2416} 2417 2418static int 2419ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2420{ 2421 struct ahci_channel *ch = device_get_softc(dev); 2422 u_int8_t *fis = &ctp->cfis[0]; 2423 2424 bzero(ctp->cfis, 64); 2425 fis[0] = 0x27; /* host to device */ 2426 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2427 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2428 fis[1] |= 0x80; 2429 fis[2] = ATA_PACKET_CMD; 2430 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2431 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2432 fis[3] = ATA_F_DMA; 2433 else { 2434 fis[5] = ccb->csio.dxfer_len; 2435 fis[6] = ccb->csio.dxfer_len >> 8; 2436 } 2437 fis[7] = ATA_D_LBA; 2438 fis[15] = ATA_A_4BIT; 2439 bzero(ctp->acmd, 32); 2440 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2441 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2442 ctp->acmd, ccb->csio.cdb_len); 2443 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2444 fis[1] |= 0x80; 2445 fis[2] = ccb->ataio.cmd.command; 2446 fis[3] = ccb->ataio.cmd.features; 2447 fis[4] = ccb->ataio.cmd.lba_low; 2448 fis[5] = ccb->ataio.cmd.lba_mid; 2449 fis[6] = ccb->ataio.cmd.lba_high; 2450 fis[7] = ccb->ataio.cmd.device; 2451 fis[8] = ccb->ataio.cmd.lba_low_exp; 2452 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2453 fis[10] = ccb->ataio.cmd.lba_high_exp; 2454 fis[11] = ccb->ataio.cmd.features_exp; 2455 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2456 fis[12] = tag << 3; 2457 fis[13] = 0; 2458 } else { 2459 fis[12] = ccb->ataio.cmd.sector_count; 2460 fis[13] = ccb->ataio.cmd.sector_count_exp; 2461 } 2462 fis[15] = ATA_A_4BIT; 2463 } else { 2464 fis[15] = ccb->ataio.cmd.control; 2465 } 2466 return (20); 2467} 2468 2469static int 2470ahci_sata_connect(struct ahci_channel *ch) 2471{ 2472 u_int32_t status; 2473 int timeout; 2474 2475 /* Wait up to 100ms for "connect well" */ 2476 for (timeout = 0; timeout < 100 ; timeout++) { 2477 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2478 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2479 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2480 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2481 break; 2482 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2483 if (bootverbose) { 2484 device_printf(ch->dev, "SATA offline status=%08x\n", 2485 status); 2486 } 2487 return (0); 2488 } 2489 DELAY(1000); 2490 } 2491 if (timeout >= 100) { 2492 if (bootverbose) { 2493 device_printf(ch->dev, "SATA connect timeout status=%08x\n", 2494 status); 2495 } 2496 return (0); 2497 } 2498 if (bootverbose) { 2499 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n", 2500 timeout, status); 2501 } 2502 /* Clear SATA error register */ 2503 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2504 return (1); 2505} 2506 2507static int 2508ahci_sata_phy_reset(device_t dev) 2509{ 2510 struct ahci_channel *ch = device_get_softc(dev); 2511 int sata_rev; 2512 uint32_t val; 2513 2514 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2515 if (sata_rev == 1) 2516 val = ATA_SC_SPD_SPEED_GEN1; 2517 else if (sata_rev == 2) 2518 val = ATA_SC_SPD_SPEED_GEN2; 2519 else if (sata_rev == 3) 2520 val = ATA_SC_SPD_SPEED_GEN3; 2521 else 2522 val = 0; 2523 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2524 ATA_SC_DET_RESET | val | 2525 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2526 DELAY(5000); 2527 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2528 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2529 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2530 DELAY(5000); 2531 if (!ahci_sata_connect(ch)) { 2532 if (ch->pm_level > 0) 2533 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2534 return (0); 2535 } 2536 return (1); 2537} 2538 2539static int 2540ahci_check_ids(device_t dev, union ccb *ccb) 2541{ 2542 struct ahci_channel *ch = device_get_softc(dev); 2543 2544 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2545 ccb->ccb_h.status = CAM_TID_INVALID; 2546 xpt_done(ccb); 2547 return (-1); 2548 } 2549 if (ccb->ccb_h.target_lun != 0) { 2550 ccb->ccb_h.status = CAM_LUN_INVALID; 2551 xpt_done(ccb); 2552 return (-1); 2553 } 2554 return (0); 2555} 2556 2557static void 2558ahciaction(struct cam_sim *sim, union ccb *ccb) 2559{ 2560 device_t dev, parent; 2561 struct ahci_channel *ch; 2562 2563 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2564 ccb->ccb_h.func_code)); 2565 2566 ch = (struct ahci_channel *)cam_sim_softc(sim); 2567 dev = ch->dev; 2568 switch (ccb->ccb_h.func_code) { 2569 /* Common cases first */ 2570 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2571 case XPT_SCSI_IO: 2572 if (ahci_check_ids(dev, ccb)) 2573 return; 2574 if (ch->devices == 0 || 2575 (ch->pm_present == 0 && 2576 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2577 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2578 break; 2579 } 2580 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2581 /* Check for command collision. */ 2582 if (ahci_check_collision(dev, ccb)) { 2583 /* Freeze command. */ 2584 ch->frozen = ccb; 2585 /* We have only one frozen slot, so freeze simq also. */ 2586 xpt_freeze_simq(ch->sim, 1); 2587 return; 2588 } 2589 ahci_begin_transaction(dev, ccb); 2590 return; 2591 case XPT_EN_LUN: /* Enable LUN as a target */ 2592 case XPT_TARGET_IO: /* Execute target I/O request */ 2593 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2594 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2595 case XPT_ABORT: /* Abort the specified CCB */ 2596 /* XXX Implement */ 2597 ccb->ccb_h.status = CAM_REQ_INVALID; 2598 break; 2599 case XPT_SET_TRAN_SETTINGS: 2600 { 2601 struct ccb_trans_settings *cts = &ccb->cts; 2602 struct ahci_device *d; 2603 2604 if (ahci_check_ids(dev, ccb)) 2605 return; 2606 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2607 d = &ch->curr[ccb->ccb_h.target_id]; 2608 else 2609 d = &ch->user[ccb->ccb_h.target_id]; 2610 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2611 d->revision = cts->xport_specific.sata.revision; 2612 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2613 d->mode = cts->xport_specific.sata.mode; 2614 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2615 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2616 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2617 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2618 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2619 ch->pm_present = cts->xport_specific.sata.pm_present; 2620 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2621 d->atapi = cts->xport_specific.sata.atapi; 2622 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2623 d->caps = cts->xport_specific.sata.caps; 2624 ccb->ccb_h.status = CAM_REQ_CMP; 2625 break; 2626 } 2627 case XPT_GET_TRAN_SETTINGS: 2628 /* Get default/user set transfer settings for the target */ 2629 { 2630 struct ccb_trans_settings *cts = &ccb->cts; 2631 struct ahci_device *d; 2632 uint32_t status; 2633 2634 if (ahci_check_ids(dev, ccb)) 2635 return; 2636 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2637 d = &ch->curr[ccb->ccb_h.target_id]; 2638 else 2639 d = &ch->user[ccb->ccb_h.target_id]; 2640 cts->protocol = PROTO_ATA; 2641 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2642 cts->transport = XPORT_SATA; 2643 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2644 cts->proto_specific.valid = 0; 2645 cts->xport_specific.sata.valid = 0; 2646 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2647 (ccb->ccb_h.target_id == 15 || 2648 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2649 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2650 if (status & 0x0f0) { 2651 cts->xport_specific.sata.revision = 2652 (status & 0x0f0) >> 4; 2653 cts->xport_specific.sata.valid |= 2654 CTS_SATA_VALID_REVISION; 2655 } 2656 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2657 if (ch->pm_level) { 2658 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 2659 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2660 if (ch->caps2 & AHCI_CAP2_APST) 2661 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 2662 } 2663 if ((ch->caps & AHCI_CAP_SNCQ) && 2664 (ch->quirks & AHCI_Q_NOAA) == 0) 2665 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 2666 cts->xport_specific.sata.caps &= 2667 ch->user[ccb->ccb_h.target_id].caps; 2668 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2669 } else { 2670 cts->xport_specific.sata.revision = d->revision; 2671 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2672 cts->xport_specific.sata.caps = d->caps; 2673 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2674 } 2675 cts->xport_specific.sata.mode = d->mode; 2676 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2677 cts->xport_specific.sata.bytecount = d->bytecount; 2678 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2679 cts->xport_specific.sata.pm_present = ch->pm_present; 2680 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2681 cts->xport_specific.sata.tags = d->tags; 2682 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2683 cts->xport_specific.sata.atapi = d->atapi; 2684 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2685 ccb->ccb_h.status = CAM_REQ_CMP; 2686 break; 2687 } 2688 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2689 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2690 ahci_reset(dev); 2691 ccb->ccb_h.status = CAM_REQ_CMP; 2692 break; 2693 case XPT_TERM_IO: /* Terminate the I/O process */ 2694 /* XXX Implement */ 2695 ccb->ccb_h.status = CAM_REQ_INVALID; 2696 break; 2697 case XPT_PATH_INQ: /* Path routing inquiry */ 2698 { 2699 struct ccb_pathinq *cpi = &ccb->cpi; 2700 2701 parent = device_get_parent(dev); 2702 cpi->version_num = 1; /* XXX??? */ 2703 cpi->hba_inquiry = PI_SDTR_ABLE; 2704 if (ch->caps & AHCI_CAP_SNCQ) 2705 cpi->hba_inquiry |= PI_TAG_ABLE; 2706 if (ch->caps & AHCI_CAP_SPM) 2707 cpi->hba_inquiry |= PI_SATAPM; 2708 cpi->target_sprt = 0; 2709 cpi->hba_misc = PIM_SEQSCAN; 2710 cpi->hba_eng_cnt = 0; 2711 if (ch->caps & AHCI_CAP_SPM) 2712 cpi->max_target = 15; 2713 else 2714 cpi->max_target = 0; 2715 cpi->max_lun = 0; 2716 cpi->initiator_id = 0; 2717 cpi->bus_id = cam_sim_bus(sim); 2718 cpi->base_transfer_speed = 150000; 2719 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2720 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2721 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2722 cpi->unit_number = cam_sim_unit(sim); 2723 cpi->transport = XPORT_SATA; 2724 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2725 cpi->protocol = PROTO_ATA; 2726 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2727 cpi->maxio = MAXPHYS; 2728 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2729 if (pci_get_devid(parent) == 0x43801002) 2730 cpi->maxio = min(cpi->maxio, 128 * 512); 2731 cpi->hba_vendor = pci_get_vendor(parent); 2732 cpi->hba_device = pci_get_device(parent); 2733 cpi->hba_subvendor = pci_get_subvendor(parent); 2734 cpi->hba_subdevice = pci_get_subdevice(parent); 2735 cpi->ccb_h.status = CAM_REQ_CMP; 2736 break; 2737 } 2738 default: 2739 ccb->ccb_h.status = CAM_REQ_INVALID; 2740 break; 2741 } 2742 xpt_done(ccb); 2743} 2744 2745static void 2746ahcipoll(struct cam_sim *sim) 2747{ 2748 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2749 2750 ahci_ch_intr(ch->dev); 2751} 2752