ahci_generic.c revision 199717
1/*- 2 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ahci/ahci.c 199717 2009-11-23 18:07:28Z mav $"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/ata.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/malloc.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <sys/sema.h> 41#include <sys/taskqueue.h> 42#include <vm/uma.h> 43#include <machine/stdarg.h> 44#include <machine/resource.h> 45#include <machine/bus.h> 46#include <sys/rman.h> 47#include <dev/pci/pcivar.h> 48#include <dev/pci/pcireg.h> 49#include "ahci.h" 50 51#include <cam/cam.h> 52#include <cam/cam_ccb.h> 53#include <cam/cam_sim.h> 54#include <cam/cam_xpt_sim.h> 55#include <cam/cam_xpt_periph.h> 56#include <cam/cam_debug.h> 57 58/* local prototypes */ 59static int ahci_setup_interrupt(device_t dev); 60static void ahci_intr(void *data); 61static void ahci_intr_one(void *data); 62static int ahci_suspend(device_t dev); 63static int ahci_resume(device_t dev); 64static int ahci_ch_suspend(device_t dev); 65static int ahci_ch_resume(device_t dev); 66static void ahci_ch_pm(void *arg); 67static void ahci_ch_intr_locked(void *data); 68static void ahci_ch_intr(void *data); 69static int ahci_ctlr_reset(device_t dev); 70static void ahci_begin_transaction(device_t dev, union ccb *ccb); 71static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 72static void ahci_execute_transaction(struct ahci_slot *slot); 73static void ahci_timeout(struct ahci_slot *slot); 74static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 75static int ahci_setup_fis(struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 76static void ahci_dmainit(device_t dev); 77static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 78static void ahci_dmafini(device_t dev); 79static void ahci_slotsalloc(device_t dev); 80static void ahci_slotsfree(device_t dev); 81static void ahci_reset(device_t dev); 82static void ahci_start(device_t dev); 83static void ahci_stop(device_t dev); 84static void ahci_clo(device_t dev); 85static void ahci_start_fr(device_t dev); 86static void ahci_stop_fr(device_t dev); 87 88static int ahci_sata_connect(struct ahci_channel *ch); 89static int ahci_sata_phy_reset(device_t dev, int quick); 90 91static void ahci_issue_read_log(device_t dev); 92static void ahci_process_read_log(device_t dev, union ccb *ccb); 93 94static void ahciaction(struct cam_sim *sim, union ccb *ccb); 95static void ahcipoll(struct cam_sim *sim); 96 97MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 98 99static struct { 100 uint32_t id; 101 const char *name; 102 int quirks; 103#define AHCI_Q_NOFORCE 1 104#define AHCI_Q_NOPMP 2 105#define AHCI_Q_NONCQ 4 106#define AHCI_Q_1CH 8 107#define AHCI_Q_2CH 16 108#define AHCI_Q_4CH 32 109#define AHCI_Q_EDGEIS 64 110} ahci_ids[] = { 111 {0x43801002, "ATI IXP600", 0}, 112 {0x43901002, "ATI IXP700", 0}, 113 {0x43911002, "ATI IXP700", 0}, 114 {0x43921002, "ATI IXP700", 0}, 115 {0x43931002, "ATI IXP700", 0}, 116 {0x43941002, "ATI IXP800", 0}, 117 {0x43951002, "ATI IXP800", 0}, 118 {0x26528086, "Intel ICH6", 0}, 119 {0x26538086, "Intel ICH6M", 0}, 120 {0x26818086, "Intel ESB2", 0}, 121 {0x26828086, "Intel ESB2", 0}, 122 {0x26838086, "Intel ESB2", 0}, 123 {0x27c18086, "Intel ICH7", 0}, 124 {0x27c38086, "Intel ICH7", 0}, 125 {0x27c58086, "Intel ICH7M", 0}, 126 {0x27c68086, "Intel ICH7M", 0}, 127 {0x28218086, "Intel ICH8", 0}, 128 {0x28228086, "Intel ICH8", 0}, 129 {0x28248086, "Intel ICH8", 0}, 130 {0x28298086, "Intel ICH8M", 0}, 131 {0x282a8086, "Intel ICH8M", 0}, 132 {0x29228086, "Intel ICH9", 0}, 133 {0x29238086, "Intel ICH9", 0}, 134 {0x29248086, "Intel ICH9", 0}, 135 {0x29258086, "Intel ICH9", 0}, 136 {0x29278086, "Intel ICH9", 0}, 137 {0x29298086, "Intel ICH9M", 0}, 138 {0x292a8086, "Intel ICH9M", 0}, 139 {0x292b8086, "Intel ICH9M", 0}, 140 {0x292c8086, "Intel ICH9M", 0}, 141 {0x292f8086, "Intel ICH9M", 0}, 142 {0x294d8086, "Intel ICH9", 0}, 143 {0x294e8086, "Intel ICH9M", 0}, 144 {0x3a058086, "Intel ICH10", 0}, 145 {0x3a228086, "Intel ICH10", 0}, 146 {0x3a258086, "Intel ICH10", 0}, 147 {0x3b228086, "Intel PCH", 0}, 148 {0x3b238086, "Intel PCH", 0}, 149 {0x3b248086, "Intel PCH", 0}, 150 {0x3b258086, "Intel PCH", 0}, 151 {0x3b298086, "Intel PCH", 0}, 152 {0x3b2b8086, "Intel PCH", 0}, 153 {0x3b2c8086, "Intel PCH", 0}, 154 {0x3b2f8086, "Intel PCH", 0}, 155 {0x2361197b, "JMicron JMB361", AHCI_Q_NOFORCE}, 156 {0x2363197b, "JMicron JMB363", AHCI_Q_NOFORCE}, 157 {0x2365197b, "JMicron JMB365", AHCI_Q_NOFORCE}, 158 {0x2366197b, "JMicron JMB366", AHCI_Q_NOFORCE}, 159 {0x2368197b, "JMicron JMB368", AHCI_Q_NOFORCE}, 160 {0x611111ab, "Marvell 88SX6111", AHCI_Q_NOFORCE|AHCI_Q_1CH|AHCI_Q_EDGEIS}, 161 {0x612111ab, "Marvell 88SX6121", AHCI_Q_NOFORCE|AHCI_Q_2CH|AHCI_Q_EDGEIS}, 162 {0x614111ab, "Marvell 88SX6141", AHCI_Q_NOFORCE|AHCI_Q_4CH|AHCI_Q_EDGEIS}, 163 {0x614511ab, "Marvell 88SX6145", AHCI_Q_NOFORCE|AHCI_Q_4CH|AHCI_Q_EDGEIS}, 164 {0x044c10de, "NVIDIA MCP65", 0}, 165 {0x044d10de, "NVIDIA MCP65", 0}, 166 {0x044e10de, "NVIDIA MCP65", 0}, 167 {0x044f10de, "NVIDIA MCP65", 0}, 168 {0x045c10de, "NVIDIA MCP65", 0}, 169 {0x045d10de, "NVIDIA MCP65", 0}, 170 {0x045e10de, "NVIDIA MCP65", 0}, 171 {0x045f10de, "NVIDIA MCP65", 0}, 172 {0x055010de, "NVIDIA MCP67", 0}, 173 {0x055110de, "NVIDIA MCP67", 0}, 174 {0x055210de, "NVIDIA MCP67", 0}, 175 {0x055310de, "NVIDIA MCP67", 0}, 176 {0x055410de, "NVIDIA MCP67", 0}, 177 {0x055510de, "NVIDIA MCP67", 0}, 178 {0x055610de, "NVIDIA MCP67", 0}, 179 {0x055710de, "NVIDIA MCP67", 0}, 180 {0x055810de, "NVIDIA MCP67", 0}, 181 {0x055910de, "NVIDIA MCP67", 0}, 182 {0x055A10de, "NVIDIA MCP67", 0}, 183 {0x055B10de, "NVIDIA MCP67", 0}, 184 {0x058410de, "NVIDIA MCP67", 0}, 185 {0x07f010de, "NVIDIA MCP73", 0}, 186 {0x07f110de, "NVIDIA MCP73", 0}, 187 {0x07f210de, "NVIDIA MCP73", 0}, 188 {0x07f310de, "NVIDIA MCP73", 0}, 189 {0x07f410de, "NVIDIA MCP73", 0}, 190 {0x07f510de, "NVIDIA MCP73", 0}, 191 {0x07f610de, "NVIDIA MCP73", 0}, 192 {0x07f710de, "NVIDIA MCP73", 0}, 193 {0x07f810de, "NVIDIA MCP73", 0}, 194 {0x07f910de, "NVIDIA MCP73", 0}, 195 {0x07fa10de, "NVIDIA MCP73", 0}, 196 {0x07fb10de, "NVIDIA MCP73", 0}, 197 {0x0ad010de, "NVIDIA MCP77", 0}, 198 {0x0ad110de, "NVIDIA MCP77", 0}, 199 {0x0ad210de, "NVIDIA MCP77", 0}, 200 {0x0ad310de, "NVIDIA MCP77", 0}, 201 {0x0ad410de, "NVIDIA MCP77", 0}, 202 {0x0ad510de, "NVIDIA MCP77", 0}, 203 {0x0ad610de, "NVIDIA MCP77", 0}, 204 {0x0ad710de, "NVIDIA MCP77", 0}, 205 {0x0ad810de, "NVIDIA MCP77", 0}, 206 {0x0ad910de, "NVIDIA MCP77", 0}, 207 {0x0ada10de, "NVIDIA MCP77", 0}, 208 {0x0adb10de, "NVIDIA MCP77", 0}, 209 {0x0ab410de, "NVIDIA MCP79", 0}, 210 {0x0ab510de, "NVIDIA MCP79", 0}, 211 {0x0ab610de, "NVIDIA MCP79", 0}, 212 {0x0ab710de, "NVIDIA MCP79", 0}, 213 {0x0ab810de, "NVIDIA MCP79", 0}, 214 {0x0ab910de, "NVIDIA MCP79", 0}, 215 {0x0aba10de, "NVIDIA MCP79", 0}, 216 {0x0abb10de, "NVIDIA MCP79", 0}, 217 {0x0abc10de, "NVIDIA MCP79", 0}, 218 {0x0abd10de, "NVIDIA MCP79", 0}, 219 {0x0abe10de, "NVIDIA MCP79", 0}, 220 {0x0abf10de, "NVIDIA MCP79", 0}, 221 {0x0d8410de, "NVIDIA MCP89", 0}, 222 {0x0d8510de, "NVIDIA MCP89", 0}, 223 {0x0d8610de, "NVIDIA MCP89", 0}, 224 {0x0d8710de, "NVIDIA MCP89", 0}, 225 {0x0d8810de, "NVIDIA MCP89", 0}, 226 {0x0d8910de, "NVIDIA MCP89", 0}, 227 {0x0d8a10de, "NVIDIA MCP89", 0}, 228 {0x0d8b10de, "NVIDIA MCP89", 0}, 229 {0x0d8c10de, "NVIDIA MCP89", 0}, 230 {0x0d8d10de, "NVIDIA MCP89", 0}, 231 {0x0d8e10de, "NVIDIA MCP89", 0}, 232 {0x0d8f10de, "NVIDIA MCP89", 0}, 233 {0x33491106, "VIA VT8251", 0}, 234 {0x62871106, "VIA VT8251", 0}, 235 {0x11841039, "SiS 966", 0}, 236 {0x11851039, "SiS 968", 0}, 237 {0x01861039, "SiS 968", 0}, 238 {0, NULL, 0} 239}; 240 241static int 242ahci_probe(device_t dev) 243{ 244 char buf[64]; 245 int i, valid = 0; 246 uint32_t devid = pci_get_devid(dev); 247 248 /* Is this a possible AHCI candidate? */ 249 if (pci_get_class(dev) == PCIC_STORAGE && 250 pci_get_subclass(dev) == PCIS_STORAGE_SATA && 251 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0) 252 valid = 1; 253 /* Is this a known AHCI chip? */ 254 for (i = 0; ahci_ids[i].id != 0; i++) { 255 if (ahci_ids[i].id == devid && 256 (valid || !(ahci_ids[i].quirks & AHCI_Q_NOFORCE))) { 257 /* Do not attach JMicrons with single PCI function. */ 258 if (pci_get_vendor(dev) == 0x197b && 259 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0) 260 return (ENXIO); 261 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 262 ahci_ids[i].name); 263 device_set_desc_copy(dev, buf); 264 return (BUS_PROBE_VENDOR); 265 } 266 } 267 if (!valid) 268 return (ENXIO); 269 device_set_desc_copy(dev, "AHCI SATA controller"); 270 return (BUS_PROBE_VENDOR); 271} 272 273static int 274ahci_ata_probe(device_t dev) 275{ 276 char buf[64]; 277 int i; 278 uint32_t devid = pci_get_devid(dev); 279 280 if ((intptr_t)device_get_ivars(dev) >= 0) 281 return (ENXIO); 282 /* Is this a known AHCI chip? */ 283 for (i = 0; ahci_ids[i].id != 0; i++) { 284 if (ahci_ids[i].id == devid) { 285 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 286 ahci_ids[i].name); 287 device_set_desc_copy(dev, buf); 288 return (BUS_PROBE_VENDOR); 289 } 290 } 291 device_set_desc_copy(dev, "AHCI SATA controller"); 292 return (BUS_PROBE_VENDOR); 293} 294 295static int 296ahci_attach(device_t dev) 297{ 298 struct ahci_controller *ctlr = device_get_softc(dev); 299 device_t child; 300 int error, unit, speed, i; 301 uint32_t devid = pci_get_devid(dev); 302 u_int32_t version; 303 304 ctlr->dev = dev; 305 i = 0; 306 while (ahci_ids[i].id != 0 && ahci_ids[i].id != devid) 307 i++; 308 ctlr->quirks = ahci_ids[i].quirks; 309 resource_int_value(device_get_name(dev), 310 device_get_unit(dev), "ccc", &ctlr->ccc); 311 /* if we have a memory BAR(5) we are likely on an AHCI part */ 312 ctlr->r_rid = PCIR_BAR(5); 313 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 314 &ctlr->r_rid, RF_ACTIVE))) 315 return ENXIO; 316 /* Setup our own memory management for channels. */ 317 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 318 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 319 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 320 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 321 return (error); 322 } 323 if ((error = rman_manage_region(&ctlr->sc_iomem, 324 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 325 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 326 rman_fini(&ctlr->sc_iomem); 327 return (error); 328 } 329 /* Reset controller */ 330 if ((error = ahci_ctlr_reset(dev)) != 0) { 331 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 332 rman_fini(&ctlr->sc_iomem); 333 return (error); 334 }; 335 /* Get the HW capabilities */ 336 version = ATA_INL(ctlr->r_mem, AHCI_VS); 337 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 338 if (version >= 0x00010020) 339 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 340 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 341 if (ctlr->quirks & AHCI_Q_1CH) { 342 ctlr->caps &= ~AHCI_CAP_NPMASK; 343 ctlr->ichannels &= 0x01; 344 } 345 if (ctlr->quirks & AHCI_Q_2CH) { 346 ctlr->caps &= ~AHCI_CAP_NPMASK; 347 ctlr->caps |= 1; 348 ctlr->ichannels &= 0x03; 349 } 350 if (ctlr->quirks & AHCI_Q_4CH) { 351 ctlr->caps &= ~AHCI_CAP_NPMASK; 352 ctlr->caps |= 3; 353 ctlr->ichannels &= 0x0f; 354 } 355 ctlr->channels = MAX(flsl(ctlr->ichannels), 356 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 357 if (ctlr->quirks & AHCI_Q_NOPMP) 358 ctlr->caps &= ~AHCI_CAP_SPM; 359 if (ctlr->quirks & AHCI_Q_NONCQ) 360 ctlr->caps &= ~AHCI_CAP_SNCQ; 361 /* Setup interrupts. */ 362 if (ahci_setup_interrupt(dev)) { 363 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 364 rman_fini(&ctlr->sc_iomem); 365 return ENXIO; 366 } 367 /* Announce HW capabilities. */ 368 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 369 device_printf(dev, 370 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s\n", 371 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 372 ((version >> 4) & 0xf0) + (version & 0x0f), 373 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 374 ((speed == 1) ? "1.5":((speed == 2) ? "3": 375 ((speed == 3) ? "6":"?"))), 376 (ctlr->caps & AHCI_CAP_SPM) ? 377 "supported" : "not supported"); 378 if (bootverbose) { 379 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 380 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 381 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 382 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 383 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 384 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 385 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 386 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 387 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 388 ((speed == 1) ? "1.5":((speed == 2) ? "3": 389 ((speed == 3) ? "6":"?")))); 390 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 391 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 392 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 393 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 394 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 395 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 396 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 397 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 398 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 399 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 400 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 401 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 402 } 403 if (bootverbose && version >= 0x00010020) { 404 device_printf(dev, "Caps2:%s%s%s\n", 405 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 406 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 407 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 408 } 409 /* Attach all channels on this controller */ 410 for (unit = 0; unit < ctlr->channels; unit++) { 411 if ((ctlr->ichannels & (1 << unit)) == 0) 412 continue; 413 child = device_add_child(dev, "ahcich", -1); 414 if (child == NULL) 415 device_printf(dev, "failed to add channel device\n"); 416 else 417 device_set_ivars(child, (void *)(intptr_t)unit); 418 } 419 bus_generic_attach(dev); 420 return 0; 421} 422 423static int 424ahci_detach(device_t dev) 425{ 426 struct ahci_controller *ctlr = device_get_softc(dev); 427 device_t *children; 428 int nchildren, i; 429 430 /* Detach & delete all children */ 431 if (!device_get_children(dev, &children, &nchildren)) { 432 for (i = 0; i < nchildren; i++) 433 device_delete_child(dev, children[i]); 434 free(children, M_TEMP); 435 } 436 /* Free interrupts. */ 437 for (i = 0; i < ctlr->numirqs; i++) { 438 if (ctlr->irqs[i].r_irq) { 439 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 440 ctlr->irqs[i].handle); 441 bus_release_resource(dev, SYS_RES_IRQ, 442 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 443 } 444 } 445 pci_release_msi(dev); 446 /* Free memory. */ 447 rman_fini(&ctlr->sc_iomem); 448 if (ctlr->r_mem) 449 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 450 return (0); 451} 452 453static int 454ahci_ctlr_reset(device_t dev) 455{ 456 struct ahci_controller *ctlr = device_get_softc(dev); 457 int timeout; 458 459 if (pci_read_config(dev, 0x00, 4) == 0x28298086 && 460 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 461 pci_write_config(dev, 0x92, 0x01, 1); 462 /* Enable AHCI mode */ 463 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 464 /* Reset AHCI controller */ 465 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 466 for (timeout = 1000; timeout > 0; timeout--) { 467 DELAY(1000); 468 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 469 break; 470 } 471 if (timeout == 0) { 472 device_printf(dev, "AHCI controller reset failure\n"); 473 return ENXIO; 474 } 475 /* Reenable AHCI mode */ 476 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 477 /* Clear interrupts */ 478 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 479 /* Configure CCC */ 480 if (ctlr->ccc) { 481 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 482 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 483 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 484 (4 << AHCI_CCCC_CC_SHIFT) | 485 AHCI_CCCC_EN); 486 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 487 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 488 if (bootverbose) { 489 device_printf(dev, 490 "CCC with %dms/4cmd enabled on vector %d\n", 491 ctlr->ccc, ctlr->cccv); 492 } 493 } 494 /* Enable AHCI interrupts */ 495 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 496 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 497 return (0); 498} 499 500static int 501ahci_suspend(device_t dev) 502{ 503 struct ahci_controller *ctlr = device_get_softc(dev); 504 505 bus_generic_suspend(dev); 506 /* Disable interupts, so the state change(s) doesn't trigger */ 507 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 508 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 509 return 0; 510} 511 512static int 513ahci_resume(device_t dev) 514{ 515 int res; 516 517 if ((res = ahci_ctlr_reset(dev)) != 0) 518 return (res); 519 return (bus_generic_resume(dev)); 520} 521 522static int 523ahci_setup_interrupt(device_t dev) 524{ 525 struct ahci_controller *ctlr = device_get_softc(dev); 526 int i, msi = 1; 527 528 /* Process hints. */ 529 resource_int_value(device_get_name(dev), 530 device_get_unit(dev), "msi", &msi); 531 if (msi < 0) 532 msi = 0; 533 else if (msi == 1) 534 msi = min(1, pci_msi_count(dev)); 535 else if (msi > 1) 536 msi = pci_msi_count(dev); 537 /* Allocate MSI if needed/present. */ 538 if (msi && pci_alloc_msi(dev, &msi) == 0) { 539 ctlr->numirqs = msi; 540 } else { 541 msi = 0; 542 ctlr->numirqs = 1; 543 } 544 /* Check for single MSI vector fallback. */ 545 if (ctlr->numirqs > 1 && 546 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 547 device_printf(dev, "Falling back to one MSI\n"); 548 ctlr->numirqs = 1; 549 } 550 /* Allocate all IRQs. */ 551 for (i = 0; i < ctlr->numirqs; i++) { 552 ctlr->irqs[i].ctlr = ctlr; 553 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0); 554 if (ctlr->numirqs == 1 || i >= ctlr->channels || 555 (ctlr->ccc && i == ctlr->cccv)) 556 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 557 else if (i == ctlr->numirqs - 1) 558 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 559 else 560 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 561 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 562 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 563 device_printf(dev, "unable to map interrupt\n"); 564 return ENXIO; 565 } 566 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 567 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr, 568 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 569 /* SOS XXX release r_irq */ 570 device_printf(dev, "unable to setup interrupt\n"); 571 return ENXIO; 572 } 573 } 574 return (0); 575} 576 577/* 578 * Common case interrupt handler. 579 */ 580static void 581ahci_intr(void *data) 582{ 583 struct ahci_controller_irq *irq = data; 584 struct ahci_controller *ctlr = irq->ctlr; 585 u_int32_t is; 586 void *arg; 587 int unit; 588 589 if (irq->mode == AHCI_IRQ_MODE_ALL) { 590 unit = 0; 591 if (ctlr->ccc) 592 is = ctlr->ichannels; 593 else 594 is = ATA_INL(ctlr->r_mem, AHCI_IS); 595 } else { /* AHCI_IRQ_MODE_AFTER */ 596 unit = irq->r_irq_rid - 1; 597 is = ATA_INL(ctlr->r_mem, AHCI_IS); 598 } 599 for (; unit < ctlr->channels; unit++) { 600 if ((is & (1 << unit)) != 0 && 601 (arg = ctlr->interrupt[unit].argument)) { 602 if (ctlr->quirks & AHCI_Q_EDGEIS) { 603 /* Some controller have edge triggered IS. */ 604 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 605 ctlr->interrupt[unit].function(arg); 606 } else { 607 /* but AHCI declares level triggered IS. */ 608 ctlr->interrupt[unit].function(arg); 609 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 610 } 611 } 612 } 613} 614 615/* 616 * Simplified interrupt handler for multivector MSI mode. 617 */ 618static void 619ahci_intr_one(void *data) 620{ 621 struct ahci_controller_irq *irq = data; 622 struct ahci_controller *ctlr = irq->ctlr; 623 void *arg; 624 int unit; 625 626 unit = irq->r_irq_rid - 1; 627 if ((arg = ctlr->interrupt[unit].argument)) 628 ctlr->interrupt[unit].function(arg); 629} 630 631static struct resource * 632ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 633 u_long start, u_long end, u_long count, u_int flags) 634{ 635 struct ahci_controller *ctlr = device_get_softc(dev); 636 int unit = ((struct ahci_channel *)device_get_softc(child))->unit; 637 struct resource *res = NULL; 638 int offset = AHCI_OFFSET + (unit << 7); 639 long st; 640 641 switch (type) { 642 case SYS_RES_MEMORY: 643 st = rman_get_start(ctlr->r_mem); 644 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 645 st + offset + 127, 128, RF_ACTIVE, child); 646 if (res) { 647 bus_space_handle_t bsh; 648 bus_space_tag_t bst; 649 bsh = rman_get_bushandle(ctlr->r_mem); 650 bst = rman_get_bustag(ctlr->r_mem); 651 bus_space_subregion(bst, bsh, offset, 128, &bsh); 652 rman_set_bushandle(res, bsh); 653 rman_set_bustag(res, bst); 654 } 655 break; 656 case SYS_RES_IRQ: 657 if (*rid == ATA_IRQ_RID) 658 res = ctlr->irqs[0].r_irq; 659 break; 660 } 661 return (res); 662} 663 664static int 665ahci_release_resource(device_t dev, device_t child, int type, int rid, 666 struct resource *r) 667{ 668 669 switch (type) { 670 case SYS_RES_MEMORY: 671 rman_release_resource(r); 672 return (0); 673 case SYS_RES_IRQ: 674 if (rid != ATA_IRQ_RID) 675 return ENOENT; 676 return (0); 677 } 678 return (EINVAL); 679} 680 681static int 682ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 683 int flags, driver_filter_t *filter, driver_intr_t *function, 684 void *argument, void **cookiep) 685{ 686 struct ahci_controller *ctlr = device_get_softc(dev); 687 int unit = (intptr_t)device_get_ivars(child); 688 689 if (filter != NULL) { 690 printf("ahci.c: we cannot use a filter here\n"); 691 return (EINVAL); 692 } 693 ctlr->interrupt[unit].function = function; 694 ctlr->interrupt[unit].argument = argument; 695 return (0); 696} 697 698static int 699ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 700 void *cookie) 701{ 702 struct ahci_controller *ctlr = device_get_softc(dev); 703 int unit = (intptr_t)device_get_ivars(child); 704 705 ctlr->interrupt[unit].function = NULL; 706 ctlr->interrupt[unit].argument = NULL; 707 return (0); 708} 709 710static int 711ahci_print_child(device_t dev, device_t child) 712{ 713 int retval; 714 715 retval = bus_print_child_header(dev, child); 716 retval += printf(" at channel %d", 717 (int)(intptr_t)device_get_ivars(child)); 718 retval += bus_print_child_footer(dev, child); 719 720 return (retval); 721} 722 723devclass_t ahci_devclass; 724static device_method_t ahci_methods[] = { 725 DEVMETHOD(device_probe, ahci_probe), 726 DEVMETHOD(device_attach, ahci_attach), 727 DEVMETHOD(device_detach, ahci_detach), 728 DEVMETHOD(device_suspend, ahci_suspend), 729 DEVMETHOD(device_resume, ahci_resume), 730 DEVMETHOD(bus_print_child, ahci_print_child), 731 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 732 DEVMETHOD(bus_release_resource, ahci_release_resource), 733 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 734 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 735 { 0, 0 } 736}; 737static driver_t ahci_driver = { 738 "ahci", 739 ahci_methods, 740 sizeof(struct ahci_controller) 741}; 742DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 743static device_method_t ahci_ata_methods[] = { 744 DEVMETHOD(device_probe, ahci_ata_probe), 745 DEVMETHOD(device_attach, ahci_attach), 746 DEVMETHOD(device_detach, ahci_detach), 747 DEVMETHOD(device_suspend, ahci_suspend), 748 DEVMETHOD(device_resume, ahci_resume), 749 DEVMETHOD(bus_print_child, ahci_print_child), 750 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 751 DEVMETHOD(bus_release_resource, ahci_release_resource), 752 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 753 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 754 { 0, 0 } 755}; 756static driver_t ahci_ata_driver = { 757 "ahci", 758 ahci_ata_methods, 759 sizeof(struct ahci_controller) 760}; 761DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0); 762MODULE_VERSION(ahci, 1); 763MODULE_DEPEND(ahci, cam, 1, 1, 1); 764 765static int 766ahci_ch_probe(device_t dev) 767{ 768 769 device_set_desc_copy(dev, "AHCI channel"); 770 return (0); 771} 772 773static int 774ahci_ch_attach(device_t dev) 775{ 776 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 777 struct ahci_channel *ch = device_get_softc(dev); 778 struct cam_devq *devq; 779 int rid, error; 780 781 ch->dev = dev; 782 ch->unit = (intptr_t)device_get_ivars(dev); 783 ch->caps = ctlr->caps; 784 ch->caps2 = ctlr->caps2; 785 ch->quirks = ctlr->quirks; 786 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 787 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 788 resource_int_value(device_get_name(dev), 789 device_get_unit(dev), "pm_level", &ch->pm_level); 790 if (ch->pm_level > 3) 791 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 792 /* Limit speed for my onboard JMicron external port. 793 * It is not eSATA really. */ 794 if (pci_get_devid(ctlr->dev) == 0x2363197b && 795 pci_get_subvendor(ctlr->dev) == 0x1043 && 796 pci_get_subdevice(ctlr->dev) == 0x81e4 && 797 ch->unit == 0) 798 ch->sata_rev = 1; 799 resource_int_value(device_get_name(dev), 800 device_get_unit(dev), "sata_rev", &ch->sata_rev); 801 rid = ch->unit; 802 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 803 &rid, RF_ACTIVE))) 804 return (ENXIO); 805 ahci_dmainit(dev); 806 ahci_slotsalloc(dev); 807 ahci_ch_resume(dev); 808 mtx_lock(&ch->mtx); 809 rid = ATA_IRQ_RID; 810 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 811 &rid, RF_SHAREABLE | RF_ACTIVE))) { 812 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 813 device_printf(dev, "Unable to map interrupt\n"); 814 return (ENXIO); 815 } 816 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 817 ahci_ch_intr_locked, dev, &ch->ih))) { 818 device_printf(dev, "Unable to setup interrupt\n"); 819 error = ENXIO; 820 goto err1; 821 } 822 /* Create the device queue for our SIM. */ 823 devq = cam_simq_alloc(ch->numslots); 824 if (devq == NULL) { 825 device_printf(dev, "Unable to allocate simq\n"); 826 error = ENOMEM; 827 goto err1; 828 } 829 /* Construct SIM entry */ 830 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 831 device_get_unit(dev), &ch->mtx, 832 min(2, ch->numslots), 833 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 834 devq); 835 if (ch->sim == NULL) { 836 device_printf(dev, "unable to allocate sim\n"); 837 error = ENOMEM; 838 goto err2; 839 } 840 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 841 device_printf(dev, "unable to register xpt bus\n"); 842 error = ENXIO; 843 goto err2; 844 } 845 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 846 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 847 device_printf(dev, "unable to create path\n"); 848 error = ENXIO; 849 goto err3; 850 } 851 if (ch->pm_level > 3) { 852 callout_reset(&ch->pm_timer, 853 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 854 ahci_ch_pm, dev); 855 } 856 mtx_unlock(&ch->mtx); 857 return (0); 858 859err3: 860 xpt_bus_deregister(cam_sim_path(ch->sim)); 861err2: 862 cam_sim_free(ch->sim, /*free_devq*/TRUE); 863err1: 864 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 865 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 866 mtx_unlock(&ch->mtx); 867 return (error); 868} 869 870static int 871ahci_ch_detach(device_t dev) 872{ 873 struct ahci_channel *ch = device_get_softc(dev); 874 875 mtx_lock(&ch->mtx); 876 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 877 xpt_free_path(ch->path); 878 xpt_bus_deregister(cam_sim_path(ch->sim)); 879 cam_sim_free(ch->sim, /*free_devq*/TRUE); 880 mtx_unlock(&ch->mtx); 881 882 if (ch->pm_level > 3) 883 callout_drain(&ch->pm_timer); 884 bus_teardown_intr(dev, ch->r_irq, ch->ih); 885 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 886 887 ahci_ch_suspend(dev); 888 ahci_slotsfree(dev); 889 ahci_dmafini(dev); 890 891 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 892 mtx_destroy(&ch->mtx); 893 return (0); 894} 895 896static int 897ahci_ch_suspend(device_t dev) 898{ 899 struct ahci_channel *ch = device_get_softc(dev); 900 901 /* Disable port interrupts. */ 902 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 903 /* Reset command register. */ 904 ahci_stop(dev); 905 ahci_stop_fr(dev); 906 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 907 /* Allow everything, including partial and slumber modes. */ 908 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 909 /* Request slumber mode transition and give some time to get there. */ 910 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 911 DELAY(100); 912 /* Disable PHY. */ 913 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 914 return (0); 915} 916 917static int 918ahci_ch_resume(device_t dev) 919{ 920 struct ahci_channel *ch = device_get_softc(dev); 921 uint64_t work; 922 923 /* Disable port interrupts */ 924 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 925 /* Setup work areas */ 926 work = ch->dma.work_bus + AHCI_CL_OFFSET; 927 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 928 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 929 work = ch->dma.rfis_bus; 930 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 931 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 932 /* Activate the channel and power/spin up device */ 933 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 934 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 935 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 936 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 937 ahci_start_fr(dev); 938 ahci_start(dev); 939 return (0); 940} 941 942devclass_t ahcich_devclass; 943static device_method_t ahcich_methods[] = { 944 DEVMETHOD(device_probe, ahci_ch_probe), 945 DEVMETHOD(device_attach, ahci_ch_attach), 946 DEVMETHOD(device_detach, ahci_ch_detach), 947 DEVMETHOD(device_suspend, ahci_ch_suspend), 948 DEVMETHOD(device_resume, ahci_ch_resume), 949 { 0, 0 } 950}; 951static driver_t ahcich_driver = { 952 "ahcich", 953 ahcich_methods, 954 sizeof(struct ahci_channel) 955}; 956DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0); 957 958struct ahci_dc_cb_args { 959 bus_addr_t maddr; 960 int error; 961}; 962 963static void 964ahci_dmainit(device_t dev) 965{ 966 struct ahci_channel *ch = device_get_softc(dev); 967 struct ahci_dc_cb_args dcba; 968 969 if (ch->caps & AHCI_CAP_64BIT) 970 ch->dma.max_address = BUS_SPACE_MAXADDR; 971 else 972 ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT; 973 /* Command area. */ 974 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 975 ch->dma.max_address, BUS_SPACE_MAXADDR, 976 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 977 0, NULL, NULL, &ch->dma.work_tag)) 978 goto error; 979 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0, 980 &ch->dma.work_map)) 981 goto error; 982 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 983 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 984 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 985 goto error; 986 } 987 ch->dma.work_bus = dcba.maddr; 988 /* FIS receive area. */ 989 if (bus_dma_tag_create(bus_get_dma_tag(dev), 4096, 0, 990 ch->dma.max_address, BUS_SPACE_MAXADDR, 991 NULL, NULL, 4096, 1, 4096, 992 0, NULL, NULL, &ch->dma.rfis_tag)) 993 goto error; 994 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 995 &ch->dma.rfis_map)) 996 goto error; 997 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 998 4096, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 999 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1000 goto error; 1001 } 1002 ch->dma.rfis_bus = dcba.maddr; 1003 /* Data area. */ 1004 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1005 ch->dma.max_address, BUS_SPACE_MAXADDR, 1006 NULL, NULL, 1007 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1008 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1009 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 1010 goto error; 1011 } 1012 return; 1013 1014error: 1015 device_printf(dev, "WARNING - DMA initialization failed\n"); 1016 ahci_dmafini(dev); 1017} 1018 1019static void 1020ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1021{ 1022 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1023 1024 if (!(dcba->error = error)) 1025 dcba->maddr = segs[0].ds_addr; 1026} 1027 1028static void 1029ahci_dmafini(device_t dev) 1030{ 1031 struct ahci_channel *ch = device_get_softc(dev); 1032 1033 if (ch->dma.data_tag) { 1034 bus_dma_tag_destroy(ch->dma.data_tag); 1035 ch->dma.data_tag = NULL; 1036 } 1037 if (ch->dma.rfis_bus) { 1038 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1039 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1040 ch->dma.rfis_bus = 0; 1041 ch->dma.rfis_map = NULL; 1042 ch->dma.rfis = NULL; 1043 } 1044 if (ch->dma.work_bus) { 1045 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1046 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1047 ch->dma.work_bus = 0; 1048 ch->dma.work_map = NULL; 1049 ch->dma.work = NULL; 1050 } 1051 if (ch->dma.work_tag) { 1052 bus_dma_tag_destroy(ch->dma.work_tag); 1053 ch->dma.work_tag = NULL; 1054 } 1055} 1056 1057static void 1058ahci_slotsalloc(device_t dev) 1059{ 1060 struct ahci_channel *ch = device_get_softc(dev); 1061 int i; 1062 1063 /* Alloc and setup command/dma slots */ 1064 bzero(ch->slot, sizeof(ch->slot)); 1065 for (i = 0; i < ch->numslots; i++) { 1066 struct ahci_slot *slot = &ch->slot[i]; 1067 1068 slot->dev = dev; 1069 slot->slot = i; 1070 slot->state = AHCI_SLOT_EMPTY; 1071 slot->ccb = NULL; 1072 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1073 1074 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1075 device_printf(ch->dev, "FAILURE - create data_map\n"); 1076 } 1077} 1078 1079static void 1080ahci_slotsfree(device_t dev) 1081{ 1082 struct ahci_channel *ch = device_get_softc(dev); 1083 int i; 1084 1085 /* Free all dma slots */ 1086 for (i = 0; i < ch->numslots; i++) { 1087 struct ahci_slot *slot = &ch->slot[i]; 1088 1089 callout_drain(&slot->timeout); 1090 if (slot->dma.data_map) { 1091 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1092 slot->dma.data_map = NULL; 1093 } 1094 } 1095} 1096 1097static void 1098ahci_phy_check_events(device_t dev, u_int32_t serr) 1099{ 1100 struct ahci_channel *ch = device_get_softc(dev); 1101 1102 if ((serr & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) { 1103 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1104 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 1105 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 1106 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) { 1107 if (bootverbose) 1108 device_printf(dev, "CONNECT requested\n"); 1109 ahci_reset(dev); 1110 } else { 1111 if (bootverbose) 1112 device_printf(dev, "DISCONNECT requested\n"); 1113 ch->devices = 0; 1114 } 1115 } 1116} 1117 1118static void 1119ahci_notify_events(device_t dev, u_int32_t status) 1120{ 1121 struct ahci_channel *ch = device_get_softc(dev); 1122 struct cam_path *dpath; 1123 int i; 1124 1125 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1126 if (bootverbose) 1127 device_printf(dev, "SNTF 0x%04x\n", status); 1128 for (i = 0; i < 16; i++) { 1129 if ((status & (1 << i)) == 0) 1130 continue; 1131 if (xpt_create_path(&dpath, NULL, 1132 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1133 xpt_async(AC_SCSI_AEN, dpath, NULL); 1134 xpt_free_path(dpath); 1135 } 1136 } 1137} 1138 1139static void 1140ahci_ch_intr_locked(void *data) 1141{ 1142 device_t dev = (device_t)data; 1143 struct ahci_channel *ch = device_get_softc(dev); 1144 1145 mtx_lock(&ch->mtx); 1146 ahci_ch_intr(data); 1147 mtx_unlock(&ch->mtx); 1148} 1149 1150static void 1151ahci_ch_pm(void *arg) 1152{ 1153 device_t dev = (device_t)arg; 1154 struct ahci_channel *ch = device_get_softc(dev); 1155 uint32_t work; 1156 1157 if (ch->numrslots != 0) 1158 return; 1159 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1160 if (ch->pm_level == 4) 1161 work |= AHCI_P_CMD_PARTIAL; 1162 else 1163 work |= AHCI_P_CMD_SLUMBER; 1164 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1165} 1166 1167static void 1168ahci_ch_intr(void *data) 1169{ 1170 device_t dev = (device_t)data; 1171 struct ahci_channel *ch = device_get_softc(dev); 1172 uint32_t istatus, sstatus, cstatus, serr = 0, sntf = 0, ok, err; 1173 enum ahci_err_type et; 1174 int i, ccs, ncq_err = 0; 1175 1176 /* Read and clear interrupt statuses. */ 1177 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1178 if (istatus == 0) 1179 return; 1180 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1181 /* Read command statuses. */ 1182 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1183 cstatus = ATA_INL(ch->r_mem, AHCI_P_CI); 1184 if ((istatus & AHCI_P_IX_SDB) && (ch->caps & AHCI_CAP_SSNTF)) 1185 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1186 /* Process PHY events */ 1187 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1188 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1189 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1190 if (serr) { 1191 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1192 ahci_phy_check_events(dev, serr); 1193 } 1194 } 1195 /* Process command errors */ 1196 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1197 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1198//device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x\n", 1199// __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1200// serr); 1201 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1202 >> AHCI_P_CMD_CCS_SHIFT; 1203 err = ch->rslots & (cstatus | sstatus); 1204 /* Kick controller into sane state */ 1205 ahci_stop(dev); 1206 ahci_start(dev); 1207 } else { 1208 ccs = 0; 1209 err = 0; 1210 } 1211 /* Complete all successfull commands. */ 1212 ok = ch->rslots & ~(cstatus | sstatus); 1213 for (i = 0; i < ch->numslots; i++) { 1214 if ((ok >> i) & 1) 1215 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1216 } 1217 /* On error, complete the rest of commands with error statuses. */ 1218 if (err) { 1219 if (ch->frozen) { 1220 union ccb *fccb = ch->frozen; 1221 ch->frozen = NULL; 1222 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1223 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1224 xpt_freeze_devq(fccb->ccb_h.path, 1); 1225 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1226 } 1227 xpt_done(fccb); 1228 } 1229 for (i = 0; i < ch->numslots; i++) { 1230 /* XXX: reqests in loading state. */ 1231 if (((err >> i) & 1) == 0) 1232 continue; 1233 if (istatus & AHCI_P_IX_TFE) { 1234 /* Task File Error */ 1235 if (ch->numtslots == 0) { 1236 /* Untagged operation. */ 1237 if (i == ccs) 1238 et = AHCI_ERR_TFE; 1239 else 1240 et = AHCI_ERR_INNOCENT; 1241 } else { 1242 /* Tagged operation. */ 1243 et = AHCI_ERR_NCQ; 1244 ncq_err = 1; 1245 } 1246 } else if (istatus & AHCI_P_IX_IF) { 1247 if (ch->numtslots == 0 && i != ccs) 1248 et = AHCI_ERR_INNOCENT; 1249 else 1250 et = AHCI_ERR_SATA; 1251 } else 1252 et = AHCI_ERR_INVALID; 1253 ahci_end_transaction(&ch->slot[i], et); 1254 } 1255 if (ncq_err) 1256 ahci_issue_read_log(dev); 1257 } 1258 /* Process NOTIFY events */ 1259 if (sntf) 1260 ahci_notify_events(dev, sntf); 1261} 1262 1263/* Must be called with channel locked. */ 1264static int 1265ahci_check_collision(device_t dev, union ccb *ccb) 1266{ 1267 struct ahci_channel *ch = device_get_softc(dev); 1268 1269 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1270 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1271 /* Tagged command while untagged are active. */ 1272 if (ch->numrslots != 0 && ch->numtslots == 0) 1273 return (1); 1274 /* Tagged command while tagged to other target is active. */ 1275 if (ch->numtslots != 0 && 1276 ch->taggedtarget != ccb->ccb_h.target_id) 1277 return (1); 1278 } else { 1279 /* Untagged command while tagged are active. */ 1280 if (ch->numrslots != 0 && ch->numtslots != 0) 1281 return (1); 1282 } 1283 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1284 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1285 /* Atomic command while anything active. */ 1286 if (ch->numrslots != 0) 1287 return (1); 1288 } 1289 /* We have some atomic command running. */ 1290 if (ch->aslots != 0) 1291 return (1); 1292 return (0); 1293} 1294 1295/* Must be called with channel locked. */ 1296static void 1297ahci_begin_transaction(device_t dev, union ccb *ccb) 1298{ 1299 struct ahci_channel *ch = device_get_softc(dev); 1300 struct ahci_slot *slot; 1301 int tag; 1302 1303 /* Choose empty slot. */ 1304 tag = ch->lastslot; 1305 while (ch->slot[tag].state != AHCI_SLOT_EMPTY) { 1306 if (++tag >= ch->numslots) 1307 tag = 0; 1308 KASSERT(tag != ch->lastslot, ("ahci: ALL SLOTS BUSY!")); 1309 } 1310 ch->lastslot = tag; 1311 /* Occupy chosen slot. */ 1312 slot = &ch->slot[tag]; 1313 slot->ccb = ccb; 1314 /* Stop PM timer. */ 1315 if (ch->numrslots == 0 && ch->pm_level > 3) 1316 callout_stop(&ch->pm_timer); 1317 /* Update channel stats. */ 1318 ch->numrslots++; 1319 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1320 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1321 ch->numtslots++; 1322 ch->taggedtarget = ccb->ccb_h.target_id; 1323 } 1324 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1325 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1326 ch->aslots |= (1 << slot->slot); 1327 slot->dma.nsegs = 0; 1328 /* If request moves data, setup and load SG list */ 1329 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1330 void *buf; 1331 bus_size_t size; 1332 1333 slot->state = AHCI_SLOT_LOADING; 1334 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1335 buf = ccb->ataio.data_ptr; 1336 size = ccb->ataio.dxfer_len; 1337 } else { 1338 buf = ccb->csio.data_ptr; 1339 size = ccb->csio.dxfer_len; 1340 } 1341 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1342 buf, size, ahci_dmasetprd, slot, 0); 1343 } else 1344 ahci_execute_transaction(slot); 1345} 1346 1347/* Locked by busdma engine. */ 1348static void 1349ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1350{ 1351 struct ahci_slot *slot = arg; 1352 struct ahci_channel *ch = device_get_softc(slot->dev); 1353 struct ahci_cmd_tab *ctp; 1354 struct ahci_dma_prd *prd; 1355 int i; 1356 1357 if (error) { 1358 device_printf(slot->dev, "DMA load error\n"); 1359 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1360 return; 1361 } 1362 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1363 /* Get a piece of the workspace for this request */ 1364 ctp = (struct ahci_cmd_tab *) 1365 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1366 /* Fill S/G table */ 1367 prd = &ctp->prd_tab[0]; 1368 for (i = 0; i < nsegs; i++) { 1369 prd[i].dba = htole64(segs[i].ds_addr); 1370 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1371 } 1372 slot->dma.nsegs = nsegs; 1373 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1374 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1375 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1376 ahci_execute_transaction(slot); 1377} 1378 1379/* Must be called with channel locked. */ 1380static void 1381ahci_execute_transaction(struct ahci_slot *slot) 1382{ 1383 device_t dev = slot->dev; 1384 struct ahci_channel *ch = device_get_softc(dev); 1385 struct ahci_cmd_tab *ctp; 1386 struct ahci_cmd_list *clp; 1387 union ccb *ccb = slot->ccb; 1388 int port = ccb->ccb_h.target_id & 0x0f; 1389 int fis_size; 1390 1391 /* Get a piece of the workspace for this request */ 1392 ctp = (struct ahci_cmd_tab *) 1393 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1394 /* Setup the FIS for this request */ 1395 if (!(fis_size = ahci_setup_fis(ctp, ccb, slot->slot))) { 1396 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1397 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1398 return; 1399 } 1400 /* Setup the command list entry */ 1401 clp = (struct ahci_cmd_list *) 1402 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1403 clp->prd_length = slot->dma.nsegs; 1404 clp->cmd_flags = (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1405 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1406 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1407 (fis_size / sizeof(u_int32_t)) | 1408 (port << 12); 1409 /* Special handling for Soft Reset command. */ 1410 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1411 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1412 (ccb->ataio.cmd.control & ATA_A_RESET)) { 1413 /* Kick controller into sane state */ 1414 ahci_stop(dev); 1415 ahci_clo(dev); 1416 ahci_start(dev); 1417 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1418 } 1419 clp->bytecount = 0; 1420 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1421 (AHCI_CT_SIZE * slot->slot)); 1422 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1423 BUS_DMASYNC_PREWRITE); 1424 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1425 BUS_DMASYNC_PREREAD); 1426 /* Set ACTIVE bit for NCQ commands. */ 1427 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1428 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1429 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1430 } 1431 /* Issue command to the controller. */ 1432 slot->state = AHCI_SLOT_RUNNING; 1433 ch->rslots |= (1 << slot->slot); 1434 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1435 /* Device reset commands doesn't interrupt. Poll them. */ 1436 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1437 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || 1438 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL))) { 1439 int count, timeout = ccb->ccb_h.timeout; 1440 enum ahci_err_type et = AHCI_ERR_NONE; 1441 1442 for (count = 0; count < timeout; count++) { 1443 DELAY(1000); 1444 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1445 break; 1446 if (ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) { 1447 device_printf(ch->dev, 1448 "Poll error on slot %d, TFD: %04x\n", 1449 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1450 et = AHCI_ERR_TFE; 1451 break; 1452 } 1453 /* Workaround for ATI SB600/SB700 chipsets. */ 1454 if (ccb->ccb_h.target_id == 15 && 1455 pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1456 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1457 et = AHCI_ERR_TIMEOUT; 1458 break; 1459 } 1460 } 1461 if (timeout && (count >= timeout)) { 1462 device_printf(ch->dev, 1463 "Poll timeout on slot %d\n", slot->slot); 1464 et = AHCI_ERR_TIMEOUT; 1465 } 1466 if (et != AHCI_ERR_NONE) { 1467 /* Kick controller into sane state */ 1468 ahci_stop(ch->dev); 1469 ahci_start(ch->dev); 1470 } 1471 ahci_end_transaction(slot, et); 1472 return; 1473 } 1474 /* Start command execution timeout */ 1475 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 1476 (timeout_t*)ahci_timeout, slot); 1477 return; 1478} 1479 1480/* Locked by callout mechanism. */ 1481static void 1482ahci_timeout(struct ahci_slot *slot) 1483{ 1484 device_t dev = slot->dev; 1485 struct ahci_channel *ch = device_get_softc(dev); 1486 uint32_t sstatus; 1487 int ccs; 1488 int i; 1489 1490 /* Check for stale timeout. */ 1491 if (slot->state < AHCI_SLOT_RUNNING) 1492 return; 1493 1494 /* Check if slot was not being executed last time we checked. */ 1495 if (slot->state < AHCI_SLOT_EXECUTING) { 1496 /* Check if slot started executing. */ 1497 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1498 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1499 >> AHCI_P_CMD_CCS_SHIFT; 1500 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot) 1501 slot->state = AHCI_SLOT_EXECUTING; 1502 1503 callout_reset(&slot->timeout, 1504 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1505 (timeout_t*)ahci_timeout, slot); 1506 return; 1507 } 1508 1509 device_printf(dev, "Timeout on slot %d\n", slot->slot); 1510 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x\n", 1511 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1512 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1513 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR)); 1514 1515 ch->fatalerr = 1; 1516 /* Handle frozen command. */ 1517 if (ch->frozen) { 1518 union ccb *fccb = ch->frozen; 1519 ch->frozen = NULL; 1520 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1521 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1522 xpt_freeze_devq(fccb->ccb_h.path, 1); 1523 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1524 } 1525 xpt_done(fccb); 1526 } 1527 /* Handle command with timeout. */ 1528 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 1529 /* Handle the rest of commands. */ 1530 for (i = 0; i < ch->numslots; i++) { 1531 /* Do we have a running request on slot? */ 1532 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1533 continue; 1534 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1535 } 1536} 1537 1538/* Must be called with channel locked. */ 1539static void 1540ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 1541{ 1542 device_t dev = slot->dev; 1543 struct ahci_channel *ch = device_get_softc(dev); 1544 union ccb *ccb = slot->ccb; 1545 1546 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1547 BUS_DMASYNC_POSTWRITE); 1548 /* Read result registers to the result struct 1549 * May be incorrect if several commands finished same time, 1550 * so read only when sure or have to. 1551 */ 1552 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1553 struct ata_res *res = &ccb->ataio.res; 1554 1555 if ((et == AHCI_ERR_TFE) || 1556 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1557 u_int8_t *fis = ch->dma.rfis + 0x40; 1558 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 1559 1560 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1561 BUS_DMASYNC_POSTREAD); 1562 res->status = tfd; 1563 res->error = tfd >> 8; 1564 res->lba_low = fis[4]; 1565 res->lba_mid = fis[5]; 1566 res->lba_high = fis[6]; 1567 res->device = fis[7]; 1568 res->lba_low_exp = fis[8]; 1569 res->lba_mid_exp = fis[9]; 1570 res->lba_high_exp = fis[10]; 1571 res->sector_count = fis[12]; 1572 res->sector_count_exp = fis[13]; 1573 } else 1574 bzero(res, sizeof(*res)); 1575 } 1576 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1577 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1578 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1579 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1580 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1581 } 1582 /* In case of error, freeze device for proper recovery. */ 1583 if ((et != AHCI_ERR_NONE) && (!ch->readlog) && 1584 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 1585 xpt_freeze_devq(ccb->ccb_h.path, 1); 1586 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1587 } 1588 /* Set proper result status. */ 1589 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1590 switch (et) { 1591 case AHCI_ERR_NONE: 1592 ccb->ccb_h.status |= CAM_REQ_CMP; 1593 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1594 ccb->csio.scsi_status = SCSI_STATUS_OK; 1595 break; 1596 case AHCI_ERR_INVALID: 1597 ch->fatalerr = 1; 1598 ccb->ccb_h.status |= CAM_REQ_INVALID; 1599 break; 1600 case AHCI_ERR_INNOCENT: 1601 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1602 break; 1603 case AHCI_ERR_TFE: 1604 case AHCI_ERR_NCQ: 1605 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1606 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1607 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1608 } else { 1609 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1610 } 1611 break; 1612 case AHCI_ERR_SATA: 1613 ch->fatalerr = 1; 1614 if (!ch->readlog) { 1615 xpt_freeze_simq(ch->sim, 1); 1616 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1617 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1618 } 1619 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1620 break; 1621 case AHCI_ERR_TIMEOUT: 1622 /* Do no treat soft-reset timeout as fatal here. */ 1623 if (ccb->ccb_h.func_code != XPT_ATA_IO || 1624 !(ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) 1625 ch->fatalerr = 1; 1626 if (!ch->readlog) { 1627 xpt_freeze_simq(ch->sim, 1); 1628 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1629 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1630 } 1631 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1632 break; 1633 default: 1634 ch->fatalerr = 1; 1635 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1636 } 1637 /* Free slot. */ 1638 ch->rslots &= ~(1 << slot->slot); 1639 ch->aslots &= ~(1 << slot->slot); 1640 slot->state = AHCI_SLOT_EMPTY; 1641 slot->ccb = NULL; 1642 /* Update channel stats. */ 1643 ch->numrslots--; 1644 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1645 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1646 ch->numtslots--; 1647 } 1648 /* If it was first request of reset sequence and there is no error, 1649 * proceed to second request. */ 1650 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1651 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1652 (ccb->ataio.cmd.control & ATA_A_RESET) && 1653 et == AHCI_ERR_NONE) { 1654 ccb->ataio.cmd.control &= ~ATA_A_RESET; 1655 ahci_begin_transaction(dev, ccb); 1656 return; 1657 } 1658 /* If it was our READ LOG command - process it. */ 1659 if (ch->readlog) { 1660 ahci_process_read_log(dev, ccb); 1661 /* If it was NCQ command error, put result on hold. */ 1662 } else if (et == AHCI_ERR_NCQ) { 1663 ch->hold[slot->slot] = ccb; 1664 } else 1665 xpt_done(ccb); 1666 /* Unfreeze frozen command. */ 1667 if (ch->frozen && ch->numrslots == 0) { 1668 union ccb *fccb = ch->frozen; 1669 ch->frozen = NULL; 1670 ahci_begin_transaction(dev, fccb); 1671 xpt_release_simq(ch->sim, TRUE); 1672 } 1673 /* If we have no other active commands, ... */ 1674 if (ch->rslots == 0) { 1675 /* if there was fatal error - reset port. */ 1676 if (ch->fatalerr) { 1677 ahci_reset(dev); 1678 } 1679 } 1680 /* Start PM timer. */ 1681 if (ch->numrslots == 0 && ch->pm_level > 3) { 1682 callout_schedule(&ch->pm_timer, 1683 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 1684 } 1685} 1686 1687static void 1688ahci_issue_read_log(device_t dev) 1689{ 1690 struct ahci_channel *ch = device_get_softc(dev); 1691 union ccb *ccb; 1692 struct ccb_ataio *ataio; 1693 int i; 1694 1695 ch->readlog = 1; 1696 /* Find some holden command. */ 1697 for (i = 0; i < ch->numslots; i++) { 1698 if (ch->hold[i]) 1699 break; 1700 } 1701 ccb = xpt_alloc_ccb_nowait(); 1702 if (ccb == NULL) { 1703 device_printf(dev, "Unable allocate READ LOG command"); 1704 return; /* XXX */ 1705 } 1706 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 1707 ccb->ccb_h.func_code = XPT_ATA_IO; 1708 ccb->ccb_h.flags = CAM_DIR_IN; 1709 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1710 ataio = &ccb->ataio; 1711 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 1712 if (ataio->data_ptr == NULL) { 1713 device_printf(dev, "Unable allocate memory for READ LOG command"); 1714 return; /* XXX */ 1715 } 1716 ataio->dxfer_len = 512; 1717 bzero(&ataio->cmd, sizeof(ataio->cmd)); 1718 ataio->cmd.flags = CAM_ATAIO_48BIT; 1719 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 1720 ataio->cmd.sector_count = 1; 1721 ataio->cmd.sector_count_exp = 0; 1722 ataio->cmd.lba_low = 0x10; 1723 ataio->cmd.lba_mid = 0; 1724 ataio->cmd.lba_mid_exp = 0; 1725 /* Freeze SIM while doing READ LOG EXT. */ 1726 xpt_freeze_simq(ch->sim, 1); 1727 ahci_begin_transaction(dev, ccb); 1728} 1729 1730static void 1731ahci_process_read_log(device_t dev, union ccb *ccb) 1732{ 1733 struct ahci_channel *ch = device_get_softc(dev); 1734 uint8_t *data; 1735 struct ata_res *res; 1736 int i; 1737 1738 ch->readlog = 0; 1739 1740 data = ccb->ataio.data_ptr; 1741 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 1742 (data[0] & 0x80) == 0) { 1743 for (i = 0; i < ch->numslots; i++) { 1744 if (!ch->hold[i]) 1745 continue; 1746 if ((data[0] & 0x1F) == i) { 1747 res = &ch->hold[i]->ataio.res; 1748 res->status = data[2]; 1749 res->error = data[3]; 1750 res->lba_low = data[4]; 1751 res->lba_mid = data[5]; 1752 res->lba_high = data[6]; 1753 res->device = data[7]; 1754 res->lba_low_exp = data[8]; 1755 res->lba_mid_exp = data[9]; 1756 res->lba_high_exp = data[10]; 1757 res->sector_count = data[12]; 1758 res->sector_count_exp = data[13]; 1759 } else { 1760 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1761 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 1762 } 1763 xpt_done(ch->hold[i]); 1764 ch->hold[i] = NULL; 1765 } 1766 } else { 1767 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 1768 device_printf(dev, "Error while READ LOG EXT\n"); 1769 else if ((data[0] & 0x80) == 0) { 1770 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 1771 } 1772 for (i = 0; i < ch->numslots; i++) { 1773 if (!ch->hold[i]) 1774 continue; 1775 xpt_done(ch->hold[i]); 1776 ch->hold[i] = NULL; 1777 } 1778 } 1779 free(ccb->ataio.data_ptr, M_AHCI); 1780 xpt_free_ccb(ccb); 1781 xpt_release_simq(ch->sim, TRUE); 1782} 1783 1784static void 1785ahci_start(device_t dev) 1786{ 1787 struct ahci_channel *ch = device_get_softc(dev); 1788 u_int32_t cmd; 1789 1790 /* Clear SATA error register */ 1791 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 1792 /* Clear any interrupts pending on this channel */ 1793 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 1794 /* Start operations on this channel */ 1795 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1796 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 1797 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 1798} 1799 1800static void 1801ahci_stop(device_t dev) 1802{ 1803 struct ahci_channel *ch = device_get_softc(dev); 1804 u_int32_t cmd; 1805 int timeout; 1806 1807 /* Kill all activity on this channel */ 1808 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1809 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 1810 /* Wait for activity stop. */ 1811 timeout = 0; 1812 do { 1813 DELAY(1000); 1814 if (timeout++ > 1000) { 1815 device_printf(dev, "stopping AHCI engine failed\n"); 1816 break; 1817 } 1818 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 1819} 1820 1821static void 1822ahci_clo(device_t dev) 1823{ 1824 struct ahci_channel *ch = device_get_softc(dev); 1825 u_int32_t cmd; 1826 int timeout; 1827 1828 /* Issue Command List Override if supported */ 1829 if (ch->caps & AHCI_CAP_SCLO) { 1830 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1831 cmd |= AHCI_P_CMD_CLO; 1832 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 1833 timeout = 0; 1834 do { 1835 DELAY(1000); 1836 if (timeout++ > 1000) { 1837 device_printf(dev, "executing CLO failed\n"); 1838 break; 1839 } 1840 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 1841 } 1842} 1843 1844static void 1845ahci_stop_fr(device_t dev) 1846{ 1847 struct ahci_channel *ch = device_get_softc(dev); 1848 u_int32_t cmd; 1849 int timeout; 1850 1851 /* Kill all FIS reception on this channel */ 1852 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1853 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 1854 /* Wait for FIS reception stop. */ 1855 timeout = 0; 1856 do { 1857 DELAY(1000); 1858 if (timeout++ > 1000) { 1859 device_printf(dev, "stopping AHCI FR engine failed\n"); 1860 break; 1861 } 1862 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 1863} 1864 1865static void 1866ahci_start_fr(device_t dev) 1867{ 1868 struct ahci_channel *ch = device_get_softc(dev); 1869 u_int32_t cmd; 1870 1871 /* Start FIS reception on this channel */ 1872 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1873 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 1874} 1875 1876static int 1877ahci_wait_ready(device_t dev, int t) 1878{ 1879 struct ahci_channel *ch = device_get_softc(dev); 1880 int timeout = 0; 1881 uint32_t val; 1882 1883 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 1884 (ATA_S_BUSY | ATA_S_DRQ)) { 1885 DELAY(1000); 1886 if (timeout++ > t) { 1887 device_printf(dev, "port is not ready (timeout %dms) " 1888 "tfd = %08x\n", t, val); 1889 return (EBUSY); 1890 } 1891 } 1892 if (bootverbose) 1893 device_printf(dev, "ready wait time=%dms\n", timeout); 1894 return (0); 1895} 1896 1897static void 1898ahci_reset(device_t dev) 1899{ 1900 struct ahci_channel *ch = device_get_softc(dev); 1901 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1902 int i; 1903 1904 if (bootverbose) 1905 device_printf(dev, "AHCI reset...\n"); 1906 /* Requeue freezed command. */ 1907 if (ch->frozen) { 1908 union ccb *fccb = ch->frozen; 1909 ch->frozen = NULL; 1910 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1911 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1912 xpt_freeze_devq(fccb->ccb_h.path, 1); 1913 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1914 } 1915 xpt_done(fccb); 1916 } 1917 /* Kill the engine and requeue all running commands. */ 1918 ahci_stop(dev); 1919 for (i = 0; i < ch->numslots; i++) { 1920 /* Do we have a running request on slot? */ 1921 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1922 continue; 1923 /* XXX; Commands in loading state. */ 1924 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1925 } 1926 for (i = 0; i < ch->numslots; i++) { 1927 if (!ch->hold[i]) 1928 continue; 1929 xpt_done(ch->hold[i]); 1930 ch->hold[i] = NULL; 1931 } 1932 ch->fatalerr = 0; 1933 /* Tell the XPT about the event */ 1934 xpt_async(AC_BUS_RESET, ch->path, NULL); 1935 /* Disable port interrupts */ 1936 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1937 /* Reset and reconnect PHY, */ 1938 if (!ahci_sata_phy_reset(dev, 0)) { 1939 if (bootverbose) 1940 device_printf(dev, 1941 "AHCI reset done: phy reset found no device\n"); 1942 ch->devices = 0; 1943 /* Enable wanted port interrupts */ 1944 ATA_OUTL(ch->r_mem, AHCI_P_IE, 1945 (AHCI_P_IX_CPD | AHCI_P_IX_PRC | AHCI_P_IX_PC)); 1946 return; 1947 } 1948 /* Wait for clearing busy status. */ 1949 if (ahci_wait_ready(dev, 10000)) { 1950 device_printf(dev, "device ready timeout\n"); 1951 ahci_clo(dev); 1952 } 1953 ahci_start(dev); 1954 ch->devices = 1; 1955 /* Enable wanted port interrupts */ 1956 ATA_OUTL(ch->r_mem, AHCI_P_IE, 1957 (AHCI_P_IX_CPD | AHCI_P_IX_TFE | AHCI_P_IX_HBF | 1958 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 1959 ((ch->pm_level == 0) ? AHCI_P_IX_PRC | AHCI_P_IX_PC : 0) | 1960 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 1961 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 1962 if (bootverbose) 1963 device_printf(dev, "AHCI reset done: device found\n"); 1964} 1965 1966static int 1967ahci_setup_fis(struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 1968{ 1969 u_int8_t *fis = &ctp->cfis[0]; 1970 1971 bzero(ctp->cfis, 64); 1972 fis[0] = 0x27; /* host to device */ 1973 fis[1] = (ccb->ccb_h.target_id & 0x0f); 1974 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1975 fis[1] |= 0x80; 1976 fis[2] = ATA_PACKET_CMD; 1977 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) 1978 fis[3] = ATA_F_DMA; 1979 else { 1980 fis[5] = ccb->csio.dxfer_len; 1981 fis[6] = ccb->csio.dxfer_len >> 8; 1982 } 1983 fis[7] = ATA_D_LBA; 1984 fis[15] = ATA_A_4BIT; 1985 bzero(ctp->acmd, 32); 1986 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 1987 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 1988 ctp->acmd, ccb->csio.cdb_len); 1989 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 1990 fis[1] |= 0x80; 1991 fis[2] = ccb->ataio.cmd.command; 1992 fis[3] = ccb->ataio.cmd.features; 1993 fis[4] = ccb->ataio.cmd.lba_low; 1994 fis[5] = ccb->ataio.cmd.lba_mid; 1995 fis[6] = ccb->ataio.cmd.lba_high; 1996 fis[7] = ccb->ataio.cmd.device; 1997 fis[8] = ccb->ataio.cmd.lba_low_exp; 1998 fis[9] = ccb->ataio.cmd.lba_mid_exp; 1999 fis[10] = ccb->ataio.cmd.lba_high_exp; 2000 fis[11] = ccb->ataio.cmd.features_exp; 2001 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2002 fis[12] = tag << 3; 2003 fis[13] = 0; 2004 } else { 2005 fis[12] = ccb->ataio.cmd.sector_count; 2006 fis[13] = ccb->ataio.cmd.sector_count_exp; 2007 } 2008 fis[15] = ATA_A_4BIT; 2009 } else { 2010 fis[15] = ccb->ataio.cmd.control; 2011 } 2012 return (20); 2013} 2014 2015static int 2016ahci_sata_connect(struct ahci_channel *ch) 2017{ 2018 u_int32_t status; 2019 int timeout; 2020 2021 /* Wait up to 100ms for "connect well" */ 2022 for (timeout = 0; timeout < 100 ; timeout++) { 2023 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2024 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2025 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2026 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2027 break; 2028 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2029 if (bootverbose) { 2030 device_printf(ch->dev, "SATA offline status=%08x\n", 2031 status); 2032 } 2033 return (0); 2034 } 2035 DELAY(1000); 2036 } 2037 if (timeout >= 100) { 2038 if (bootverbose) { 2039 device_printf(ch->dev, "SATA connect timeout status=%08x\n", 2040 status); 2041 } 2042 return (0); 2043 } 2044 if (bootverbose) { 2045 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n", 2046 timeout, status); 2047 } 2048 /* Clear SATA error register */ 2049 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2050 return (1); 2051} 2052 2053static int 2054ahci_sata_phy_reset(device_t dev, int quick) 2055{ 2056 struct ahci_channel *ch = device_get_softc(dev); 2057 uint32_t val; 2058 2059 if (quick) { 2060 val = ATA_INL(ch->r_mem, AHCI_P_SCTL); 2061 if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) 2062 return (ahci_sata_connect(ch)); 2063 } 2064 2065 if (bootverbose) 2066 device_printf(dev, "hardware reset ...\n"); 2067 if (ch->sata_rev == 1) 2068 val = ATA_SC_SPD_SPEED_GEN1; 2069 else if (ch->sata_rev == 2) 2070 val = ATA_SC_SPD_SPEED_GEN2; 2071 else if (ch->sata_rev == 3) 2072 val = ATA_SC_SPD_SPEED_GEN3; 2073 else 2074 val = 0; 2075 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2076 ATA_SC_DET_RESET | val | 2077 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2078 DELAY(5000); 2079 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2080 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2081 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2082 DELAY(5000); 2083 return (ahci_sata_connect(ch)); 2084} 2085 2086static void 2087ahciaction(struct cam_sim *sim, union ccb *ccb) 2088{ 2089 device_t dev; 2090 struct ahci_channel *ch; 2091 2092 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2093 ccb->ccb_h.func_code)); 2094 2095 ch = (struct ahci_channel *)cam_sim_softc(sim); 2096 dev = ch->dev; 2097 switch (ccb->ccb_h.func_code) { 2098 /* Common cases first */ 2099 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2100 case XPT_SCSI_IO: 2101 if (ch->devices == 0) { 2102 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2103 xpt_done(ccb); 2104 break; 2105 } 2106 /* Check for command collision. */ 2107 if (ahci_check_collision(dev, ccb)) { 2108 /* Freeze command. */ 2109 ch->frozen = ccb; 2110 /* We have only one frozen slot, so freeze simq also. */ 2111 xpt_freeze_simq(ch->sim, 1); 2112 return; 2113 } 2114 ahci_begin_transaction(dev, ccb); 2115 break; 2116 case XPT_EN_LUN: /* Enable LUN as a target */ 2117 case XPT_TARGET_IO: /* Execute target I/O request */ 2118 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2119 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2120 case XPT_ABORT: /* Abort the specified CCB */ 2121 /* XXX Implement */ 2122 ccb->ccb_h.status = CAM_REQ_INVALID; 2123 xpt_done(ccb); 2124 break; 2125 case XPT_SET_TRAN_SETTINGS: 2126 { 2127 struct ccb_trans_settings *cts = &ccb->cts; 2128 2129 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) { 2130 ch->pm_present = cts->xport_specific.sata.pm_present; 2131 } 2132 ccb->ccb_h.status = CAM_REQ_CMP; 2133 xpt_done(ccb); 2134 break; 2135 } 2136 case XPT_GET_TRAN_SETTINGS: 2137 /* Get default/user set transfer settings for the target */ 2138 { 2139 struct ccb_trans_settings *cts = &ccb->cts; 2140 uint32_t status; 2141 2142 cts->protocol = PROTO_ATA; 2143 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2144 cts->transport = XPORT_SATA; 2145 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2146 cts->proto_specific.valid = 0; 2147 cts->xport_specific.sata.valid = 0; 2148 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2149 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2150 else 2151 status = ATA_INL(ch->r_mem, AHCI_P_SCTL) & ATA_SC_SPD_MASK; 2152 if (status & ATA_SS_SPD_GEN3) { 2153 cts->xport_specific.sata.bitrate = 600000; 2154 cts->xport_specific.sata.valid |= CTS_SATA_VALID_SPEED; 2155 } else if (status & ATA_SS_SPD_GEN2) { 2156 cts->xport_specific.sata.bitrate = 300000; 2157 cts->xport_specific.sata.valid |= CTS_SATA_VALID_SPEED; 2158 } else if (status & ATA_SS_SPD_GEN1) { 2159 cts->xport_specific.sata.bitrate = 150000; 2160 cts->xport_specific.sata.valid |= CTS_SATA_VALID_SPEED; 2161 } 2162 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 2163 cts->xport_specific.sata.pm_present = 2164 (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_PMA) ? 2165 1 : 0; 2166 } else { 2167 cts->xport_specific.sata.pm_present = ch->pm_present; 2168 } 2169 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2170 ccb->ccb_h.status = CAM_REQ_CMP; 2171 xpt_done(ccb); 2172 break; 2173 } 2174#if 0 2175 case XPT_CALC_GEOMETRY: 2176 { 2177 struct ccb_calc_geometry *ccg; 2178 uint32_t size_mb; 2179 uint32_t secs_per_cylinder; 2180 2181 ccg = &ccb->ccg; 2182 size_mb = ccg->volume_size 2183 / ((1024L * 1024L) / ccg->block_size); 2184 if (size_mb >= 1024 && (aha->extended_trans != 0)) { 2185 if (size_mb >= 2048) { 2186 ccg->heads = 255; 2187 ccg->secs_per_track = 63; 2188 } else { 2189 ccg->heads = 128; 2190 ccg->secs_per_track = 32; 2191 } 2192 } else { 2193 ccg->heads = 64; 2194 ccg->secs_per_track = 32; 2195 } 2196 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 2197 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 2198 ccb->ccb_h.status = CAM_REQ_CMP; 2199 xpt_done(ccb); 2200 break; 2201 } 2202#endif 2203 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2204 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2205 ahci_reset(dev); 2206 ccb->ccb_h.status = CAM_REQ_CMP; 2207 xpt_done(ccb); 2208 break; 2209 case XPT_TERM_IO: /* Terminate the I/O process */ 2210 /* XXX Implement */ 2211 ccb->ccb_h.status = CAM_REQ_INVALID; 2212 xpt_done(ccb); 2213 break; 2214 case XPT_PATH_INQ: /* Path routing inquiry */ 2215 { 2216 struct ccb_pathinq *cpi = &ccb->cpi; 2217 2218 cpi->version_num = 1; /* XXX??? */ 2219 cpi->hba_inquiry = PI_SDTR_ABLE; 2220 if (ch->caps & AHCI_CAP_SNCQ) 2221 cpi->hba_inquiry |= PI_TAG_ABLE; 2222 if (ch->caps & AHCI_CAP_SPM) 2223 cpi->hba_inquiry |= PI_SATAPM; 2224 cpi->target_sprt = 0; 2225 cpi->hba_misc = PIM_SEQSCAN; 2226 cpi->hba_eng_cnt = 0; 2227 if (ch->caps & AHCI_CAP_SPM) 2228 cpi->max_target = 15; 2229 else 2230 cpi->max_target = 0; 2231 cpi->max_lun = 0; 2232 cpi->initiator_id = 0; 2233 cpi->bus_id = cam_sim_bus(sim); 2234 cpi->base_transfer_speed = 150000; 2235 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2236 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2237 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2238 cpi->unit_number = cam_sim_unit(sim); 2239 cpi->transport = XPORT_SATA; 2240 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2241 cpi->protocol = PROTO_ATA; 2242 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2243 cpi->maxio = MAXPHYS; 2244 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2245 if (pci_get_devid(device_get_parent(dev)) == 0x43801002) 2246 cpi->maxio = min(cpi->maxio, 128 * 512); 2247 cpi->ccb_h.status = CAM_REQ_CMP; 2248 xpt_done(ccb); 2249 break; 2250 } 2251 default: 2252 ccb->ccb_h.status = CAM_REQ_INVALID; 2253 xpt_done(ccb); 2254 break; 2255 } 2256} 2257 2258static void 2259ahcipoll(struct cam_sim *sim) 2260{ 2261 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2262 2263 ahci_ch_intr(ch->dev); 2264} 2265