ahci_generic.c revision 228200
1/*- 2 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ahci/ahci.c 228200 2011-12-02 12:52:33Z mav $"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/ata.h> 35#include <sys/bus.h> 36#include <sys/conf.h> 37#include <sys/endian.h> 38#include <sys/malloc.h> 39#include <sys/lock.h> 40#include <sys/mutex.h> 41#include <sys/sema.h> 42#include <sys/taskqueue.h> 43#include <vm/uma.h> 44#include <machine/stdarg.h> 45#include <machine/resource.h> 46#include <machine/bus.h> 47#include <sys/rman.h> 48#include <dev/led/led.h> 49#include <dev/pci/pcivar.h> 50#include <dev/pci/pcireg.h> 51#include "ahci.h" 52 53#include <cam/cam.h> 54#include <cam/cam_ccb.h> 55#include <cam/cam_sim.h> 56#include <cam/cam_xpt_sim.h> 57#include <cam/cam_debug.h> 58 59/* local prototypes */ 60static int ahci_setup_interrupt(device_t dev); 61static void ahci_intr(void *data); 62static void ahci_intr_one(void *data); 63static int ahci_suspend(device_t dev); 64static int ahci_resume(device_t dev); 65static int ahci_ch_init(device_t dev); 66static int ahci_ch_deinit(device_t dev); 67static int ahci_ch_suspend(device_t dev); 68static int ahci_ch_resume(device_t dev); 69static void ahci_ch_pm(void *arg); 70static void ahci_ch_intr_locked(void *data); 71static void ahci_ch_intr(void *data); 72static void ahci_ch_led(void *priv, int onoff); 73static int ahci_ctlr_reset(device_t dev); 74static int ahci_ctlr_setup(device_t dev); 75static void ahci_begin_transaction(device_t dev, union ccb *ccb); 76static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 77static void ahci_execute_transaction(struct ahci_slot *slot); 78static void ahci_timeout(struct ahci_slot *slot); 79static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 80static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 81static void ahci_dmainit(device_t dev); 82static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 83static void ahci_dmafini(device_t dev); 84static void ahci_slotsalloc(device_t dev); 85static void ahci_slotsfree(device_t dev); 86static void ahci_reset(device_t dev); 87static void ahci_start(device_t dev, int fbs); 88static void ahci_stop(device_t dev); 89static void ahci_clo(device_t dev); 90static void ahci_start_fr(device_t dev); 91static void ahci_stop_fr(device_t dev); 92 93static int ahci_sata_connect(struct ahci_channel *ch); 94static int ahci_sata_phy_reset(device_t dev); 95static int ahci_wait_ready(device_t dev, int t, int t0); 96 97static void ahci_issue_recovery(device_t dev); 98static void ahci_process_read_log(device_t dev, union ccb *ccb); 99static void ahci_process_request_sense(device_t dev, union ccb *ccb); 100 101static void ahciaction(struct cam_sim *sim, union ccb *ccb); 102static void ahcipoll(struct cam_sim *sim); 103 104static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 105 106static struct { 107 uint32_t id; 108 uint8_t rev; 109 const char *name; 110 int quirks; 111#define AHCI_Q_NOFORCE 1 112#define AHCI_Q_NOPMP 2 113#define AHCI_Q_NONCQ 4 114#define AHCI_Q_1CH 8 115#define AHCI_Q_2CH 16 116#define AHCI_Q_4CH 32 117#define AHCI_Q_EDGEIS 64 118#define AHCI_Q_SATA2 128 119#define AHCI_Q_NOBSYRES 256 120#define AHCI_Q_NOAA 512 121#define AHCI_Q_NOCOUNT 1024 122#define AHCI_Q_ALTSIG 2048 123} ahci_ids[] = { 124 {0x43801002, 0x00, "ATI IXP600", 0}, 125 {0x43901002, 0x00, "ATI IXP700", 0}, 126 {0x43911002, 0x00, "ATI IXP700", 0}, 127 {0x43921002, 0x00, "ATI IXP700", 0}, 128 {0x43931002, 0x00, "ATI IXP700", 0}, 129 {0x43941002, 0x00, "ATI IXP800", 0}, 130 {0x43951002, 0x00, "ATI IXP800", 0}, 131 {0x06121b21, 0x00, "ASMedia ASM1061", 0}, 132 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE}, 133 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE}, 134 {0x26818086, 0x00, "Intel ESB2", 0}, 135 {0x26828086, 0x00, "Intel ESB2", 0}, 136 {0x26838086, 0x00, "Intel ESB2", 0}, 137 {0x27c18086, 0x00, "Intel ICH7", 0}, 138 {0x27c38086, 0x00, "Intel ICH7", 0}, 139 {0x27c58086, 0x00, "Intel ICH7M", 0}, 140 {0x27c68086, 0x00, "Intel ICH7M", 0}, 141 {0x28218086, 0x00, "Intel ICH8", 0}, 142 {0x28228086, 0x00, "Intel ICH8", 0}, 143 {0x28248086, 0x00, "Intel ICH8", 0}, 144 {0x28298086, 0x00, "Intel ICH8M", 0}, 145 {0x282a8086, 0x00, "Intel ICH8M", 0}, 146 {0x29228086, 0x00, "Intel ICH9", 0}, 147 {0x29238086, 0x00, "Intel ICH9", 0}, 148 {0x29248086, 0x00, "Intel ICH9", 0}, 149 {0x29258086, 0x00, "Intel ICH9", 0}, 150 {0x29278086, 0x00, "Intel ICH9", 0}, 151 {0x29298086, 0x00, "Intel ICH9M", 0}, 152 {0x292a8086, 0x00, "Intel ICH9M", 0}, 153 {0x292b8086, 0x00, "Intel ICH9M", 0}, 154 {0x292c8086, 0x00, "Intel ICH9M", 0}, 155 {0x292f8086, 0x00, "Intel ICH9M", 0}, 156 {0x294d8086, 0x00, "Intel ICH9", 0}, 157 {0x294e8086, 0x00, "Intel ICH9M", 0}, 158 {0x3a058086, 0x00, "Intel ICH10", 0}, 159 {0x3a228086, 0x00, "Intel ICH10", 0}, 160 {0x3a258086, 0x00, "Intel ICH10", 0}, 161 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0}, 162 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0}, 163 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0}, 164 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0}, 165 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0}, 166 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0}, 167 {0x1c028086, 0x00, "Intel Cougar Point", 0}, 168 {0x1c038086, 0x00, "Intel Cougar Point", 0}, 169 {0x1c048086, 0x00, "Intel Cougar Point", 0}, 170 {0x1c058086, 0x00, "Intel Cougar Point", 0}, 171 {0x1d028086, 0x00, "Intel Patsburg", 0}, 172 {0x1d048086, 0x00, "Intel Patsburg", 0}, 173 {0x1d068086, 0x00, "Intel Patsburg", 0}, 174 {0x1e028086, 0x00, "Intel Panther Point", 0}, 175 {0x1e038086, 0x00, "Intel Panther Point", 0}, 176 {0x1e048086, 0x00, "Intel Panther Point", 0}, 177 {0x1e058086, 0x00, "Intel Panther Point", 0}, 178 {0x1e068086, 0x00, "Intel Panther Point", 0}, 179 {0x1e078086, 0x00, "Intel Panther Point", 0}, 180 {0x1e0e8086, 0x00, "Intel Panther Point", 0}, 181 {0x1e0f8086, 0x00, "Intel Panther Point", 0}, 182 {0x23238086, 0x00, "Intel DH89xxCC", 0}, 183 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE}, 184 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE}, 185 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE}, 186 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE}, 187 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE}, 188 {0x611111ab, 0x00, "Marvell 88SX6111", AHCI_Q_NOFORCE | AHCI_Q_1CH | 189 AHCI_Q_EDGEIS}, 190 {0x612111ab, 0x00, "Marvell 88SX6121", AHCI_Q_NOFORCE | AHCI_Q_2CH | 191 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 192 {0x614111ab, 0x00, "Marvell 88SX6141", AHCI_Q_NOFORCE | AHCI_Q_4CH | 193 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 194 {0x614511ab, 0x00, "Marvell 88SX6145", AHCI_Q_NOFORCE | AHCI_Q_4CH | 195 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 196 {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_NOBSYRES}, 197 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 198 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES}, 199 {0x91251b4b, 0x00, "Marvell 88SE9125", AHCI_Q_NOBSYRES}, 200 {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 201 {0x91721b4b, 0x00, "Marvell 88SE9172", AHCI_Q_NOBSYRES}, 202 {0x91821b4b, 0x00, "Marvell 88SE9182", AHCI_Q_NOBSYRES}, 203 {0x06201103, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 204 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 205 {0x06221103, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 206 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 207 {0x06401103, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 208 {0x06401b4b, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 209 {0x06441103, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 210 {0x06441b4b, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 211 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 212 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 213 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 214 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 215 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 216 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 217 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 218 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 219 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 220 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 221 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 222 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 223 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 224 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 225 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 226 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 227 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 228 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 229 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 230 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 231 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 232 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 233 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 234 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 235 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 236 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 237 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 238 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 239 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 240 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 241 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 242 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 243 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 244 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 245 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 246 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 247 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 248 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 249 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 250 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 251 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 252 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 253 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 254 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 255 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 256 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 257 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 258 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 259 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 260 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 261 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 262 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 263 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 264 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 265 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 266 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 267 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 268 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 269 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA}, 270 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 271 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 272 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 273 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 274 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 275 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 276 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 277 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 278 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 279 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 280 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 281 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 282 {0x11841039, 0x00, "SiS 966", 0}, 283 {0x11851039, 0x00, "SiS 968", 0}, 284 {0x01861039, 0x00, "SiS 968", 0}, 285 {0x00000000, 0x00, NULL, 0} 286}; 287 288#define recovery_type spriv_field0 289#define RECOVERY_NONE 0 290#define RECOVERY_READ_LOG 1 291#define RECOVERY_REQUEST_SENSE 2 292#define recovery_slot spriv_field1 293 294static int force_ahci = 1; 295TUNABLE_INT("hw.ahci.force", &force_ahci); 296 297static int 298ahci_probe(device_t dev) 299{ 300 char buf[64]; 301 int i, valid = 0; 302 uint32_t devid = pci_get_devid(dev); 303 uint8_t revid = pci_get_revid(dev); 304 305 /* Is this a possible AHCI candidate? */ 306 if (pci_get_class(dev) == PCIC_STORAGE && 307 pci_get_subclass(dev) == PCIS_STORAGE_SATA && 308 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0) 309 valid = 1; 310 /* Is this a known AHCI chip? */ 311 for (i = 0; ahci_ids[i].id != 0; i++) { 312 if (ahci_ids[i].id == devid && 313 ahci_ids[i].rev <= revid && 314 (valid || (force_ahci == 1 && 315 !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) { 316 /* Do not attach JMicrons with single PCI function. */ 317 if (pci_get_vendor(dev) == 0x197b && 318 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0) 319 return (ENXIO); 320 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 321 ahci_ids[i].name); 322 device_set_desc_copy(dev, buf); 323 return (BUS_PROBE_VENDOR); 324 } 325 } 326 if (!valid) 327 return (ENXIO); 328 device_set_desc_copy(dev, "AHCI SATA controller"); 329 return (BUS_PROBE_VENDOR); 330} 331 332static int 333ahci_ata_probe(device_t dev) 334{ 335 char buf[64]; 336 int i; 337 uint32_t devid = pci_get_devid(dev); 338 uint8_t revid = pci_get_revid(dev); 339 340 if ((intptr_t)device_get_ivars(dev) >= 0) 341 return (ENXIO); 342 /* Is this a known AHCI chip? */ 343 for (i = 0; ahci_ids[i].id != 0; i++) { 344 if (ahci_ids[i].id == devid && 345 ahci_ids[i].rev <= revid) { 346 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 347 ahci_ids[i].name); 348 device_set_desc_copy(dev, buf); 349 return (BUS_PROBE_VENDOR); 350 } 351 } 352 device_set_desc_copy(dev, "AHCI SATA controller"); 353 return (BUS_PROBE_VENDOR); 354} 355 356static int 357ahci_attach(device_t dev) 358{ 359 struct ahci_controller *ctlr = device_get_softc(dev); 360 device_t child; 361 int error, unit, speed, i; 362 uint32_t devid = pci_get_devid(dev); 363 uint8_t revid = pci_get_revid(dev); 364 u_int32_t version; 365 366 ctlr->dev = dev; 367 i = 0; 368 while (ahci_ids[i].id != 0 && 369 (ahci_ids[i].id != devid || 370 ahci_ids[i].rev > revid)) 371 i++; 372 ctlr->quirks = ahci_ids[i].quirks; 373 resource_int_value(device_get_name(dev), 374 device_get_unit(dev), "ccc", &ctlr->ccc); 375 /* if we have a memory BAR(5) we are likely on an AHCI part */ 376 ctlr->r_rid = PCIR_BAR(5); 377 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 378 &ctlr->r_rid, RF_ACTIVE))) 379 return ENXIO; 380 /* Setup our own memory management for channels. */ 381 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 382 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 383 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 384 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 385 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 386 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 387 return (error); 388 } 389 if ((error = rman_manage_region(&ctlr->sc_iomem, 390 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 391 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 392 rman_fini(&ctlr->sc_iomem); 393 return (error); 394 } 395 pci_enable_busmaster(dev); 396 /* Reset controller */ 397 if ((error = ahci_ctlr_reset(dev)) != 0) { 398 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 399 rman_fini(&ctlr->sc_iomem); 400 return (error); 401 }; 402 /* Get the HW capabilities */ 403 version = ATA_INL(ctlr->r_mem, AHCI_VS); 404 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 405 if (version >= 0x00010020) 406 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 407 if (ctlr->caps & AHCI_CAP_EMS) 408 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 409 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 410 411 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */ 412 if ((ctlr->quirks & AHCI_Q_NOBSYRES) && 413 (ctlr->quirks & AHCI_Q_ALTSIG) && 414 (ctlr->caps & AHCI_CAP_SPM) == 0) 415 ctlr->quirks &= ~AHCI_Q_NOBSYRES; 416 417 if (ctlr->quirks & AHCI_Q_1CH) { 418 ctlr->caps &= ~AHCI_CAP_NPMASK; 419 ctlr->ichannels &= 0x01; 420 } 421 if (ctlr->quirks & AHCI_Q_2CH) { 422 ctlr->caps &= ~AHCI_CAP_NPMASK; 423 ctlr->caps |= 1; 424 ctlr->ichannels &= 0x03; 425 } 426 if (ctlr->quirks & AHCI_Q_4CH) { 427 ctlr->caps &= ~AHCI_CAP_NPMASK; 428 ctlr->caps |= 3; 429 ctlr->ichannels &= 0x0f; 430 } 431 ctlr->channels = MAX(flsl(ctlr->ichannels), 432 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 433 if (ctlr->quirks & AHCI_Q_NOPMP) 434 ctlr->caps &= ~AHCI_CAP_SPM; 435 if (ctlr->quirks & AHCI_Q_NONCQ) 436 ctlr->caps &= ~AHCI_CAP_SNCQ; 437 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 438 ctlr->ccc = 0; 439 mtx_init(&ctlr->em_mtx, "AHCI EM lock", NULL, MTX_DEF); 440 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC); 441 ahci_ctlr_setup(dev); 442 /* Setup interrupts. */ 443 if (ahci_setup_interrupt(dev)) { 444 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 445 rman_fini(&ctlr->sc_iomem); 446 return ENXIO; 447 } 448 /* Announce HW capabilities. */ 449 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 450 device_printf(dev, 451 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 452 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 453 ((version >> 4) & 0xf0) + (version & 0x0f), 454 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 455 ((speed == 1) ? "1.5":((speed == 2) ? "3": 456 ((speed == 3) ? "6":"?"))), 457 (ctlr->caps & AHCI_CAP_SPM) ? 458 "supported" : "not supported", 459 (ctlr->caps & AHCI_CAP_FBSS) ? 460 " with FBS" : ""); 461 if (bootverbose) { 462 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 463 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 464 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 465 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 466 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 467 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 468 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 469 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 470 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 471 ((speed == 1) ? "1.5":((speed == 2) ? "3": 472 ((speed == 3) ? "6":"?")))); 473 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 474 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 475 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 476 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 477 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 478 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 479 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 480 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 481 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 482 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 483 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 484 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 485 } 486 if (bootverbose && version >= 0x00010020) { 487 device_printf(dev, "Caps2:%s%s%s\n", 488 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 489 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 490 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 491 } 492 if (bootverbose && (ctlr->caps & AHCI_CAP_EMS)) { 493 device_printf(dev, "EM Caps:%s%s%s%s%s%s%s%s\n", 494 (ctlr->capsem & AHCI_EM_PM) ? " PM":"", 495 (ctlr->capsem & AHCI_EM_ALHD) ? " ALHD":"", 496 (ctlr->capsem & AHCI_EM_XMT) ? " XMT":"", 497 (ctlr->capsem & AHCI_EM_SMB) ? " SMB":"", 498 (ctlr->capsem & AHCI_EM_SGPIO) ? " SGPIO":"", 499 (ctlr->capsem & AHCI_EM_SES2) ? " SES-2":"", 500 (ctlr->capsem & AHCI_EM_SAFTE) ? " SAF-TE":"", 501 (ctlr->capsem & AHCI_EM_LED) ? " LED":""); 502 } 503 /* Attach all channels on this controller */ 504 for (unit = 0; unit < ctlr->channels; unit++) { 505 child = device_add_child(dev, "ahcich", -1); 506 if (child == NULL) { 507 device_printf(dev, "failed to add channel device\n"); 508 continue; 509 } 510 device_set_ivars(child, (void *)(intptr_t)unit); 511 if ((ctlr->ichannels & (1 << unit)) == 0) 512 device_disable(child); 513 } 514 bus_generic_attach(dev); 515 return 0; 516} 517 518static int 519ahci_detach(device_t dev) 520{ 521 struct ahci_controller *ctlr = device_get_softc(dev); 522 int i; 523 524 /* Detach & delete all children */ 525 device_delete_children(dev); 526 527 /* Free interrupts. */ 528 for (i = 0; i < ctlr->numirqs; i++) { 529 if (ctlr->irqs[i].r_irq) { 530 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 531 ctlr->irqs[i].handle); 532 bus_release_resource(dev, SYS_RES_IRQ, 533 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 534 } 535 } 536 pci_release_msi(dev); 537 /* Free memory. */ 538 rman_fini(&ctlr->sc_iomem); 539 if (ctlr->r_mem) 540 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 541 mtx_destroy(&ctlr->em_mtx); 542 return (0); 543} 544 545static int 546ahci_ctlr_reset(device_t dev) 547{ 548 struct ahci_controller *ctlr = device_get_softc(dev); 549 int timeout; 550 551 if (pci_read_config(dev, 0x00, 4) == 0x28298086 && 552 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 553 pci_write_config(dev, 0x92, 0x01, 1); 554 /* Enable AHCI mode */ 555 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 556 /* Reset AHCI controller */ 557 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 558 for (timeout = 1000; timeout > 0; timeout--) { 559 DELAY(1000); 560 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 561 break; 562 } 563 if (timeout == 0) { 564 device_printf(dev, "AHCI controller reset failure\n"); 565 return ENXIO; 566 } 567 /* Reenable AHCI mode */ 568 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 569 return (0); 570} 571 572static int 573ahci_ctlr_setup(device_t dev) 574{ 575 struct ahci_controller *ctlr = device_get_softc(dev); 576 /* Clear interrupts */ 577 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 578 /* Configure CCC */ 579 if (ctlr->ccc) { 580 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 581 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 582 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 583 (4 << AHCI_CCCC_CC_SHIFT) | 584 AHCI_CCCC_EN); 585 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 586 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 587 if (bootverbose) { 588 device_printf(dev, 589 "CCC with %dms/4cmd enabled on vector %d\n", 590 ctlr->ccc, ctlr->cccv); 591 } 592 } 593 /* Enable AHCI interrupts */ 594 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 595 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 596 return (0); 597} 598 599static int 600ahci_suspend(device_t dev) 601{ 602 struct ahci_controller *ctlr = device_get_softc(dev); 603 604 bus_generic_suspend(dev); 605 /* Disable interupts, so the state change(s) doesn't trigger */ 606 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 607 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 608 return 0; 609} 610 611static int 612ahci_resume(device_t dev) 613{ 614 int res; 615 616 if ((res = ahci_ctlr_reset(dev)) != 0) 617 return (res); 618 ahci_ctlr_setup(dev); 619 return (bus_generic_resume(dev)); 620} 621 622static int 623ahci_setup_interrupt(device_t dev) 624{ 625 struct ahci_controller *ctlr = device_get_softc(dev); 626 int i, msi = 1; 627 628 /* Process hints. */ 629 resource_int_value(device_get_name(dev), 630 device_get_unit(dev), "msi", &msi); 631 if (msi < 0) 632 msi = 0; 633 else if (msi == 1) 634 msi = min(1, pci_msi_count(dev)); 635 else if (msi > 1) 636 msi = pci_msi_count(dev); 637 /* Allocate MSI if needed/present. */ 638 if (msi && pci_alloc_msi(dev, &msi) == 0) { 639 ctlr->numirqs = msi; 640 } else { 641 msi = 0; 642 ctlr->numirqs = 1; 643 } 644 /* Check for single MSI vector fallback. */ 645 if (ctlr->numirqs > 1 && 646 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 647 device_printf(dev, "Falling back to one MSI\n"); 648 ctlr->numirqs = 1; 649 } 650 /* Allocate all IRQs. */ 651 for (i = 0; i < ctlr->numirqs; i++) { 652 ctlr->irqs[i].ctlr = ctlr; 653 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0); 654 if (ctlr->numirqs == 1 || i >= ctlr->channels || 655 (ctlr->ccc && i == ctlr->cccv)) 656 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 657 else if (i == ctlr->numirqs - 1) 658 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 659 else 660 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 661 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 662 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 663 device_printf(dev, "unable to map interrupt\n"); 664 return ENXIO; 665 } 666 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 667 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr, 668 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 669 /* SOS XXX release r_irq */ 670 device_printf(dev, "unable to setup interrupt\n"); 671 return ENXIO; 672 } 673 if (ctlr->numirqs > 1) { 674 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 675 ctlr->irqs[i].handle, 676 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 677 "ch%d" : "%d", i); 678 } 679 } 680 return (0); 681} 682 683/* 684 * Common case interrupt handler. 685 */ 686static void 687ahci_intr(void *data) 688{ 689 struct ahci_controller_irq *irq = data; 690 struct ahci_controller *ctlr = irq->ctlr; 691 u_int32_t is, ise = 0; 692 void *arg; 693 int unit; 694 695 if (irq->mode == AHCI_IRQ_MODE_ALL) { 696 unit = 0; 697 if (ctlr->ccc) 698 is = ctlr->ichannels; 699 else 700 is = ATA_INL(ctlr->r_mem, AHCI_IS); 701 } else { /* AHCI_IRQ_MODE_AFTER */ 702 unit = irq->r_irq_rid - 1; 703 is = ATA_INL(ctlr->r_mem, AHCI_IS); 704 } 705 /* CCC interrupt is edge triggered. */ 706 if (ctlr->ccc) 707 ise = 1 << ctlr->cccv; 708 /* Some controllers have edge triggered IS. */ 709 if (ctlr->quirks & AHCI_Q_EDGEIS) 710 ise |= is; 711 if (ise != 0) 712 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 713 for (; unit < ctlr->channels; unit++) { 714 if ((is & (1 << unit)) != 0 && 715 (arg = ctlr->interrupt[unit].argument)) { 716 ctlr->interrupt[unit].function(arg); 717 } 718 } 719 /* AHCI declares level triggered IS. */ 720 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 721 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 722} 723 724/* 725 * Simplified interrupt handler for multivector MSI mode. 726 */ 727static void 728ahci_intr_one(void *data) 729{ 730 struct ahci_controller_irq *irq = data; 731 struct ahci_controller *ctlr = irq->ctlr; 732 void *arg; 733 int unit; 734 735 unit = irq->r_irq_rid - 1; 736 /* Some controllers have edge triggered IS. */ 737 if (ctlr->quirks & AHCI_Q_EDGEIS) 738 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 739 if ((arg = ctlr->interrupt[unit].argument)) 740 ctlr->interrupt[unit].function(arg); 741 /* AHCI declares level triggered IS. */ 742 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 743 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 744} 745 746static struct resource * 747ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 748 u_long start, u_long end, u_long count, u_int flags) 749{ 750 struct ahci_controller *ctlr = device_get_softc(dev); 751 int unit = ((struct ahci_channel *)device_get_softc(child))->unit; 752 struct resource *res = NULL; 753 int offset = AHCI_OFFSET + (unit << 7); 754 long st; 755 756 switch (type) { 757 case SYS_RES_MEMORY: 758 st = rman_get_start(ctlr->r_mem); 759 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 760 st + offset + 127, 128, RF_ACTIVE, child); 761 if (res) { 762 bus_space_handle_t bsh; 763 bus_space_tag_t bst; 764 bsh = rman_get_bushandle(ctlr->r_mem); 765 bst = rman_get_bustag(ctlr->r_mem); 766 bus_space_subregion(bst, bsh, offset, 128, &bsh); 767 rman_set_bushandle(res, bsh); 768 rman_set_bustag(res, bst); 769 } 770 break; 771 case SYS_RES_IRQ: 772 if (*rid == ATA_IRQ_RID) 773 res = ctlr->irqs[0].r_irq; 774 break; 775 } 776 return (res); 777} 778 779static int 780ahci_release_resource(device_t dev, device_t child, int type, int rid, 781 struct resource *r) 782{ 783 784 switch (type) { 785 case SYS_RES_MEMORY: 786 rman_release_resource(r); 787 return (0); 788 case SYS_RES_IRQ: 789 if (rid != ATA_IRQ_RID) 790 return ENOENT; 791 return (0); 792 } 793 return (EINVAL); 794} 795 796static int 797ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 798 int flags, driver_filter_t *filter, driver_intr_t *function, 799 void *argument, void **cookiep) 800{ 801 struct ahci_controller *ctlr = device_get_softc(dev); 802 int unit = (intptr_t)device_get_ivars(child); 803 804 if (filter != NULL) { 805 printf("ahci.c: we cannot use a filter here\n"); 806 return (EINVAL); 807 } 808 ctlr->interrupt[unit].function = function; 809 ctlr->interrupt[unit].argument = argument; 810 return (0); 811} 812 813static int 814ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 815 void *cookie) 816{ 817 struct ahci_controller *ctlr = device_get_softc(dev); 818 int unit = (intptr_t)device_get_ivars(child); 819 820 ctlr->interrupt[unit].function = NULL; 821 ctlr->interrupt[unit].argument = NULL; 822 return (0); 823} 824 825static int 826ahci_print_child(device_t dev, device_t child) 827{ 828 int retval; 829 830 retval = bus_print_child_header(dev, child); 831 retval += printf(" at channel %d", 832 (int)(intptr_t)device_get_ivars(child)); 833 retval += bus_print_child_footer(dev, child); 834 835 return (retval); 836} 837 838static int 839ahci_child_location_str(device_t dev, device_t child, char *buf, 840 size_t buflen) 841{ 842 843 snprintf(buf, buflen, "channel=%d", 844 (int)(intptr_t)device_get_ivars(child)); 845 return (0); 846} 847 848devclass_t ahci_devclass; 849static device_method_t ahci_methods[] = { 850 DEVMETHOD(device_probe, ahci_probe), 851 DEVMETHOD(device_attach, ahci_attach), 852 DEVMETHOD(device_detach, ahci_detach), 853 DEVMETHOD(device_suspend, ahci_suspend), 854 DEVMETHOD(device_resume, ahci_resume), 855 DEVMETHOD(bus_print_child, ahci_print_child), 856 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 857 DEVMETHOD(bus_release_resource, ahci_release_resource), 858 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 859 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 860 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 861 { 0, 0 } 862}; 863static driver_t ahci_driver = { 864 "ahci", 865 ahci_methods, 866 sizeof(struct ahci_controller) 867}; 868DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 869static device_method_t ahci_ata_methods[] = { 870 DEVMETHOD(device_probe, ahci_ata_probe), 871 DEVMETHOD(device_attach, ahci_attach), 872 DEVMETHOD(device_detach, ahci_detach), 873 DEVMETHOD(device_suspend, ahci_suspend), 874 DEVMETHOD(device_resume, ahci_resume), 875 DEVMETHOD(bus_print_child, ahci_print_child), 876 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 877 DEVMETHOD(bus_release_resource, ahci_release_resource), 878 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 879 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 880 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 881 { 0, 0 } 882}; 883static driver_t ahci_ata_driver = { 884 "ahci", 885 ahci_ata_methods, 886 sizeof(struct ahci_controller) 887}; 888DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0); 889MODULE_VERSION(ahci, 1); 890MODULE_DEPEND(ahci, cam, 1, 1, 1); 891 892static int 893ahci_ch_probe(device_t dev) 894{ 895 896 device_set_desc_copy(dev, "AHCI channel"); 897 return (0); 898} 899 900static int 901ahci_ch_attach(device_t dev) 902{ 903 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 904 struct ahci_channel *ch = device_get_softc(dev); 905 struct cam_devq *devq; 906 int rid, error, i, sata_rev = 0; 907 u_int32_t version; 908 char buf[32]; 909 910 ch->dev = dev; 911 ch->unit = (intptr_t)device_get_ivars(dev); 912 ch->caps = ctlr->caps; 913 ch->caps2 = ctlr->caps2; 914 ch->quirks = ctlr->quirks; 915 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 916 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 917 resource_int_value(device_get_name(dev), 918 device_get_unit(dev), "pm_level", &ch->pm_level); 919 if (ch->pm_level > 3) 920 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 921 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 922 /* Limit speed for my onboard JMicron external port. 923 * It is not eSATA really. */ 924 if (pci_get_devid(ctlr->dev) == 0x2363197b && 925 pci_get_subvendor(ctlr->dev) == 0x1043 && 926 pci_get_subdevice(ctlr->dev) == 0x81e4 && 927 ch->unit == 0) 928 sata_rev = 1; 929 if (ch->quirks & AHCI_Q_SATA2) 930 sata_rev = 2; 931 resource_int_value(device_get_name(dev), 932 device_get_unit(dev), "sata_rev", &sata_rev); 933 for (i = 0; i < 16; i++) { 934 ch->user[i].revision = sata_rev; 935 ch->user[i].mode = 0; 936 ch->user[i].bytecount = 8192; 937 ch->user[i].tags = ch->numslots; 938 ch->user[i].caps = 0; 939 ch->curr[i] = ch->user[i]; 940 if (ch->pm_level) { 941 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 942 CTS_SATA_CAPS_H_APST | 943 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 944 } 945 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA | 946 CTS_SATA_CAPS_H_AN; 947 } 948 rid = ch->unit; 949 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 950 &rid, RF_ACTIVE))) 951 return (ENXIO); 952 ahci_dmainit(dev); 953 ahci_slotsalloc(dev); 954 ahci_ch_init(dev); 955 mtx_lock(&ch->mtx); 956 rid = ATA_IRQ_RID; 957 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 958 &rid, RF_SHAREABLE | RF_ACTIVE))) { 959 device_printf(dev, "Unable to map interrupt\n"); 960 error = ENXIO; 961 goto err0; 962 } 963 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 964 ahci_ch_intr_locked, dev, &ch->ih))) { 965 device_printf(dev, "Unable to setup interrupt\n"); 966 error = ENXIO; 967 goto err1; 968 } 969 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 970 version = ATA_INL(ctlr->r_mem, AHCI_VS); 971 if (version < 0x00010020 && (ctlr->caps & AHCI_CAP_FBSS)) 972 ch->chcaps |= AHCI_P_CMD_FBSCP; 973 if (bootverbose) { 974 device_printf(dev, "Caps:%s%s%s%s%s\n", 975 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 976 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 977 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 978 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 979 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":""); 980 } 981 /* Create the device queue for our SIM. */ 982 devq = cam_simq_alloc(ch->numslots); 983 if (devq == NULL) { 984 device_printf(dev, "Unable to allocate simq\n"); 985 error = ENOMEM; 986 goto err1; 987 } 988 /* Construct SIM entry */ 989 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 990 device_get_unit(dev), &ch->mtx, 991 min(2, ch->numslots), 992 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 993 devq); 994 if (ch->sim == NULL) { 995 cam_simq_free(devq); 996 device_printf(dev, "unable to allocate sim\n"); 997 error = ENOMEM; 998 goto err1; 999 } 1000 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 1001 device_printf(dev, "unable to register xpt bus\n"); 1002 error = ENXIO; 1003 goto err2; 1004 } 1005 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 1006 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1007 device_printf(dev, "unable to create path\n"); 1008 error = ENXIO; 1009 goto err3; 1010 } 1011 if (ch->pm_level > 3) { 1012 callout_reset(&ch->pm_timer, 1013 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 1014 ahci_ch_pm, dev); 1015 } 1016 mtx_unlock(&ch->mtx); 1017 if ((ch->caps & AHCI_CAP_EMS) && 1018 (ctlr->capsem & AHCI_EM_LED)) { 1019 for (i = 0; i < AHCI_NUM_LEDS; i++) { 1020 ch->leds[i].dev = dev; 1021 ch->leds[i].num = i; 1022 } 1023 if ((ctlr->capsem & AHCI_EM_ALHD) == 0) { 1024 snprintf(buf, sizeof(buf), "%s.act", 1025 device_get_nameunit(dev)); 1026 ch->leds[0].led = led_create(ahci_ch_led, 1027 &ch->leds[0], buf); 1028 } 1029 snprintf(buf, sizeof(buf), "%s.locate", 1030 device_get_nameunit(dev)); 1031 ch->leds[1].led = led_create(ahci_ch_led, &ch->leds[1], buf); 1032 snprintf(buf, sizeof(buf), "%s.fault", 1033 device_get_nameunit(dev)); 1034 ch->leds[2].led = led_create(ahci_ch_led, &ch->leds[2], buf); 1035 } 1036 return (0); 1037 1038err3: 1039 xpt_bus_deregister(cam_sim_path(ch->sim)); 1040err2: 1041 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1042err1: 1043 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1044err0: 1045 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1046 mtx_unlock(&ch->mtx); 1047 mtx_destroy(&ch->mtx); 1048 return (error); 1049} 1050 1051static int 1052ahci_ch_detach(device_t dev) 1053{ 1054 struct ahci_channel *ch = device_get_softc(dev); 1055 int i; 1056 1057 for (i = 0; i < AHCI_NUM_LEDS; i++) { 1058 if (ch->leds[i].led) 1059 led_destroy(ch->leds[i].led); 1060 } 1061 mtx_lock(&ch->mtx); 1062 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 1063 /* Forget about reset. */ 1064 if (ch->resetting) { 1065 ch->resetting = 0; 1066 xpt_release_simq(ch->sim, TRUE); 1067 } 1068 xpt_free_path(ch->path); 1069 xpt_bus_deregister(cam_sim_path(ch->sim)); 1070 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1071 mtx_unlock(&ch->mtx); 1072 1073 if (ch->pm_level > 3) 1074 callout_drain(&ch->pm_timer); 1075 callout_drain(&ch->reset_timer); 1076 bus_teardown_intr(dev, ch->r_irq, ch->ih); 1077 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1078 1079 ahci_ch_deinit(dev); 1080 ahci_slotsfree(dev); 1081 ahci_dmafini(dev); 1082 1083 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1084 mtx_destroy(&ch->mtx); 1085 return (0); 1086} 1087 1088static int 1089ahci_ch_init(device_t dev) 1090{ 1091 struct ahci_channel *ch = device_get_softc(dev); 1092 uint64_t work; 1093 1094 /* Disable port interrupts */ 1095 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1096 /* Setup work areas */ 1097 work = ch->dma.work_bus + AHCI_CL_OFFSET; 1098 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 1099 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 1100 work = ch->dma.rfis_bus; 1101 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 1102 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 1103 /* Activate the channel and power/spin up device */ 1104 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 1105 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1106 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 1107 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 1108 ahci_start_fr(dev); 1109 ahci_start(dev, 1); 1110 return (0); 1111} 1112 1113static int 1114ahci_ch_deinit(device_t dev) 1115{ 1116 struct ahci_channel *ch = device_get_softc(dev); 1117 1118 /* Disable port interrupts. */ 1119 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1120 /* Reset command register. */ 1121 ahci_stop(dev); 1122 ahci_stop_fr(dev); 1123 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 1124 /* Allow everything, including partial and slumber modes. */ 1125 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 1126 /* Request slumber mode transition and give some time to get there. */ 1127 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 1128 DELAY(100); 1129 /* Disable PHY. */ 1130 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 1131 return (0); 1132} 1133 1134static int 1135ahci_ch_suspend(device_t dev) 1136{ 1137 struct ahci_channel *ch = device_get_softc(dev); 1138 1139 mtx_lock(&ch->mtx); 1140 xpt_freeze_simq(ch->sim, 1); 1141 /* Forget about reset. */ 1142 if (ch->resetting) { 1143 ch->resetting = 0; 1144 callout_stop(&ch->reset_timer); 1145 xpt_release_simq(ch->sim, TRUE); 1146 } 1147 while (ch->oslots) 1148 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 1149 ahci_ch_deinit(dev); 1150 mtx_unlock(&ch->mtx); 1151 return (0); 1152} 1153 1154static int 1155ahci_ch_resume(device_t dev) 1156{ 1157 struct ahci_channel *ch = device_get_softc(dev); 1158 1159 mtx_lock(&ch->mtx); 1160 ahci_ch_init(dev); 1161 ahci_reset(dev); 1162 xpt_release_simq(ch->sim, TRUE); 1163 mtx_unlock(&ch->mtx); 1164 return (0); 1165} 1166 1167devclass_t ahcich_devclass; 1168static device_method_t ahcich_methods[] = { 1169 DEVMETHOD(device_probe, ahci_ch_probe), 1170 DEVMETHOD(device_attach, ahci_ch_attach), 1171 DEVMETHOD(device_detach, ahci_ch_detach), 1172 DEVMETHOD(device_suspend, ahci_ch_suspend), 1173 DEVMETHOD(device_resume, ahci_ch_resume), 1174 { 0, 0 } 1175}; 1176static driver_t ahcich_driver = { 1177 "ahcich", 1178 ahcich_methods, 1179 sizeof(struct ahci_channel) 1180}; 1181DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0); 1182 1183static void 1184ahci_ch_setleds(device_t dev) 1185{ 1186 struct ahci_channel *ch; 1187 struct ahci_controller *ctlr; 1188 size_t buf; 1189 int i, timeout; 1190 int16_t val; 1191 1192 ctlr = device_get_softc(device_get_parent(dev)); 1193 ch = device_get_softc(dev); 1194 1195 val = 0; 1196 for (i = 0; i < AHCI_NUM_LEDS; i++) 1197 val |= ch->leds[i].state << (i * 3); 1198 1199 buf = (ctlr->emloc & 0xffff0000) >> 14; 1200 mtx_lock(&ctlr->em_mtx); 1201 timeout = 1000; 1202 while (ATA_INL(ctlr->r_mem, AHCI_EM_CTL) & (AHCI_EM_TM | AHCI_EM_RST) && 1203 --timeout > 0) 1204 DELAY(1000); 1205 if (timeout == 0) 1206 device_printf(dev, "EM timeout\n"); 1207 ATA_OUTL(ctlr->r_mem, buf, (1 << 8) | (0 << 16) | (0 << 24)); 1208 ATA_OUTL(ctlr->r_mem, buf + 4, ch->unit | (val << 16)); 1209 ATA_OUTL(ctlr->r_mem, AHCI_EM_CTL, AHCI_EM_TM); 1210 mtx_unlock(&ctlr->em_mtx); 1211} 1212 1213static void 1214ahci_ch_led(void *priv, int onoff) 1215{ 1216 struct ahci_led *led; 1217 1218 led = (struct ahci_led *)priv; 1219 1220 led->state = onoff; 1221 ahci_ch_setleds(led->dev); 1222} 1223 1224struct ahci_dc_cb_args { 1225 bus_addr_t maddr; 1226 int error; 1227}; 1228 1229static void 1230ahci_dmainit(device_t dev) 1231{ 1232 struct ahci_channel *ch = device_get_softc(dev); 1233 struct ahci_dc_cb_args dcba; 1234 size_t rfsize; 1235 1236 if (ch->caps & AHCI_CAP_64BIT) 1237 ch->dma.max_address = BUS_SPACE_MAXADDR; 1238 else 1239 ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT; 1240 /* Command area. */ 1241 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1242 ch->dma.max_address, BUS_SPACE_MAXADDR, 1243 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1244 0, NULL, NULL, &ch->dma.work_tag)) 1245 goto error; 1246 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0, 1247 &ch->dma.work_map)) 1248 goto error; 1249 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1250 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1251 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1252 goto error; 1253 } 1254 ch->dma.work_bus = dcba.maddr; 1255 /* FIS receive area. */ 1256 if (ch->chcaps & AHCI_P_CMD_FBSCP) 1257 rfsize = 4096; 1258 else 1259 rfsize = 256; 1260 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 1261 ch->dma.max_address, BUS_SPACE_MAXADDR, 1262 NULL, NULL, rfsize, 1, rfsize, 1263 0, NULL, NULL, &ch->dma.rfis_tag)) 1264 goto error; 1265 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1266 &ch->dma.rfis_map)) 1267 goto error; 1268 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1269 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1270 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1271 goto error; 1272 } 1273 ch->dma.rfis_bus = dcba.maddr; 1274 /* Data area. */ 1275 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1276 ch->dma.max_address, BUS_SPACE_MAXADDR, 1277 NULL, NULL, 1278 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1279 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1280 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 1281 goto error; 1282 } 1283 return; 1284 1285error: 1286 device_printf(dev, "WARNING - DMA initialization failed\n"); 1287 ahci_dmafini(dev); 1288} 1289 1290static void 1291ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1292{ 1293 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1294 1295 if (!(dcba->error = error)) 1296 dcba->maddr = segs[0].ds_addr; 1297} 1298 1299static void 1300ahci_dmafini(device_t dev) 1301{ 1302 struct ahci_channel *ch = device_get_softc(dev); 1303 1304 if (ch->dma.data_tag) { 1305 bus_dma_tag_destroy(ch->dma.data_tag); 1306 ch->dma.data_tag = NULL; 1307 } 1308 if (ch->dma.rfis_bus) { 1309 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1310 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1311 ch->dma.rfis_bus = 0; 1312 ch->dma.rfis_map = NULL; 1313 ch->dma.rfis = NULL; 1314 } 1315 if (ch->dma.work_bus) { 1316 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1317 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1318 ch->dma.work_bus = 0; 1319 ch->dma.work_map = NULL; 1320 ch->dma.work = NULL; 1321 } 1322 if (ch->dma.work_tag) { 1323 bus_dma_tag_destroy(ch->dma.work_tag); 1324 ch->dma.work_tag = NULL; 1325 } 1326} 1327 1328static void 1329ahci_slotsalloc(device_t dev) 1330{ 1331 struct ahci_channel *ch = device_get_softc(dev); 1332 int i; 1333 1334 /* Alloc and setup command/dma slots */ 1335 bzero(ch->slot, sizeof(ch->slot)); 1336 for (i = 0; i < ch->numslots; i++) { 1337 struct ahci_slot *slot = &ch->slot[i]; 1338 1339 slot->dev = dev; 1340 slot->slot = i; 1341 slot->state = AHCI_SLOT_EMPTY; 1342 slot->ccb = NULL; 1343 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1344 1345 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1346 device_printf(ch->dev, "FAILURE - create data_map\n"); 1347 } 1348} 1349 1350static void 1351ahci_slotsfree(device_t dev) 1352{ 1353 struct ahci_channel *ch = device_get_softc(dev); 1354 int i; 1355 1356 /* Free all dma slots */ 1357 for (i = 0; i < ch->numslots; i++) { 1358 struct ahci_slot *slot = &ch->slot[i]; 1359 1360 callout_drain(&slot->timeout); 1361 if (slot->dma.data_map) { 1362 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1363 slot->dma.data_map = NULL; 1364 } 1365 } 1366} 1367 1368static int 1369ahci_phy_check_events(device_t dev, u_int32_t serr) 1370{ 1371 struct ahci_channel *ch = device_get_softc(dev); 1372 1373 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 1374 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) { 1375 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1376 union ccb *ccb; 1377 1378 if (bootverbose) { 1379 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 1380 device_printf(dev, "CONNECT requested\n"); 1381 else 1382 device_printf(dev, "DISCONNECT requested\n"); 1383 } 1384 ahci_reset(dev); 1385 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1386 return (0); 1387 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1388 cam_sim_path(ch->sim), 1389 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1390 xpt_free_ccb(ccb); 1391 return (0); 1392 } 1393 xpt_rescan(ccb); 1394 return (1); 1395 } 1396 return (0); 1397} 1398 1399static void 1400ahci_cpd_check_events(device_t dev) 1401{ 1402 struct ahci_channel *ch = device_get_softc(dev); 1403 u_int32_t status; 1404 union ccb *ccb; 1405 1406 if (ch->pm_level == 0) 1407 return; 1408 1409 status = ATA_INL(ch->r_mem, AHCI_P_CMD); 1410 if ((status & AHCI_P_CMD_CPD) == 0) 1411 return; 1412 1413 if (bootverbose) { 1414 if (status & AHCI_P_CMD_CPS) { 1415 device_printf(dev, "COLD CONNECT requested\n"); 1416 } else 1417 device_printf(dev, "COLD DISCONNECT requested\n"); 1418 } 1419 ahci_reset(dev); 1420 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1421 return; 1422 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim), 1423 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1424 xpt_free_ccb(ccb); 1425 return; 1426 } 1427 xpt_rescan(ccb); 1428} 1429 1430static void 1431ahci_notify_events(device_t dev, u_int32_t status) 1432{ 1433 struct ahci_channel *ch = device_get_softc(dev); 1434 struct cam_path *dpath; 1435 int i; 1436 1437 if (ch->caps & AHCI_CAP_SSNTF) 1438 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1439 if (bootverbose) 1440 device_printf(dev, "SNTF 0x%04x\n", status); 1441 for (i = 0; i < 16; i++) { 1442 if ((status & (1 << i)) == 0) 1443 continue; 1444 if (xpt_create_path(&dpath, NULL, 1445 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1446 xpt_async(AC_SCSI_AEN, dpath, NULL); 1447 xpt_free_path(dpath); 1448 } 1449 } 1450} 1451 1452static void 1453ahci_ch_intr_locked(void *data) 1454{ 1455 device_t dev = (device_t)data; 1456 struct ahci_channel *ch = device_get_softc(dev); 1457 1458 mtx_lock(&ch->mtx); 1459 ahci_ch_intr(data); 1460 mtx_unlock(&ch->mtx); 1461} 1462 1463static void 1464ahci_ch_pm(void *arg) 1465{ 1466 device_t dev = (device_t)arg; 1467 struct ahci_channel *ch = device_get_softc(dev); 1468 uint32_t work; 1469 1470 if (ch->numrslots != 0) 1471 return; 1472 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1473 if (ch->pm_level == 4) 1474 work |= AHCI_P_CMD_PARTIAL; 1475 else 1476 work |= AHCI_P_CMD_SLUMBER; 1477 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1478} 1479 1480static void 1481ahci_ch_intr(void *data) 1482{ 1483 device_t dev = (device_t)data; 1484 struct ahci_channel *ch = device_get_softc(dev); 1485 uint32_t istatus, sstatus, cstatus, serr = 0, sntf = 0, ok, err; 1486 enum ahci_err_type et; 1487 int i, ccs, port, reset = 0; 1488 1489 /* Read and clear interrupt statuses. */ 1490 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1491 if (istatus == 0) 1492 return; 1493 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1494 /* Read command statuses. */ 1495 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1496 cstatus = ATA_INL(ch->r_mem, AHCI_P_CI); 1497 if (istatus & AHCI_P_IX_SDB) { 1498 if (ch->caps & AHCI_CAP_SSNTF) 1499 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1500 else if (ch->fbs_enabled) { 1501 u_int8_t *fis = ch->dma.rfis + 0x58; 1502 1503 for (i = 0; i < 16; i++) { 1504 if (fis[1] & 0x80) { 1505 fis[1] &= 0x7f; 1506 sntf |= 1 << i; 1507 } 1508 fis += 256; 1509 } 1510 } else { 1511 u_int8_t *fis = ch->dma.rfis + 0x58; 1512 1513 if (fis[1] & 0x80) 1514 sntf = (1 << (fis[1] & 0x0f)); 1515 } 1516 } 1517 /* Process PHY events */ 1518 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1519 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1520 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1521 if (serr) { 1522 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1523 reset = ahci_phy_check_events(dev, serr); 1524 } 1525 } 1526 /* Process cold presence detection events */ 1527 if ((istatus & AHCI_P_IX_CPD) && !reset) 1528 ahci_cpd_check_events(dev); 1529 /* Process command errors */ 1530 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1531 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1532 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1533 >> AHCI_P_CMD_CCS_SHIFT; 1534//device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1535// __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1536// serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1537 port = -1; 1538 if (ch->fbs_enabled) { 1539 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1540 if (fbs & AHCI_P_FBS_SDE) { 1541 port = (fbs & AHCI_P_FBS_DWE) 1542 >> AHCI_P_FBS_DWE_SHIFT; 1543 } else { 1544 for (i = 0; i < 16; i++) { 1545 if (ch->numrslotspd[i] == 0) 1546 continue; 1547 if (port == -1) 1548 port = i; 1549 else if (port != i) { 1550 port = -2; 1551 break; 1552 } 1553 } 1554 } 1555 } 1556 err = ch->rslots & (cstatus | sstatus); 1557 } else { 1558 ccs = 0; 1559 err = 0; 1560 port = -1; 1561 } 1562 /* Complete all successfull commands. */ 1563 ok = ch->rslots & ~(cstatus | sstatus); 1564 for (i = 0; i < ch->numslots; i++) { 1565 if ((ok >> i) & 1) 1566 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1567 } 1568 /* On error, complete the rest of commands with error statuses. */ 1569 if (err) { 1570 if (ch->frozen) { 1571 union ccb *fccb = ch->frozen; 1572 ch->frozen = NULL; 1573 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1574 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1575 xpt_freeze_devq(fccb->ccb_h.path, 1); 1576 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1577 } 1578 xpt_done(fccb); 1579 } 1580 for (i = 0; i < ch->numslots; i++) { 1581 /* XXX: reqests in loading state. */ 1582 if (((err >> i) & 1) == 0) 1583 continue; 1584 if (port >= 0 && 1585 ch->slot[i].ccb->ccb_h.target_id != port) 1586 continue; 1587 if (istatus & AHCI_P_IX_TFE) { 1588 if (port != -2) { 1589 /* Task File Error */ 1590 if (ch->numtslotspd[ 1591 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1592 /* Untagged operation. */ 1593 if (i == ccs) 1594 et = AHCI_ERR_TFE; 1595 else 1596 et = AHCI_ERR_INNOCENT; 1597 } else { 1598 /* Tagged operation. */ 1599 et = AHCI_ERR_NCQ; 1600 } 1601 } else { 1602 et = AHCI_ERR_TFE; 1603 ch->fatalerr = 1; 1604 } 1605 } else if (istatus & AHCI_P_IX_IF) { 1606 if (ch->numtslots == 0 && i != ccs && port != -2) 1607 et = AHCI_ERR_INNOCENT; 1608 else 1609 et = AHCI_ERR_SATA; 1610 } else 1611 et = AHCI_ERR_INVALID; 1612 ahci_end_transaction(&ch->slot[i], et); 1613 } 1614 /* 1615 * We can't reinit port if there are some other 1616 * commands active, use resume to complete them. 1617 */ 1618 if (ch->rslots != 0 && !ch->recoverycmd) 1619 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1620 } 1621 /* Process NOTIFY events */ 1622 if (sntf) 1623 ahci_notify_events(dev, sntf); 1624} 1625 1626/* Must be called with channel locked. */ 1627static int 1628ahci_check_collision(device_t dev, union ccb *ccb) 1629{ 1630 struct ahci_channel *ch = device_get_softc(dev); 1631 int t = ccb->ccb_h.target_id; 1632 1633 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1634 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1635 /* Tagged command while we have no supported tag free. */ 1636 if (((~ch->oslots) & (0xffffffff >> (32 - 1637 ch->curr[t].tags))) == 0) 1638 return (1); 1639 /* If we have FBS */ 1640 if (ch->fbs_enabled) { 1641 /* Tagged command while untagged are active. */ 1642 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1643 return (1); 1644 } else { 1645 /* Tagged command while untagged are active. */ 1646 if (ch->numrslots != 0 && ch->numtslots == 0) 1647 return (1); 1648 /* Tagged command while tagged to other target is active. */ 1649 if (ch->numtslots != 0 && 1650 ch->taggedtarget != ccb->ccb_h.target_id) 1651 return (1); 1652 } 1653 } else { 1654 /* If we have FBS */ 1655 if (ch->fbs_enabled) { 1656 /* Untagged command while tagged are active. */ 1657 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1658 return (1); 1659 } else { 1660 /* Untagged command while tagged are active. */ 1661 if (ch->numrslots != 0 && ch->numtslots != 0) 1662 return (1); 1663 } 1664 } 1665 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1666 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1667 /* Atomic command while anything active. */ 1668 if (ch->numrslots != 0) 1669 return (1); 1670 } 1671 /* We have some atomic command running. */ 1672 if (ch->aslots != 0) 1673 return (1); 1674 return (0); 1675} 1676 1677/* Must be called with channel locked. */ 1678static void 1679ahci_begin_transaction(device_t dev, union ccb *ccb) 1680{ 1681 struct ahci_channel *ch = device_get_softc(dev); 1682 struct ahci_slot *slot; 1683 int tag, tags; 1684 1685 /* Choose empty slot. */ 1686 tags = ch->numslots; 1687 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1688 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1689 tags = ch->curr[ccb->ccb_h.target_id].tags; 1690 tag = ch->lastslot; 1691 while (1) { 1692 if (tag >= tags) 1693 tag = 0; 1694 if (ch->slot[tag].state == AHCI_SLOT_EMPTY) 1695 break; 1696 tag++; 1697 }; 1698 ch->lastslot = tag; 1699 /* Occupy chosen slot. */ 1700 slot = &ch->slot[tag]; 1701 slot->ccb = ccb; 1702 /* Stop PM timer. */ 1703 if (ch->numrslots == 0 && ch->pm_level > 3) 1704 callout_stop(&ch->pm_timer); 1705 /* Update channel stats. */ 1706 ch->oslots |= (1 << slot->slot); 1707 ch->numrslots++; 1708 ch->numrslotspd[ccb->ccb_h.target_id]++; 1709 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1710 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1711 ch->numtslots++; 1712 ch->numtslotspd[ccb->ccb_h.target_id]++; 1713 ch->taggedtarget = ccb->ccb_h.target_id; 1714 } 1715 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1716 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1717 ch->aslots |= (1 << slot->slot); 1718 slot->dma.nsegs = 0; 1719 /* If request moves data, setup and load SG list */ 1720 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1721 void *buf; 1722 bus_size_t size; 1723 1724 slot->state = AHCI_SLOT_LOADING; 1725 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1726 buf = ccb->ataio.data_ptr; 1727 size = ccb->ataio.dxfer_len; 1728 } else { 1729 buf = ccb->csio.data_ptr; 1730 size = ccb->csio.dxfer_len; 1731 } 1732 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1733 buf, size, ahci_dmasetprd, slot, 0); 1734 } else 1735 ahci_execute_transaction(slot); 1736} 1737 1738/* Locked by busdma engine. */ 1739static void 1740ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1741{ 1742 struct ahci_slot *slot = arg; 1743 struct ahci_channel *ch = device_get_softc(slot->dev); 1744 struct ahci_cmd_tab *ctp; 1745 struct ahci_dma_prd *prd; 1746 int i; 1747 1748 if (error) { 1749 device_printf(slot->dev, "DMA load error\n"); 1750 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1751 return; 1752 } 1753 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1754 /* Get a piece of the workspace for this request */ 1755 ctp = (struct ahci_cmd_tab *) 1756 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1757 /* Fill S/G table */ 1758 prd = &ctp->prd_tab[0]; 1759 for (i = 0; i < nsegs; i++) { 1760 prd[i].dba = htole64(segs[i].ds_addr); 1761 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1762 } 1763 slot->dma.nsegs = nsegs; 1764 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1765 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1766 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1767 ahci_execute_transaction(slot); 1768} 1769 1770/* Must be called with channel locked. */ 1771static void 1772ahci_execute_transaction(struct ahci_slot *slot) 1773{ 1774 device_t dev = slot->dev; 1775 struct ahci_channel *ch = device_get_softc(dev); 1776 struct ahci_cmd_tab *ctp; 1777 struct ahci_cmd_list *clp; 1778 union ccb *ccb = slot->ccb; 1779 int port = ccb->ccb_h.target_id & 0x0f; 1780 int fis_size, i, softreset; 1781 uint8_t *fis = ch->dma.rfis + 0x40; 1782 uint8_t val; 1783 1784 /* Get a piece of the workspace for this request */ 1785 ctp = (struct ahci_cmd_tab *) 1786 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1787 /* Setup the FIS for this request */ 1788 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) { 1789 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1790 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1791 return; 1792 } 1793 /* Setup the command list entry */ 1794 clp = (struct ahci_cmd_list *) 1795 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1796 clp->cmd_flags = htole16( 1797 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1798 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1799 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1800 (fis_size / sizeof(u_int32_t)) | 1801 (port << 12)); 1802 clp->prd_length = htole16(slot->dma.nsegs); 1803 /* Special handling for Soft Reset command. */ 1804 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1805 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1806 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1807 softreset = 1; 1808 /* Kick controller into sane state */ 1809 ahci_stop(dev); 1810 ahci_clo(dev); 1811 ahci_start(dev, 0); 1812 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1813 } else { 1814 softreset = 2; 1815 /* Prepare FIS receive area for check. */ 1816 for (i = 0; i < 20; i++) 1817 fis[i] = 0xff; 1818 } 1819 } else 1820 softreset = 0; 1821 clp->bytecount = 0; 1822 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1823 (AHCI_CT_SIZE * slot->slot)); 1824 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1825 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1826 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1827 BUS_DMASYNC_PREREAD); 1828 /* Set ACTIVE bit for NCQ commands. */ 1829 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1830 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1831 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1832 } 1833 /* If FBS is enabled, set PMP port. */ 1834 if (ch->fbs_enabled) { 1835 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1836 (port << AHCI_P_FBS_DEV_SHIFT)); 1837 } 1838 /* Issue command to the controller. */ 1839 slot->state = AHCI_SLOT_RUNNING; 1840 ch->rslots |= (1 << slot->slot); 1841 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1842 /* Device reset commands doesn't interrupt. Poll them. */ 1843 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1844 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) { 1845 int count, timeout = ccb->ccb_h.timeout * 100; 1846 enum ahci_err_type et = AHCI_ERR_NONE; 1847 1848 for (count = 0; count < timeout; count++) { 1849 DELAY(10); 1850 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1851 break; 1852 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) && 1853 softreset != 1) { 1854#if 0 1855 device_printf(ch->dev, 1856 "Poll error on slot %d, TFD: %04x\n", 1857 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1858#endif 1859 et = AHCI_ERR_TFE; 1860 break; 1861 } 1862 /* Workaround for ATI SB600/SB700 chipsets. */ 1863 if (ccb->ccb_h.target_id == 15 && 1864 pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1865 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1866 et = AHCI_ERR_TIMEOUT; 1867 break; 1868 } 1869 } 1870 1871 /* Marvell controllers do not wait for readyness. */ 1872 if ((ch->quirks & AHCI_Q_NOBSYRES) && softreset == 2 && 1873 et == AHCI_ERR_NONE) { 1874 while ((val = fis[2]) & ATA_S_BUSY) { 1875 DELAY(10); 1876 if (count++ >= timeout) 1877 break; 1878 } 1879 } 1880 1881 if (timeout && (count >= timeout)) { 1882 device_printf(dev, "Poll timeout on slot %d port %d\n", 1883 slot->slot, port); 1884 device_printf(dev, "is %08x cs %08x ss %08x " 1885 "rs %08x tfd %02x serr %08x cmd %08x\n", 1886 ATA_INL(ch->r_mem, AHCI_P_IS), 1887 ATA_INL(ch->r_mem, AHCI_P_CI), 1888 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1889 ATA_INL(ch->r_mem, AHCI_P_TFD), 1890 ATA_INL(ch->r_mem, AHCI_P_SERR), 1891 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1892 et = AHCI_ERR_TIMEOUT; 1893 } 1894 1895 /* Kick controller into sane state and enable FBS. */ 1896 if (softreset == 2) 1897 ch->eslots |= (1 << slot->slot); 1898 ahci_end_transaction(slot, et); 1899 return; 1900 } 1901 /* Start command execution timeout */ 1902 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 1903 (timeout_t*)ahci_timeout, slot); 1904 return; 1905} 1906 1907/* Must be called with channel locked. */ 1908static void 1909ahci_process_timeout(device_t dev) 1910{ 1911 struct ahci_channel *ch = device_get_softc(dev); 1912 int i; 1913 1914 mtx_assert(&ch->mtx, MA_OWNED); 1915 /* Handle the rest of commands. */ 1916 for (i = 0; i < ch->numslots; i++) { 1917 /* Do we have a running request on slot? */ 1918 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1919 continue; 1920 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 1921 } 1922} 1923 1924/* Must be called with channel locked. */ 1925static void 1926ahci_rearm_timeout(device_t dev) 1927{ 1928 struct ahci_channel *ch = device_get_softc(dev); 1929 int i; 1930 1931 mtx_assert(&ch->mtx, MA_OWNED); 1932 for (i = 0; i < ch->numslots; i++) { 1933 struct ahci_slot *slot = &ch->slot[i]; 1934 1935 /* Do we have a running request on slot? */ 1936 if (slot->state < AHCI_SLOT_RUNNING) 1937 continue; 1938 if ((ch->toslots & (1 << i)) == 0) 1939 continue; 1940 callout_reset(&slot->timeout, 1941 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1942 (timeout_t*)ahci_timeout, slot); 1943 } 1944} 1945 1946/* Locked by callout mechanism. */ 1947static void 1948ahci_timeout(struct ahci_slot *slot) 1949{ 1950 device_t dev = slot->dev; 1951 struct ahci_channel *ch = device_get_softc(dev); 1952 uint32_t sstatus; 1953 int ccs; 1954 int i; 1955 1956 /* Check for stale timeout. */ 1957 if (slot->state < AHCI_SLOT_RUNNING) 1958 return; 1959 1960 /* Check if slot was not being executed last time we checked. */ 1961 if (slot->state < AHCI_SLOT_EXECUTING) { 1962 /* Check if slot started executing. */ 1963 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1964 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1965 >> AHCI_P_CMD_CCS_SHIFT; 1966 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 1967 ch->fbs_enabled || ch->wrongccs) 1968 slot->state = AHCI_SLOT_EXECUTING; 1969 else if ((ch->rslots & (1 << ccs)) == 0) { 1970 ch->wrongccs = 1; 1971 slot->state = AHCI_SLOT_EXECUTING; 1972 } 1973 1974 callout_reset(&slot->timeout, 1975 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1976 (timeout_t*)ahci_timeout, slot); 1977 return; 1978 } 1979 1980 device_printf(dev, "Timeout on slot %d port %d\n", 1981 slot->slot, slot->ccb->ccb_h.target_id & 0x0f); 1982 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x " 1983 "serr %08x cmd %08x\n", 1984 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1985 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1986 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR), 1987 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1988 1989 /* Handle frozen command. */ 1990 if (ch->frozen) { 1991 union ccb *fccb = ch->frozen; 1992 ch->frozen = NULL; 1993 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1994 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1995 xpt_freeze_devq(fccb->ccb_h.path, 1); 1996 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1997 } 1998 xpt_done(fccb); 1999 } 2000 if (!ch->fbs_enabled && !ch->wrongccs) { 2001 /* Without FBS we know real timeout source. */ 2002 ch->fatalerr = 1; 2003 /* Handle command with timeout. */ 2004 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 2005 /* Handle the rest of commands. */ 2006 for (i = 0; i < ch->numslots; i++) { 2007 /* Do we have a running request on slot? */ 2008 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2009 continue; 2010 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2011 } 2012 } else { 2013 /* With FBS we wait for other commands timeout and pray. */ 2014 if (ch->toslots == 0) 2015 xpt_freeze_simq(ch->sim, 1); 2016 ch->toslots |= (1 << slot->slot); 2017 if ((ch->rslots & ~ch->toslots) == 0) 2018 ahci_process_timeout(dev); 2019 else 2020 device_printf(dev, " ... waiting for slots %08x\n", 2021 ch->rslots & ~ch->toslots); 2022 } 2023} 2024 2025/* Must be called with channel locked. */ 2026static void 2027ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 2028{ 2029 device_t dev = slot->dev; 2030 struct ahci_channel *ch = device_get_softc(dev); 2031 union ccb *ccb = slot->ccb; 2032 struct ahci_cmd_list *clp; 2033 int lastto; 2034 uint32_t sig; 2035 2036 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 2037 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2038 clp = (struct ahci_cmd_list *) 2039 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 2040 /* Read result registers to the result struct 2041 * May be incorrect if several commands finished same time, 2042 * so read only when sure or have to. 2043 */ 2044 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2045 struct ata_res *res = &ccb->ataio.res; 2046 2047 if ((et == AHCI_ERR_TFE) || 2048 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 2049 u_int8_t *fis = ch->dma.rfis + 0x40; 2050 2051 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 2052 BUS_DMASYNC_POSTREAD); 2053 if (ch->fbs_enabled) { 2054 fis += ccb->ccb_h.target_id * 256; 2055 res->status = fis[2]; 2056 res->error = fis[3]; 2057 } else { 2058 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 2059 2060 res->status = tfd; 2061 res->error = tfd >> 8; 2062 } 2063 res->lba_low = fis[4]; 2064 res->lba_mid = fis[5]; 2065 res->lba_high = fis[6]; 2066 res->device = fis[7]; 2067 res->lba_low_exp = fis[8]; 2068 res->lba_mid_exp = fis[9]; 2069 res->lba_high_exp = fis[10]; 2070 res->sector_count = fis[12]; 2071 res->sector_count_exp = fis[13]; 2072 2073 /* 2074 * Some weird controllers do not return signature in 2075 * FIS receive area. Read it from PxSIG register. 2076 */ 2077 if ((ch->quirks & AHCI_Q_ALTSIG) && 2078 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2079 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 2080 sig = ATA_INL(ch->r_mem, AHCI_P_SIG); 2081 res->lba_high = sig >> 24; 2082 res->lba_mid = sig >> 16; 2083 res->lba_low = sig >> 8; 2084 res->sector_count = sig; 2085 } 2086 } else 2087 bzero(res, sizeof(*res)); 2088 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 2089 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2090 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2091 ccb->ataio.resid = 2092 ccb->ataio.dxfer_len - le32toh(clp->bytecount); 2093 } 2094 } else { 2095 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2096 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2097 ccb->csio.resid = 2098 ccb->csio.dxfer_len - le32toh(clp->bytecount); 2099 } 2100 } 2101 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2102 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 2103 (ccb->ccb_h.flags & CAM_DIR_IN) ? 2104 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2105 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 2106 } 2107 if (et != AHCI_ERR_NONE) 2108 ch->eslots |= (1 << slot->slot); 2109 /* In case of error, freeze device for proper recovery. */ 2110 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) && 2111 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 2112 xpt_freeze_devq(ccb->ccb_h.path, 1); 2113 ccb->ccb_h.status |= CAM_DEV_QFRZN; 2114 } 2115 /* Set proper result status. */ 2116 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2117 switch (et) { 2118 case AHCI_ERR_NONE: 2119 ccb->ccb_h.status |= CAM_REQ_CMP; 2120 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 2121 ccb->csio.scsi_status = SCSI_STATUS_OK; 2122 break; 2123 case AHCI_ERR_INVALID: 2124 ch->fatalerr = 1; 2125 ccb->ccb_h.status |= CAM_REQ_INVALID; 2126 break; 2127 case AHCI_ERR_INNOCENT: 2128 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 2129 break; 2130 case AHCI_ERR_TFE: 2131 case AHCI_ERR_NCQ: 2132 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2133 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2134 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2135 } else { 2136 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 2137 } 2138 break; 2139 case AHCI_ERR_SATA: 2140 ch->fatalerr = 1; 2141 if (!ch->recoverycmd) { 2142 xpt_freeze_simq(ch->sim, 1); 2143 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2144 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2145 } 2146 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 2147 break; 2148 case AHCI_ERR_TIMEOUT: 2149 if (!ch->recoverycmd) { 2150 xpt_freeze_simq(ch->sim, 1); 2151 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2152 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2153 } 2154 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 2155 break; 2156 default: 2157 ch->fatalerr = 1; 2158 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 2159 } 2160 /* Free slot. */ 2161 ch->oslots &= ~(1 << slot->slot); 2162 ch->rslots &= ~(1 << slot->slot); 2163 ch->aslots &= ~(1 << slot->slot); 2164 slot->state = AHCI_SLOT_EMPTY; 2165 slot->ccb = NULL; 2166 /* Update channel stats. */ 2167 ch->numrslots--; 2168 ch->numrslotspd[ccb->ccb_h.target_id]--; 2169 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2170 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 2171 ch->numtslots--; 2172 ch->numtslotspd[ccb->ccb_h.target_id]--; 2173 } 2174 /* Cancel timeout state if request completed normally. */ 2175 if (et != AHCI_ERR_TIMEOUT) { 2176 lastto = (ch->toslots == (1 << slot->slot)); 2177 ch->toslots &= ~(1 << slot->slot); 2178 if (lastto) 2179 xpt_release_simq(ch->sim, TRUE); 2180 } 2181 /* If it was first request of reset sequence and there is no error, 2182 * proceed to second request. */ 2183 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2184 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2185 (ccb->ataio.cmd.control & ATA_A_RESET) && 2186 et == AHCI_ERR_NONE) { 2187 ccb->ataio.cmd.control &= ~ATA_A_RESET; 2188 ahci_begin_transaction(dev, ccb); 2189 return; 2190 } 2191 /* If it was our READ LOG command - process it. */ 2192 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 2193 ahci_process_read_log(dev, ccb); 2194 /* If it was our REQUEST SENSE command - process it. */ 2195 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 2196 ahci_process_request_sense(dev, ccb); 2197 /* If it was NCQ or ATAPI command error, put result on hold. */ 2198 } else if (et == AHCI_ERR_NCQ || 2199 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 2200 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 2201 ch->hold[slot->slot] = ccb; 2202 ch->numhslots++; 2203 } else 2204 xpt_done(ccb); 2205 /* If we have no other active commands, ... */ 2206 if (ch->rslots == 0) { 2207 /* if there was fatal error - reset port. */ 2208 if (ch->toslots != 0 || ch->fatalerr) { 2209 ahci_reset(dev); 2210 } else { 2211 /* if we have slots in error, we can reinit port. */ 2212 if (ch->eslots != 0) { 2213 ahci_stop(dev); 2214 ahci_clo(dev); 2215 ahci_start(dev, 1); 2216 } 2217 /* if there commands on hold, we can do READ LOG. */ 2218 if (!ch->recoverycmd && ch->numhslots) 2219 ahci_issue_recovery(dev); 2220 } 2221 /* If all the rest of commands are in timeout - give them chance. */ 2222 } else if ((ch->rslots & ~ch->toslots) == 0 && 2223 et != AHCI_ERR_TIMEOUT) 2224 ahci_rearm_timeout(dev); 2225 /* Unfreeze frozen command. */ 2226 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) { 2227 union ccb *fccb = ch->frozen; 2228 ch->frozen = NULL; 2229 ahci_begin_transaction(dev, fccb); 2230 xpt_release_simq(ch->sim, TRUE); 2231 } 2232 /* Start PM timer. */ 2233 if (ch->numrslots == 0 && ch->pm_level > 3 && 2234 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 2235 callout_schedule(&ch->pm_timer, 2236 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 2237 } 2238} 2239 2240static void 2241ahci_issue_recovery(device_t dev) 2242{ 2243 struct ahci_channel *ch = device_get_softc(dev); 2244 union ccb *ccb; 2245 struct ccb_ataio *ataio; 2246 struct ccb_scsiio *csio; 2247 int i; 2248 2249 /* Find some held command. */ 2250 for (i = 0; i < ch->numslots; i++) { 2251 if (ch->hold[i]) 2252 break; 2253 } 2254 ccb = xpt_alloc_ccb_nowait(); 2255 if (ccb == NULL) { 2256 device_printf(dev, "Unable to allocate recovery command\n"); 2257completeall: 2258 /* We can't do anything -- complete held commands. */ 2259 for (i = 0; i < ch->numslots; i++) { 2260 if (ch->hold[i] == NULL) 2261 continue; 2262 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2263 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 2264 xpt_done(ch->hold[i]); 2265 ch->hold[i] = NULL; 2266 ch->numhslots--; 2267 } 2268 ahci_reset(dev); 2269 return; 2270 } 2271 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 2272 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2273 /* READ LOG */ 2274 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 2275 ccb->ccb_h.func_code = XPT_ATA_IO; 2276 ccb->ccb_h.flags = CAM_DIR_IN; 2277 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2278 ataio = &ccb->ataio; 2279 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 2280 if (ataio->data_ptr == NULL) { 2281 xpt_free_ccb(ccb); 2282 device_printf(dev, 2283 "Unable to allocate memory for READ LOG command\n"); 2284 goto completeall; 2285 } 2286 ataio->dxfer_len = 512; 2287 bzero(&ataio->cmd, sizeof(ataio->cmd)); 2288 ataio->cmd.flags = CAM_ATAIO_48BIT; 2289 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2290 ataio->cmd.sector_count = 1; 2291 ataio->cmd.sector_count_exp = 0; 2292 ataio->cmd.lba_low = 0x10; 2293 ataio->cmd.lba_mid = 0; 2294 ataio->cmd.lba_mid_exp = 0; 2295 } else { 2296 /* REQUEST SENSE */ 2297 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 2298 ccb->ccb_h.recovery_slot = i; 2299 ccb->ccb_h.func_code = XPT_SCSI_IO; 2300 ccb->ccb_h.flags = CAM_DIR_IN; 2301 ccb->ccb_h.status = 0; 2302 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2303 csio = &ccb->csio; 2304 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 2305 csio->dxfer_len = ch->hold[i]->csio.sense_len; 2306 csio->cdb_len = 6; 2307 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 2308 csio->cdb_io.cdb_bytes[0] = 0x03; 2309 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 2310 } 2311 /* Freeze SIM while doing recovery. */ 2312 ch->recoverycmd = 1; 2313 xpt_freeze_simq(ch->sim, 1); 2314 ahci_begin_transaction(dev, ccb); 2315} 2316 2317static void 2318ahci_process_read_log(device_t dev, union ccb *ccb) 2319{ 2320 struct ahci_channel *ch = device_get_softc(dev); 2321 uint8_t *data; 2322 struct ata_res *res; 2323 int i; 2324 2325 ch->recoverycmd = 0; 2326 2327 data = ccb->ataio.data_ptr; 2328 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2329 (data[0] & 0x80) == 0) { 2330 for (i = 0; i < ch->numslots; i++) { 2331 if (!ch->hold[i]) 2332 continue; 2333 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2334 continue; 2335 if ((data[0] & 0x1F) == i) { 2336 res = &ch->hold[i]->ataio.res; 2337 res->status = data[2]; 2338 res->error = data[3]; 2339 res->lba_low = data[4]; 2340 res->lba_mid = data[5]; 2341 res->lba_high = data[6]; 2342 res->device = data[7]; 2343 res->lba_low_exp = data[8]; 2344 res->lba_mid_exp = data[9]; 2345 res->lba_high_exp = data[10]; 2346 res->sector_count = data[12]; 2347 res->sector_count_exp = data[13]; 2348 } else { 2349 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2350 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2351 } 2352 xpt_done(ch->hold[i]); 2353 ch->hold[i] = NULL; 2354 ch->numhslots--; 2355 } 2356 } else { 2357 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2358 device_printf(dev, "Error while READ LOG EXT\n"); 2359 else if ((data[0] & 0x80) == 0) { 2360 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 2361 } 2362 for (i = 0; i < ch->numslots; i++) { 2363 if (!ch->hold[i]) 2364 continue; 2365 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2366 continue; 2367 xpt_done(ch->hold[i]); 2368 ch->hold[i] = NULL; 2369 ch->numhslots--; 2370 } 2371 } 2372 free(ccb->ataio.data_ptr, M_AHCI); 2373 xpt_free_ccb(ccb); 2374 xpt_release_simq(ch->sim, TRUE); 2375} 2376 2377static void 2378ahci_process_request_sense(device_t dev, union ccb *ccb) 2379{ 2380 struct ahci_channel *ch = device_get_softc(dev); 2381 int i; 2382 2383 ch->recoverycmd = 0; 2384 2385 i = ccb->ccb_h.recovery_slot; 2386 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 2387 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 2388 } else { 2389 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2390 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 2391 } 2392 xpt_done(ch->hold[i]); 2393 ch->hold[i] = NULL; 2394 ch->numhslots--; 2395 xpt_free_ccb(ccb); 2396 xpt_release_simq(ch->sim, TRUE); 2397} 2398 2399static void 2400ahci_start(device_t dev, int fbs) 2401{ 2402 struct ahci_channel *ch = device_get_softc(dev); 2403 u_int32_t cmd; 2404 2405 /* Clear SATA error register */ 2406 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2407 /* Clear any interrupts pending on this channel */ 2408 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2409 /* Configure FIS-based switching if supported. */ 2410 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2411 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2412 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2413 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2414 } 2415 /* Start operations on this channel */ 2416 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2417 cmd &= ~AHCI_P_CMD_PMA; 2418 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2419 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2420} 2421 2422static void 2423ahci_stop(device_t dev) 2424{ 2425 struct ahci_channel *ch = device_get_softc(dev); 2426 u_int32_t cmd; 2427 int timeout; 2428 2429 /* Kill all activity on this channel */ 2430 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2431 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2432 /* Wait for activity stop. */ 2433 timeout = 0; 2434 do { 2435 DELAY(10); 2436 if (timeout++ > 50000) { 2437 device_printf(dev, "stopping AHCI engine failed\n"); 2438 break; 2439 } 2440 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2441 ch->eslots = 0; 2442} 2443 2444static void 2445ahci_clo(device_t dev) 2446{ 2447 struct ahci_channel *ch = device_get_softc(dev); 2448 u_int32_t cmd; 2449 int timeout; 2450 2451 /* Issue Command List Override if supported */ 2452 if (ch->caps & AHCI_CAP_SCLO) { 2453 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2454 cmd |= AHCI_P_CMD_CLO; 2455 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2456 timeout = 0; 2457 do { 2458 DELAY(10); 2459 if (timeout++ > 50000) { 2460 device_printf(dev, "executing CLO failed\n"); 2461 break; 2462 } 2463 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2464 } 2465} 2466 2467static void 2468ahci_stop_fr(device_t dev) 2469{ 2470 struct ahci_channel *ch = device_get_softc(dev); 2471 u_int32_t cmd; 2472 int timeout; 2473 2474 /* Kill all FIS reception on this channel */ 2475 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2476 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2477 /* Wait for FIS reception stop. */ 2478 timeout = 0; 2479 do { 2480 DELAY(10); 2481 if (timeout++ > 50000) { 2482 device_printf(dev, "stopping AHCI FR engine failed\n"); 2483 break; 2484 } 2485 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2486} 2487 2488static void 2489ahci_start_fr(device_t dev) 2490{ 2491 struct ahci_channel *ch = device_get_softc(dev); 2492 u_int32_t cmd; 2493 2494 /* Start FIS reception on this channel */ 2495 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2496 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2497} 2498 2499static int 2500ahci_wait_ready(device_t dev, int t, int t0) 2501{ 2502 struct ahci_channel *ch = device_get_softc(dev); 2503 int timeout = 0; 2504 uint32_t val; 2505 2506 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2507 (ATA_S_BUSY | ATA_S_DRQ)) { 2508 if (timeout > t) { 2509 if (t != 0) { 2510 device_printf(dev, 2511 "AHCI reset: device not ready after %dms " 2512 "(tfd = %08x)\n", 2513 MAX(t, 0) + t0, val); 2514 } 2515 return (EBUSY); 2516 } 2517 DELAY(1000); 2518 timeout++; 2519 } 2520 if (bootverbose) 2521 device_printf(dev, "AHCI reset: device ready after %dms\n", 2522 timeout + t0); 2523 return (0); 2524} 2525 2526static void 2527ahci_reset_to(void *arg) 2528{ 2529 device_t dev = arg; 2530 struct ahci_channel *ch = device_get_softc(dev); 2531 2532 if (ch->resetting == 0) 2533 return; 2534 ch->resetting--; 2535 if (ahci_wait_ready(dev, ch->resetting == 0 ? -1 : 0, 2536 (310 - ch->resetting) * 100) == 0) { 2537 ch->resetting = 0; 2538 ahci_start(dev, 1); 2539 xpt_release_simq(ch->sim, TRUE); 2540 return; 2541 } 2542 if (ch->resetting == 0) { 2543 ahci_clo(dev); 2544 ahci_start(dev, 1); 2545 xpt_release_simq(ch->sim, TRUE); 2546 return; 2547 } 2548 callout_schedule(&ch->reset_timer, hz / 10); 2549} 2550 2551static void 2552ahci_reset(device_t dev) 2553{ 2554 struct ahci_channel *ch = device_get_softc(dev); 2555 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2556 int i; 2557 2558 xpt_freeze_simq(ch->sim, 1); 2559 if (bootverbose) 2560 device_printf(dev, "AHCI reset...\n"); 2561 /* Forget about previous reset. */ 2562 if (ch->resetting) { 2563 ch->resetting = 0; 2564 callout_stop(&ch->reset_timer); 2565 xpt_release_simq(ch->sim, TRUE); 2566 } 2567 /* Requeue freezed command. */ 2568 if (ch->frozen) { 2569 union ccb *fccb = ch->frozen; 2570 ch->frozen = NULL; 2571 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2572 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2573 xpt_freeze_devq(fccb->ccb_h.path, 1); 2574 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2575 } 2576 xpt_done(fccb); 2577 } 2578 /* Kill the engine and requeue all running commands. */ 2579 ahci_stop(dev); 2580 for (i = 0; i < ch->numslots; i++) { 2581 /* Do we have a running request on slot? */ 2582 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2583 continue; 2584 /* XXX; Commands in loading state. */ 2585 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2586 } 2587 for (i = 0; i < ch->numslots; i++) { 2588 if (!ch->hold[i]) 2589 continue; 2590 xpt_done(ch->hold[i]); 2591 ch->hold[i] = NULL; 2592 ch->numhslots--; 2593 } 2594 if (ch->toslots != 0) 2595 xpt_release_simq(ch->sim, TRUE); 2596 ch->eslots = 0; 2597 ch->toslots = 0; 2598 ch->wrongccs = 0; 2599 ch->fatalerr = 0; 2600 /* Tell the XPT about the event */ 2601 xpt_async(AC_BUS_RESET, ch->path, NULL); 2602 /* Disable port interrupts */ 2603 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2604 /* Reset and reconnect PHY, */ 2605 if (!ahci_sata_phy_reset(dev)) { 2606 if (bootverbose) 2607 device_printf(dev, 2608 "AHCI reset: device not found\n"); 2609 ch->devices = 0; 2610 /* Enable wanted port interrupts */ 2611 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2612 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2613 AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2614 xpt_release_simq(ch->sim, TRUE); 2615 return; 2616 } 2617 if (bootverbose) 2618 device_printf(dev, "AHCI reset: device found\n"); 2619 /* Wait for clearing busy status. */ 2620 if (ahci_wait_ready(dev, dumping ? 31000 : 0, 0)) { 2621 if (dumping) 2622 ahci_clo(dev); 2623 else 2624 ch->resetting = 310; 2625 } 2626 ch->devices = 1; 2627 /* Enable wanted port interrupts */ 2628 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2629 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2630 AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2631 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2632 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC | 2633 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2634 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2635 if (ch->resetting) 2636 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, dev); 2637 else { 2638 ahci_start(dev, 1); 2639 xpt_release_simq(ch->sim, TRUE); 2640 } 2641} 2642 2643static int 2644ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2645{ 2646 struct ahci_channel *ch = device_get_softc(dev); 2647 u_int8_t *fis = &ctp->cfis[0]; 2648 2649 bzero(ctp->cfis, 64); 2650 fis[0] = 0x27; /* host to device */ 2651 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2652 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2653 fis[1] |= 0x80; 2654 fis[2] = ATA_PACKET_CMD; 2655 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2656 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2657 fis[3] = ATA_F_DMA; 2658 else { 2659 fis[5] = ccb->csio.dxfer_len; 2660 fis[6] = ccb->csio.dxfer_len >> 8; 2661 } 2662 fis[7] = ATA_D_LBA; 2663 fis[15] = ATA_A_4BIT; 2664 bzero(ctp->acmd, 32); 2665 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2666 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2667 ctp->acmd, ccb->csio.cdb_len); 2668 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2669 fis[1] |= 0x80; 2670 fis[2] = ccb->ataio.cmd.command; 2671 fis[3] = ccb->ataio.cmd.features; 2672 fis[4] = ccb->ataio.cmd.lba_low; 2673 fis[5] = ccb->ataio.cmd.lba_mid; 2674 fis[6] = ccb->ataio.cmd.lba_high; 2675 fis[7] = ccb->ataio.cmd.device; 2676 fis[8] = ccb->ataio.cmd.lba_low_exp; 2677 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2678 fis[10] = ccb->ataio.cmd.lba_high_exp; 2679 fis[11] = ccb->ataio.cmd.features_exp; 2680 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2681 fis[12] = tag << 3; 2682 fis[13] = 0; 2683 } else { 2684 fis[12] = ccb->ataio.cmd.sector_count; 2685 fis[13] = ccb->ataio.cmd.sector_count_exp; 2686 } 2687 fis[15] = ATA_A_4BIT; 2688 } else { 2689 fis[15] = ccb->ataio.cmd.control; 2690 } 2691 return (20); 2692} 2693 2694static int 2695ahci_sata_connect(struct ahci_channel *ch) 2696{ 2697 u_int32_t status; 2698 int timeout, found = 0; 2699 2700 /* Wait up to 100ms for "connect well" */ 2701 for (timeout = 0; timeout < 1000 ; timeout++) { 2702 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2703 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 2704 found = 1; 2705 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2706 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2707 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2708 break; 2709 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2710 if (bootverbose) { 2711 device_printf(ch->dev, "SATA offline status=%08x\n", 2712 status); 2713 } 2714 return (0); 2715 } 2716 if (found == 0 && timeout >= 100) 2717 break; 2718 DELAY(100); 2719 } 2720 if (timeout >= 1000 || !found) { 2721 if (bootverbose) { 2722 device_printf(ch->dev, 2723 "SATA connect timeout time=%dus status=%08x\n", 2724 timeout * 100, status); 2725 } 2726 return (0); 2727 } 2728 if (bootverbose) { 2729 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2730 timeout * 100, status); 2731 } 2732 /* Clear SATA error register */ 2733 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2734 return (1); 2735} 2736 2737static int 2738ahci_sata_phy_reset(device_t dev) 2739{ 2740 struct ahci_channel *ch = device_get_softc(dev); 2741 int sata_rev; 2742 uint32_t val; 2743 2744 if (ch->listening) { 2745 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2746 val |= AHCI_P_CMD_SUD; 2747 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2748 ch->listening = 0; 2749 } 2750 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2751 if (sata_rev == 1) 2752 val = ATA_SC_SPD_SPEED_GEN1; 2753 else if (sata_rev == 2) 2754 val = ATA_SC_SPD_SPEED_GEN2; 2755 else if (sata_rev == 3) 2756 val = ATA_SC_SPD_SPEED_GEN3; 2757 else 2758 val = 0; 2759 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2760 ATA_SC_DET_RESET | val | 2761 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2762 DELAY(1000); 2763 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2764 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2765 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2766 if (!ahci_sata_connect(ch)) { 2767 if (ch->caps & AHCI_CAP_SSS) { 2768 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2769 val &= ~AHCI_P_CMD_SUD; 2770 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2771 ch->listening = 1; 2772 } else if (ch->pm_level > 0) 2773 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2774 return (0); 2775 } 2776 return (1); 2777} 2778 2779static int 2780ahci_check_ids(device_t dev, union ccb *ccb) 2781{ 2782 struct ahci_channel *ch = device_get_softc(dev); 2783 2784 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2785 ccb->ccb_h.status = CAM_TID_INVALID; 2786 xpt_done(ccb); 2787 return (-1); 2788 } 2789 if (ccb->ccb_h.target_lun != 0) { 2790 ccb->ccb_h.status = CAM_LUN_INVALID; 2791 xpt_done(ccb); 2792 return (-1); 2793 } 2794 return (0); 2795} 2796 2797static void 2798ahciaction(struct cam_sim *sim, union ccb *ccb) 2799{ 2800 device_t dev, parent; 2801 struct ahci_channel *ch; 2802 2803 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2804 ccb->ccb_h.func_code)); 2805 2806 ch = (struct ahci_channel *)cam_sim_softc(sim); 2807 dev = ch->dev; 2808 switch (ccb->ccb_h.func_code) { 2809 /* Common cases first */ 2810 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2811 case XPT_SCSI_IO: 2812 if (ahci_check_ids(dev, ccb)) 2813 return; 2814 if (ch->devices == 0 || 2815 (ch->pm_present == 0 && 2816 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2817 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2818 break; 2819 } 2820 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2821 /* Check for command collision. */ 2822 if (ahci_check_collision(dev, ccb)) { 2823 /* Freeze command. */ 2824 ch->frozen = ccb; 2825 /* We have only one frozen slot, so freeze simq also. */ 2826 xpt_freeze_simq(ch->sim, 1); 2827 return; 2828 } 2829 ahci_begin_transaction(dev, ccb); 2830 return; 2831 case XPT_EN_LUN: /* Enable LUN as a target */ 2832 case XPT_TARGET_IO: /* Execute target I/O request */ 2833 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2834 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2835 case XPT_ABORT: /* Abort the specified CCB */ 2836 /* XXX Implement */ 2837 ccb->ccb_h.status = CAM_REQ_INVALID; 2838 break; 2839 case XPT_SET_TRAN_SETTINGS: 2840 { 2841 struct ccb_trans_settings *cts = &ccb->cts; 2842 struct ahci_device *d; 2843 2844 if (ahci_check_ids(dev, ccb)) 2845 return; 2846 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2847 d = &ch->curr[ccb->ccb_h.target_id]; 2848 else 2849 d = &ch->user[ccb->ccb_h.target_id]; 2850 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2851 d->revision = cts->xport_specific.sata.revision; 2852 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2853 d->mode = cts->xport_specific.sata.mode; 2854 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2855 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2856 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2857 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2858 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2859 ch->pm_present = cts->xport_specific.sata.pm_present; 2860 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2861 d->atapi = cts->xport_specific.sata.atapi; 2862 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2863 d->caps = cts->xport_specific.sata.caps; 2864 ccb->ccb_h.status = CAM_REQ_CMP; 2865 break; 2866 } 2867 case XPT_GET_TRAN_SETTINGS: 2868 /* Get default/user set transfer settings for the target */ 2869 { 2870 struct ccb_trans_settings *cts = &ccb->cts; 2871 struct ahci_device *d; 2872 uint32_t status; 2873 2874 if (ahci_check_ids(dev, ccb)) 2875 return; 2876 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2877 d = &ch->curr[ccb->ccb_h.target_id]; 2878 else 2879 d = &ch->user[ccb->ccb_h.target_id]; 2880 cts->protocol = PROTO_ATA; 2881 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2882 cts->transport = XPORT_SATA; 2883 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2884 cts->proto_specific.valid = 0; 2885 cts->xport_specific.sata.valid = 0; 2886 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2887 (ccb->ccb_h.target_id == 15 || 2888 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2889 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2890 if (status & 0x0f0) { 2891 cts->xport_specific.sata.revision = 2892 (status & 0x0f0) >> 4; 2893 cts->xport_specific.sata.valid |= 2894 CTS_SATA_VALID_REVISION; 2895 } 2896 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2897 if (ch->pm_level) { 2898 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 2899 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2900 if (ch->caps2 & AHCI_CAP2_APST) 2901 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 2902 } 2903 if ((ch->caps & AHCI_CAP_SNCQ) && 2904 (ch->quirks & AHCI_Q_NOAA) == 0) 2905 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 2906 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 2907 cts->xport_specific.sata.caps &= 2908 ch->user[ccb->ccb_h.target_id].caps; 2909 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2910 } else { 2911 cts->xport_specific.sata.revision = d->revision; 2912 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2913 cts->xport_specific.sata.caps = d->caps; 2914 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2915 } 2916 cts->xport_specific.sata.mode = d->mode; 2917 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2918 cts->xport_specific.sata.bytecount = d->bytecount; 2919 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2920 cts->xport_specific.sata.pm_present = ch->pm_present; 2921 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2922 cts->xport_specific.sata.tags = d->tags; 2923 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2924 cts->xport_specific.sata.atapi = d->atapi; 2925 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2926 ccb->ccb_h.status = CAM_REQ_CMP; 2927 break; 2928 } 2929 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2930 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2931 ahci_reset(dev); 2932 ccb->ccb_h.status = CAM_REQ_CMP; 2933 break; 2934 case XPT_TERM_IO: /* Terminate the I/O process */ 2935 /* XXX Implement */ 2936 ccb->ccb_h.status = CAM_REQ_INVALID; 2937 break; 2938 case XPT_PATH_INQ: /* Path routing inquiry */ 2939 { 2940 struct ccb_pathinq *cpi = &ccb->cpi; 2941 2942 parent = device_get_parent(dev); 2943 cpi->version_num = 1; /* XXX??? */ 2944 cpi->hba_inquiry = PI_SDTR_ABLE; 2945 if (ch->caps & AHCI_CAP_SNCQ) 2946 cpi->hba_inquiry |= PI_TAG_ABLE; 2947 if (ch->caps & AHCI_CAP_SPM) 2948 cpi->hba_inquiry |= PI_SATAPM; 2949 cpi->target_sprt = 0; 2950 cpi->hba_misc = PIM_SEQSCAN; 2951 cpi->hba_eng_cnt = 0; 2952 if (ch->caps & AHCI_CAP_SPM) 2953 cpi->max_target = 15; 2954 else 2955 cpi->max_target = 0; 2956 cpi->max_lun = 0; 2957 cpi->initiator_id = 0; 2958 cpi->bus_id = cam_sim_bus(sim); 2959 cpi->base_transfer_speed = 150000; 2960 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2961 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2962 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2963 cpi->unit_number = cam_sim_unit(sim); 2964 cpi->transport = XPORT_SATA; 2965 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2966 cpi->protocol = PROTO_ATA; 2967 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2968 cpi->maxio = MAXPHYS; 2969 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2970 if (pci_get_devid(parent) == 0x43801002) 2971 cpi->maxio = min(cpi->maxio, 128 * 512); 2972 cpi->hba_vendor = pci_get_vendor(parent); 2973 cpi->hba_device = pci_get_device(parent); 2974 cpi->hba_subvendor = pci_get_subvendor(parent); 2975 cpi->hba_subdevice = pci_get_subdevice(parent); 2976 cpi->ccb_h.status = CAM_REQ_CMP; 2977 break; 2978 } 2979 default: 2980 ccb->ccb_h.status = CAM_REQ_INVALID; 2981 break; 2982 } 2983 xpt_done(ccb); 2984} 2985 2986static void 2987ahcipoll(struct cam_sim *sim) 2988{ 2989 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2990 2991 ahci_ch_intr(ch->dev); 2992 if (ch->resetting != 0 && 2993 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 2994 ch->resetpolldiv = 1000; 2995 ahci_reset_to(ch->dev); 2996 } 2997} 2998