ahci_generic.c revision 199278
1/*- 2 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ahci/ahci.c 199278 2009-11-14 20:06:04Z mav $"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/ata.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/malloc.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <sys/sema.h> 41#include <sys/taskqueue.h> 42#include <vm/uma.h> 43#include <machine/stdarg.h> 44#include <machine/resource.h> 45#include <machine/bus.h> 46#include <sys/rman.h> 47#include <dev/pci/pcivar.h> 48#include <dev/pci/pcireg.h> 49#include "ahci.h" 50 51#include <cam/cam.h> 52#include <cam/cam_ccb.h> 53#include <cam/cam_sim.h> 54#include <cam/cam_xpt_sim.h> 55#include <cam/cam_xpt_periph.h> 56#include <cam/cam_debug.h> 57 58/* local prototypes */ 59static int ahci_setup_interrupt(device_t dev); 60static void ahci_intr(void *data); 61static void ahci_intr_one(void *data); 62static int ahci_suspend(device_t dev); 63static int ahci_resume(device_t dev); 64static int ahci_ch_suspend(device_t dev); 65static int ahci_ch_resume(device_t dev); 66static void ahci_ch_pm(void *arg); 67static void ahci_ch_intr_locked(void *data); 68static void ahci_ch_intr(void *data); 69static int ahci_ctlr_reset(device_t dev); 70static void ahci_begin_transaction(device_t dev, union ccb *ccb); 71static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 72static void ahci_execute_transaction(struct ahci_slot *slot); 73static void ahci_timeout(struct ahci_slot *slot); 74static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 75static int ahci_setup_fis(struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 76static void ahci_dmainit(device_t dev); 77static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 78static void ahci_dmafini(device_t dev); 79static void ahci_slotsalloc(device_t dev); 80static void ahci_slotsfree(device_t dev); 81static void ahci_reset(device_t dev); 82static void ahci_start(device_t dev); 83static void ahci_stop(device_t dev); 84static void ahci_clo(device_t dev); 85static void ahci_start_fr(device_t dev); 86static void ahci_stop_fr(device_t dev); 87 88static int ahci_sata_connect(struct ahci_channel *ch); 89static int ahci_sata_phy_reset(device_t dev, int quick); 90 91static void ahci_issue_read_log(device_t dev); 92static void ahci_process_read_log(device_t dev, union ccb *ccb); 93 94static void ahciaction(struct cam_sim *sim, union ccb *ccb); 95static void ahcipoll(struct cam_sim *sim); 96 97MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 98 99static struct { 100 uint32_t id; 101 const char *name; 102 int flags; 103} ahci_ids[] = { 104 {0x43801002, "ATI IXP600", 0}, 105 {0x43901002, "ATI IXP700", 0}, 106 {0x43911002, "ATI IXP700", 0}, 107 {0x43921002, "ATI IXP700", 0}, 108 {0x43931002, "ATI IXP700", 0}, 109 {0x43941002, "ATI IXP800", 0}, 110 {0x43951002, "ATI IXP800", 0}, 111 {0x26528086, "Intel ICH6", 0}, 112 {0x26538086, "Intel ICH6M", 0}, 113 {0x26818086, "Intel ESB2", 0}, 114 {0x26828086, "Intel ESB2", 0}, 115 {0x26838086, "Intel ESB2", 0}, 116 {0x27c18086, "Intel ICH7", 0}, 117 {0x27c38086, "Intel ICH7", 0}, 118 {0x27c58086, "Intel ICH7M", 0}, 119 {0x27c68086, "Intel ICH7M", 0}, 120 {0x28218086, "Intel ICH8", 0}, 121 {0x28228086, "Intel ICH8", 0}, 122 {0x28248086, "Intel ICH8", 0}, 123 {0x28298086, "Intel ICH8M", 0}, 124 {0x282a8086, "Intel ICH8M", 0}, 125 {0x29228086, "Intel ICH9", 0}, 126 {0x29238086, "Intel ICH9", 0}, 127 {0x29248086, "Intel ICH9", 0}, 128 {0x29258086, "Intel ICH9", 0}, 129 {0x29278086, "Intel ICH9", 0}, 130 {0x29298086, "Intel ICH9M", 0}, 131 {0x292a8086, "Intel ICH9M", 0}, 132 {0x292b8086, "Intel ICH9M", 0}, 133 {0x292c8086, "Intel ICH9M", 0}, 134 {0x292f8086, "Intel ICH9M", 0}, 135 {0x294d8086, "Intel ICH9", 0}, 136 {0x294e8086, "Intel ICH9M", 0}, 137 {0x3a058086, "Intel ICH10", 0}, 138 {0x3a228086, "Intel ICH10", 0}, 139 {0x3a258086, "Intel ICH10", 0}, 140 {0x3b228086, "Intel PCH", 0}, 141 {0x3b238086, "Intel PCH", 0}, 142 {0x3b248086, "Intel PCH", 0}, 143 {0x3b258086, "Intel PCH", 0}, 144 {0x3b298086, "Intel PCH", 0}, 145 {0x3b2b8086, "Intel PCH", 0}, 146 {0x3b2c8086, "Intel PCH", 0}, 147 {0x3b2f8086, "Intel PCH", 0}, 148 {0x044c10de, "NVIDIA MCP65", 0}, 149 {0x044d10de, "NVIDIA MCP65", 0}, 150 {0x044e10de, "NVIDIA MCP65", 0}, 151 {0x044f10de, "NVIDIA MCP65", 0}, 152 {0x045c10de, "NVIDIA MCP65", 0}, 153 {0x045d10de, "NVIDIA MCP65", 0}, 154 {0x045e10de, "NVIDIA MCP65", 0}, 155 {0x045f10de, "NVIDIA MCP65", 0}, 156 {0x055010de, "NVIDIA MCP67", 0}, 157 {0x055110de, "NVIDIA MCP67", 0}, 158 {0x055210de, "NVIDIA MCP67", 0}, 159 {0x055310de, "NVIDIA MCP67", 0}, 160 {0x055410de, "NVIDIA MCP67", 0}, 161 {0x055510de, "NVIDIA MCP67", 0}, 162 {0x055610de, "NVIDIA MCP67", 0}, 163 {0x055710de, "NVIDIA MCP67", 0}, 164 {0x055810de, "NVIDIA MCP67", 0}, 165 {0x055910de, "NVIDIA MCP67", 0}, 166 {0x055A10de, "NVIDIA MCP67", 0}, 167 {0x055B10de, "NVIDIA MCP67", 0}, 168 {0x058410de, "NVIDIA MCP67", 0}, 169 {0x07f010de, "NVIDIA MCP73", 0}, 170 {0x07f110de, "NVIDIA MCP73", 0}, 171 {0x07f210de, "NVIDIA MCP73", 0}, 172 {0x07f310de, "NVIDIA MCP73", 0}, 173 {0x07f410de, "NVIDIA MCP73", 0}, 174 {0x07f510de, "NVIDIA MCP73", 0}, 175 {0x07f610de, "NVIDIA MCP73", 0}, 176 {0x07f710de, "NVIDIA MCP73", 0}, 177 {0x07f810de, "NVIDIA MCP73", 0}, 178 {0x07f910de, "NVIDIA MCP73", 0}, 179 {0x07fa10de, "NVIDIA MCP73", 0}, 180 {0x07fb10de, "NVIDIA MCP73", 0}, 181 {0x0ad010de, "NVIDIA MCP77", 0}, 182 {0x0ad110de, "NVIDIA MCP77", 0}, 183 {0x0ad210de, "NVIDIA MCP77", 0}, 184 {0x0ad310de, "NVIDIA MCP77", 0}, 185 {0x0ad410de, "NVIDIA MCP77", 0}, 186 {0x0ad510de, "NVIDIA MCP77", 0}, 187 {0x0ad610de, "NVIDIA MCP77", 0}, 188 {0x0ad710de, "NVIDIA MCP77", 0}, 189 {0x0ad810de, "NVIDIA MCP77", 0}, 190 {0x0ad910de, "NVIDIA MCP77", 0}, 191 {0x0ada10de, "NVIDIA MCP77", 0}, 192 {0x0adb10de, "NVIDIA MCP77", 0}, 193 {0x0ab410de, "NVIDIA MCP79", 0}, 194 {0x0ab510de, "NVIDIA MCP79", 0}, 195 {0x0ab610de, "NVIDIA MCP79", 0}, 196 {0x0ab710de, "NVIDIA MCP79", 0}, 197 {0x0ab810de, "NVIDIA MCP79", 0}, 198 {0x0ab910de, "NVIDIA MCP79", 0}, 199 {0x0aba10de, "NVIDIA MCP79", 0}, 200 {0x0abb10de, "NVIDIA MCP79", 0}, 201 {0x0abc10de, "NVIDIA MCP79", 0}, 202 {0x0abd10de, "NVIDIA MCP79", 0}, 203 {0x0abe10de, "NVIDIA MCP79", 0}, 204 {0x0abf10de, "NVIDIA MCP79", 0}, 205 {0x0d8410de, "NVIDIA MCP89", 0}, 206 {0x0d8510de, "NVIDIA MCP89", 0}, 207 {0x0d8610de, "NVIDIA MCP89", 0}, 208 {0x0d8710de, "NVIDIA MCP89", 0}, 209 {0x0d8810de, "NVIDIA MCP89", 0}, 210 {0x0d8910de, "NVIDIA MCP89", 0}, 211 {0x0d8a10de, "NVIDIA MCP89", 0}, 212 {0x0d8b10de, "NVIDIA MCP89", 0}, 213 {0x0d8c10de, "NVIDIA MCP89", 0}, 214 {0x0d8d10de, "NVIDIA MCP89", 0}, 215 {0x0d8e10de, "NVIDIA MCP89", 0}, 216 {0x0d8f10de, "NVIDIA MCP89", 0}, 217 {0x33491106, "VIA VT8251", 0}, 218 {0x62871106, "VIA VT8251", 0}, 219 {0x11841039, "SiS 966", 0}, 220 {0x11851039, "SiS 968", 0}, 221 {0x01861039, "SiS 968", 0}, 222 {0, NULL, 0} 223}; 224 225static int 226ahci_probe(device_t dev) 227{ 228 char buf[64]; 229 int i; 230 uint32_t devid = pci_get_devid(dev); 231 232 /* Is this a known AHCI chip? */ 233 for (i = 0; ahci_ids[i].id != 0; i++) { 234 if (ahci_ids[i].id == devid) { 235 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 236 ahci_ids[i].name); 237 device_set_desc_copy(dev, buf); 238 return (BUS_PROBE_VENDOR); 239 } 240 } 241 /* Is this a possible AHCI candidate? */ 242 if (pci_get_class(dev) != PCIC_STORAGE || 243 pci_get_subclass(dev) != PCIS_STORAGE_SATA || 244 pci_get_progif(dev) != PCIP_STORAGE_SATA_AHCI_1_0) 245 return (ENXIO); 246 device_set_desc_copy(dev, "AHCI SATA controller"); 247 return (BUS_PROBE_VENDOR); 248} 249 250static int 251ahci_attach(device_t dev) 252{ 253 struct ahci_controller *ctlr = device_get_softc(dev); 254 device_t child; 255 int error, unit, speed; 256 u_int32_t version; 257 258 ctlr->dev = dev; 259 resource_int_value(device_get_name(dev), 260 device_get_unit(dev), "ccc", &ctlr->ccc); 261 /* if we have a memory BAR(5) we are likely on an AHCI part */ 262 ctlr->r_rid = PCIR_BAR(5); 263 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 264 &ctlr->r_rid, RF_ACTIVE))) 265 return ENXIO; 266 /* Setup our own memory management for channels. */ 267 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 268 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 269 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 270 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 271 return (error); 272 } 273 if ((error = rman_manage_region(&ctlr->sc_iomem, 274 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 275 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 276 rman_fini(&ctlr->sc_iomem); 277 return (error); 278 } 279 /* Reset controller */ 280 if ((error = ahci_ctlr_reset(dev)) != 0) { 281 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 282 rman_fini(&ctlr->sc_iomem); 283 return (error); 284 }; 285 /* Get the number of HW channels */ 286 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 287 ctlr->channels = MAX(flsl(ctlr->ichannels), 288 (ATA_INL(ctlr->r_mem, AHCI_CAP) & AHCI_CAP_NPMASK) + 1); 289 /* Setup interrupts. */ 290 if (ahci_setup_interrupt(dev)) { 291 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 292 rman_fini(&ctlr->sc_iomem); 293 return ENXIO; 294 } 295 /* Announce HW capabilities. */ 296 version = ATA_INL(ctlr->r_mem, AHCI_VS); 297 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 298 if (version >= 0x00010020) 299 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 300 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 301 device_printf(dev, 302 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s\n", 303 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 304 ((version >> 4) & 0xf0) + (version & 0x0f), 305 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 306 ((speed == 1) ? "1.5":((speed == 2) ? "3": 307 ((speed == 3) ? "6":"?"))), 308 (ctlr->caps & AHCI_CAP_SPM) ? 309 "supported" : "not supported"); 310 if (bootverbose) { 311 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 312 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 313 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 314 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 315 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 316 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 317 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 318 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 319 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 320 ((speed == 1) ? "1.5":((speed == 2) ? "3": 321 ((speed == 3) ? "6":"?")))); 322 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 323 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 324 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 325 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 326 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 327 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 328 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 329 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 330 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 331 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 332 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 333 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 334 } 335 if (bootverbose && version >= 0x00010020) { 336 device_printf(dev, "Caps2:%s%s%s\n", 337 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 338 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 339 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 340 } 341 /* Attach all channels on this controller */ 342 for (unit = 0; unit < ctlr->channels; unit++) { 343 if ((ctlr->ichannels & (1 << unit)) == 0) 344 continue; 345 child = device_add_child(dev, "ahcich", -1); 346 if (child == NULL) 347 device_printf(dev, "failed to add channel device\n"); 348 else 349 device_set_ivars(child, (void *)(intptr_t)unit); 350 } 351 bus_generic_attach(dev); 352 return 0; 353} 354 355static int 356ahci_detach(device_t dev) 357{ 358 struct ahci_controller *ctlr = device_get_softc(dev); 359 device_t *children; 360 int nchildren, i; 361 362 /* Detach & delete all children */ 363 if (!device_get_children(dev, &children, &nchildren)) { 364 for (i = 0; i < nchildren; i++) 365 device_delete_child(dev, children[i]); 366 free(children, M_TEMP); 367 } 368 /* Free interrupts. */ 369 for (i = 0; i < ctlr->numirqs; i++) { 370 if (ctlr->irqs[i].r_irq) { 371 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 372 ctlr->irqs[i].handle); 373 bus_release_resource(dev, SYS_RES_IRQ, 374 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 375 } 376 } 377 pci_release_msi(dev); 378 /* Free memory. */ 379 rman_fini(&ctlr->sc_iomem); 380 if (ctlr->r_mem) 381 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 382 return (0); 383} 384 385static int 386ahci_ctlr_reset(device_t dev) 387{ 388 struct ahci_controller *ctlr = device_get_softc(dev); 389 int timeout; 390 391 if (pci_read_config(dev, 0x00, 4) == 0x28298086 && 392 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 393 pci_write_config(dev, 0x92, 0x01, 1); 394 /* Enable AHCI mode */ 395 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 396 /* Reset AHCI controller */ 397 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 398 for (timeout = 1000; timeout > 0; timeout--) { 399 DELAY(1000); 400 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 401 break; 402 } 403 if (timeout == 0) { 404 device_printf(dev, "AHCI controller reset failure\n"); 405 return ENXIO; 406 } 407 /* Reenable AHCI mode */ 408 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 409 /* Clear interrupts */ 410 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 411 /* Configure CCC */ 412 if (ctlr->ccc) { 413 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 414 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 415 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 416 (4 << AHCI_CCCC_CC_SHIFT) | 417 AHCI_CCCC_EN); 418 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 419 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 420 if (bootverbose) { 421 device_printf(dev, 422 "CCC with %dms/4cmd enabled on vector %d\n", 423 ctlr->ccc, ctlr->cccv); 424 } 425 } 426 /* Enable AHCI interrupts */ 427 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 428 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 429 return (0); 430} 431 432static int 433ahci_suspend(device_t dev) 434{ 435 struct ahci_controller *ctlr = device_get_softc(dev); 436 437 bus_generic_suspend(dev); 438 /* Disable interupts, so the state change(s) doesn't trigger */ 439 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 440 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 441 return 0; 442} 443 444static int 445ahci_resume(device_t dev) 446{ 447 int res; 448 449 if ((res = ahci_ctlr_reset(dev)) != 0) 450 return (res); 451 return (bus_generic_resume(dev)); 452} 453 454static int 455ahci_setup_interrupt(device_t dev) 456{ 457 struct ahci_controller *ctlr = device_get_softc(dev); 458 int i, msi = 1; 459 460 /* Process hints. */ 461 resource_int_value(device_get_name(dev), 462 device_get_unit(dev), "msi", &msi); 463 if (msi < 0) 464 msi = 0; 465 else if (msi == 1) 466 msi = min(1, pci_msi_count(dev)); 467 else if (msi > 1) 468 msi = pci_msi_count(dev); 469 /* Allocate MSI if needed/present. */ 470 if (msi && pci_alloc_msi(dev, &msi) == 0) { 471 ctlr->numirqs = msi; 472 } else { 473 msi = 0; 474 ctlr->numirqs = 1; 475 } 476 /* Check for single MSI vector fallback. */ 477 if (ctlr->numirqs > 1 && 478 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 479 device_printf(dev, "Falling back to one MSI\n"); 480 ctlr->numirqs = 1; 481 } 482 /* Allocate all IRQs. */ 483 for (i = 0; i < ctlr->numirqs; i++) { 484 ctlr->irqs[i].ctlr = ctlr; 485 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0); 486 if (ctlr->numirqs == 1 || i >= ctlr->channels || 487 (ctlr->ccc && i == ctlr->cccv)) 488 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 489 else if (i == ctlr->numirqs - 1) 490 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 491 else 492 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 493 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 494 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 495 device_printf(dev, "unable to map interrupt\n"); 496 return ENXIO; 497 } 498 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 499 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr, 500 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 501 /* SOS XXX release r_irq */ 502 device_printf(dev, "unable to setup interrupt\n"); 503 return ENXIO; 504 } 505 } 506 return (0); 507} 508 509/* 510 * Common case interrupt handler. 511 */ 512static void 513ahci_intr(void *data) 514{ 515 struct ahci_controller_irq *irq = data; 516 struct ahci_controller *ctlr = irq->ctlr; 517 u_int32_t is; 518 void *arg; 519 int unit; 520 521 if (irq->mode == AHCI_IRQ_MODE_ALL) { 522 unit = 0; 523 if (ctlr->ccc) 524 is = ctlr->ichannels; 525 else 526 is = ATA_INL(ctlr->r_mem, AHCI_IS); 527 } else { /* AHCI_IRQ_MODE_AFTER */ 528 unit = irq->r_irq_rid - 1; 529 is = ATA_INL(ctlr->r_mem, AHCI_IS); 530 } 531 for (; unit < ctlr->channels; unit++) { 532 if ((is & (1 << unit)) != 0 && 533 (arg = ctlr->interrupt[unit].argument)) { 534 ctlr->interrupt[unit].function(arg); 535 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 536 } 537 } 538} 539 540/* 541 * Simplified interrupt handler for multivector MSI mode. 542 */ 543static void 544ahci_intr_one(void *data) 545{ 546 struct ahci_controller_irq *irq = data; 547 struct ahci_controller *ctlr = irq->ctlr; 548 void *arg; 549 int unit; 550 551 unit = irq->r_irq_rid - 1; 552 if ((arg = ctlr->interrupt[unit].argument)) 553 ctlr->interrupt[unit].function(arg); 554} 555 556static struct resource * 557ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 558 u_long start, u_long end, u_long count, u_int flags) 559{ 560 struct ahci_controller *ctlr = device_get_softc(dev); 561 int unit = ((struct ahci_channel *)device_get_softc(child))->unit; 562 struct resource *res = NULL; 563 int offset = AHCI_OFFSET + (unit << 7); 564 long st; 565 566 switch (type) { 567 case SYS_RES_MEMORY: 568 st = rman_get_start(ctlr->r_mem); 569 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 570 st + offset + 127, 128, RF_ACTIVE, child); 571 if (res) { 572 bus_space_handle_t bsh; 573 bus_space_tag_t bst; 574 bsh = rman_get_bushandle(ctlr->r_mem); 575 bst = rman_get_bustag(ctlr->r_mem); 576 bus_space_subregion(bst, bsh, offset, 128, &bsh); 577 rman_set_bushandle(res, bsh); 578 rman_set_bustag(res, bst); 579 } 580 break; 581 case SYS_RES_IRQ: 582 if (*rid == ATA_IRQ_RID) 583 res = ctlr->irqs[0].r_irq; 584 break; 585 } 586 return (res); 587} 588 589static int 590ahci_release_resource(device_t dev, device_t child, int type, int rid, 591 struct resource *r) 592{ 593 594 switch (type) { 595 case SYS_RES_MEMORY: 596 rman_release_resource(r); 597 return (0); 598 case SYS_RES_IRQ: 599 if (rid != ATA_IRQ_RID) 600 return ENOENT; 601 return (0); 602 } 603 return (EINVAL); 604} 605 606static int 607ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 608 int flags, driver_filter_t *filter, driver_intr_t *function, 609 void *argument, void **cookiep) 610{ 611 struct ahci_controller *ctlr = device_get_softc(dev); 612 int unit = (intptr_t)device_get_ivars(child); 613 614 if (filter != NULL) { 615 printf("ahci.c: we cannot use a filter here\n"); 616 return (EINVAL); 617 } 618 ctlr->interrupt[unit].function = function; 619 ctlr->interrupt[unit].argument = argument; 620 return (0); 621} 622 623static int 624ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 625 void *cookie) 626{ 627 struct ahci_controller *ctlr = device_get_softc(dev); 628 int unit = (intptr_t)device_get_ivars(child); 629 630 ctlr->interrupt[unit].function = NULL; 631 ctlr->interrupt[unit].argument = NULL; 632 return (0); 633} 634 635static int 636ahci_print_child(device_t dev, device_t child) 637{ 638 int retval; 639 640 retval = bus_print_child_header(dev, child); 641 retval += printf(" at channel %d", 642 (int)(intptr_t)device_get_ivars(child)); 643 retval += bus_print_child_footer(dev, child); 644 645 return (retval); 646} 647 648devclass_t ahci_devclass; 649static device_method_t ahci_methods[] = { 650 DEVMETHOD(device_probe, ahci_probe), 651 DEVMETHOD(device_attach, ahci_attach), 652 DEVMETHOD(device_detach, ahci_detach), 653 DEVMETHOD(device_suspend, ahci_suspend), 654 DEVMETHOD(device_resume, ahci_resume), 655 DEVMETHOD(bus_print_child, ahci_print_child), 656 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 657 DEVMETHOD(bus_release_resource, ahci_release_resource), 658 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 659 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 660 { 0, 0 } 661}; 662static driver_t ahci_driver = { 663 "ahci", 664 ahci_methods, 665 sizeof(struct ahci_controller) 666}; 667DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 668MODULE_VERSION(ahci, 1); 669MODULE_DEPEND(ahci, cam, 1, 1, 1); 670 671static int 672ahci_ch_probe(device_t dev) 673{ 674 675 device_set_desc_copy(dev, "AHCI channel"); 676 return (0); 677} 678 679static int 680ahci_ch_attach(device_t dev) 681{ 682 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 683 struct ahci_channel *ch = device_get_softc(dev); 684 struct cam_devq *devq; 685 int rid, error; 686 687 ch->dev = dev; 688 ch->unit = (intptr_t)device_get_ivars(dev); 689 ch->caps = ctlr->caps; 690 ch->caps2 = ctlr->caps2; 691 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 692 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 693 resource_int_value(device_get_name(dev), 694 device_get_unit(dev), "pm_level", &ch->pm_level); 695 if (ch->pm_level > 3) 696 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 697 /* Limit speed for my onboard JMicron external port. 698 * It is not eSATA really. */ 699 if (pci_get_devid(ctlr->dev) == 0x2363197b && 700 pci_get_subvendor(ctlr->dev) == 0x1043 && 701 pci_get_subdevice(ctlr->dev) == 0x81e4 && 702 ch->unit == 0) 703 ch->sata_rev = 1; 704 resource_int_value(device_get_name(dev), 705 device_get_unit(dev), "sata_rev", &ch->sata_rev); 706 rid = ch->unit; 707 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 708 &rid, RF_ACTIVE))) 709 return (ENXIO); 710 ahci_dmainit(dev); 711 ahci_slotsalloc(dev); 712 ahci_ch_resume(dev); 713 mtx_lock(&ch->mtx); 714 rid = ATA_IRQ_RID; 715 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 716 &rid, RF_SHAREABLE | RF_ACTIVE))) { 717 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 718 device_printf(dev, "Unable to map interrupt\n"); 719 return (ENXIO); 720 } 721 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 722 ahci_ch_intr_locked, dev, &ch->ih))) { 723 device_printf(dev, "Unable to setup interrupt\n"); 724 error = ENXIO; 725 goto err1; 726 } 727 /* Create the device queue for our SIM. */ 728 devq = cam_simq_alloc(ch->numslots); 729 if (devq == NULL) { 730 device_printf(dev, "Unable to allocate simq\n"); 731 error = ENOMEM; 732 goto err1; 733 } 734 /* Construct SIM entry */ 735 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 736 device_get_unit(dev), &ch->mtx, 737 min(2, ch->numslots), 738 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 739 devq); 740 if (ch->sim == NULL) { 741 device_printf(dev, "unable to allocate sim\n"); 742 error = ENOMEM; 743 goto err2; 744 } 745 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 746 device_printf(dev, "unable to register xpt bus\n"); 747 error = ENXIO; 748 goto err2; 749 } 750 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 751 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 752 device_printf(dev, "unable to create path\n"); 753 error = ENXIO; 754 goto err3; 755 } 756 if (ch->pm_level > 3) { 757 callout_reset(&ch->pm_timer, 758 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 759 ahci_ch_pm, dev); 760 } 761 mtx_unlock(&ch->mtx); 762 return (0); 763 764err3: 765 xpt_bus_deregister(cam_sim_path(ch->sim)); 766err2: 767 cam_sim_free(ch->sim, /*free_devq*/TRUE); 768err1: 769 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 770 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 771 mtx_unlock(&ch->mtx); 772 return (error); 773} 774 775static int 776ahci_ch_detach(device_t dev) 777{ 778 struct ahci_channel *ch = device_get_softc(dev); 779 780 mtx_lock(&ch->mtx); 781 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 782 xpt_free_path(ch->path); 783 xpt_bus_deregister(cam_sim_path(ch->sim)); 784 cam_sim_free(ch->sim, /*free_devq*/TRUE); 785 mtx_unlock(&ch->mtx); 786 787 if (ch->pm_level > 3) 788 callout_drain(&ch->pm_timer); 789 bus_teardown_intr(dev, ch->r_irq, ch->ih); 790 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 791 792 ahci_ch_suspend(dev); 793 ahci_slotsfree(dev); 794 ahci_dmafini(dev); 795 796 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 797 mtx_destroy(&ch->mtx); 798 return (0); 799} 800 801static int 802ahci_ch_suspend(device_t dev) 803{ 804 struct ahci_channel *ch = device_get_softc(dev); 805 806 /* Disable port interrupts. */ 807 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 808 /* Reset command register. */ 809 ahci_stop(dev); 810 ahci_stop_fr(dev); 811 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 812 /* Allow everything, including partial and slumber modes. */ 813 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 814 /* Request slumber mode transition and give some time to get there. */ 815 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 816 DELAY(100); 817 /* Disable PHY. */ 818 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 819 return (0); 820} 821 822static int 823ahci_ch_resume(device_t dev) 824{ 825 struct ahci_channel *ch = device_get_softc(dev); 826 uint64_t work; 827 828 /* Disable port interrupts */ 829 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 830 /* Setup work areas */ 831 work = ch->dma.work_bus + AHCI_CL_OFFSET; 832 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 833 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 834 work = ch->dma.rfis_bus; 835 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 836 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 837 /* Activate the channel and power/spin up device */ 838 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 839 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 840 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 841 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 842 ahci_start_fr(dev); 843 ahci_start(dev); 844 return (0); 845} 846 847devclass_t ahcich_devclass; 848static device_method_t ahcich_methods[] = { 849 DEVMETHOD(device_probe, ahci_ch_probe), 850 DEVMETHOD(device_attach, ahci_ch_attach), 851 DEVMETHOD(device_detach, ahci_ch_detach), 852 DEVMETHOD(device_suspend, ahci_ch_suspend), 853 DEVMETHOD(device_resume, ahci_ch_resume), 854 { 0, 0 } 855}; 856static driver_t ahcich_driver = { 857 "ahcich", 858 ahcich_methods, 859 sizeof(struct ahci_channel) 860}; 861DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahci_devclass, 0, 0); 862 863struct ahci_dc_cb_args { 864 bus_addr_t maddr; 865 int error; 866}; 867 868static void 869ahci_dmainit(device_t dev) 870{ 871 struct ahci_channel *ch = device_get_softc(dev); 872 struct ahci_dc_cb_args dcba; 873 874 if (ch->caps & AHCI_CAP_64BIT) 875 ch->dma.max_address = BUS_SPACE_MAXADDR; 876 else 877 ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT; 878 /* Command area. */ 879 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 880 ch->dma.max_address, BUS_SPACE_MAXADDR, 881 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 882 0, NULL, NULL, &ch->dma.work_tag)) 883 goto error; 884 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0, 885 &ch->dma.work_map)) 886 goto error; 887 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 888 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 889 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 890 goto error; 891 } 892 ch->dma.work_bus = dcba.maddr; 893 /* FIS receive area. */ 894 if (bus_dma_tag_create(bus_get_dma_tag(dev), 4096, 0, 895 ch->dma.max_address, BUS_SPACE_MAXADDR, 896 NULL, NULL, 4096, 1, 4096, 897 0, NULL, NULL, &ch->dma.rfis_tag)) 898 goto error; 899 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 900 &ch->dma.rfis_map)) 901 goto error; 902 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 903 4096, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 904 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 905 goto error; 906 } 907 ch->dma.rfis_bus = dcba.maddr; 908 /* Data area. */ 909 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 910 ch->dma.max_address, BUS_SPACE_MAXADDR, 911 NULL, NULL, 912 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 913 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 914 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 915 goto error; 916 } 917 return; 918 919error: 920 device_printf(dev, "WARNING - DMA initialization failed\n"); 921 ahci_dmafini(dev); 922} 923 924static void 925ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 926{ 927 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 928 929 if (!(dcba->error = error)) 930 dcba->maddr = segs[0].ds_addr; 931} 932 933static void 934ahci_dmafini(device_t dev) 935{ 936 struct ahci_channel *ch = device_get_softc(dev); 937 938 if (ch->dma.data_tag) { 939 bus_dma_tag_destroy(ch->dma.data_tag); 940 ch->dma.data_tag = NULL; 941 } 942 if (ch->dma.rfis_bus) { 943 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 944 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 945 ch->dma.rfis_bus = 0; 946 ch->dma.rfis_map = NULL; 947 ch->dma.rfis = NULL; 948 } 949 if (ch->dma.work_bus) { 950 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 951 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 952 ch->dma.work_bus = 0; 953 ch->dma.work_map = NULL; 954 ch->dma.work = NULL; 955 } 956 if (ch->dma.work_tag) { 957 bus_dma_tag_destroy(ch->dma.work_tag); 958 ch->dma.work_tag = NULL; 959 } 960} 961 962static void 963ahci_slotsalloc(device_t dev) 964{ 965 struct ahci_channel *ch = device_get_softc(dev); 966 int i; 967 968 /* Alloc and setup command/dma slots */ 969 bzero(ch->slot, sizeof(ch->slot)); 970 for (i = 0; i < ch->numslots; i++) { 971 struct ahci_slot *slot = &ch->slot[i]; 972 973 slot->dev = dev; 974 slot->slot = i; 975 slot->state = AHCI_SLOT_EMPTY; 976 slot->ccb = NULL; 977 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 978 979 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 980 device_printf(ch->dev, "FAILURE - create data_map\n"); 981 } 982} 983 984static void 985ahci_slotsfree(device_t dev) 986{ 987 struct ahci_channel *ch = device_get_softc(dev); 988 int i; 989 990 /* Free all dma slots */ 991 for (i = 0; i < ch->numslots; i++) { 992 struct ahci_slot *slot = &ch->slot[i]; 993 994 callout_drain(&slot->timeout); 995 if (slot->dma.data_map) { 996 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 997 slot->dma.data_map = NULL; 998 } 999 } 1000} 1001 1002static void 1003ahci_phy_check_events(device_t dev, u_int32_t serr) 1004{ 1005 struct ahci_channel *ch = device_get_softc(dev); 1006 1007 if ((serr & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) { 1008 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1009 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 1010 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 1011 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) { 1012 if (bootverbose) 1013 device_printf(dev, "CONNECT requested\n"); 1014 ahci_reset(dev); 1015 } else { 1016 if (bootverbose) 1017 device_printf(dev, "DISCONNECT requested\n"); 1018 ch->devices = 0; 1019 } 1020 } 1021} 1022 1023static void 1024ahci_notify_events(device_t dev, u_int32_t status) 1025{ 1026 struct ahci_channel *ch = device_get_softc(dev); 1027 struct cam_path *dpath; 1028 int i; 1029 1030 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1031 if (bootverbose) 1032 device_printf(dev, "SNTF 0x%04x\n", status); 1033 for (i = 0; i < 16; i++) { 1034 if ((status & (1 << i)) == 0) 1035 continue; 1036 if (xpt_create_path(&dpath, NULL, 1037 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1038 xpt_async(AC_SCSI_AEN, dpath, NULL); 1039 xpt_free_path(dpath); 1040 } 1041 } 1042} 1043 1044static void 1045ahci_ch_intr_locked(void *data) 1046{ 1047 device_t dev = (device_t)data; 1048 struct ahci_channel *ch = device_get_softc(dev); 1049 1050 mtx_lock(&ch->mtx); 1051 ahci_ch_intr(data); 1052 mtx_unlock(&ch->mtx); 1053} 1054 1055static void 1056ahci_ch_pm(void *arg) 1057{ 1058 device_t dev = (device_t)arg; 1059 struct ahci_channel *ch = device_get_softc(dev); 1060 uint32_t work; 1061 1062 if (ch->numrslots != 0) 1063 return; 1064 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1065 if (ch->pm_level == 4) 1066 work |= AHCI_P_CMD_PARTIAL; 1067 else 1068 work |= AHCI_P_CMD_SLUMBER; 1069 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1070} 1071 1072static void 1073ahci_ch_intr(void *data) 1074{ 1075 device_t dev = (device_t)data; 1076 struct ahci_channel *ch = device_get_softc(dev); 1077 uint32_t istatus, sstatus, cstatus, serr = 0, sntf = 0, ok, err; 1078 enum ahci_err_type et; 1079 int i, ccs, ncq_err = 0; 1080 1081 /* Read and clear interrupt statuses. */ 1082 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1083 if (istatus == 0) 1084 return; 1085 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1086 /* Read command statuses. */ 1087 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1088 cstatus = ATA_INL(ch->r_mem, AHCI_P_CI); 1089 if ((istatus & AHCI_P_IX_SDB) && (ch->caps & AHCI_CAP_SSNTF)) 1090 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1091 /* Process PHY events */ 1092 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1093 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1094 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1095 if (serr) { 1096 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1097 ahci_phy_check_events(dev, serr); 1098 } 1099 } 1100 /* Process command errors */ 1101 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1102 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1103//device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x\n", 1104// __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1105// serr); 1106 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1107 >> AHCI_P_CMD_CCS_SHIFT; 1108 err = ch->rslots & (cstatus | sstatus); 1109 /* Kick controller into sane state */ 1110 ahci_stop(dev); 1111 ahci_start(dev); 1112 } else { 1113 ccs = 0; 1114 err = 0; 1115 } 1116 /* Complete all successfull commands. */ 1117 ok = ch->rslots & ~(cstatus | sstatus); 1118 for (i = 0; i < ch->numslots; i++) { 1119 if ((ok >> i) & 1) 1120 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1121 } 1122 /* On error, complete the rest of commands with error statuses. */ 1123 if (err) { 1124 if (ch->frozen) { 1125 union ccb *fccb = ch->frozen; 1126 ch->frozen = NULL; 1127 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1128 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1129 xpt_freeze_devq(fccb->ccb_h.path, 1); 1130 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1131 } 1132 xpt_done(fccb); 1133 } 1134 for (i = 0; i < ch->numslots; i++) { 1135 /* XXX: reqests in loading state. */ 1136 if (((err >> i) & 1) == 0) 1137 continue; 1138 if (istatus & AHCI_P_IX_TFE) { 1139 /* Task File Error */ 1140 if (ch->numtslots == 0) { 1141 /* Untagged operation. */ 1142 if (i == ccs) 1143 et = AHCI_ERR_TFE; 1144 else 1145 et = AHCI_ERR_INNOCENT; 1146 } else { 1147 /* Tagged operation. */ 1148 et = AHCI_ERR_NCQ; 1149 ncq_err = 1; 1150 } 1151 } else if (istatus & AHCI_P_IX_IF) { 1152 if (ch->numtslots == 0 && i != ccs) 1153 et = AHCI_ERR_INNOCENT; 1154 else 1155 et = AHCI_ERR_SATA; 1156 } else 1157 et = AHCI_ERR_INVALID; 1158 ahci_end_transaction(&ch->slot[i], et); 1159 } 1160 if (ncq_err) 1161 ahci_issue_read_log(dev); 1162 } 1163 /* Process NOTIFY events */ 1164 if (sntf) 1165 ahci_notify_events(dev, sntf); 1166} 1167 1168/* Must be called with channel locked. */ 1169static int 1170ahci_check_collision(device_t dev, union ccb *ccb) 1171{ 1172 struct ahci_channel *ch = device_get_softc(dev); 1173 1174 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1175 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1176 /* Tagged command while untagged are active. */ 1177 if (ch->numrslots != 0 && ch->numtslots == 0) 1178 return (1); 1179 /* Tagged command while tagged to other target is active. */ 1180 if (ch->numtslots != 0 && 1181 ch->taggedtarget != ccb->ccb_h.target_id) 1182 return (1); 1183 } else { 1184 /* Untagged command while tagged are active. */ 1185 if (ch->numrslots != 0 && ch->numtslots != 0) 1186 return (1); 1187 } 1188 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1189 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1190 /* Atomic command while anything active. */ 1191 if (ch->numrslots != 0) 1192 return (1); 1193 } 1194 /* We have some atomic command running. */ 1195 if (ch->aslots != 0) 1196 return (1); 1197 return (0); 1198} 1199 1200/* Must be called with channel locked. */ 1201static void 1202ahci_begin_transaction(device_t dev, union ccb *ccb) 1203{ 1204 struct ahci_channel *ch = device_get_softc(dev); 1205 struct ahci_slot *slot; 1206 int tag; 1207 1208 /* Choose empty slot. */ 1209 tag = ch->lastslot; 1210 while (ch->slot[tag].state != AHCI_SLOT_EMPTY) { 1211 if (++tag >= ch->numslots) 1212 tag = 0; 1213 KASSERT(tag != ch->lastslot, ("ahci: ALL SLOTS BUSY!")); 1214 } 1215 ch->lastslot = tag; 1216 /* Occupy chosen slot. */ 1217 slot = &ch->slot[tag]; 1218 slot->ccb = ccb; 1219 /* Stop PM timer. */ 1220 if (ch->numrslots == 0 && ch->pm_level > 3) 1221 callout_stop(&ch->pm_timer); 1222 /* Update channel stats. */ 1223 ch->numrslots++; 1224 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1225 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1226 ch->numtslots++; 1227 ch->taggedtarget = ccb->ccb_h.target_id; 1228 } 1229 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1230 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1231 ch->aslots |= (1 << slot->slot); 1232 slot->dma.nsegs = 0; 1233 /* If request moves data, setup and load SG list */ 1234 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1235 void *buf; 1236 bus_size_t size; 1237 1238 slot->state = AHCI_SLOT_LOADING; 1239 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1240 buf = ccb->ataio.data_ptr; 1241 size = ccb->ataio.dxfer_len; 1242 } else { 1243 buf = ccb->csio.data_ptr; 1244 size = ccb->csio.dxfer_len; 1245 } 1246 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1247 buf, size, ahci_dmasetprd, slot, 0); 1248 } else 1249 ahci_execute_transaction(slot); 1250} 1251 1252/* Locked by busdma engine. */ 1253static void 1254ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1255{ 1256 struct ahci_slot *slot = arg; 1257 struct ahci_channel *ch = device_get_softc(slot->dev); 1258 struct ahci_cmd_tab *ctp; 1259 struct ahci_dma_prd *prd; 1260 int i; 1261 1262 if (error) { 1263 device_printf(slot->dev, "DMA load error\n"); 1264 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1265 return; 1266 } 1267 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1268 /* Get a piece of the workspace for this request */ 1269 ctp = (struct ahci_cmd_tab *) 1270 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1271 /* Fill S/G table */ 1272 prd = &ctp->prd_tab[0]; 1273 for (i = 0; i < nsegs; i++) { 1274 prd[i].dba = htole64(segs[i].ds_addr); 1275 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1276 } 1277 slot->dma.nsegs = nsegs; 1278 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1279 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1280 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1281 ahci_execute_transaction(slot); 1282} 1283 1284/* Must be called with channel locked. */ 1285static void 1286ahci_execute_transaction(struct ahci_slot *slot) 1287{ 1288 device_t dev = slot->dev; 1289 struct ahci_channel *ch = device_get_softc(dev); 1290 struct ahci_cmd_tab *ctp; 1291 struct ahci_cmd_list *clp; 1292 union ccb *ccb = slot->ccb; 1293 int port = ccb->ccb_h.target_id & 0x0f; 1294 int fis_size; 1295 1296 /* Get a piece of the workspace for this request */ 1297 ctp = (struct ahci_cmd_tab *) 1298 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1299 /* Setup the FIS for this request */ 1300 if (!(fis_size = ahci_setup_fis(ctp, ccb, slot->slot))) { 1301 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1302 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1303 return; 1304 } 1305 /* Setup the command list entry */ 1306 clp = (struct ahci_cmd_list *) 1307 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1308 clp->prd_length = slot->dma.nsegs; 1309 clp->cmd_flags = (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1310 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1311 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1312 (fis_size / sizeof(u_int32_t)) | 1313 (port << 12); 1314 /* Special handling for Soft Reset command. */ 1315 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1316 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1317 (ccb->ataio.cmd.control & ATA_A_RESET)) { 1318 /* Kick controller into sane state */ 1319 ahci_stop(dev); 1320 ahci_clo(dev); 1321 ahci_start(dev); 1322 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1323 } 1324 clp->bytecount = 0; 1325 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1326 (AHCI_CT_SIZE * slot->slot)); 1327 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1328 BUS_DMASYNC_PREWRITE); 1329 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1330 BUS_DMASYNC_PREREAD); 1331 /* Set ACTIVE bit for NCQ commands. */ 1332 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1333 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1334 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1335 } 1336 /* Issue command to the controller. */ 1337 slot->state = AHCI_SLOT_RUNNING; 1338 ch->rslots |= (1 << slot->slot); 1339 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1340 /* Device reset commands doesn't interrupt. Poll them. */ 1341 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1342 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || 1343 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL))) { 1344 int count, timeout = ccb->ccb_h.timeout; 1345 enum ahci_err_type et = AHCI_ERR_NONE; 1346 1347 for (count = 0; count < timeout; count++) { 1348 DELAY(1000); 1349 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1350 break; 1351 if (ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) { 1352 device_printf(ch->dev, 1353 "Poll error on slot %d, TFD: %04x\n", 1354 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1355 et = AHCI_ERR_TFE; 1356 break; 1357 } 1358 /* Workaround for ATI SB600/SB700 chipsets. */ 1359 if (ccb->ccb_h.target_id == 15 && 1360 pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1361 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1362 et = AHCI_ERR_TIMEOUT; 1363 break; 1364 } 1365 } 1366 if (timeout && (count >= timeout)) { 1367 device_printf(ch->dev, 1368 "Poll timeout on slot %d\n", slot->slot); 1369 et = AHCI_ERR_TIMEOUT; 1370 } 1371 if (et != AHCI_ERR_NONE) { 1372 /* Kick controller into sane state */ 1373 ahci_stop(ch->dev); 1374 ahci_start(ch->dev); 1375 } 1376 ahci_end_transaction(slot, et); 1377 return; 1378 } 1379 /* Start command execution timeout */ 1380 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 1381 (timeout_t*)ahci_timeout, slot); 1382 return; 1383} 1384 1385/* Locked by callout mechanism. */ 1386static void 1387ahci_timeout(struct ahci_slot *slot) 1388{ 1389 device_t dev = slot->dev; 1390 struct ahci_channel *ch = device_get_softc(dev); 1391 uint32_t sstatus; 1392 int ccs; 1393 int i; 1394 1395 /* Check for stale timeout. */ 1396 if (slot->state < AHCI_SLOT_RUNNING) 1397 return; 1398 1399 /* Check if slot was not being executed last time we checked. */ 1400 if (slot->state < AHCI_SLOT_EXECUTING) { 1401 /* Check if slot started executing. */ 1402 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1403 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1404 >> AHCI_P_CMD_CCS_SHIFT; 1405 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot) 1406 slot->state = AHCI_SLOT_EXECUTING; 1407 1408 callout_reset(&slot->timeout, 1409 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1410 (timeout_t*)ahci_timeout, slot); 1411 return; 1412 } 1413 1414 device_printf(dev, "Timeout on slot %d\n", slot->slot); 1415 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x\n", 1416 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1417 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1418 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR)); 1419 1420 ch->fatalerr = 1; 1421 /* Handle frozen command. */ 1422 if (ch->frozen) { 1423 union ccb *fccb = ch->frozen; 1424 ch->frozen = NULL; 1425 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1426 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1427 xpt_freeze_devq(fccb->ccb_h.path, 1); 1428 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1429 } 1430 xpt_done(fccb); 1431 } 1432 /* Handle command with timeout. */ 1433 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 1434 /* Handle the rest of commands. */ 1435 for (i = 0; i < ch->numslots; i++) { 1436 /* Do we have a running request on slot? */ 1437 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1438 continue; 1439 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1440 } 1441} 1442 1443/* Must be called with channel locked. */ 1444static void 1445ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 1446{ 1447 device_t dev = slot->dev; 1448 struct ahci_channel *ch = device_get_softc(dev); 1449 union ccb *ccb = slot->ccb; 1450 1451 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1452 BUS_DMASYNC_POSTWRITE); 1453 /* Read result registers to the result struct 1454 * May be incorrect if several commands finished same time, 1455 * so read only when sure or have to. 1456 */ 1457 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1458 struct ata_res *res = &ccb->ataio.res; 1459 1460 if ((et == AHCI_ERR_TFE) || 1461 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1462 u_int8_t *fis = ch->dma.rfis + 0x40; 1463 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 1464 1465 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1466 BUS_DMASYNC_POSTREAD); 1467 res->status = tfd; 1468 res->error = tfd >> 8; 1469 res->lba_low = fis[4]; 1470 res->lba_mid = fis[5]; 1471 res->lba_high = fis[6]; 1472 res->device = fis[7]; 1473 res->lba_low_exp = fis[8]; 1474 res->lba_mid_exp = fis[9]; 1475 res->lba_high_exp = fis[10]; 1476 res->sector_count = fis[12]; 1477 res->sector_count_exp = fis[13]; 1478 } else 1479 bzero(res, sizeof(*res)); 1480 } 1481 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1482 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1483 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1484 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1485 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1486 } 1487 /* In case of error, freeze device for proper recovery. */ 1488 if ((et != AHCI_ERR_NONE) && (!ch->readlog) && 1489 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 1490 xpt_freeze_devq(ccb->ccb_h.path, 1); 1491 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1492 } 1493 /* Set proper result status. */ 1494 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1495 switch (et) { 1496 case AHCI_ERR_NONE: 1497 ccb->ccb_h.status |= CAM_REQ_CMP; 1498 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1499 ccb->csio.scsi_status = SCSI_STATUS_OK; 1500 break; 1501 case AHCI_ERR_INVALID: 1502 ch->fatalerr = 1; 1503 ccb->ccb_h.status |= CAM_REQ_INVALID; 1504 break; 1505 case AHCI_ERR_INNOCENT: 1506 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1507 break; 1508 case AHCI_ERR_TFE: 1509 case AHCI_ERR_NCQ: 1510 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1511 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1512 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1513 } else { 1514 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1515 } 1516 break; 1517 case AHCI_ERR_SATA: 1518 ch->fatalerr = 1; 1519 if (!ch->readlog) { 1520 xpt_freeze_simq(ch->sim, 1); 1521 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1522 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1523 } 1524 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1525 break; 1526 case AHCI_ERR_TIMEOUT: 1527 /* Do no treat soft-reset timeout as fatal here. */ 1528 if (ccb->ccb_h.func_code != XPT_ATA_IO || 1529 !(ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) 1530 ch->fatalerr = 1; 1531 if (!ch->readlog) { 1532 xpt_freeze_simq(ch->sim, 1); 1533 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1534 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1535 } 1536 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1537 break; 1538 default: 1539 ch->fatalerr = 1; 1540 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1541 } 1542 /* Free slot. */ 1543 ch->rslots &= ~(1 << slot->slot); 1544 ch->aslots &= ~(1 << slot->slot); 1545 slot->state = AHCI_SLOT_EMPTY; 1546 slot->ccb = NULL; 1547 /* Update channel stats. */ 1548 ch->numrslots--; 1549 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1550 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1551 ch->numtslots--; 1552 } 1553 /* If it was first request of reset sequence and there is no error, 1554 * proceed to second request. */ 1555 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1556 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1557 (ccb->ataio.cmd.control & ATA_A_RESET) && 1558 et == AHCI_ERR_NONE) { 1559 ccb->ataio.cmd.control &= ~ATA_A_RESET; 1560 ahci_begin_transaction(dev, ccb); 1561 return; 1562 } 1563 /* If it was our READ LOG command - process it. */ 1564 if (ch->readlog) { 1565 ahci_process_read_log(dev, ccb); 1566 /* If it was NCQ command error, put result on hold. */ 1567 } else if (et == AHCI_ERR_NCQ) { 1568 ch->hold[slot->slot] = ccb; 1569 } else 1570 xpt_done(ccb); 1571 /* Unfreeze frozen command. */ 1572 if (ch->frozen && ch->numrslots == 0) { 1573 union ccb *fccb = ch->frozen; 1574 ch->frozen = NULL; 1575 ahci_begin_transaction(dev, fccb); 1576 xpt_release_simq(ch->sim, TRUE); 1577 } 1578 /* If we have no other active commands, ... */ 1579 if (ch->rslots == 0) { 1580 /* if there was fatal error - reset port. */ 1581 if (ch->fatalerr) { 1582 ahci_reset(dev); 1583 } 1584 } 1585 /* Start PM timer. */ 1586 if (ch->numrslots == 0 && ch->pm_level > 3) { 1587 callout_schedule(&ch->pm_timer, 1588 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 1589 } 1590} 1591 1592static void 1593ahci_issue_read_log(device_t dev) 1594{ 1595 struct ahci_channel *ch = device_get_softc(dev); 1596 union ccb *ccb; 1597 struct ccb_ataio *ataio; 1598 int i; 1599 1600 ch->readlog = 1; 1601 /* Find some holden command. */ 1602 for (i = 0; i < ch->numslots; i++) { 1603 if (ch->hold[i]) 1604 break; 1605 } 1606 ccb = xpt_alloc_ccb_nowait(); 1607 if (ccb == NULL) { 1608 device_printf(dev, "Unable allocate READ LOG command"); 1609 return; /* XXX */ 1610 } 1611 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 1612 ccb->ccb_h.func_code = XPT_ATA_IO; 1613 ccb->ccb_h.flags = CAM_DIR_IN; 1614 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1615 ataio = &ccb->ataio; 1616 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 1617 if (ataio->data_ptr == NULL) { 1618 device_printf(dev, "Unable allocate memory for READ LOG command"); 1619 return; /* XXX */ 1620 } 1621 ataio->dxfer_len = 512; 1622 bzero(&ataio->cmd, sizeof(ataio->cmd)); 1623 ataio->cmd.flags = CAM_ATAIO_48BIT; 1624 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 1625 ataio->cmd.sector_count = 1; 1626 ataio->cmd.sector_count_exp = 0; 1627 ataio->cmd.lba_low = 0x10; 1628 ataio->cmd.lba_mid = 0; 1629 ataio->cmd.lba_mid_exp = 0; 1630 /* Freeze SIM while doing READ LOG EXT. */ 1631 xpt_freeze_simq(ch->sim, 1); 1632 ahci_begin_transaction(dev, ccb); 1633} 1634 1635static void 1636ahci_process_read_log(device_t dev, union ccb *ccb) 1637{ 1638 struct ahci_channel *ch = device_get_softc(dev); 1639 uint8_t *data; 1640 struct ata_res *res; 1641 int i; 1642 1643 ch->readlog = 0; 1644 1645 data = ccb->ataio.data_ptr; 1646 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 1647 (data[0] & 0x80) == 0) { 1648 for (i = 0; i < ch->numslots; i++) { 1649 if (!ch->hold[i]) 1650 continue; 1651 if ((data[0] & 0x1F) == i) { 1652 res = &ch->hold[i]->ataio.res; 1653 res->status = data[2]; 1654 res->error = data[3]; 1655 res->lba_low = data[4]; 1656 res->lba_mid = data[5]; 1657 res->lba_high = data[6]; 1658 res->device = data[7]; 1659 res->lba_low_exp = data[8]; 1660 res->lba_mid_exp = data[9]; 1661 res->lba_high_exp = data[10]; 1662 res->sector_count = data[12]; 1663 res->sector_count_exp = data[13]; 1664 } else { 1665 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1666 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 1667 } 1668 xpt_done(ch->hold[i]); 1669 ch->hold[i] = NULL; 1670 } 1671 } else { 1672 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 1673 device_printf(dev, "Error while READ LOG EXT\n"); 1674 else if ((data[0] & 0x80) == 0) { 1675 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 1676 } 1677 for (i = 0; i < ch->numslots; i++) { 1678 if (!ch->hold[i]) 1679 continue; 1680 xpt_done(ch->hold[i]); 1681 ch->hold[i] = NULL; 1682 } 1683 } 1684 free(ccb->ataio.data_ptr, M_AHCI); 1685 xpt_free_ccb(ccb); 1686 xpt_release_simq(ch->sim, TRUE); 1687} 1688 1689static void 1690ahci_start(device_t dev) 1691{ 1692 struct ahci_channel *ch = device_get_softc(dev); 1693 u_int32_t cmd; 1694 1695 /* Clear SATA error register */ 1696 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 1697 /* Clear any interrupts pending on this channel */ 1698 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 1699 /* Start operations on this channel */ 1700 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1701 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 1702 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 1703} 1704 1705static void 1706ahci_stop(device_t dev) 1707{ 1708 struct ahci_channel *ch = device_get_softc(dev); 1709 u_int32_t cmd; 1710 int timeout; 1711 1712 /* Kill all activity on this channel */ 1713 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1714 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 1715 /* Wait for activity stop. */ 1716 timeout = 0; 1717 do { 1718 DELAY(1000); 1719 if (timeout++ > 1000) { 1720 device_printf(dev, "stopping AHCI engine failed\n"); 1721 break; 1722 } 1723 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 1724} 1725 1726static void 1727ahci_clo(device_t dev) 1728{ 1729 struct ahci_channel *ch = device_get_softc(dev); 1730 u_int32_t cmd; 1731 int timeout; 1732 1733 /* Issue Command List Override if supported */ 1734 if (ch->caps & AHCI_CAP_SCLO) { 1735 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1736 cmd |= AHCI_P_CMD_CLO; 1737 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 1738 timeout = 0; 1739 do { 1740 DELAY(1000); 1741 if (timeout++ > 1000) { 1742 device_printf(dev, "executing CLO failed\n"); 1743 break; 1744 } 1745 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 1746 } 1747} 1748 1749static void 1750ahci_stop_fr(device_t dev) 1751{ 1752 struct ahci_channel *ch = device_get_softc(dev); 1753 u_int32_t cmd; 1754 int timeout; 1755 1756 /* Kill all FIS reception on this channel */ 1757 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1758 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 1759 /* Wait for FIS reception stop. */ 1760 timeout = 0; 1761 do { 1762 DELAY(1000); 1763 if (timeout++ > 1000) { 1764 device_printf(dev, "stopping AHCI FR engine failed\n"); 1765 break; 1766 } 1767 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 1768} 1769 1770static void 1771ahci_start_fr(device_t dev) 1772{ 1773 struct ahci_channel *ch = device_get_softc(dev); 1774 u_int32_t cmd; 1775 1776 /* Start FIS reception on this channel */ 1777 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1778 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 1779} 1780 1781static int 1782ahci_wait_ready(device_t dev, int t) 1783{ 1784 struct ahci_channel *ch = device_get_softc(dev); 1785 int timeout = 0; 1786 uint32_t val; 1787 1788 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 1789 (ATA_S_BUSY | ATA_S_DRQ)) { 1790 DELAY(1000); 1791 if (timeout++ > t) { 1792 device_printf(dev, "port is not ready (timeout %dms) " 1793 "tfd = %08x\n", t, val); 1794 return (EBUSY); 1795 } 1796 } 1797 if (bootverbose) 1798 device_printf(dev, "ready wait time=%dms\n", timeout); 1799 return (0); 1800} 1801 1802static void 1803ahci_reset(device_t dev) 1804{ 1805 struct ahci_channel *ch = device_get_softc(dev); 1806 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1807 int i; 1808 1809 if (bootverbose) 1810 device_printf(dev, "AHCI reset...\n"); 1811 /* Requeue freezed command. */ 1812 if (ch->frozen) { 1813 union ccb *fccb = ch->frozen; 1814 ch->frozen = NULL; 1815 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1816 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1817 xpt_freeze_devq(fccb->ccb_h.path, 1); 1818 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1819 } 1820 xpt_done(fccb); 1821 } 1822 /* Kill the engine and requeue all running commands. */ 1823 ahci_stop(dev); 1824 for (i = 0; i < ch->numslots; i++) { 1825 /* Do we have a running request on slot? */ 1826 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1827 continue; 1828 /* XXX; Commands in loading state. */ 1829 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1830 } 1831 for (i = 0; i < ch->numslots; i++) { 1832 if (!ch->hold[i]) 1833 continue; 1834 xpt_done(ch->hold[i]); 1835 ch->hold[i] = NULL; 1836 } 1837 ch->fatalerr = 0; 1838 /* Tell the XPT about the event */ 1839 xpt_async(AC_BUS_RESET, ch->path, NULL); 1840 /* Disable port interrupts */ 1841 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1842 /* Reset and reconnect PHY, */ 1843 if (!ahci_sata_phy_reset(dev, 0)) { 1844 if (bootverbose) 1845 device_printf(dev, 1846 "AHCI reset done: phy reset found no device\n"); 1847 ch->devices = 0; 1848 /* Enable wanted port interrupts */ 1849 ATA_OUTL(ch->r_mem, AHCI_P_IE, 1850 (AHCI_P_IX_CPD | AHCI_P_IX_PRC | AHCI_P_IX_PC)); 1851 return; 1852 } 1853 /* Wait for clearing busy status. */ 1854 if (ahci_wait_ready(dev, 10000)) { 1855 device_printf(dev, "device ready timeout\n"); 1856 ahci_clo(dev); 1857 } 1858 ahci_start(dev); 1859 ch->devices = 1; 1860 /* Enable wanted port interrupts */ 1861 ATA_OUTL(ch->r_mem, AHCI_P_IE, 1862 (AHCI_P_IX_CPD | AHCI_P_IX_TFE | AHCI_P_IX_HBF | 1863 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 1864 ((ch->pm_level == 0) ? AHCI_P_IX_PRC | AHCI_P_IX_PC : 0) | 1865 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 1866 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 1867 if (bootverbose) 1868 device_printf(dev, "AHCI reset done: device found\n"); 1869} 1870 1871static int 1872ahci_setup_fis(struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 1873{ 1874 u_int8_t *fis = &ctp->cfis[0]; 1875 1876 bzero(ctp->cfis, 64); 1877 fis[0] = 0x27; /* host to device */ 1878 fis[1] = (ccb->ccb_h.target_id & 0x0f); 1879 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1880 fis[1] |= 0x80; 1881 fis[2] = ATA_PACKET_CMD; 1882 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) 1883 fis[3] = ATA_F_DMA; 1884 else { 1885 fis[5] = ccb->csio.dxfer_len; 1886 fis[6] = ccb->csio.dxfer_len >> 8; 1887 } 1888 fis[7] = ATA_D_LBA; 1889 fis[15] = ATA_A_4BIT; 1890 bzero(ctp->acmd, 32); 1891 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 1892 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 1893 ctp->acmd, ccb->csio.cdb_len); 1894 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 1895 fis[1] |= 0x80; 1896 fis[2] = ccb->ataio.cmd.command; 1897 fis[3] = ccb->ataio.cmd.features; 1898 fis[4] = ccb->ataio.cmd.lba_low; 1899 fis[5] = ccb->ataio.cmd.lba_mid; 1900 fis[6] = ccb->ataio.cmd.lba_high; 1901 fis[7] = ccb->ataio.cmd.device; 1902 fis[8] = ccb->ataio.cmd.lba_low_exp; 1903 fis[9] = ccb->ataio.cmd.lba_mid_exp; 1904 fis[10] = ccb->ataio.cmd.lba_high_exp; 1905 fis[11] = ccb->ataio.cmd.features_exp; 1906 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1907 fis[12] = tag << 3; 1908 fis[13] = 0; 1909 } else { 1910 fis[12] = ccb->ataio.cmd.sector_count; 1911 fis[13] = ccb->ataio.cmd.sector_count_exp; 1912 } 1913 fis[15] = ATA_A_4BIT; 1914 } else { 1915 fis[15] = ccb->ataio.cmd.control; 1916 } 1917 return (20); 1918} 1919 1920static int 1921ahci_sata_connect(struct ahci_channel *ch) 1922{ 1923 u_int32_t status; 1924 int timeout; 1925 1926 /* Wait up to 100ms for "connect well" */ 1927 for (timeout = 0; timeout < 100 ; timeout++) { 1928 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1929 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 1930 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 1931 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 1932 break; 1933 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 1934 if (bootverbose) { 1935 device_printf(ch->dev, "SATA offline status=%08x\n", 1936 status); 1937 } 1938 return (0); 1939 } 1940 DELAY(1000); 1941 } 1942 if (timeout >= 100) { 1943 if (bootverbose) { 1944 device_printf(ch->dev, "SATA connect timeout status=%08x\n", 1945 status); 1946 } 1947 return (0); 1948 } 1949 if (bootverbose) { 1950 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n", 1951 timeout, status); 1952 } 1953 /* Clear SATA error register */ 1954 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 1955 return (1); 1956} 1957 1958static int 1959ahci_sata_phy_reset(device_t dev, int quick) 1960{ 1961 struct ahci_channel *ch = device_get_softc(dev); 1962 uint32_t val; 1963 1964 if (quick) { 1965 val = ATA_INL(ch->r_mem, AHCI_P_SCTL); 1966 if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) 1967 return (ahci_sata_connect(ch)); 1968 } 1969 1970 if (bootverbose) 1971 device_printf(dev, "hardware reset ...\n"); 1972 if (ch->sata_rev == 1) 1973 val = ATA_SC_SPD_SPEED_GEN1; 1974 else if (ch->sata_rev == 2) 1975 val = ATA_SC_SPD_SPEED_GEN2; 1976 else if (ch->sata_rev == 3) 1977 val = ATA_SC_SPD_SPEED_GEN3; 1978 else 1979 val = 0; 1980 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 1981 ATA_SC_DET_RESET | val | 1982 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 1983 DELAY(5000); 1984 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 1985 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 1986 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 1987 DELAY(5000); 1988 return (ahci_sata_connect(ch)); 1989} 1990 1991static void 1992ahciaction(struct cam_sim *sim, union ccb *ccb) 1993{ 1994 device_t dev; 1995 struct ahci_channel *ch; 1996 1997 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 1998 ccb->ccb_h.func_code)); 1999 2000 ch = (struct ahci_channel *)cam_sim_softc(sim); 2001 dev = ch->dev; 2002 switch (ccb->ccb_h.func_code) { 2003 /* Common cases first */ 2004 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2005 case XPT_SCSI_IO: 2006 if (ch->devices == 0) { 2007 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2008 xpt_done(ccb); 2009 break; 2010 } 2011 /* Check for command collision. */ 2012 if (ahci_check_collision(dev, ccb)) { 2013 /* Freeze command. */ 2014 ch->frozen = ccb; 2015 /* We have only one frozen slot, so freeze simq also. */ 2016 xpt_freeze_simq(ch->sim, 1); 2017 return; 2018 } 2019 ahci_begin_transaction(dev, ccb); 2020 break; 2021 case XPT_EN_LUN: /* Enable LUN as a target */ 2022 case XPT_TARGET_IO: /* Execute target I/O request */ 2023 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2024 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2025 case XPT_ABORT: /* Abort the specified CCB */ 2026 /* XXX Implement */ 2027 ccb->ccb_h.status = CAM_REQ_INVALID; 2028 xpt_done(ccb); 2029 break; 2030 case XPT_SET_TRAN_SETTINGS: 2031 { 2032 struct ccb_trans_settings *cts = &ccb->cts; 2033 2034 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) { 2035 ch->pm_present = cts->xport_specific.sata.pm_present; 2036 } 2037 ccb->ccb_h.status = CAM_REQ_CMP; 2038 xpt_done(ccb); 2039 break; 2040 } 2041 case XPT_GET_TRAN_SETTINGS: 2042 /* Get default/user set transfer settings for the target */ 2043 { 2044 struct ccb_trans_settings *cts = &ccb->cts; 2045 uint32_t status; 2046 2047 cts->protocol = PROTO_ATA; 2048 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2049 cts->transport = XPORT_SATA; 2050 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2051 cts->proto_specific.valid = 0; 2052 cts->xport_specific.sata.valid = 0; 2053 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2054 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2055 else 2056 status = ATA_INL(ch->r_mem, AHCI_P_SCTL) & ATA_SC_SPD_MASK; 2057 if (status & ATA_SS_SPD_GEN3) { 2058 cts->xport_specific.sata.bitrate = 600000; 2059 cts->xport_specific.sata.valid |= CTS_SATA_VALID_SPEED; 2060 } else if (status & ATA_SS_SPD_GEN2) { 2061 cts->xport_specific.sata.bitrate = 300000; 2062 cts->xport_specific.sata.valid |= CTS_SATA_VALID_SPEED; 2063 } else if (status & ATA_SS_SPD_GEN1) { 2064 cts->xport_specific.sata.bitrate = 150000; 2065 cts->xport_specific.sata.valid |= CTS_SATA_VALID_SPEED; 2066 } 2067 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 2068 cts->xport_specific.sata.pm_present = 2069 (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_PMA) ? 2070 1 : 0; 2071 } else { 2072 cts->xport_specific.sata.pm_present = ch->pm_present; 2073 } 2074 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2075 ccb->ccb_h.status = CAM_REQ_CMP; 2076 xpt_done(ccb); 2077 break; 2078 } 2079#if 0 2080 case XPT_CALC_GEOMETRY: 2081 { 2082 struct ccb_calc_geometry *ccg; 2083 uint32_t size_mb; 2084 uint32_t secs_per_cylinder; 2085 2086 ccg = &ccb->ccg; 2087 size_mb = ccg->volume_size 2088 / ((1024L * 1024L) / ccg->block_size); 2089 if (size_mb >= 1024 && (aha->extended_trans != 0)) { 2090 if (size_mb >= 2048) { 2091 ccg->heads = 255; 2092 ccg->secs_per_track = 63; 2093 } else { 2094 ccg->heads = 128; 2095 ccg->secs_per_track = 32; 2096 } 2097 } else { 2098 ccg->heads = 64; 2099 ccg->secs_per_track = 32; 2100 } 2101 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 2102 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 2103 ccb->ccb_h.status = CAM_REQ_CMP; 2104 xpt_done(ccb); 2105 break; 2106 } 2107#endif 2108 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2109 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2110 ahci_reset(dev); 2111 ccb->ccb_h.status = CAM_REQ_CMP; 2112 xpt_done(ccb); 2113 break; 2114 case XPT_TERM_IO: /* Terminate the I/O process */ 2115 /* XXX Implement */ 2116 ccb->ccb_h.status = CAM_REQ_INVALID; 2117 xpt_done(ccb); 2118 break; 2119 case XPT_PATH_INQ: /* Path routing inquiry */ 2120 { 2121 struct ccb_pathinq *cpi = &ccb->cpi; 2122 2123 cpi->version_num = 1; /* XXX??? */ 2124 cpi->hba_inquiry = PI_SDTR_ABLE; 2125 if (ch->caps & AHCI_CAP_SNCQ) 2126 cpi->hba_inquiry |= PI_TAG_ABLE; 2127 if (ch->caps & AHCI_CAP_SPM) 2128 cpi->hba_inquiry |= PI_SATAPM; 2129 cpi->target_sprt = 0; 2130 cpi->hba_misc = PIM_SEQSCAN; 2131 cpi->hba_eng_cnt = 0; 2132 if (ch->caps & AHCI_CAP_SPM) 2133 cpi->max_target = 15; 2134 else 2135 cpi->max_target = 0; 2136 cpi->max_lun = 0; 2137 cpi->initiator_id = 0; 2138 cpi->bus_id = cam_sim_bus(sim); 2139 cpi->base_transfer_speed = 150000; 2140 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2141 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2142 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2143 cpi->unit_number = cam_sim_unit(sim); 2144 cpi->transport = XPORT_SATA; 2145 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2146 cpi->protocol = PROTO_ATA; 2147 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2148 cpi->maxio = MAXPHYS; 2149 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2150 if (pci_get_devid(device_get_parent(dev)) == 0x43801002) 2151 cpi->maxio = min(cpi->maxio, 128 * 512); 2152 cpi->ccb_h.status = CAM_REQ_CMP; 2153 xpt_done(ccb); 2154 break; 2155 } 2156 default: 2157 ccb->ccb_h.status = CAM_REQ_INVALID; 2158 xpt_done(ccb); 2159 break; 2160 } 2161} 2162 2163static void 2164ahcipoll(struct cam_sim *sim) 2165{ 2166 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2167 2168 ahci_ch_intr(ch->dev); 2169} 2170