ahci_generic.c revision 221504
1/*- 2 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ahci/ahci.c 221504 2011-05-05 17:11:26Z mav $"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/ata.h> 35#include <sys/bus.h> 36#include <sys/conf.h> 37#include <sys/endian.h> 38#include <sys/malloc.h> 39#include <sys/lock.h> 40#include <sys/mutex.h> 41#include <sys/sema.h> 42#include <sys/taskqueue.h> 43#include <vm/uma.h> 44#include <machine/stdarg.h> 45#include <machine/resource.h> 46#include <machine/bus.h> 47#include <sys/rman.h> 48#include <dev/pci/pcivar.h> 49#include <dev/pci/pcireg.h> 50#include "ahci.h" 51 52#include <cam/cam.h> 53#include <cam/cam_ccb.h> 54#include <cam/cam_sim.h> 55#include <cam/cam_xpt_sim.h> 56#include <cam/cam_debug.h> 57 58/* local prototypes */ 59static int ahci_setup_interrupt(device_t dev); 60static void ahci_intr(void *data); 61static void ahci_intr_one(void *data); 62static int ahci_suspend(device_t dev); 63static int ahci_resume(device_t dev); 64static int ahci_ch_init(device_t dev); 65static int ahci_ch_deinit(device_t dev); 66static int ahci_ch_suspend(device_t dev); 67static int ahci_ch_resume(device_t dev); 68static void ahci_ch_pm(void *arg); 69static void ahci_ch_intr_locked(void *data); 70static void ahci_ch_intr(void *data); 71static int ahci_ctlr_reset(device_t dev); 72static int ahci_ctlr_setup(device_t dev); 73static void ahci_begin_transaction(device_t dev, union ccb *ccb); 74static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 75static void ahci_execute_transaction(struct ahci_slot *slot); 76static void ahci_timeout(struct ahci_slot *slot); 77static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 78static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 79static void ahci_dmainit(device_t dev); 80static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 81static void ahci_dmafini(device_t dev); 82static void ahci_slotsalloc(device_t dev); 83static void ahci_slotsfree(device_t dev); 84static void ahci_reset(device_t dev); 85static void ahci_start(device_t dev, int fbs); 86static void ahci_stop(device_t dev); 87static void ahci_clo(device_t dev); 88static void ahci_start_fr(device_t dev); 89static void ahci_stop_fr(device_t dev); 90 91static int ahci_sata_connect(struct ahci_channel *ch); 92static int ahci_sata_phy_reset(device_t dev); 93static int ahci_wait_ready(device_t dev, int t, int t0); 94 95static void ahci_issue_recovery(device_t dev); 96static void ahci_process_read_log(device_t dev, union ccb *ccb); 97static void ahci_process_request_sense(device_t dev, union ccb *ccb); 98 99static void ahciaction(struct cam_sim *sim, union ccb *ccb); 100static void ahcipoll(struct cam_sim *sim); 101 102MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 103 104static struct { 105 uint32_t id; 106 uint8_t rev; 107 const char *name; 108 int quirks; 109#define AHCI_Q_NOFORCE 1 110#define AHCI_Q_NOPMP 2 111#define AHCI_Q_NONCQ 4 112#define AHCI_Q_1CH 8 113#define AHCI_Q_2CH 16 114#define AHCI_Q_4CH 32 115#define AHCI_Q_EDGEIS 64 116#define AHCI_Q_SATA2 128 117#define AHCI_Q_NOBSYRES 256 118#define AHCI_Q_NOAA 512 119#define AHCI_Q_NOCOUNT 1024 120} ahci_ids[] = { 121 {0x43801002, 0x00, "ATI IXP600", 0}, 122 {0x43901002, 0x00, "ATI IXP700", 0}, 123 {0x43911002, 0x00, "ATI IXP700", 0}, 124 {0x43921002, 0x00, "ATI IXP700", 0}, 125 {0x43931002, 0x00, "ATI IXP700", 0}, 126 {0x43941002, 0x00, "ATI IXP800", 0}, 127 {0x43951002, 0x00, "ATI IXP800", 0}, 128 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE}, 129 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE}, 130 {0x26818086, 0x00, "Intel ESB2", 0}, 131 {0x26828086, 0x00, "Intel ESB2", 0}, 132 {0x26838086, 0x00, "Intel ESB2", 0}, 133 {0x27c18086, 0x00, "Intel ICH7", 0}, 134 {0x27c38086, 0x00, "Intel ICH7", 0}, 135 {0x27c58086, 0x00, "Intel ICH7M", 0}, 136 {0x27c68086, 0x00, "Intel ICH7M", 0}, 137 {0x28218086, 0x00, "Intel ICH8", 0}, 138 {0x28228086, 0x00, "Intel ICH8", 0}, 139 {0x28248086, 0x00, "Intel ICH8", 0}, 140 {0x28298086, 0x00, "Intel ICH8M", 0}, 141 {0x282a8086, 0x00, "Intel ICH8M", 0}, 142 {0x29228086, 0x00, "Intel ICH9", 0}, 143 {0x29238086, 0x00, "Intel ICH9", 0}, 144 {0x29248086, 0x00, "Intel ICH9", 0}, 145 {0x29258086, 0x00, "Intel ICH9", 0}, 146 {0x29278086, 0x00, "Intel ICH9", 0}, 147 {0x29298086, 0x00, "Intel ICH9M", 0}, 148 {0x292a8086, 0x00, "Intel ICH9M", 0}, 149 {0x292b8086, 0x00, "Intel ICH9M", 0}, 150 {0x292c8086, 0x00, "Intel ICH9M", 0}, 151 {0x292f8086, 0x00, "Intel ICH9M", 0}, 152 {0x294d8086, 0x00, "Intel ICH9", 0}, 153 {0x294e8086, 0x00, "Intel ICH9M", 0}, 154 {0x3a058086, 0x00, "Intel ICH10", 0}, 155 {0x3a228086, 0x00, "Intel ICH10", 0}, 156 {0x3a258086, 0x00, "Intel ICH10", 0}, 157 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0}, 158 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0}, 159 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0}, 160 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0}, 161 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0}, 162 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0}, 163 {0x1c028086, 0x00, "Intel Cougar Point", 0}, 164 {0x1c038086, 0x00, "Intel Cougar Point", 0}, 165 {0x1c048086, 0x00, "Intel Cougar Point", 0}, 166 {0x1c058086, 0x00, "Intel Cougar Point", 0}, 167 {0x23238086, 0x00, "Intel DH89xxCC", 0}, 168 {0x1d028086, 0x00, "Intel Patsburg", 0}, 169 {0x1d048086, 0x00, "Intel Patsburg", 0}, 170 {0x1d068086, 0x00, "Intel Patsburg", 0}, 171 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE}, 172 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE}, 173 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE}, 174 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE}, 175 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE}, 176 {0x611111ab, 0x00, "Marvell 88SX6111", AHCI_Q_NOFORCE | AHCI_Q_1CH | 177 AHCI_Q_EDGEIS}, 178 {0x612111ab, 0x00, "Marvell 88SX6121", AHCI_Q_NOFORCE | AHCI_Q_2CH | 179 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 180 {0x614111ab, 0x00, "Marvell 88SX6141", AHCI_Q_NOFORCE | AHCI_Q_4CH | 181 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 182 {0x614511ab, 0x00, "Marvell 88SX6145", AHCI_Q_NOFORCE | AHCI_Q_4CH | 183 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 184 {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_NOBSYRES}, 185 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES}, 186 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES}, 187 {0x91821b4b, 0x00, "Marvell 88SE9182", AHCI_Q_NOBSYRES}, 188 {0x06201103, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 189 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 190 {0x06221103, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 191 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 192 {0x06401103, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 193 {0x06401b4b, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 194 {0x06441103, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 195 {0x06441b4b, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 196 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 197 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 198 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 199 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 200 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 201 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 202 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 203 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 204 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 205 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 206 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 207 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 208 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 209 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 210 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 211 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 212 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 213 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 214 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 215 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 216 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 217 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 218 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 219 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 220 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 221 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 222 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 223 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 224 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 225 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 226 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 227 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 228 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 229 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 230 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 231 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 232 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 233 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 234 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 235 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 236 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 237 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 238 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 239 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 240 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 241 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 242 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 243 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 244 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 245 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 246 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 247 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 248 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 249 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 250 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 251 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 252 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 253 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 254 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 255 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 256 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 257 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 258 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 259 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 260 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 261 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 262 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 263 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 264 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 265 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 266 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 267 {0x11841039, 0x00, "SiS 966", 0}, 268 {0x11851039, 0x00, "SiS 968", 0}, 269 {0x01861039, 0x00, "SiS 968", 0}, 270 {0x00000000, 0x00, NULL, 0} 271}; 272 273#define recovery_type spriv_field0 274#define RECOVERY_NONE 0 275#define RECOVERY_READ_LOG 1 276#define RECOVERY_REQUEST_SENSE 2 277#define recovery_slot spriv_field1 278 279static int 280ahci_probe(device_t dev) 281{ 282 char buf[64]; 283 int i, valid = 0; 284 uint32_t devid = pci_get_devid(dev); 285 uint8_t revid = pci_get_revid(dev); 286 287 /* Is this a possible AHCI candidate? */ 288 if (pci_get_class(dev) == PCIC_STORAGE && 289 pci_get_subclass(dev) == PCIS_STORAGE_SATA && 290 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0) 291 valid = 1; 292 /* Is this a known AHCI chip? */ 293 for (i = 0; ahci_ids[i].id != 0; i++) { 294 if (ahci_ids[i].id == devid && 295 ahci_ids[i].rev <= revid && 296 (valid || !(ahci_ids[i].quirks & AHCI_Q_NOFORCE))) { 297 /* Do not attach JMicrons with single PCI function. */ 298 if (pci_get_vendor(dev) == 0x197b && 299 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0) 300 return (ENXIO); 301 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 302 ahci_ids[i].name); 303 device_set_desc_copy(dev, buf); 304 return (BUS_PROBE_VENDOR); 305 } 306 } 307 if (!valid) 308 return (ENXIO); 309 device_set_desc_copy(dev, "AHCI SATA controller"); 310 return (BUS_PROBE_VENDOR); 311} 312 313static int 314ahci_ata_probe(device_t dev) 315{ 316 char buf[64]; 317 int i; 318 uint32_t devid = pci_get_devid(dev); 319 uint8_t revid = pci_get_revid(dev); 320 321 if ((intptr_t)device_get_ivars(dev) >= 0) 322 return (ENXIO); 323 /* Is this a known AHCI chip? */ 324 for (i = 0; ahci_ids[i].id != 0; i++) { 325 if (ahci_ids[i].id == devid && 326 ahci_ids[i].rev <= revid) { 327 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 328 ahci_ids[i].name); 329 device_set_desc_copy(dev, buf); 330 return (BUS_PROBE_VENDOR); 331 } 332 } 333 device_set_desc_copy(dev, "AHCI SATA controller"); 334 return (BUS_PROBE_VENDOR); 335} 336 337static int 338ahci_attach(device_t dev) 339{ 340 struct ahci_controller *ctlr = device_get_softc(dev); 341 device_t child; 342 int error, unit, speed, i; 343 uint32_t devid = pci_get_devid(dev); 344 uint8_t revid = pci_get_revid(dev); 345 u_int32_t version; 346 347 ctlr->dev = dev; 348 i = 0; 349 while (ahci_ids[i].id != 0 && 350 (ahci_ids[i].id != devid || 351 ahci_ids[i].rev > revid)) 352 i++; 353 ctlr->quirks = ahci_ids[i].quirks; 354 resource_int_value(device_get_name(dev), 355 device_get_unit(dev), "ccc", &ctlr->ccc); 356 /* if we have a memory BAR(5) we are likely on an AHCI part */ 357 ctlr->r_rid = PCIR_BAR(5); 358 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 359 &ctlr->r_rid, RF_ACTIVE))) 360 return ENXIO; 361 /* Setup our own memory management for channels. */ 362 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 363 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 364 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 365 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 366 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 367 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 368 return (error); 369 } 370 if ((error = rman_manage_region(&ctlr->sc_iomem, 371 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 372 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 373 rman_fini(&ctlr->sc_iomem); 374 return (error); 375 } 376 pci_enable_busmaster(dev); 377 /* Reset controller */ 378 if ((error = ahci_ctlr_reset(dev)) != 0) { 379 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 380 rman_fini(&ctlr->sc_iomem); 381 return (error); 382 }; 383 /* Get the HW capabilities */ 384 version = ATA_INL(ctlr->r_mem, AHCI_VS); 385 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 386 if (version >= 0x00010020) 387 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 388 if (ctlr->caps & AHCI_CAP_EMS) 389 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 390 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 391 if (ctlr->quirks & AHCI_Q_1CH) { 392 ctlr->caps &= ~AHCI_CAP_NPMASK; 393 ctlr->ichannels &= 0x01; 394 } 395 if (ctlr->quirks & AHCI_Q_2CH) { 396 ctlr->caps &= ~AHCI_CAP_NPMASK; 397 ctlr->caps |= 1; 398 ctlr->ichannels &= 0x03; 399 } 400 if (ctlr->quirks & AHCI_Q_4CH) { 401 ctlr->caps &= ~AHCI_CAP_NPMASK; 402 ctlr->caps |= 3; 403 ctlr->ichannels &= 0x0f; 404 } 405 ctlr->channels = MAX(flsl(ctlr->ichannels), 406 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 407 if (ctlr->quirks & AHCI_Q_NOPMP) 408 ctlr->caps &= ~AHCI_CAP_SPM; 409 if (ctlr->quirks & AHCI_Q_NONCQ) 410 ctlr->caps &= ~AHCI_CAP_SNCQ; 411 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 412 ctlr->ccc = 0; 413 ahci_ctlr_setup(dev); 414 /* Setup interrupts. */ 415 if (ahci_setup_interrupt(dev)) { 416 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 417 rman_fini(&ctlr->sc_iomem); 418 return ENXIO; 419 } 420 /* Announce HW capabilities. */ 421 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 422 device_printf(dev, 423 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 424 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 425 ((version >> 4) & 0xf0) + (version & 0x0f), 426 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 427 ((speed == 1) ? "1.5":((speed == 2) ? "3": 428 ((speed == 3) ? "6":"?"))), 429 (ctlr->caps & AHCI_CAP_SPM) ? 430 "supported" : "not supported", 431 (ctlr->caps & AHCI_CAP_FBSS) ? 432 " with FBS" : ""); 433 if (bootverbose) { 434 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 435 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 436 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 437 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 438 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 439 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 440 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 441 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 442 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 443 ((speed == 1) ? "1.5":((speed == 2) ? "3": 444 ((speed == 3) ? "6":"?")))); 445 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 446 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 447 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 448 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 449 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 450 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 451 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 452 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 453 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 454 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 455 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 456 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 457 } 458 if (bootverbose && version >= 0x00010020) { 459 device_printf(dev, "Caps2:%s%s%s\n", 460 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 461 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 462 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 463 } 464 if (bootverbose && (ctlr->caps & AHCI_CAP_EMS)) { 465 device_printf(dev, "EM Caps:%s%s%s%s%s%s%s%s\n", 466 (ctlr->capsem & AHCI_EM_PM) ? " PM":"", 467 (ctlr->capsem & AHCI_EM_ALHD) ? " ALHD":"", 468 (ctlr->capsem & AHCI_EM_XMT) ? " XMT":"", 469 (ctlr->capsem & AHCI_EM_SMB) ? " SMB":"", 470 (ctlr->capsem & AHCI_EM_SGPIO) ? " SGPIO":"", 471 (ctlr->capsem & AHCI_EM_SES2) ? " SES-2":"", 472 (ctlr->capsem & AHCI_EM_SAFTE) ? " SAF-TE":"", 473 (ctlr->capsem & AHCI_EM_LED) ? " LED":""); 474 } 475 /* Attach all channels on this controller */ 476 for (unit = 0; unit < ctlr->channels; unit++) { 477 if ((ctlr->ichannels & (1 << unit)) == 0) 478 continue; 479 child = device_add_child(dev, "ahcich", -1); 480 if (child == NULL) 481 device_printf(dev, "failed to add channel device\n"); 482 else 483 device_set_ivars(child, (void *)(intptr_t)unit); 484 } 485 bus_generic_attach(dev); 486 return 0; 487} 488 489static int 490ahci_detach(device_t dev) 491{ 492 struct ahci_controller *ctlr = device_get_softc(dev); 493 device_t *children; 494 int nchildren, i; 495 496 /* Detach & delete all children */ 497 if (!device_get_children(dev, &children, &nchildren)) { 498 for (i = 0; i < nchildren; i++) 499 device_delete_child(dev, children[i]); 500 free(children, M_TEMP); 501 } 502 /* Free interrupts. */ 503 for (i = 0; i < ctlr->numirqs; i++) { 504 if (ctlr->irqs[i].r_irq) { 505 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 506 ctlr->irqs[i].handle); 507 bus_release_resource(dev, SYS_RES_IRQ, 508 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 509 } 510 } 511 pci_release_msi(dev); 512 /* Free memory. */ 513 rman_fini(&ctlr->sc_iomem); 514 if (ctlr->r_mem) 515 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 516 return (0); 517} 518 519static int 520ahci_ctlr_reset(device_t dev) 521{ 522 struct ahci_controller *ctlr = device_get_softc(dev); 523 int timeout; 524 525 if (pci_read_config(dev, 0x00, 4) == 0x28298086 && 526 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 527 pci_write_config(dev, 0x92, 0x01, 1); 528 /* Enable AHCI mode */ 529 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 530 /* Reset AHCI controller */ 531 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 532 for (timeout = 1000; timeout > 0; timeout--) { 533 DELAY(1000); 534 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 535 break; 536 } 537 if (timeout == 0) { 538 device_printf(dev, "AHCI controller reset failure\n"); 539 return ENXIO; 540 } 541 /* Reenable AHCI mode */ 542 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 543 return (0); 544} 545 546static int 547ahci_ctlr_setup(device_t dev) 548{ 549 struct ahci_controller *ctlr = device_get_softc(dev); 550 /* Clear interrupts */ 551 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 552 /* Configure CCC */ 553 if (ctlr->ccc) { 554 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 555 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 556 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 557 (4 << AHCI_CCCC_CC_SHIFT) | 558 AHCI_CCCC_EN); 559 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 560 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 561 if (bootverbose) { 562 device_printf(dev, 563 "CCC with %dms/4cmd enabled on vector %d\n", 564 ctlr->ccc, ctlr->cccv); 565 } 566 } 567 /* Enable AHCI interrupts */ 568 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 569 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 570 return (0); 571} 572 573static int 574ahci_suspend(device_t dev) 575{ 576 struct ahci_controller *ctlr = device_get_softc(dev); 577 578 bus_generic_suspend(dev); 579 /* Disable interupts, so the state change(s) doesn't trigger */ 580 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 581 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 582 return 0; 583} 584 585static int 586ahci_resume(device_t dev) 587{ 588 int res; 589 590 if ((res = ahci_ctlr_reset(dev)) != 0) 591 return (res); 592 ahci_ctlr_setup(dev); 593 return (bus_generic_resume(dev)); 594} 595 596static int 597ahci_setup_interrupt(device_t dev) 598{ 599 struct ahci_controller *ctlr = device_get_softc(dev); 600 int i, msi = 1; 601 602 /* Process hints. */ 603 resource_int_value(device_get_name(dev), 604 device_get_unit(dev), "msi", &msi); 605 if (msi < 0) 606 msi = 0; 607 else if (msi == 1) 608 msi = min(1, pci_msi_count(dev)); 609 else if (msi > 1) 610 msi = pci_msi_count(dev); 611 /* Allocate MSI if needed/present. */ 612 if (msi && pci_alloc_msi(dev, &msi) == 0) { 613 ctlr->numirqs = msi; 614 } else { 615 msi = 0; 616 ctlr->numirqs = 1; 617 } 618 /* Check for single MSI vector fallback. */ 619 if (ctlr->numirqs > 1 && 620 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 621 device_printf(dev, "Falling back to one MSI\n"); 622 ctlr->numirqs = 1; 623 } 624 /* Allocate all IRQs. */ 625 for (i = 0; i < ctlr->numirqs; i++) { 626 ctlr->irqs[i].ctlr = ctlr; 627 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0); 628 if (ctlr->numirqs == 1 || i >= ctlr->channels || 629 (ctlr->ccc && i == ctlr->cccv)) 630 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 631 else if (i == ctlr->numirqs - 1) 632 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 633 else 634 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 635 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 636 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 637 device_printf(dev, "unable to map interrupt\n"); 638 return ENXIO; 639 } 640 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 641 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr, 642 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 643 /* SOS XXX release r_irq */ 644 device_printf(dev, "unable to setup interrupt\n"); 645 return ENXIO; 646 } 647 if (ctlr->numirqs > 1) { 648 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 649 ctlr->irqs[i].handle, 650 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 651 "ch%d" : "%d", i); 652 } 653 } 654 return (0); 655} 656 657/* 658 * Common case interrupt handler. 659 */ 660static void 661ahci_intr(void *data) 662{ 663 struct ahci_controller_irq *irq = data; 664 struct ahci_controller *ctlr = irq->ctlr; 665 u_int32_t is, ise = 0; 666 void *arg; 667 int unit; 668 669 if (irq->mode == AHCI_IRQ_MODE_ALL) { 670 unit = 0; 671 if (ctlr->ccc) 672 is = ctlr->ichannels; 673 else 674 is = ATA_INL(ctlr->r_mem, AHCI_IS); 675 } else { /* AHCI_IRQ_MODE_AFTER */ 676 unit = irq->r_irq_rid - 1; 677 is = ATA_INL(ctlr->r_mem, AHCI_IS); 678 } 679 /* CCC interrupt is edge triggered. */ 680 if (ctlr->ccc) 681 ise = 1 << ctlr->cccv; 682 /* Some controllers have edge triggered IS. */ 683 if (ctlr->quirks & AHCI_Q_EDGEIS) 684 ise |= is; 685 if (ise != 0) 686 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 687 for (; unit < ctlr->channels; unit++) { 688 if ((is & (1 << unit)) != 0 && 689 (arg = ctlr->interrupt[unit].argument)) { 690 ctlr->interrupt[unit].function(arg); 691 } 692 } 693 /* AHCI declares level triggered IS. */ 694 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 695 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 696} 697 698/* 699 * Simplified interrupt handler for multivector MSI mode. 700 */ 701static void 702ahci_intr_one(void *data) 703{ 704 struct ahci_controller_irq *irq = data; 705 struct ahci_controller *ctlr = irq->ctlr; 706 void *arg; 707 int unit; 708 709 unit = irq->r_irq_rid - 1; 710 /* Some controllers have edge triggered IS. */ 711 if (ctlr->quirks & AHCI_Q_EDGEIS) 712 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 713 if ((arg = ctlr->interrupt[unit].argument)) 714 ctlr->interrupt[unit].function(arg); 715 /* AHCI declares level triggered IS. */ 716 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 717 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 718} 719 720static struct resource * 721ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 722 u_long start, u_long end, u_long count, u_int flags) 723{ 724 struct ahci_controller *ctlr = device_get_softc(dev); 725 int unit = ((struct ahci_channel *)device_get_softc(child))->unit; 726 struct resource *res = NULL; 727 int offset = AHCI_OFFSET + (unit << 7); 728 long st; 729 730 switch (type) { 731 case SYS_RES_MEMORY: 732 st = rman_get_start(ctlr->r_mem); 733 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 734 st + offset + 127, 128, RF_ACTIVE, child); 735 if (res) { 736 bus_space_handle_t bsh; 737 bus_space_tag_t bst; 738 bsh = rman_get_bushandle(ctlr->r_mem); 739 bst = rman_get_bustag(ctlr->r_mem); 740 bus_space_subregion(bst, bsh, offset, 128, &bsh); 741 rman_set_bushandle(res, bsh); 742 rman_set_bustag(res, bst); 743 } 744 break; 745 case SYS_RES_IRQ: 746 if (*rid == ATA_IRQ_RID) 747 res = ctlr->irqs[0].r_irq; 748 break; 749 } 750 return (res); 751} 752 753static int 754ahci_release_resource(device_t dev, device_t child, int type, int rid, 755 struct resource *r) 756{ 757 758 switch (type) { 759 case SYS_RES_MEMORY: 760 rman_release_resource(r); 761 return (0); 762 case SYS_RES_IRQ: 763 if (rid != ATA_IRQ_RID) 764 return ENOENT; 765 return (0); 766 } 767 return (EINVAL); 768} 769 770static int 771ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 772 int flags, driver_filter_t *filter, driver_intr_t *function, 773 void *argument, void **cookiep) 774{ 775 struct ahci_controller *ctlr = device_get_softc(dev); 776 int unit = (intptr_t)device_get_ivars(child); 777 778 if (filter != NULL) { 779 printf("ahci.c: we cannot use a filter here\n"); 780 return (EINVAL); 781 } 782 ctlr->interrupt[unit].function = function; 783 ctlr->interrupt[unit].argument = argument; 784 return (0); 785} 786 787static int 788ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 789 void *cookie) 790{ 791 struct ahci_controller *ctlr = device_get_softc(dev); 792 int unit = (intptr_t)device_get_ivars(child); 793 794 ctlr->interrupt[unit].function = NULL; 795 ctlr->interrupt[unit].argument = NULL; 796 return (0); 797} 798 799static int 800ahci_print_child(device_t dev, device_t child) 801{ 802 int retval; 803 804 retval = bus_print_child_header(dev, child); 805 retval += printf(" at channel %d", 806 (int)(intptr_t)device_get_ivars(child)); 807 retval += bus_print_child_footer(dev, child); 808 809 return (retval); 810} 811 812static int 813ahci_child_location_str(device_t dev, device_t child, char *buf, 814 size_t buflen) 815{ 816 817 snprintf(buf, buflen, "channel=%d", 818 (int)(intptr_t)device_get_ivars(child)); 819 return (0); 820} 821 822devclass_t ahci_devclass; 823static device_method_t ahci_methods[] = { 824 DEVMETHOD(device_probe, ahci_probe), 825 DEVMETHOD(device_attach, ahci_attach), 826 DEVMETHOD(device_detach, ahci_detach), 827 DEVMETHOD(device_suspend, ahci_suspend), 828 DEVMETHOD(device_resume, ahci_resume), 829 DEVMETHOD(bus_print_child, ahci_print_child), 830 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 831 DEVMETHOD(bus_release_resource, ahci_release_resource), 832 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 833 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 834 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 835 { 0, 0 } 836}; 837static driver_t ahci_driver = { 838 "ahci", 839 ahci_methods, 840 sizeof(struct ahci_controller) 841}; 842DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 843static device_method_t ahci_ata_methods[] = { 844 DEVMETHOD(device_probe, ahci_ata_probe), 845 DEVMETHOD(device_attach, ahci_attach), 846 DEVMETHOD(device_detach, ahci_detach), 847 DEVMETHOD(device_suspend, ahci_suspend), 848 DEVMETHOD(device_resume, ahci_resume), 849 DEVMETHOD(bus_print_child, ahci_print_child), 850 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 851 DEVMETHOD(bus_release_resource, ahci_release_resource), 852 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 853 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 854 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 855 { 0, 0 } 856}; 857static driver_t ahci_ata_driver = { 858 "ahci", 859 ahci_ata_methods, 860 sizeof(struct ahci_controller) 861}; 862DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0); 863MODULE_VERSION(ahci, 1); 864MODULE_DEPEND(ahci, cam, 1, 1, 1); 865 866static int 867ahci_ch_probe(device_t dev) 868{ 869 870 device_set_desc_copy(dev, "AHCI channel"); 871 return (0); 872} 873 874static int 875ahci_ch_attach(device_t dev) 876{ 877 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 878 struct ahci_channel *ch = device_get_softc(dev); 879 struct cam_devq *devq; 880 int rid, error, i, sata_rev = 0; 881 u_int32_t version; 882 883 ch->dev = dev; 884 ch->unit = (intptr_t)device_get_ivars(dev); 885 ch->caps = ctlr->caps; 886 ch->caps2 = ctlr->caps2; 887 ch->quirks = ctlr->quirks; 888 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 889 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 890 resource_int_value(device_get_name(dev), 891 device_get_unit(dev), "pm_level", &ch->pm_level); 892 if (ch->pm_level > 3) 893 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 894 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 895 /* Limit speed for my onboard JMicron external port. 896 * It is not eSATA really. */ 897 if (pci_get_devid(ctlr->dev) == 0x2363197b && 898 pci_get_subvendor(ctlr->dev) == 0x1043 && 899 pci_get_subdevice(ctlr->dev) == 0x81e4 && 900 ch->unit == 0) 901 sata_rev = 1; 902 if (ch->quirks & AHCI_Q_SATA2) 903 sata_rev = 2; 904 resource_int_value(device_get_name(dev), 905 device_get_unit(dev), "sata_rev", &sata_rev); 906 for (i = 0; i < 16; i++) { 907 ch->user[i].revision = sata_rev; 908 ch->user[i].mode = 0; 909 ch->user[i].bytecount = 8192; 910 ch->user[i].tags = ch->numslots; 911 ch->user[i].caps = 0; 912 ch->curr[i] = ch->user[i]; 913 if (ch->pm_level) { 914 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 915 CTS_SATA_CAPS_H_APST | 916 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 917 } 918 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA | 919 CTS_SATA_CAPS_H_AN; 920 } 921 rid = ch->unit; 922 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 923 &rid, RF_ACTIVE))) 924 return (ENXIO); 925 ahci_dmainit(dev); 926 ahci_slotsalloc(dev); 927 ahci_ch_init(dev); 928 mtx_lock(&ch->mtx); 929 rid = ATA_IRQ_RID; 930 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 931 &rid, RF_SHAREABLE | RF_ACTIVE))) { 932 device_printf(dev, "Unable to map interrupt\n"); 933 error = ENXIO; 934 goto err0; 935 } 936 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 937 ahci_ch_intr_locked, dev, &ch->ih))) { 938 device_printf(dev, "Unable to setup interrupt\n"); 939 error = ENXIO; 940 goto err1; 941 } 942 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 943 version = ATA_INL(ctlr->r_mem, AHCI_VS); 944 if (version < 0x00010020 && (ctlr->caps & AHCI_CAP_FBSS)) 945 ch->chcaps |= AHCI_P_CMD_FBSCP; 946 if (bootverbose) { 947 device_printf(dev, "Caps:%s%s%s%s%s\n", 948 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 949 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 950 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 951 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 952 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":""); 953 } 954 /* Create the device queue for our SIM. */ 955 devq = cam_simq_alloc(ch->numslots); 956 if (devq == NULL) { 957 device_printf(dev, "Unable to allocate simq\n"); 958 error = ENOMEM; 959 goto err1; 960 } 961 /* Construct SIM entry */ 962 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 963 device_get_unit(dev), &ch->mtx, 964 min(2, ch->numslots), 965 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 966 devq); 967 if (ch->sim == NULL) { 968 cam_simq_free(devq); 969 device_printf(dev, "unable to allocate sim\n"); 970 error = ENOMEM; 971 goto err1; 972 } 973 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 974 device_printf(dev, "unable to register xpt bus\n"); 975 error = ENXIO; 976 goto err2; 977 } 978 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 979 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 980 device_printf(dev, "unable to create path\n"); 981 error = ENXIO; 982 goto err3; 983 } 984 if (ch->pm_level > 3) { 985 callout_reset(&ch->pm_timer, 986 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 987 ahci_ch_pm, dev); 988 } 989 mtx_unlock(&ch->mtx); 990 return (0); 991 992err3: 993 xpt_bus_deregister(cam_sim_path(ch->sim)); 994err2: 995 cam_sim_free(ch->sim, /*free_devq*/TRUE); 996err1: 997 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 998err0: 999 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1000 mtx_unlock(&ch->mtx); 1001 mtx_destroy(&ch->mtx); 1002 return (error); 1003} 1004 1005static int 1006ahci_ch_detach(device_t dev) 1007{ 1008 struct ahci_channel *ch = device_get_softc(dev); 1009 1010 mtx_lock(&ch->mtx); 1011 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 1012 /* Forget about reset. */ 1013 if (ch->resetting) { 1014 ch->resetting = 0; 1015 xpt_release_simq(ch->sim, TRUE); 1016 } 1017 xpt_free_path(ch->path); 1018 xpt_bus_deregister(cam_sim_path(ch->sim)); 1019 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1020 mtx_unlock(&ch->mtx); 1021 1022 if (ch->pm_level > 3) 1023 callout_drain(&ch->pm_timer); 1024 callout_drain(&ch->reset_timer); 1025 bus_teardown_intr(dev, ch->r_irq, ch->ih); 1026 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1027 1028 ahci_ch_deinit(dev); 1029 ahci_slotsfree(dev); 1030 ahci_dmafini(dev); 1031 1032 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1033 mtx_destroy(&ch->mtx); 1034 return (0); 1035} 1036 1037static int 1038ahci_ch_init(device_t dev) 1039{ 1040 struct ahci_channel *ch = device_get_softc(dev); 1041 uint64_t work; 1042 1043 /* Disable port interrupts */ 1044 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1045 /* Setup work areas */ 1046 work = ch->dma.work_bus + AHCI_CL_OFFSET; 1047 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 1048 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 1049 work = ch->dma.rfis_bus; 1050 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 1051 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 1052 /* Activate the channel and power/spin up device */ 1053 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 1054 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1055 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 1056 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 1057 ahci_start_fr(dev); 1058 ahci_start(dev, 1); 1059 return (0); 1060} 1061 1062static int 1063ahci_ch_deinit(device_t dev) 1064{ 1065 struct ahci_channel *ch = device_get_softc(dev); 1066 1067 /* Disable port interrupts. */ 1068 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1069 /* Reset command register. */ 1070 ahci_stop(dev); 1071 ahci_stop_fr(dev); 1072 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 1073 /* Allow everything, including partial and slumber modes. */ 1074 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 1075 /* Request slumber mode transition and give some time to get there. */ 1076 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 1077 DELAY(100); 1078 /* Disable PHY. */ 1079 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 1080 return (0); 1081} 1082 1083static int 1084ahci_ch_suspend(device_t dev) 1085{ 1086 struct ahci_channel *ch = device_get_softc(dev); 1087 1088 mtx_lock(&ch->mtx); 1089 xpt_freeze_simq(ch->sim, 1); 1090 /* Forget about reset. */ 1091 if (ch->resetting) { 1092 ch->resetting = 0; 1093 callout_stop(&ch->reset_timer); 1094 xpt_release_simq(ch->sim, TRUE); 1095 } 1096 while (ch->oslots) 1097 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 1098 ahci_ch_deinit(dev); 1099 mtx_unlock(&ch->mtx); 1100 return (0); 1101} 1102 1103static int 1104ahci_ch_resume(device_t dev) 1105{ 1106 struct ahci_channel *ch = device_get_softc(dev); 1107 1108 mtx_lock(&ch->mtx); 1109 ahci_ch_init(dev); 1110 ahci_reset(dev); 1111 xpt_release_simq(ch->sim, TRUE); 1112 mtx_unlock(&ch->mtx); 1113 return (0); 1114} 1115 1116devclass_t ahcich_devclass; 1117static device_method_t ahcich_methods[] = { 1118 DEVMETHOD(device_probe, ahci_ch_probe), 1119 DEVMETHOD(device_attach, ahci_ch_attach), 1120 DEVMETHOD(device_detach, ahci_ch_detach), 1121 DEVMETHOD(device_suspend, ahci_ch_suspend), 1122 DEVMETHOD(device_resume, ahci_ch_resume), 1123 { 0, 0 } 1124}; 1125static driver_t ahcich_driver = { 1126 "ahcich", 1127 ahcich_methods, 1128 sizeof(struct ahci_channel) 1129}; 1130DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0); 1131 1132struct ahci_dc_cb_args { 1133 bus_addr_t maddr; 1134 int error; 1135}; 1136 1137static void 1138ahci_dmainit(device_t dev) 1139{ 1140 struct ahci_channel *ch = device_get_softc(dev); 1141 struct ahci_dc_cb_args dcba; 1142 size_t rfsize; 1143 1144 if (ch->caps & AHCI_CAP_64BIT) 1145 ch->dma.max_address = BUS_SPACE_MAXADDR; 1146 else 1147 ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT; 1148 /* Command area. */ 1149 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1150 ch->dma.max_address, BUS_SPACE_MAXADDR, 1151 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1152 0, NULL, NULL, &ch->dma.work_tag)) 1153 goto error; 1154 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0, 1155 &ch->dma.work_map)) 1156 goto error; 1157 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1158 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1159 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1160 goto error; 1161 } 1162 ch->dma.work_bus = dcba.maddr; 1163 /* FIS receive area. */ 1164 if (ch->chcaps & AHCI_P_CMD_FBSCP) 1165 rfsize = 4096; 1166 else 1167 rfsize = 256; 1168 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 1169 ch->dma.max_address, BUS_SPACE_MAXADDR, 1170 NULL, NULL, rfsize, 1, rfsize, 1171 0, NULL, NULL, &ch->dma.rfis_tag)) 1172 goto error; 1173 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1174 &ch->dma.rfis_map)) 1175 goto error; 1176 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1177 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1178 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1179 goto error; 1180 } 1181 ch->dma.rfis_bus = dcba.maddr; 1182 /* Data area. */ 1183 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1184 ch->dma.max_address, BUS_SPACE_MAXADDR, 1185 NULL, NULL, 1186 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1187 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1188 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 1189 goto error; 1190 } 1191 return; 1192 1193error: 1194 device_printf(dev, "WARNING - DMA initialization failed\n"); 1195 ahci_dmafini(dev); 1196} 1197 1198static void 1199ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1200{ 1201 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1202 1203 if (!(dcba->error = error)) 1204 dcba->maddr = segs[0].ds_addr; 1205} 1206 1207static void 1208ahci_dmafini(device_t dev) 1209{ 1210 struct ahci_channel *ch = device_get_softc(dev); 1211 1212 if (ch->dma.data_tag) { 1213 bus_dma_tag_destroy(ch->dma.data_tag); 1214 ch->dma.data_tag = NULL; 1215 } 1216 if (ch->dma.rfis_bus) { 1217 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1218 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1219 ch->dma.rfis_bus = 0; 1220 ch->dma.rfis_map = NULL; 1221 ch->dma.rfis = NULL; 1222 } 1223 if (ch->dma.work_bus) { 1224 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1225 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1226 ch->dma.work_bus = 0; 1227 ch->dma.work_map = NULL; 1228 ch->dma.work = NULL; 1229 } 1230 if (ch->dma.work_tag) { 1231 bus_dma_tag_destroy(ch->dma.work_tag); 1232 ch->dma.work_tag = NULL; 1233 } 1234} 1235 1236static void 1237ahci_slotsalloc(device_t dev) 1238{ 1239 struct ahci_channel *ch = device_get_softc(dev); 1240 int i; 1241 1242 /* Alloc and setup command/dma slots */ 1243 bzero(ch->slot, sizeof(ch->slot)); 1244 for (i = 0; i < ch->numslots; i++) { 1245 struct ahci_slot *slot = &ch->slot[i]; 1246 1247 slot->dev = dev; 1248 slot->slot = i; 1249 slot->state = AHCI_SLOT_EMPTY; 1250 slot->ccb = NULL; 1251 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1252 1253 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1254 device_printf(ch->dev, "FAILURE - create data_map\n"); 1255 } 1256} 1257 1258static void 1259ahci_slotsfree(device_t dev) 1260{ 1261 struct ahci_channel *ch = device_get_softc(dev); 1262 int i; 1263 1264 /* Free all dma slots */ 1265 for (i = 0; i < ch->numslots; i++) { 1266 struct ahci_slot *slot = &ch->slot[i]; 1267 1268 callout_drain(&slot->timeout); 1269 if (slot->dma.data_map) { 1270 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1271 slot->dma.data_map = NULL; 1272 } 1273 } 1274} 1275 1276static int 1277ahci_phy_check_events(device_t dev, u_int32_t serr) 1278{ 1279 struct ahci_channel *ch = device_get_softc(dev); 1280 1281 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 1282 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) { 1283 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1284 union ccb *ccb; 1285 1286 if (bootverbose) { 1287 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 1288 device_printf(dev, "CONNECT requested\n"); 1289 else 1290 device_printf(dev, "DISCONNECT requested\n"); 1291 } 1292 ahci_reset(dev); 1293 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1294 return (0); 1295 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1296 cam_sim_path(ch->sim), 1297 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1298 xpt_free_ccb(ccb); 1299 return (0); 1300 } 1301 xpt_rescan(ccb); 1302 return (1); 1303 } 1304 return (0); 1305} 1306 1307static void 1308ahci_cpd_check_events(device_t dev) 1309{ 1310 struct ahci_channel *ch = device_get_softc(dev); 1311 u_int32_t status; 1312 union ccb *ccb; 1313 1314 if (ch->pm_level == 0) 1315 return; 1316 1317 status = ATA_INL(ch->r_mem, AHCI_P_CMD); 1318 if ((status & AHCI_P_CMD_CPD) == 0) 1319 return; 1320 1321 if (bootverbose) { 1322 if (status & AHCI_P_CMD_CPS) { 1323 device_printf(dev, "COLD CONNECT requested\n"); 1324 } else 1325 device_printf(dev, "COLD DISCONNECT requested\n"); 1326 } 1327 ahci_reset(dev); 1328 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1329 return; 1330 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim), 1331 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1332 xpt_free_ccb(ccb); 1333 return; 1334 } 1335 xpt_rescan(ccb); 1336} 1337 1338static void 1339ahci_notify_events(device_t dev, u_int32_t status) 1340{ 1341 struct ahci_channel *ch = device_get_softc(dev); 1342 struct cam_path *dpath; 1343 int i; 1344 1345 if (ch->caps & AHCI_CAP_SSNTF) 1346 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1347 if (bootverbose) 1348 device_printf(dev, "SNTF 0x%04x\n", status); 1349 for (i = 0; i < 16; i++) { 1350 if ((status & (1 << i)) == 0) 1351 continue; 1352 if (xpt_create_path(&dpath, NULL, 1353 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1354 xpt_async(AC_SCSI_AEN, dpath, NULL); 1355 xpt_free_path(dpath); 1356 } 1357 } 1358} 1359 1360static void 1361ahci_ch_intr_locked(void *data) 1362{ 1363 device_t dev = (device_t)data; 1364 struct ahci_channel *ch = device_get_softc(dev); 1365 1366 mtx_lock(&ch->mtx); 1367 ahci_ch_intr(data); 1368 mtx_unlock(&ch->mtx); 1369} 1370 1371static void 1372ahci_ch_pm(void *arg) 1373{ 1374 device_t dev = (device_t)arg; 1375 struct ahci_channel *ch = device_get_softc(dev); 1376 uint32_t work; 1377 1378 if (ch->numrslots != 0) 1379 return; 1380 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1381 if (ch->pm_level == 4) 1382 work |= AHCI_P_CMD_PARTIAL; 1383 else 1384 work |= AHCI_P_CMD_SLUMBER; 1385 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1386} 1387 1388static void 1389ahci_ch_intr(void *data) 1390{ 1391 device_t dev = (device_t)data; 1392 struct ahci_channel *ch = device_get_softc(dev); 1393 uint32_t istatus, sstatus, cstatus, serr = 0, sntf = 0, ok, err; 1394 enum ahci_err_type et; 1395 int i, ccs, port, reset = 0; 1396 1397 /* Read and clear interrupt statuses. */ 1398 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1399 if (istatus == 0) 1400 return; 1401 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1402 /* Read command statuses. */ 1403 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1404 cstatus = ATA_INL(ch->r_mem, AHCI_P_CI); 1405 if (istatus & AHCI_P_IX_SDB) { 1406 if (ch->caps & AHCI_CAP_SSNTF) 1407 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1408 else if (ch->fbs_enabled) { 1409 u_int8_t *fis = ch->dma.rfis + 0x58; 1410 1411 for (i = 0; i < 16; i++) { 1412 if (fis[1] & 0x80) { 1413 fis[1] &= 0x7f; 1414 sntf |= 1 << i; 1415 } 1416 fis += 256; 1417 } 1418 } else { 1419 u_int8_t *fis = ch->dma.rfis + 0x58; 1420 1421 if (fis[1] & 0x80) 1422 sntf = (1 << (fis[1] & 0x0f)); 1423 } 1424 } 1425 /* Process PHY events */ 1426 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1427 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1428 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1429 if (serr) { 1430 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1431 reset = ahci_phy_check_events(dev, serr); 1432 } 1433 } 1434 /* Process cold presence detection events */ 1435 if ((istatus & AHCI_P_IX_CPD) && !reset) 1436 ahci_cpd_check_events(dev); 1437 /* Process command errors */ 1438 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1439 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1440 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1441 >> AHCI_P_CMD_CCS_SHIFT; 1442//device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1443// __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1444// serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1445 port = -1; 1446 if (ch->fbs_enabled) { 1447 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1448 if (fbs & AHCI_P_FBS_SDE) { 1449 port = (fbs & AHCI_P_FBS_DWE) 1450 >> AHCI_P_FBS_DWE_SHIFT; 1451 } else { 1452 for (i = 0; i < 16; i++) { 1453 if (ch->numrslotspd[i] == 0) 1454 continue; 1455 if (port == -1) 1456 port = i; 1457 else if (port != i) { 1458 port = -2; 1459 break; 1460 } 1461 } 1462 } 1463 } 1464 err = ch->rslots & (cstatus | sstatus); 1465 } else { 1466 ccs = 0; 1467 err = 0; 1468 port = -1; 1469 } 1470 /* Complete all successfull commands. */ 1471 ok = ch->rslots & ~(cstatus | sstatus); 1472 for (i = 0; i < ch->numslots; i++) { 1473 if ((ok >> i) & 1) 1474 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1475 } 1476 /* On error, complete the rest of commands with error statuses. */ 1477 if (err) { 1478 if (ch->frozen) { 1479 union ccb *fccb = ch->frozen; 1480 ch->frozen = NULL; 1481 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1482 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1483 xpt_freeze_devq(fccb->ccb_h.path, 1); 1484 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1485 } 1486 xpt_done(fccb); 1487 } 1488 for (i = 0; i < ch->numslots; i++) { 1489 /* XXX: reqests in loading state. */ 1490 if (((err >> i) & 1) == 0) 1491 continue; 1492 if (port >= 0 && 1493 ch->slot[i].ccb->ccb_h.target_id != port) 1494 continue; 1495 if (istatus & AHCI_P_IX_TFE) { 1496 if (port != -2) { 1497 /* Task File Error */ 1498 if (ch->numtslotspd[ 1499 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1500 /* Untagged operation. */ 1501 if (i == ccs) 1502 et = AHCI_ERR_TFE; 1503 else 1504 et = AHCI_ERR_INNOCENT; 1505 } else { 1506 /* Tagged operation. */ 1507 et = AHCI_ERR_NCQ; 1508 } 1509 } else { 1510 et = AHCI_ERR_TFE; 1511 ch->fatalerr = 1; 1512 } 1513 } else if (istatus & AHCI_P_IX_IF) { 1514 if (ch->numtslots == 0 && i != ccs && port != -2) 1515 et = AHCI_ERR_INNOCENT; 1516 else 1517 et = AHCI_ERR_SATA; 1518 } else 1519 et = AHCI_ERR_INVALID; 1520 ahci_end_transaction(&ch->slot[i], et); 1521 } 1522 /* 1523 * We can't reinit port if there are some other 1524 * commands active, use resume to complete them. 1525 */ 1526 if (ch->rslots != 0 && !ch->recoverycmd) 1527 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1528 } 1529 /* Process NOTIFY events */ 1530 if (sntf) 1531 ahci_notify_events(dev, sntf); 1532} 1533 1534/* Must be called with channel locked. */ 1535static int 1536ahci_check_collision(device_t dev, union ccb *ccb) 1537{ 1538 struct ahci_channel *ch = device_get_softc(dev); 1539 int t = ccb->ccb_h.target_id; 1540 1541 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1542 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1543 /* Tagged command while we have no supported tag free. */ 1544 if (((~ch->oslots) & (0xffffffff >> (32 - 1545 ch->curr[t].tags))) == 0) 1546 return (1); 1547 /* If we have FBS */ 1548 if (ch->fbs_enabled) { 1549 /* Tagged command while untagged are active. */ 1550 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1551 return (1); 1552 } else { 1553 /* Tagged command while untagged are active. */ 1554 if (ch->numrslots != 0 && ch->numtslots == 0) 1555 return (1); 1556 /* Tagged command while tagged to other target is active. */ 1557 if (ch->numtslots != 0 && 1558 ch->taggedtarget != ccb->ccb_h.target_id) 1559 return (1); 1560 } 1561 } else { 1562 /* If we have FBS */ 1563 if (ch->fbs_enabled) { 1564 /* Untagged command while tagged are active. */ 1565 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1566 return (1); 1567 } else { 1568 /* Untagged command while tagged are active. */ 1569 if (ch->numrslots != 0 && ch->numtslots != 0) 1570 return (1); 1571 } 1572 } 1573 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1574 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1575 /* Atomic command while anything active. */ 1576 if (ch->numrslots != 0) 1577 return (1); 1578 } 1579 /* We have some atomic command running. */ 1580 if (ch->aslots != 0) 1581 return (1); 1582 return (0); 1583} 1584 1585/* Must be called with channel locked. */ 1586static void 1587ahci_begin_transaction(device_t dev, union ccb *ccb) 1588{ 1589 struct ahci_channel *ch = device_get_softc(dev); 1590 struct ahci_slot *slot; 1591 int tag, tags; 1592 1593 /* Choose empty slot. */ 1594 tags = ch->numslots; 1595 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1596 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1597 tags = ch->curr[ccb->ccb_h.target_id].tags; 1598 tag = ch->lastslot; 1599 while (1) { 1600 if (tag >= tags) 1601 tag = 0; 1602 if (ch->slot[tag].state == AHCI_SLOT_EMPTY) 1603 break; 1604 tag++; 1605 }; 1606 ch->lastslot = tag; 1607 /* Occupy chosen slot. */ 1608 slot = &ch->slot[tag]; 1609 slot->ccb = ccb; 1610 /* Stop PM timer. */ 1611 if (ch->numrslots == 0 && ch->pm_level > 3) 1612 callout_stop(&ch->pm_timer); 1613 /* Update channel stats. */ 1614 ch->oslots |= (1 << slot->slot); 1615 ch->numrslots++; 1616 ch->numrslotspd[ccb->ccb_h.target_id]++; 1617 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1618 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1619 ch->numtslots++; 1620 ch->numtslotspd[ccb->ccb_h.target_id]++; 1621 ch->taggedtarget = ccb->ccb_h.target_id; 1622 } 1623 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1624 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1625 ch->aslots |= (1 << slot->slot); 1626 slot->dma.nsegs = 0; 1627 /* If request moves data, setup and load SG list */ 1628 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1629 void *buf; 1630 bus_size_t size; 1631 1632 slot->state = AHCI_SLOT_LOADING; 1633 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1634 buf = ccb->ataio.data_ptr; 1635 size = ccb->ataio.dxfer_len; 1636 } else { 1637 buf = ccb->csio.data_ptr; 1638 size = ccb->csio.dxfer_len; 1639 } 1640 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1641 buf, size, ahci_dmasetprd, slot, 0); 1642 } else 1643 ahci_execute_transaction(slot); 1644} 1645 1646/* Locked by busdma engine. */ 1647static void 1648ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1649{ 1650 struct ahci_slot *slot = arg; 1651 struct ahci_channel *ch = device_get_softc(slot->dev); 1652 struct ahci_cmd_tab *ctp; 1653 struct ahci_dma_prd *prd; 1654 int i; 1655 1656 if (error) { 1657 device_printf(slot->dev, "DMA load error\n"); 1658 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1659 return; 1660 } 1661 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1662 /* Get a piece of the workspace for this request */ 1663 ctp = (struct ahci_cmd_tab *) 1664 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1665 /* Fill S/G table */ 1666 prd = &ctp->prd_tab[0]; 1667 for (i = 0; i < nsegs; i++) { 1668 prd[i].dba = htole64(segs[i].ds_addr); 1669 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1670 } 1671 slot->dma.nsegs = nsegs; 1672 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1673 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1674 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1675 ahci_execute_transaction(slot); 1676} 1677 1678/* Must be called with channel locked. */ 1679static void 1680ahci_execute_transaction(struct ahci_slot *slot) 1681{ 1682 device_t dev = slot->dev; 1683 struct ahci_channel *ch = device_get_softc(dev); 1684 struct ahci_cmd_tab *ctp; 1685 struct ahci_cmd_list *clp; 1686 union ccb *ccb = slot->ccb; 1687 int port = ccb->ccb_h.target_id & 0x0f; 1688 int fis_size, i; 1689 uint8_t *fis = ch->dma.rfis + 0x40; 1690 uint8_t val; 1691 1692 /* Get a piece of the workspace for this request */ 1693 ctp = (struct ahci_cmd_tab *) 1694 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1695 /* Setup the FIS for this request */ 1696 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) { 1697 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1698 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1699 return; 1700 } 1701 /* Setup the command list entry */ 1702 clp = (struct ahci_cmd_list *) 1703 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1704 clp->cmd_flags = htole16( 1705 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1706 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1707 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1708 (fis_size / sizeof(u_int32_t)) | 1709 (port << 12)); 1710 clp->prd_length = htole16(slot->dma.nsegs); 1711 /* Special handling for Soft Reset command. */ 1712 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1713 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1714 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1715 /* Kick controller into sane state */ 1716 ahci_stop(dev); 1717 ahci_clo(dev); 1718 ahci_start(dev, 0); 1719 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1720 } else { 1721 /* Prepare FIS receive area for check. */ 1722 for (i = 0; i < 20; i++) 1723 fis[i] = 0xff; 1724 } 1725 } 1726 clp->bytecount = 0; 1727 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1728 (AHCI_CT_SIZE * slot->slot)); 1729 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1730 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1731 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1732 BUS_DMASYNC_PREREAD); 1733 /* Set ACTIVE bit for NCQ commands. */ 1734 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1735 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1736 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1737 } 1738 /* If FBS is enabled, set PMP port. */ 1739 if (ch->fbs_enabled) { 1740 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1741 (port << AHCI_P_FBS_DEV_SHIFT)); 1742 } 1743 /* Issue command to the controller. */ 1744 slot->state = AHCI_SLOT_RUNNING; 1745 ch->rslots |= (1 << slot->slot); 1746 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1747 /* Device reset commands doesn't interrupt. Poll them. */ 1748 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1749 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || 1750 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL))) { 1751 int count, timeout = ccb->ccb_h.timeout * 100; 1752 enum ahci_err_type et = AHCI_ERR_NONE; 1753 1754 for (count = 0; count < timeout; count++) { 1755 DELAY(10); 1756 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1757 break; 1758 if (ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) { 1759 device_printf(ch->dev, 1760 "Poll error on slot %d, TFD: %04x\n", 1761 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1762 et = AHCI_ERR_TFE; 1763 break; 1764 } 1765 /* Workaround for ATI SB600/SB700 chipsets. */ 1766 if (ccb->ccb_h.target_id == 15 && 1767 pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1768 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1769 et = AHCI_ERR_TIMEOUT; 1770 break; 1771 } 1772 } 1773 if (timeout && (count >= timeout)) { 1774 device_printf(ch->dev, 1775 "Poll timeout on slot %d\n", slot->slot); 1776 device_printf(dev, "is %08x cs %08x ss %08x " 1777 "rs %08x tfd %02x serr %08x\n", 1778 ATA_INL(ch->r_mem, AHCI_P_IS), 1779 ATA_INL(ch->r_mem, AHCI_P_CI), 1780 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1781 ATA_INL(ch->r_mem, AHCI_P_TFD), 1782 ATA_INL(ch->r_mem, AHCI_P_SERR)); 1783 et = AHCI_ERR_TIMEOUT; 1784 } 1785 /* Marvell controllers do not wait for readyness. */ 1786 if ((ch->quirks & AHCI_Q_NOBSYRES) && 1787 (ccb->ccb_h.func_code == XPT_ATA_IO) && 1788 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1789 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 1790 while ((val = fis[2]) & (ATA_S_BUSY | ATA_S_DRQ)) { 1791 DELAY(10); 1792 if (count++ >= timeout) { 1793 device_printf(dev, "device is not " 1794 "ready after soft-reset: " 1795 "tfd = %08x\n", val); 1796 et = AHCI_ERR_TIMEOUT; 1797 break; 1798 } 1799 } 1800 } 1801 ahci_end_transaction(slot, et); 1802 /* Kick controller into sane state and enable FBS. */ 1803 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1804 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1805 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 1806 ahci_stop(ch->dev); 1807 ahci_start(ch->dev, 1); 1808 } 1809 return; 1810 } 1811 /* Start command execution timeout */ 1812 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 1813 (timeout_t*)ahci_timeout, slot); 1814 return; 1815} 1816 1817/* Must be called with channel locked. */ 1818static void 1819ahci_process_timeout(device_t dev) 1820{ 1821 struct ahci_channel *ch = device_get_softc(dev); 1822 int i; 1823 1824 mtx_assert(&ch->mtx, MA_OWNED); 1825 /* Handle the rest of commands. */ 1826 for (i = 0; i < ch->numslots; i++) { 1827 /* Do we have a running request on slot? */ 1828 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1829 continue; 1830 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 1831 } 1832} 1833 1834/* Must be called with channel locked. */ 1835static void 1836ahci_rearm_timeout(device_t dev) 1837{ 1838 struct ahci_channel *ch = device_get_softc(dev); 1839 int i; 1840 1841 mtx_assert(&ch->mtx, MA_OWNED); 1842 for (i = 0; i < ch->numslots; i++) { 1843 struct ahci_slot *slot = &ch->slot[i]; 1844 1845 /* Do we have a running request on slot? */ 1846 if (slot->state < AHCI_SLOT_RUNNING) 1847 continue; 1848 if ((ch->toslots & (1 << i)) == 0) 1849 continue; 1850 callout_reset(&slot->timeout, 1851 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1852 (timeout_t*)ahci_timeout, slot); 1853 } 1854} 1855 1856/* Locked by callout mechanism. */ 1857static void 1858ahci_timeout(struct ahci_slot *slot) 1859{ 1860 device_t dev = slot->dev; 1861 struct ahci_channel *ch = device_get_softc(dev); 1862 uint32_t sstatus; 1863 int ccs; 1864 int i; 1865 1866 /* Check for stale timeout. */ 1867 if (slot->state < AHCI_SLOT_RUNNING) 1868 return; 1869 1870 /* Check if slot was not being executed last time we checked. */ 1871 if (slot->state < AHCI_SLOT_EXECUTING) { 1872 /* Check if slot started executing. */ 1873 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1874 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1875 >> AHCI_P_CMD_CCS_SHIFT; 1876 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 1877 ch->fbs_enabled) 1878 slot->state = AHCI_SLOT_EXECUTING; 1879 1880 callout_reset(&slot->timeout, 1881 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1882 (timeout_t*)ahci_timeout, slot); 1883 return; 1884 } 1885 1886 device_printf(dev, "Timeout on slot %d\n", slot->slot); 1887 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x\n", 1888 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1889 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1890 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR)); 1891 1892 /* Handle frozen command. */ 1893 if (ch->frozen) { 1894 union ccb *fccb = ch->frozen; 1895 ch->frozen = NULL; 1896 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1897 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1898 xpt_freeze_devq(fccb->ccb_h.path, 1); 1899 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1900 } 1901 xpt_done(fccb); 1902 } 1903 if (!ch->fbs_enabled) { 1904 /* Without FBS we know real timeout source. */ 1905 ch->fatalerr = 1; 1906 /* Handle command with timeout. */ 1907 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 1908 /* Handle the rest of commands. */ 1909 for (i = 0; i < ch->numslots; i++) { 1910 /* Do we have a running request on slot? */ 1911 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1912 continue; 1913 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1914 } 1915 } else { 1916 /* With FBS we wait for other commands timeout and pray. */ 1917 if (ch->toslots == 0) 1918 xpt_freeze_simq(ch->sim, 1); 1919 ch->toslots |= (1 << slot->slot); 1920 if ((ch->rslots & ~ch->toslots) == 0) 1921 ahci_process_timeout(dev); 1922 else 1923 device_printf(dev, " ... waiting for slots %08x\n", 1924 ch->rslots & ~ch->toslots); 1925 } 1926} 1927 1928/* Must be called with channel locked. */ 1929static void 1930ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 1931{ 1932 device_t dev = slot->dev; 1933 struct ahci_channel *ch = device_get_softc(dev); 1934 union ccb *ccb = slot->ccb; 1935 struct ahci_cmd_list *clp; 1936 int lastto; 1937 1938 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1939 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1940 clp = (struct ahci_cmd_list *) 1941 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1942 /* Read result registers to the result struct 1943 * May be incorrect if several commands finished same time, 1944 * so read only when sure or have to. 1945 */ 1946 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1947 struct ata_res *res = &ccb->ataio.res; 1948 1949 if ((et == AHCI_ERR_TFE) || 1950 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1951 u_int8_t *fis = ch->dma.rfis + 0x40; 1952 1953 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1954 BUS_DMASYNC_POSTREAD); 1955 if (ch->fbs_enabled) { 1956 fis += ccb->ccb_h.target_id * 256; 1957 res->status = fis[2]; 1958 res->error = fis[3]; 1959 } else { 1960 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 1961 1962 res->status = tfd; 1963 res->error = tfd >> 8; 1964 } 1965 res->lba_low = fis[4]; 1966 res->lba_mid = fis[5]; 1967 res->lba_high = fis[6]; 1968 res->device = fis[7]; 1969 res->lba_low_exp = fis[8]; 1970 res->lba_mid_exp = fis[9]; 1971 res->lba_high_exp = fis[10]; 1972 res->sector_count = fis[12]; 1973 res->sector_count_exp = fis[13]; 1974 } else 1975 bzero(res, sizeof(*res)); 1976 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 1977 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1978 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 1979 ccb->ataio.resid = 1980 ccb->ataio.dxfer_len - le32toh(clp->bytecount); 1981 } 1982 } else { 1983 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1984 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 1985 ccb->csio.resid = 1986 ccb->csio.dxfer_len - le32toh(clp->bytecount); 1987 } 1988 } 1989 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1990 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1991 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1992 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1993 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1994 } 1995 if (et != AHCI_ERR_NONE) 1996 ch->eslots |= (1 << slot->slot); 1997 /* In case of error, freeze device for proper recovery. */ 1998 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) && 1999 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 2000 xpt_freeze_devq(ccb->ccb_h.path, 1); 2001 ccb->ccb_h.status |= CAM_DEV_QFRZN; 2002 } 2003 /* Set proper result status. */ 2004 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2005 switch (et) { 2006 case AHCI_ERR_NONE: 2007 ccb->ccb_h.status |= CAM_REQ_CMP; 2008 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 2009 ccb->csio.scsi_status = SCSI_STATUS_OK; 2010 break; 2011 case AHCI_ERR_INVALID: 2012 ch->fatalerr = 1; 2013 ccb->ccb_h.status |= CAM_REQ_INVALID; 2014 break; 2015 case AHCI_ERR_INNOCENT: 2016 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 2017 break; 2018 case AHCI_ERR_TFE: 2019 case AHCI_ERR_NCQ: 2020 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2021 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2022 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2023 } else { 2024 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 2025 } 2026 break; 2027 case AHCI_ERR_SATA: 2028 ch->fatalerr = 1; 2029 if (!ch->recoverycmd) { 2030 xpt_freeze_simq(ch->sim, 1); 2031 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2032 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2033 } 2034 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 2035 break; 2036 case AHCI_ERR_TIMEOUT: 2037 if (!ch->recoverycmd) { 2038 xpt_freeze_simq(ch->sim, 1); 2039 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2040 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2041 } 2042 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 2043 break; 2044 default: 2045 ch->fatalerr = 1; 2046 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 2047 } 2048 /* Free slot. */ 2049 ch->oslots &= ~(1 << slot->slot); 2050 ch->rslots &= ~(1 << slot->slot); 2051 ch->aslots &= ~(1 << slot->slot); 2052 slot->state = AHCI_SLOT_EMPTY; 2053 slot->ccb = NULL; 2054 /* Update channel stats. */ 2055 ch->numrslots--; 2056 ch->numrslotspd[ccb->ccb_h.target_id]--; 2057 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2058 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 2059 ch->numtslots--; 2060 ch->numtslotspd[ccb->ccb_h.target_id]--; 2061 } 2062 /* Cancel timeout state if request completed normally. */ 2063 if (et != AHCI_ERR_TIMEOUT) { 2064 lastto = (ch->toslots == (1 << slot->slot)); 2065 ch->toslots &= ~(1 << slot->slot); 2066 if (lastto) 2067 xpt_release_simq(ch->sim, TRUE); 2068 } 2069 /* If it was first request of reset sequence and there is no error, 2070 * proceed to second request. */ 2071 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2072 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2073 (ccb->ataio.cmd.control & ATA_A_RESET) && 2074 et == AHCI_ERR_NONE) { 2075 ccb->ataio.cmd.control &= ~ATA_A_RESET; 2076 ahci_begin_transaction(dev, ccb); 2077 return; 2078 } 2079 /* If it was our READ LOG command - process it. */ 2080 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 2081 ahci_process_read_log(dev, ccb); 2082 /* If it was our REQUEST SENSE command - process it. */ 2083 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 2084 ahci_process_request_sense(dev, ccb); 2085 /* If it was NCQ or ATAPI command error, put result on hold. */ 2086 } else if (et == AHCI_ERR_NCQ || 2087 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 2088 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 2089 ch->hold[slot->slot] = ccb; 2090 ch->numhslots++; 2091 } else 2092 xpt_done(ccb); 2093 /* Unfreeze frozen command. */ 2094 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) { 2095 union ccb *fccb = ch->frozen; 2096 ch->frozen = NULL; 2097 ahci_begin_transaction(dev, fccb); 2098 xpt_release_simq(ch->sim, TRUE); 2099 } 2100 /* If we have no other active commands, ... */ 2101 if (ch->rslots == 0) { 2102 /* if there was fatal error - reset port. */ 2103 if (ch->toslots != 0 || ch->fatalerr) { 2104 ahci_reset(dev); 2105 } else { 2106 /* if we have slots in error, we can reinit port. */ 2107 if (ch->eslots != 0) { 2108 ahci_stop(dev); 2109 ahci_start(dev, 1); 2110 } 2111 /* if there commands on hold, we can do READ LOG. */ 2112 if (!ch->recoverycmd && ch->numhslots) 2113 ahci_issue_recovery(dev); 2114 } 2115 /* If all the rest of commands are in timeout - give them chance. */ 2116 } else if ((ch->rslots & ~ch->toslots) == 0 && 2117 et != AHCI_ERR_TIMEOUT) 2118 ahci_rearm_timeout(dev); 2119 /* Start PM timer. */ 2120 if (ch->numrslots == 0 && ch->pm_level > 3 && 2121 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 2122 callout_schedule(&ch->pm_timer, 2123 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 2124 } 2125} 2126 2127static void 2128ahci_issue_recovery(device_t dev) 2129{ 2130 struct ahci_channel *ch = device_get_softc(dev); 2131 union ccb *ccb; 2132 struct ccb_ataio *ataio; 2133 struct ccb_scsiio *csio; 2134 int i; 2135 2136 /* Find some held command. */ 2137 for (i = 0; i < ch->numslots; i++) { 2138 if (ch->hold[i]) 2139 break; 2140 } 2141 ccb = xpt_alloc_ccb_nowait(); 2142 if (ccb == NULL) { 2143 device_printf(dev, "Unable to allocate recovery command\n"); 2144completeall: 2145 /* We can't do anything -- complete held commands. */ 2146 for (i = 0; i < ch->numslots; i++) { 2147 if (ch->hold[i] == NULL) 2148 continue; 2149 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2150 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 2151 xpt_done(ch->hold[i]); 2152 ch->hold[i] = NULL; 2153 ch->numhslots--; 2154 } 2155 ahci_reset(dev); 2156 return; 2157 } 2158 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 2159 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2160 /* READ LOG */ 2161 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 2162 ccb->ccb_h.func_code = XPT_ATA_IO; 2163 ccb->ccb_h.flags = CAM_DIR_IN; 2164 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2165 ataio = &ccb->ataio; 2166 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 2167 if (ataio->data_ptr == NULL) { 2168 xpt_free_ccb(ccb); 2169 device_printf(dev, 2170 "Unable to allocate memory for READ LOG command\n"); 2171 goto completeall; 2172 } 2173 ataio->dxfer_len = 512; 2174 bzero(&ataio->cmd, sizeof(ataio->cmd)); 2175 ataio->cmd.flags = CAM_ATAIO_48BIT; 2176 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2177 ataio->cmd.sector_count = 1; 2178 ataio->cmd.sector_count_exp = 0; 2179 ataio->cmd.lba_low = 0x10; 2180 ataio->cmd.lba_mid = 0; 2181 ataio->cmd.lba_mid_exp = 0; 2182 } else { 2183 /* REQUEST SENSE */ 2184 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 2185 ccb->ccb_h.recovery_slot = i; 2186 ccb->ccb_h.func_code = XPT_SCSI_IO; 2187 ccb->ccb_h.flags = CAM_DIR_IN; 2188 ccb->ccb_h.status = 0; 2189 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2190 csio = &ccb->csio; 2191 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 2192 csio->dxfer_len = ch->hold[i]->csio.sense_len; 2193 csio->cdb_len = 6; 2194 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 2195 csio->cdb_io.cdb_bytes[0] = 0x03; 2196 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 2197 } 2198 /* Freeze SIM while doing recovery. */ 2199 ch->recoverycmd = 1; 2200 xpt_freeze_simq(ch->sim, 1); 2201 ahci_begin_transaction(dev, ccb); 2202} 2203 2204static void 2205ahci_process_read_log(device_t dev, union ccb *ccb) 2206{ 2207 struct ahci_channel *ch = device_get_softc(dev); 2208 uint8_t *data; 2209 struct ata_res *res; 2210 int i; 2211 2212 ch->recoverycmd = 0; 2213 2214 data = ccb->ataio.data_ptr; 2215 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2216 (data[0] & 0x80) == 0) { 2217 for (i = 0; i < ch->numslots; i++) { 2218 if (!ch->hold[i]) 2219 continue; 2220 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2221 continue; 2222 if ((data[0] & 0x1F) == i) { 2223 res = &ch->hold[i]->ataio.res; 2224 res->status = data[2]; 2225 res->error = data[3]; 2226 res->lba_low = data[4]; 2227 res->lba_mid = data[5]; 2228 res->lba_high = data[6]; 2229 res->device = data[7]; 2230 res->lba_low_exp = data[8]; 2231 res->lba_mid_exp = data[9]; 2232 res->lba_high_exp = data[10]; 2233 res->sector_count = data[12]; 2234 res->sector_count_exp = data[13]; 2235 } else { 2236 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2237 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2238 } 2239 xpt_done(ch->hold[i]); 2240 ch->hold[i] = NULL; 2241 ch->numhslots--; 2242 } 2243 } else { 2244 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2245 device_printf(dev, "Error while READ LOG EXT\n"); 2246 else if ((data[0] & 0x80) == 0) { 2247 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 2248 } 2249 for (i = 0; i < ch->numslots; i++) { 2250 if (!ch->hold[i]) 2251 continue; 2252 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2253 continue; 2254 xpt_done(ch->hold[i]); 2255 ch->hold[i] = NULL; 2256 ch->numhslots--; 2257 } 2258 } 2259 free(ccb->ataio.data_ptr, M_AHCI); 2260 xpt_free_ccb(ccb); 2261 xpt_release_simq(ch->sim, TRUE); 2262} 2263 2264static void 2265ahci_process_request_sense(device_t dev, union ccb *ccb) 2266{ 2267 struct ahci_channel *ch = device_get_softc(dev); 2268 int i; 2269 2270 ch->recoverycmd = 0; 2271 2272 i = ccb->ccb_h.recovery_slot; 2273 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 2274 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 2275 } else { 2276 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2277 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 2278 } 2279 xpt_done(ch->hold[i]); 2280 ch->hold[i] = NULL; 2281 ch->numhslots--; 2282 xpt_free_ccb(ccb); 2283 xpt_release_simq(ch->sim, TRUE); 2284} 2285 2286static void 2287ahci_start(device_t dev, int fbs) 2288{ 2289 struct ahci_channel *ch = device_get_softc(dev); 2290 u_int32_t cmd; 2291 2292 /* Clear SATA error register */ 2293 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2294 /* Clear any interrupts pending on this channel */ 2295 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2296 /* Configure FIS-based switching if supported. */ 2297 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2298 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2299 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2300 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2301 } 2302 /* Start operations on this channel */ 2303 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2304 cmd &= ~AHCI_P_CMD_PMA; 2305 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2306 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2307} 2308 2309static void 2310ahci_stop(device_t dev) 2311{ 2312 struct ahci_channel *ch = device_get_softc(dev); 2313 u_int32_t cmd; 2314 int timeout; 2315 2316 /* Kill all activity on this channel */ 2317 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2318 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2319 /* Wait for activity stop. */ 2320 timeout = 0; 2321 do { 2322 DELAY(10); 2323 if (timeout++ > 50000) { 2324 device_printf(dev, "stopping AHCI engine failed\n"); 2325 break; 2326 } 2327 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2328 ch->eslots = 0; 2329} 2330 2331static void 2332ahci_clo(device_t dev) 2333{ 2334 struct ahci_channel *ch = device_get_softc(dev); 2335 u_int32_t cmd; 2336 int timeout; 2337 2338 /* Issue Command List Override if supported */ 2339 if (ch->caps & AHCI_CAP_SCLO) { 2340 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2341 cmd |= AHCI_P_CMD_CLO; 2342 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2343 timeout = 0; 2344 do { 2345 DELAY(10); 2346 if (timeout++ > 50000) { 2347 device_printf(dev, "executing CLO failed\n"); 2348 break; 2349 } 2350 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2351 } 2352} 2353 2354static void 2355ahci_stop_fr(device_t dev) 2356{ 2357 struct ahci_channel *ch = device_get_softc(dev); 2358 u_int32_t cmd; 2359 int timeout; 2360 2361 /* Kill all FIS reception on this channel */ 2362 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2363 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2364 /* Wait for FIS reception stop. */ 2365 timeout = 0; 2366 do { 2367 DELAY(10); 2368 if (timeout++ > 50000) { 2369 device_printf(dev, "stopping AHCI FR engine failed\n"); 2370 break; 2371 } 2372 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2373} 2374 2375static void 2376ahci_start_fr(device_t dev) 2377{ 2378 struct ahci_channel *ch = device_get_softc(dev); 2379 u_int32_t cmd; 2380 2381 /* Start FIS reception on this channel */ 2382 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2383 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2384} 2385 2386static int 2387ahci_wait_ready(device_t dev, int t, int t0) 2388{ 2389 struct ahci_channel *ch = device_get_softc(dev); 2390 int timeout = 0; 2391 uint32_t val; 2392 2393 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2394 (ATA_S_BUSY | ATA_S_DRQ)) { 2395 if (timeout > t) { 2396 if (t != 0) { 2397 device_printf(dev, 2398 "AHCI reset: device not ready after %dms " 2399 "(tfd = %08x)\n", 2400 MAX(t, 0) + t0, val); 2401 } 2402 return (EBUSY); 2403 } 2404 DELAY(1000); 2405 timeout++; 2406 } 2407 if (bootverbose) 2408 device_printf(dev, "AHCI reset: device ready after %dms\n", 2409 timeout + t0); 2410 return (0); 2411} 2412 2413static void 2414ahci_reset_to(void *arg) 2415{ 2416 device_t dev = arg; 2417 struct ahci_channel *ch = device_get_softc(dev); 2418 2419 if (ch->resetting == 0) 2420 return; 2421 ch->resetting--; 2422 if (ahci_wait_ready(dev, ch->resetting == 0 ? -1 : 0, 2423 (310 - ch->resetting) * 100) == 0) { 2424 ch->resetting = 0; 2425 ahci_start(dev, 1); 2426 xpt_release_simq(ch->sim, TRUE); 2427 return; 2428 } 2429 if (ch->resetting == 0) { 2430 ahci_clo(dev); 2431 ahci_start(dev, 1); 2432 xpt_release_simq(ch->sim, TRUE); 2433 return; 2434 } 2435 callout_schedule(&ch->reset_timer, hz / 10); 2436} 2437 2438static void 2439ahci_reset(device_t dev) 2440{ 2441 struct ahci_channel *ch = device_get_softc(dev); 2442 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2443 int i; 2444 2445 xpt_freeze_simq(ch->sim, 1); 2446 if (bootverbose) 2447 device_printf(dev, "AHCI reset...\n"); 2448 /* Forget about previous reset. */ 2449 if (ch->resetting) { 2450 ch->resetting = 0; 2451 callout_stop(&ch->reset_timer); 2452 xpt_release_simq(ch->sim, TRUE); 2453 } 2454 /* Requeue freezed command. */ 2455 if (ch->frozen) { 2456 union ccb *fccb = ch->frozen; 2457 ch->frozen = NULL; 2458 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2459 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2460 xpt_freeze_devq(fccb->ccb_h.path, 1); 2461 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2462 } 2463 xpt_done(fccb); 2464 } 2465 /* Kill the engine and requeue all running commands. */ 2466 ahci_stop(dev); 2467 for (i = 0; i < ch->numslots; i++) { 2468 /* Do we have a running request on slot? */ 2469 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2470 continue; 2471 /* XXX; Commands in loading state. */ 2472 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2473 } 2474 for (i = 0; i < ch->numslots; i++) { 2475 if (!ch->hold[i]) 2476 continue; 2477 xpt_done(ch->hold[i]); 2478 ch->hold[i] = NULL; 2479 ch->numhslots--; 2480 } 2481 if (ch->toslots != 0) 2482 xpt_release_simq(ch->sim, TRUE); 2483 ch->eslots = 0; 2484 ch->toslots = 0; 2485 ch->fatalerr = 0; 2486 /* Tell the XPT about the event */ 2487 xpt_async(AC_BUS_RESET, ch->path, NULL); 2488 /* Disable port interrupts */ 2489 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2490 /* Reset and reconnect PHY, */ 2491 if (!ahci_sata_phy_reset(dev)) { 2492 if (bootverbose) 2493 device_printf(dev, 2494 "AHCI reset: device not found\n"); 2495 ch->devices = 0; 2496 /* Enable wanted port interrupts */ 2497 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2498 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2499 AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2500 xpt_release_simq(ch->sim, TRUE); 2501 return; 2502 } 2503 if (bootverbose) 2504 device_printf(dev, "AHCI reset: device found\n"); 2505 /* Wait for clearing busy status. */ 2506 if (ahci_wait_ready(dev, dumping ? 31000 : 0, 0)) { 2507 if (dumping) 2508 ahci_clo(dev); 2509 else 2510 ch->resetting = 310; 2511 } 2512 ch->devices = 1; 2513 /* Enable wanted port interrupts */ 2514 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2515 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2516 AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2517 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2518 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC | 2519 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2520 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2521 if (ch->resetting) 2522 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, dev); 2523 else { 2524 ahci_start(dev, 1); 2525 xpt_release_simq(ch->sim, TRUE); 2526 } 2527} 2528 2529static int 2530ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2531{ 2532 struct ahci_channel *ch = device_get_softc(dev); 2533 u_int8_t *fis = &ctp->cfis[0]; 2534 2535 bzero(ctp->cfis, 64); 2536 fis[0] = 0x27; /* host to device */ 2537 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2538 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2539 fis[1] |= 0x80; 2540 fis[2] = ATA_PACKET_CMD; 2541 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2542 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2543 fis[3] = ATA_F_DMA; 2544 else { 2545 fis[5] = ccb->csio.dxfer_len; 2546 fis[6] = ccb->csio.dxfer_len >> 8; 2547 } 2548 fis[7] = ATA_D_LBA; 2549 fis[15] = ATA_A_4BIT; 2550 bzero(ctp->acmd, 32); 2551 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2552 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2553 ctp->acmd, ccb->csio.cdb_len); 2554 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2555 fis[1] |= 0x80; 2556 fis[2] = ccb->ataio.cmd.command; 2557 fis[3] = ccb->ataio.cmd.features; 2558 fis[4] = ccb->ataio.cmd.lba_low; 2559 fis[5] = ccb->ataio.cmd.lba_mid; 2560 fis[6] = ccb->ataio.cmd.lba_high; 2561 fis[7] = ccb->ataio.cmd.device; 2562 fis[8] = ccb->ataio.cmd.lba_low_exp; 2563 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2564 fis[10] = ccb->ataio.cmd.lba_high_exp; 2565 fis[11] = ccb->ataio.cmd.features_exp; 2566 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2567 fis[12] = tag << 3; 2568 fis[13] = 0; 2569 } else { 2570 fis[12] = ccb->ataio.cmd.sector_count; 2571 fis[13] = ccb->ataio.cmd.sector_count_exp; 2572 } 2573 fis[15] = ATA_A_4BIT; 2574 } else { 2575 fis[15] = ccb->ataio.cmd.control; 2576 } 2577 return (20); 2578} 2579 2580static int 2581ahci_sata_connect(struct ahci_channel *ch) 2582{ 2583 u_int32_t status; 2584 int timeout, found = 0; 2585 2586 /* Wait up to 100ms for "connect well" */ 2587 for (timeout = 0; timeout < 1000 ; timeout++) { 2588 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2589 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 2590 found = 1; 2591 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2592 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2593 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2594 break; 2595 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2596 if (bootverbose) { 2597 device_printf(ch->dev, "SATA offline status=%08x\n", 2598 status); 2599 } 2600 return (0); 2601 } 2602 if (found == 0 && timeout >= 100) 2603 break; 2604 DELAY(100); 2605 } 2606 if (timeout >= 1000 || !found) { 2607 if (bootverbose) { 2608 device_printf(ch->dev, 2609 "SATA connect timeout time=%dus status=%08x\n", 2610 timeout * 100, status); 2611 } 2612 return (0); 2613 } 2614 if (bootverbose) { 2615 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2616 timeout * 100, status); 2617 } 2618 /* Clear SATA error register */ 2619 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2620 return (1); 2621} 2622 2623static int 2624ahci_sata_phy_reset(device_t dev) 2625{ 2626 struct ahci_channel *ch = device_get_softc(dev); 2627 int sata_rev; 2628 uint32_t val; 2629 2630 if (ch->listening) { 2631 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2632 val |= AHCI_P_CMD_SUD; 2633 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2634 ch->listening = 0; 2635 } 2636 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2637 if (sata_rev == 1) 2638 val = ATA_SC_SPD_SPEED_GEN1; 2639 else if (sata_rev == 2) 2640 val = ATA_SC_SPD_SPEED_GEN2; 2641 else if (sata_rev == 3) 2642 val = ATA_SC_SPD_SPEED_GEN3; 2643 else 2644 val = 0; 2645 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2646 ATA_SC_DET_RESET | val | 2647 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2648 DELAY(1000); 2649 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2650 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2651 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2652 if (!ahci_sata_connect(ch)) { 2653 if (ch->caps & AHCI_CAP_SSS) { 2654 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2655 val &= ~AHCI_P_CMD_SUD; 2656 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2657 ch->listening = 1; 2658 } else if (ch->pm_level > 0) 2659 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2660 return (0); 2661 } 2662 return (1); 2663} 2664 2665static int 2666ahci_check_ids(device_t dev, union ccb *ccb) 2667{ 2668 struct ahci_channel *ch = device_get_softc(dev); 2669 2670 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2671 ccb->ccb_h.status = CAM_TID_INVALID; 2672 xpt_done(ccb); 2673 return (-1); 2674 } 2675 if (ccb->ccb_h.target_lun != 0) { 2676 ccb->ccb_h.status = CAM_LUN_INVALID; 2677 xpt_done(ccb); 2678 return (-1); 2679 } 2680 return (0); 2681} 2682 2683static void 2684ahciaction(struct cam_sim *sim, union ccb *ccb) 2685{ 2686 device_t dev, parent; 2687 struct ahci_channel *ch; 2688 2689 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2690 ccb->ccb_h.func_code)); 2691 2692 ch = (struct ahci_channel *)cam_sim_softc(sim); 2693 dev = ch->dev; 2694 switch (ccb->ccb_h.func_code) { 2695 /* Common cases first */ 2696 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2697 case XPT_SCSI_IO: 2698 if (ahci_check_ids(dev, ccb)) 2699 return; 2700 if (ch->devices == 0 || 2701 (ch->pm_present == 0 && 2702 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2703 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2704 break; 2705 } 2706 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2707 /* Check for command collision. */ 2708 if (ahci_check_collision(dev, ccb)) { 2709 /* Freeze command. */ 2710 ch->frozen = ccb; 2711 /* We have only one frozen slot, so freeze simq also. */ 2712 xpt_freeze_simq(ch->sim, 1); 2713 return; 2714 } 2715 ahci_begin_transaction(dev, ccb); 2716 return; 2717 case XPT_EN_LUN: /* Enable LUN as a target */ 2718 case XPT_TARGET_IO: /* Execute target I/O request */ 2719 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2720 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2721 case XPT_ABORT: /* Abort the specified CCB */ 2722 /* XXX Implement */ 2723 ccb->ccb_h.status = CAM_REQ_INVALID; 2724 break; 2725 case XPT_SET_TRAN_SETTINGS: 2726 { 2727 struct ccb_trans_settings *cts = &ccb->cts; 2728 struct ahci_device *d; 2729 2730 if (ahci_check_ids(dev, ccb)) 2731 return; 2732 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2733 d = &ch->curr[ccb->ccb_h.target_id]; 2734 else 2735 d = &ch->user[ccb->ccb_h.target_id]; 2736 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2737 d->revision = cts->xport_specific.sata.revision; 2738 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2739 d->mode = cts->xport_specific.sata.mode; 2740 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2741 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2742 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2743 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2744 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2745 ch->pm_present = cts->xport_specific.sata.pm_present; 2746 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2747 d->atapi = cts->xport_specific.sata.atapi; 2748 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2749 d->caps = cts->xport_specific.sata.caps; 2750 ccb->ccb_h.status = CAM_REQ_CMP; 2751 break; 2752 } 2753 case XPT_GET_TRAN_SETTINGS: 2754 /* Get default/user set transfer settings for the target */ 2755 { 2756 struct ccb_trans_settings *cts = &ccb->cts; 2757 struct ahci_device *d; 2758 uint32_t status; 2759 2760 if (ahci_check_ids(dev, ccb)) 2761 return; 2762 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2763 d = &ch->curr[ccb->ccb_h.target_id]; 2764 else 2765 d = &ch->user[ccb->ccb_h.target_id]; 2766 cts->protocol = PROTO_ATA; 2767 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2768 cts->transport = XPORT_SATA; 2769 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2770 cts->proto_specific.valid = 0; 2771 cts->xport_specific.sata.valid = 0; 2772 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2773 (ccb->ccb_h.target_id == 15 || 2774 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2775 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2776 if (status & 0x0f0) { 2777 cts->xport_specific.sata.revision = 2778 (status & 0x0f0) >> 4; 2779 cts->xport_specific.sata.valid |= 2780 CTS_SATA_VALID_REVISION; 2781 } 2782 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2783 if (ch->pm_level) { 2784 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 2785 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2786 if (ch->caps2 & AHCI_CAP2_APST) 2787 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 2788 } 2789 if ((ch->caps & AHCI_CAP_SNCQ) && 2790 (ch->quirks & AHCI_Q_NOAA) == 0) 2791 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 2792 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 2793 cts->xport_specific.sata.caps &= 2794 ch->user[ccb->ccb_h.target_id].caps; 2795 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2796 } else { 2797 cts->xport_specific.sata.revision = d->revision; 2798 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2799 cts->xport_specific.sata.caps = d->caps; 2800 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2801 } 2802 cts->xport_specific.sata.mode = d->mode; 2803 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2804 cts->xport_specific.sata.bytecount = d->bytecount; 2805 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2806 cts->xport_specific.sata.pm_present = ch->pm_present; 2807 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2808 cts->xport_specific.sata.tags = d->tags; 2809 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2810 cts->xport_specific.sata.atapi = d->atapi; 2811 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2812 ccb->ccb_h.status = CAM_REQ_CMP; 2813 break; 2814 } 2815 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2816 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2817 ahci_reset(dev); 2818 ccb->ccb_h.status = CAM_REQ_CMP; 2819 break; 2820 case XPT_TERM_IO: /* Terminate the I/O process */ 2821 /* XXX Implement */ 2822 ccb->ccb_h.status = CAM_REQ_INVALID; 2823 break; 2824 case XPT_PATH_INQ: /* Path routing inquiry */ 2825 { 2826 struct ccb_pathinq *cpi = &ccb->cpi; 2827 2828 parent = device_get_parent(dev); 2829 cpi->version_num = 1; /* XXX??? */ 2830 cpi->hba_inquiry = PI_SDTR_ABLE; 2831 if (ch->caps & AHCI_CAP_SNCQ) 2832 cpi->hba_inquiry |= PI_TAG_ABLE; 2833 if (ch->caps & AHCI_CAP_SPM) 2834 cpi->hba_inquiry |= PI_SATAPM; 2835 cpi->target_sprt = 0; 2836 cpi->hba_misc = PIM_SEQSCAN; 2837 cpi->hba_eng_cnt = 0; 2838 if (ch->caps & AHCI_CAP_SPM) 2839 cpi->max_target = 15; 2840 else 2841 cpi->max_target = 0; 2842 cpi->max_lun = 0; 2843 cpi->initiator_id = 0; 2844 cpi->bus_id = cam_sim_bus(sim); 2845 cpi->base_transfer_speed = 150000; 2846 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2847 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2848 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2849 cpi->unit_number = cam_sim_unit(sim); 2850 cpi->transport = XPORT_SATA; 2851 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2852 cpi->protocol = PROTO_ATA; 2853 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2854 cpi->maxio = MAXPHYS; 2855 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2856 if (pci_get_devid(parent) == 0x43801002) 2857 cpi->maxio = min(cpi->maxio, 128 * 512); 2858 cpi->hba_vendor = pci_get_vendor(parent); 2859 cpi->hba_device = pci_get_device(parent); 2860 cpi->hba_subvendor = pci_get_subvendor(parent); 2861 cpi->hba_subdevice = pci_get_subdevice(parent); 2862 cpi->ccb_h.status = CAM_REQ_CMP; 2863 break; 2864 } 2865 default: 2866 ccb->ccb_h.status = CAM_REQ_INVALID; 2867 break; 2868 } 2869 xpt_done(ccb); 2870} 2871 2872static void 2873ahcipoll(struct cam_sim *sim) 2874{ 2875 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2876 2877 ahci_ch_intr(ch->dev); 2878 if (ch->resetting != 0 && 2879 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 2880 ch->resetpolldiv = 1000; 2881 ahci_reset_to(ch->dev); 2882 } 2883} 2884