ahci_generic.c revision 250185
1/*- 2 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ahci/ahci.c 250185 2013-05-02 16:09:06Z mav $"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/bus.h> 35#include <sys/conf.h> 36#include <sys/endian.h> 37#include <sys/malloc.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <machine/stdarg.h> 41#include <machine/resource.h> 42#include <machine/bus.h> 43#include <sys/rman.h> 44#include <dev/pci/pcivar.h> 45#include <dev/pci/pcireg.h> 46#include "ahci.h" 47 48#include <cam/cam.h> 49#include <cam/cam_ccb.h> 50#include <cam/cam_sim.h> 51#include <cam/cam_xpt_sim.h> 52#include <cam/cam_debug.h> 53 54/* local prototypes */ 55static int ahci_setup_interrupt(device_t dev); 56static void ahci_intr(void *data); 57static void ahci_intr_one(void *data); 58static int ahci_suspend(device_t dev); 59static int ahci_resume(device_t dev); 60static int ahci_ch_init(device_t dev); 61static int ahci_ch_deinit(device_t dev); 62static int ahci_ch_suspend(device_t dev); 63static int ahci_ch_resume(device_t dev); 64static void ahci_ch_pm(void *arg); 65static void ahci_ch_intr_locked(void *data); 66static void ahci_ch_intr(void *data); 67static int ahci_ctlr_reset(device_t dev); 68static int ahci_ctlr_setup(device_t dev); 69static void ahci_begin_transaction(device_t dev, union ccb *ccb); 70static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 71static void ahci_execute_transaction(struct ahci_slot *slot); 72static void ahci_timeout(struct ahci_slot *slot); 73static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 74static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 75static void ahci_dmainit(device_t dev); 76static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 77static void ahci_dmafini(device_t dev); 78static void ahci_slotsalloc(device_t dev); 79static void ahci_slotsfree(device_t dev); 80static void ahci_reset(device_t dev); 81static void ahci_start(device_t dev, int fbs); 82static void ahci_stop(device_t dev); 83static void ahci_clo(device_t dev); 84static void ahci_start_fr(device_t dev); 85static void ahci_stop_fr(device_t dev); 86 87static int ahci_sata_connect(struct ahci_channel *ch); 88static int ahci_sata_phy_reset(device_t dev); 89static int ahci_wait_ready(device_t dev, int t, int t0); 90 91static void ahci_issue_recovery(device_t dev); 92static void ahci_process_read_log(device_t dev, union ccb *ccb); 93static void ahci_process_request_sense(device_t dev, union ccb *ccb); 94 95static void ahciaction(struct cam_sim *sim, union ccb *ccb); 96static void ahcipoll(struct cam_sim *sim); 97 98static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 99 100static struct { 101 uint32_t id; 102 uint8_t rev; 103 const char *name; 104 int quirks; 105#define AHCI_Q_NOFORCE 1 106#define AHCI_Q_NOPMP 2 107#define AHCI_Q_NONCQ 4 108#define AHCI_Q_1CH 8 109#define AHCI_Q_2CH 16 110#define AHCI_Q_4CH 32 111#define AHCI_Q_EDGEIS 64 112#define AHCI_Q_SATA2 128 113#define AHCI_Q_NOBSYRES 256 114#define AHCI_Q_NOAA 512 115#define AHCI_Q_NOCOUNT 1024 116#define AHCI_Q_ALTSIG 2048 117#define AHCI_Q_NOMSI 4096 118} ahci_ids[] = { 119 {0x43801002, 0x00, "ATI IXP600", AHCI_Q_NOMSI}, 120 {0x43901002, 0x00, "ATI IXP700", 0}, 121 {0x43911002, 0x00, "ATI IXP700", 0}, 122 {0x43921002, 0x00, "ATI IXP700", 0}, 123 {0x43931002, 0x00, "ATI IXP700", 0}, 124 {0x43941002, 0x00, "ATI IXP800", 0}, 125 {0x43951002, 0x00, "ATI IXP800", 0}, 126 {0x78001022, 0x00, "AMD Hudson-2", 0}, 127 {0x78011022, 0x00, "AMD Hudson-2", 0}, 128 {0x78021022, 0x00, "AMD Hudson-2", 0}, 129 {0x78031022, 0x00, "AMD Hudson-2", 0}, 130 {0x78041022, 0x00, "AMD Hudson-2", 0}, 131 {0x06121b21, 0x00, "ASMedia ASM1061", 0}, 132 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE}, 133 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE}, 134 {0x26818086, 0x00, "Intel ESB2", 0}, 135 {0x26828086, 0x00, "Intel ESB2", 0}, 136 {0x26838086, 0x00, "Intel ESB2", 0}, 137 {0x27c18086, 0x00, "Intel ICH7", 0}, 138 {0x27c38086, 0x00, "Intel ICH7", 0}, 139 {0x27c58086, 0x00, "Intel ICH7M", 0}, 140 {0x27c68086, 0x00, "Intel ICH7M", 0}, 141 {0x28218086, 0x00, "Intel ICH8", 0}, 142 {0x28228086, 0x00, "Intel ICH8", 0}, 143 {0x28248086, 0x00, "Intel ICH8", 0}, 144 {0x28298086, 0x00, "Intel ICH8M", 0}, 145 {0x282a8086, 0x00, "Intel ICH8M", 0}, 146 {0x29228086, 0x00, "Intel ICH9", 0}, 147 {0x29238086, 0x00, "Intel ICH9", 0}, 148 {0x29248086, 0x00, "Intel ICH9", 0}, 149 {0x29258086, 0x00, "Intel ICH9", 0}, 150 {0x29278086, 0x00, "Intel ICH9", 0}, 151 {0x29298086, 0x00, "Intel ICH9M", 0}, 152 {0x292a8086, 0x00, "Intel ICH9M", 0}, 153 {0x292b8086, 0x00, "Intel ICH9M", 0}, 154 {0x292c8086, 0x00, "Intel ICH9M", 0}, 155 {0x292f8086, 0x00, "Intel ICH9M", 0}, 156 {0x294d8086, 0x00, "Intel ICH9", 0}, 157 {0x294e8086, 0x00, "Intel ICH9M", 0}, 158 {0x3a058086, 0x00, "Intel ICH10", 0}, 159 {0x3a228086, 0x00, "Intel ICH10", 0}, 160 {0x3a258086, 0x00, "Intel ICH10", 0}, 161 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0}, 162 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0}, 163 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0}, 164 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0}, 165 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0}, 166 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0}, 167 {0x1c028086, 0x00, "Intel Cougar Point", 0}, 168 {0x1c038086, 0x00, "Intel Cougar Point", 0}, 169 {0x1c048086, 0x00, "Intel Cougar Point", 0}, 170 {0x1c058086, 0x00, "Intel Cougar Point", 0}, 171 {0x1d028086, 0x00, "Intel Patsburg", 0}, 172 {0x1d048086, 0x00, "Intel Patsburg", 0}, 173 {0x1d068086, 0x00, "Intel Patsburg", 0}, 174 {0x28268086, 0x00, "Intel Patsburg (RAID)", 0}, 175 {0x1e028086, 0x00, "Intel Panther Point", 0}, 176 {0x1e038086, 0x00, "Intel Panther Point", 0}, 177 {0x1e048086, 0x00, "Intel Panther Point", 0}, 178 {0x1e058086, 0x00, "Intel Panther Point", 0}, 179 {0x1e068086, 0x00, "Intel Panther Point", 0}, 180 {0x1e078086, 0x00, "Intel Panther Point", 0}, 181 {0x1e0e8086, 0x00, "Intel Panther Point", 0}, 182 {0x1e0f8086, 0x00, "Intel Panther Point", 0}, 183 {0x8c028086, 0x00, "Intel Lynx Point", 0}, 184 {0x8c038086, 0x00, "Intel Lynx Point", 0}, 185 {0x8c048086, 0x00, "Intel Lynx Point", 0}, 186 {0x8c058086, 0x00, "Intel Lynx Point", 0}, 187 {0x8c068086, 0x00, "Intel Lynx Point", 0}, 188 {0x8c078086, 0x00, "Intel Lynx Point", 0}, 189 {0x8c0e8086, 0x00, "Intel Lynx Point", 0}, 190 {0x8c0f8086, 0x00, "Intel Lynx Point", 0}, 191 {0x23238086, 0x00, "Intel DH89xxCC", 0}, 192 {0x2360197b, 0x00, "JMicron JMB360", 0}, 193 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE}, 194 {0x2362197b, 0x00, "JMicron JMB362", 0}, 195 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE}, 196 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE}, 197 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE}, 198 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE}, 199 {0x611111ab, 0x00, "Marvell 88SE6111", AHCI_Q_NOFORCE | AHCI_Q_1CH | 200 AHCI_Q_EDGEIS}, 201 {0x612111ab, 0x00, "Marvell 88SE6121", AHCI_Q_NOFORCE | AHCI_Q_2CH | 202 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 203 {0x614111ab, 0x00, "Marvell 88SE6141", AHCI_Q_NOFORCE | AHCI_Q_4CH | 204 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 205 {0x614511ab, 0x00, "Marvell 88SE6145", AHCI_Q_NOFORCE | AHCI_Q_4CH | 206 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 207 {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_NOBSYRES}, 208 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 209 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES}, 210 {0x91251b4b, 0x00, "Marvell 88SE9125", AHCI_Q_NOBSYRES}, 211 {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 212 {0x91301b4b, 0x00, "Marvell 88SE9130", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 213 {0x91721b4b, 0x00, "Marvell 88SE9172", AHCI_Q_NOBSYRES}, 214 {0x91821b4b, 0x00, "Marvell 88SE9182", AHCI_Q_NOBSYRES}, 215 {0x92201b4b, 0x00, "Marvell 88SE9220", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 216 {0x92301b4b, 0x00, "Marvell 88SE9230", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 217 {0x92351b4b, 0x00, "Marvell 88SE9235", AHCI_Q_NOBSYRES}, 218 {0x06201103, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 219 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 220 {0x06221103, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 221 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 222 {0x06401103, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 223 {0x06401b4b, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 224 {0x06441103, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 225 {0x06441b4b, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 226 {0x06411103, 0x00, "HighPoint RocketRAID 640L", AHCI_Q_NOBSYRES}, 227 {0x06421103, 0x00, "HighPoint RocketRAID 642L", AHCI_Q_NOBSYRES}, 228 {0x06451103, 0x00, "HighPoint RocketRAID 644L", AHCI_Q_NOBSYRES}, 229 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 230 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 231 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 232 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 233 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 234 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 235 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 236 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 237 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 238 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 239 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 240 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 241 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 242 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 243 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 244 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 245 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 246 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 247 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 248 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 249 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 250 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 251 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 252 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 253 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 254 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 255 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 256 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 257 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 258 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 259 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 260 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 261 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 262 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 263 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 264 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 265 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 266 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 267 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 268 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 269 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 270 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 271 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 272 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 273 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 274 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 275 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 276 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 277 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 278 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 279 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 280 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 281 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 282 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 283 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 284 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 285 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 286 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 287 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA}, 288 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 289 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 290 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 291 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 292 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 293 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 294 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 295 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 296 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 297 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 298 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 299 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 300 {0x11841039, 0x00, "SiS 966", 0}, 301 {0x11851039, 0x00, "SiS 968", 0}, 302 {0x01861039, 0x00, "SiS 968", 0}, 303 {0x00000000, 0x00, NULL, 0} 304}; 305 306#define recovery_type spriv_field0 307#define RECOVERY_NONE 0 308#define RECOVERY_READ_LOG 1 309#define RECOVERY_REQUEST_SENSE 2 310#define recovery_slot spriv_field1 311 312static int force_ahci = 1; 313TUNABLE_INT("hw.ahci.force", &force_ahci); 314 315static int 316ahci_probe(device_t dev) 317{ 318 char buf[64]; 319 int i, valid = 0; 320 uint32_t devid = pci_get_devid(dev); 321 uint8_t revid = pci_get_revid(dev); 322 323 /* Is this a possible AHCI candidate? */ 324 if (pci_get_class(dev) == PCIC_STORAGE && 325 pci_get_subclass(dev) == PCIS_STORAGE_SATA && 326 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0) 327 valid = 1; 328 /* Is this a known AHCI chip? */ 329 for (i = 0; ahci_ids[i].id != 0; i++) { 330 if (ahci_ids[i].id == devid && 331 ahci_ids[i].rev <= revid && 332 (valid || (force_ahci == 1 && 333 !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) { 334 /* Do not attach JMicrons with single PCI function. */ 335 if (pci_get_vendor(dev) == 0x197b && 336 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0) 337 return (ENXIO); 338 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 339 ahci_ids[i].name); 340 device_set_desc_copy(dev, buf); 341 return (BUS_PROBE_VENDOR); 342 } 343 } 344 if (!valid) 345 return (ENXIO); 346 device_set_desc_copy(dev, "AHCI SATA controller"); 347 return (BUS_PROBE_VENDOR); 348} 349 350static int 351ahci_ata_probe(device_t dev) 352{ 353 char buf[64]; 354 int i; 355 uint32_t devid = pci_get_devid(dev); 356 uint8_t revid = pci_get_revid(dev); 357 358 if ((intptr_t)device_get_ivars(dev) >= 0) 359 return (ENXIO); 360 /* Is this a known AHCI chip? */ 361 for (i = 0; ahci_ids[i].id != 0; i++) { 362 if (ahci_ids[i].id == devid && 363 ahci_ids[i].rev <= revid) { 364 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 365 ahci_ids[i].name); 366 device_set_desc_copy(dev, buf); 367 return (BUS_PROBE_VENDOR); 368 } 369 } 370 device_set_desc_copy(dev, "AHCI SATA controller"); 371 return (BUS_PROBE_VENDOR); 372} 373 374static int 375ahci_attach(device_t dev) 376{ 377 struct ahci_controller *ctlr = device_get_softc(dev); 378 device_t child; 379 int error, unit, speed, i; 380 uint32_t devid = pci_get_devid(dev); 381 uint8_t revid = pci_get_revid(dev); 382 u_int32_t version; 383 384 ctlr->dev = dev; 385 i = 0; 386 while (ahci_ids[i].id != 0 && 387 (ahci_ids[i].id != devid || 388 ahci_ids[i].rev > revid)) 389 i++; 390 ctlr->quirks = ahci_ids[i].quirks; 391 resource_int_value(device_get_name(dev), 392 device_get_unit(dev), "ccc", &ctlr->ccc); 393 /* if we have a memory BAR(5) we are likely on an AHCI part */ 394 ctlr->r_rid = PCIR_BAR(5); 395 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 396 &ctlr->r_rid, RF_ACTIVE))) 397 return ENXIO; 398 /* Setup our own memory management for channels. */ 399 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 400 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 401 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 402 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 403 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 404 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 405 return (error); 406 } 407 if ((error = rman_manage_region(&ctlr->sc_iomem, 408 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 409 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 410 rman_fini(&ctlr->sc_iomem); 411 return (error); 412 } 413 pci_enable_busmaster(dev); 414 /* Reset controller */ 415 if ((error = ahci_ctlr_reset(dev)) != 0) { 416 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 417 rman_fini(&ctlr->sc_iomem); 418 return (error); 419 }; 420 /* Get the HW capabilities */ 421 version = ATA_INL(ctlr->r_mem, AHCI_VS); 422 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 423 if (version >= 0x00010200) 424 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 425 if (ctlr->caps & AHCI_CAP_EMS) 426 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 427 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 428 429 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */ 430 if ((ctlr->quirks & AHCI_Q_NOBSYRES) && 431 (ctlr->quirks & AHCI_Q_ALTSIG) && 432 (ctlr->caps & AHCI_CAP_SPM) == 0) 433 ctlr->quirks &= ~AHCI_Q_NOBSYRES; 434 435 if (ctlr->quirks & AHCI_Q_1CH) { 436 ctlr->caps &= ~AHCI_CAP_NPMASK; 437 ctlr->ichannels &= 0x01; 438 } 439 if (ctlr->quirks & AHCI_Q_2CH) { 440 ctlr->caps &= ~AHCI_CAP_NPMASK; 441 ctlr->caps |= 1; 442 ctlr->ichannels &= 0x03; 443 } 444 if (ctlr->quirks & AHCI_Q_4CH) { 445 ctlr->caps &= ~AHCI_CAP_NPMASK; 446 ctlr->caps |= 3; 447 ctlr->ichannels &= 0x0f; 448 } 449 ctlr->channels = MAX(flsl(ctlr->ichannels), 450 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 451 if (ctlr->quirks & AHCI_Q_NOPMP) 452 ctlr->caps &= ~AHCI_CAP_SPM; 453 if (ctlr->quirks & AHCI_Q_NONCQ) 454 ctlr->caps &= ~AHCI_CAP_SNCQ; 455 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 456 ctlr->ccc = 0; 457 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC); 458 459 /* Create controller-wide DMA tag. */ 460 if (bus_dma_tag_create(bus_get_dma_tag(dev), 0, 0, 461 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR : 462 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 463 BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, 464 0, NULL, NULL, &ctlr->dma_tag)) { 465 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, 466 ctlr->r_mem); 467 rman_fini(&ctlr->sc_iomem); 468 return ENXIO; 469 } 470 471 ahci_ctlr_setup(dev); 472 /* Setup interrupts. */ 473 if (ahci_setup_interrupt(dev)) { 474 bus_dma_tag_destroy(ctlr->dma_tag); 475 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 476 rman_fini(&ctlr->sc_iomem); 477 return ENXIO; 478 } 479 /* Announce HW capabilities. */ 480 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 481 device_printf(dev, 482 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 483 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 484 ((version >> 4) & 0xf0) + (version & 0x0f), 485 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 486 ((speed == 1) ? "1.5":((speed == 2) ? "3": 487 ((speed == 3) ? "6":"?"))), 488 (ctlr->caps & AHCI_CAP_SPM) ? 489 "supported" : "not supported", 490 (ctlr->caps & AHCI_CAP_FBSS) ? 491 " with FBS" : ""); 492 if (bootverbose) { 493 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 494 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 495 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 496 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 497 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 498 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 499 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 500 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 501 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 502 ((speed == 1) ? "1.5":((speed == 2) ? "3": 503 ((speed == 3) ? "6":"?")))); 504 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 505 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 506 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 507 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 508 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 509 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 510 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 511 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 512 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 513 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 514 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 515 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 516 } 517 if (bootverbose && version >= 0x00010200) { 518 device_printf(dev, "Caps2:%s%s%s\n", 519 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 520 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 521 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 522 } 523 /* Attach all channels on this controller */ 524 for (unit = 0; unit < ctlr->channels; unit++) { 525 child = device_add_child(dev, "ahcich", -1); 526 if (child == NULL) { 527 device_printf(dev, "failed to add channel device\n"); 528 continue; 529 } 530 device_set_ivars(child, (void *)(intptr_t)unit); 531 if ((ctlr->ichannels & (1 << unit)) == 0) 532 device_disable(child); 533 } 534 if (ctlr->caps & AHCI_CAP_EMS) { 535 child = device_add_child(dev, "ahciem", -1); 536 if (child == NULL) 537 device_printf(dev, "failed to add enclosure device\n"); 538 else 539 device_set_ivars(child, (void *)(intptr_t)-1); 540 } 541 bus_generic_attach(dev); 542 return 0; 543} 544 545static int 546ahci_detach(device_t dev) 547{ 548 struct ahci_controller *ctlr = device_get_softc(dev); 549 int i; 550 551 /* Detach & delete all children */ 552 device_delete_children(dev); 553 554 /* Free interrupts. */ 555 for (i = 0; i < ctlr->numirqs; i++) { 556 if (ctlr->irqs[i].r_irq) { 557 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 558 ctlr->irqs[i].handle); 559 bus_release_resource(dev, SYS_RES_IRQ, 560 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 561 } 562 } 563 pci_release_msi(dev); 564 bus_dma_tag_destroy(ctlr->dma_tag); 565 /* Free memory. */ 566 rman_fini(&ctlr->sc_iomem); 567 if (ctlr->r_mem) 568 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 569 return (0); 570} 571 572static int 573ahci_ctlr_reset(device_t dev) 574{ 575 struct ahci_controller *ctlr = device_get_softc(dev); 576 int timeout; 577 578 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == 0x28298086 && 579 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 580 pci_write_config(dev, 0x92, 0x01, 1); 581 /* Enable AHCI mode */ 582 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 583 /* Reset AHCI controller */ 584 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 585 for (timeout = 1000; timeout > 0; timeout--) { 586 DELAY(1000); 587 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 588 break; 589 } 590 if (timeout == 0) { 591 device_printf(dev, "AHCI controller reset failure\n"); 592 return ENXIO; 593 } 594 /* Reenable AHCI mode */ 595 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 596 return (0); 597} 598 599static int 600ahci_ctlr_setup(device_t dev) 601{ 602 struct ahci_controller *ctlr = device_get_softc(dev); 603 /* Clear interrupts */ 604 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 605 /* Configure CCC */ 606 if (ctlr->ccc) { 607 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 608 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 609 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 610 (4 << AHCI_CCCC_CC_SHIFT) | 611 AHCI_CCCC_EN); 612 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 613 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 614 if (bootverbose) { 615 device_printf(dev, 616 "CCC with %dms/4cmd enabled on vector %d\n", 617 ctlr->ccc, ctlr->cccv); 618 } 619 } 620 /* Enable AHCI interrupts */ 621 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 622 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 623 return (0); 624} 625 626static int 627ahci_suspend(device_t dev) 628{ 629 struct ahci_controller *ctlr = device_get_softc(dev); 630 631 bus_generic_suspend(dev); 632 /* Disable interupts, so the state change(s) doesn't trigger */ 633 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 634 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 635 return 0; 636} 637 638static int 639ahci_resume(device_t dev) 640{ 641 int res; 642 643 if ((res = ahci_ctlr_reset(dev)) != 0) 644 return (res); 645 ahci_ctlr_setup(dev); 646 return (bus_generic_resume(dev)); 647} 648 649static int 650ahci_setup_interrupt(device_t dev) 651{ 652 struct ahci_controller *ctlr = device_get_softc(dev); 653 int i, msi = 1; 654 655 /* Process hints. */ 656 if (ctlr->quirks & AHCI_Q_NOMSI) 657 msi = 0; 658 resource_int_value(device_get_name(dev), 659 device_get_unit(dev), "msi", &msi); 660 if (msi < 0) 661 msi = 0; 662 else if (msi == 1) 663 msi = min(1, pci_msi_count(dev)); 664 else if (msi > 1) 665 msi = pci_msi_count(dev); 666 /* Allocate MSI if needed/present. */ 667 if (msi && pci_alloc_msi(dev, &msi) == 0) { 668 ctlr->numirqs = msi; 669 } else { 670 msi = 0; 671 ctlr->numirqs = 1; 672 } 673 /* Check for single MSI vector fallback. */ 674 if (ctlr->numirqs > 1 && 675 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 676 device_printf(dev, "Falling back to one MSI\n"); 677 ctlr->numirqs = 1; 678 } 679 /* Allocate all IRQs. */ 680 for (i = 0; i < ctlr->numirqs; i++) { 681 ctlr->irqs[i].ctlr = ctlr; 682 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0); 683 if (ctlr->numirqs == 1 || i >= ctlr->channels || 684 (ctlr->ccc && i == ctlr->cccv)) 685 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 686 else if (i == ctlr->numirqs - 1) 687 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 688 else 689 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 690 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 691 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 692 device_printf(dev, "unable to map interrupt\n"); 693 return ENXIO; 694 } 695 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 696 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr, 697 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 698 /* SOS XXX release r_irq */ 699 device_printf(dev, "unable to setup interrupt\n"); 700 return ENXIO; 701 } 702 if (ctlr->numirqs > 1) { 703 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 704 ctlr->irqs[i].handle, 705 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 706 "ch%d" : "%d", i); 707 } 708 } 709 return (0); 710} 711 712/* 713 * Common case interrupt handler. 714 */ 715static void 716ahci_intr(void *data) 717{ 718 struct ahci_controller_irq *irq = data; 719 struct ahci_controller *ctlr = irq->ctlr; 720 u_int32_t is, ise = 0; 721 void *arg; 722 int unit; 723 724 if (irq->mode == AHCI_IRQ_MODE_ALL) { 725 unit = 0; 726 if (ctlr->ccc) 727 is = ctlr->ichannels; 728 else 729 is = ATA_INL(ctlr->r_mem, AHCI_IS); 730 } else { /* AHCI_IRQ_MODE_AFTER */ 731 unit = irq->r_irq_rid - 1; 732 is = ATA_INL(ctlr->r_mem, AHCI_IS); 733 } 734 /* CCC interrupt is edge triggered. */ 735 if (ctlr->ccc) 736 ise = 1 << ctlr->cccv; 737 /* Some controllers have edge triggered IS. */ 738 if (ctlr->quirks & AHCI_Q_EDGEIS) 739 ise |= is; 740 if (ise != 0) 741 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 742 for (; unit < ctlr->channels; unit++) { 743 if ((is & (1 << unit)) != 0 && 744 (arg = ctlr->interrupt[unit].argument)) { 745 ctlr->interrupt[unit].function(arg); 746 } 747 } 748 /* AHCI declares level triggered IS. */ 749 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 750 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 751} 752 753/* 754 * Simplified interrupt handler for multivector MSI mode. 755 */ 756static void 757ahci_intr_one(void *data) 758{ 759 struct ahci_controller_irq *irq = data; 760 struct ahci_controller *ctlr = irq->ctlr; 761 void *arg; 762 int unit; 763 764 unit = irq->r_irq_rid - 1; 765 /* Some controllers have edge triggered IS. */ 766 if (ctlr->quirks & AHCI_Q_EDGEIS) 767 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 768 if ((arg = ctlr->interrupt[unit].argument)) 769 ctlr->interrupt[unit].function(arg); 770 /* AHCI declares level triggered IS. */ 771 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 772 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 773} 774 775static struct resource * 776ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 777 u_long start, u_long end, u_long count, u_int flags) 778{ 779 struct ahci_controller *ctlr = device_get_softc(dev); 780 struct resource *res; 781 long st; 782 int offset, size, unit; 783 784 unit = (intptr_t)device_get_ivars(child); 785 res = NULL; 786 switch (type) { 787 case SYS_RES_MEMORY: 788 if (unit >= 0) { 789 offset = AHCI_OFFSET + (unit << 7); 790 size = 128; 791 } else if (*rid == 0) { 792 offset = AHCI_EM_CTL; 793 size = 4; 794 } else { 795 offset = (ctlr->emloc & 0xffff0000) >> 14; 796 size = (ctlr->emloc & 0x0000ffff) << 2; 797 if (*rid != 1) { 798 if (*rid == 2 && (ctlr->capsem & 799 (AHCI_EM_XMT | AHCI_EM_SMB)) == 0) 800 offset += size; 801 else 802 break; 803 } 804 } 805 st = rman_get_start(ctlr->r_mem); 806 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 807 st + offset + size - 1, size, RF_ACTIVE, child); 808 if (res) { 809 bus_space_handle_t bsh; 810 bus_space_tag_t bst; 811 bsh = rman_get_bushandle(ctlr->r_mem); 812 bst = rman_get_bustag(ctlr->r_mem); 813 bus_space_subregion(bst, bsh, offset, 128, &bsh); 814 rman_set_bushandle(res, bsh); 815 rman_set_bustag(res, bst); 816 } 817 break; 818 case SYS_RES_IRQ: 819 if (*rid == ATA_IRQ_RID) 820 res = ctlr->irqs[0].r_irq; 821 break; 822 } 823 return (res); 824} 825 826static int 827ahci_release_resource(device_t dev, device_t child, int type, int rid, 828 struct resource *r) 829{ 830 831 switch (type) { 832 case SYS_RES_MEMORY: 833 rman_release_resource(r); 834 return (0); 835 case SYS_RES_IRQ: 836 if (rid != ATA_IRQ_RID) 837 return ENOENT; 838 return (0); 839 } 840 return (EINVAL); 841} 842 843static int 844ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 845 int flags, driver_filter_t *filter, driver_intr_t *function, 846 void *argument, void **cookiep) 847{ 848 struct ahci_controller *ctlr = device_get_softc(dev); 849 int unit = (intptr_t)device_get_ivars(child); 850 851 if (filter != NULL) { 852 printf("ahci.c: we cannot use a filter here\n"); 853 return (EINVAL); 854 } 855 ctlr->interrupt[unit].function = function; 856 ctlr->interrupt[unit].argument = argument; 857 return (0); 858} 859 860static int 861ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 862 void *cookie) 863{ 864 struct ahci_controller *ctlr = device_get_softc(dev); 865 int unit = (intptr_t)device_get_ivars(child); 866 867 ctlr->interrupt[unit].function = NULL; 868 ctlr->interrupt[unit].argument = NULL; 869 return (0); 870} 871 872static int 873ahci_print_child(device_t dev, device_t child) 874{ 875 int retval, channel; 876 877 retval = bus_print_child_header(dev, child); 878 channel = (int)(intptr_t)device_get_ivars(child); 879 if (channel >= 0) 880 retval += printf(" at channel %d", channel); 881 retval += bus_print_child_footer(dev, child); 882 return (retval); 883} 884 885static int 886ahci_child_location_str(device_t dev, device_t child, char *buf, 887 size_t buflen) 888{ 889 int channel; 890 891 channel = (int)(intptr_t)device_get_ivars(child); 892 if (channel >= 0) 893 snprintf(buf, buflen, "channel=%d", channel); 894 return (0); 895} 896 897static bus_dma_tag_t 898ahci_get_dma_tag(device_t dev, device_t child) 899{ 900 struct ahci_controller *ctlr = device_get_softc(dev); 901 902 return (ctlr->dma_tag); 903} 904 905devclass_t ahci_devclass; 906static device_method_t ahci_methods[] = { 907 DEVMETHOD(device_probe, ahci_probe), 908 DEVMETHOD(device_attach, ahci_attach), 909 DEVMETHOD(device_detach, ahci_detach), 910 DEVMETHOD(device_suspend, ahci_suspend), 911 DEVMETHOD(device_resume, ahci_resume), 912 DEVMETHOD(bus_print_child, ahci_print_child), 913 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 914 DEVMETHOD(bus_release_resource, ahci_release_resource), 915 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 916 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 917 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 918 DEVMETHOD(bus_get_dma_tag, ahci_get_dma_tag), 919 { 0, 0 } 920}; 921static driver_t ahci_driver = { 922 "ahci", 923 ahci_methods, 924 sizeof(struct ahci_controller) 925}; 926DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 927static device_method_t ahci_ata_methods[] = { 928 DEVMETHOD(device_probe, ahci_ata_probe), 929 DEVMETHOD(device_attach, ahci_attach), 930 DEVMETHOD(device_detach, ahci_detach), 931 DEVMETHOD(device_suspend, ahci_suspend), 932 DEVMETHOD(device_resume, ahci_resume), 933 DEVMETHOD(bus_print_child, ahci_print_child), 934 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 935 DEVMETHOD(bus_release_resource, ahci_release_resource), 936 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 937 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 938 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 939 { 0, 0 } 940}; 941static driver_t ahci_ata_driver = { 942 "ahci", 943 ahci_ata_methods, 944 sizeof(struct ahci_controller) 945}; 946DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0); 947MODULE_VERSION(ahci, 1); 948MODULE_DEPEND(ahci, cam, 1, 1, 1); 949 950static int 951ahci_ch_probe(device_t dev) 952{ 953 954 device_set_desc_copy(dev, "AHCI channel"); 955 return (0); 956} 957 958static int 959ahci_ch_attach(device_t dev) 960{ 961 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 962 struct ahci_channel *ch = device_get_softc(dev); 963 struct cam_devq *devq; 964 int rid, error, i, sata_rev = 0; 965 u_int32_t version; 966 967 ch->dev = dev; 968 ch->unit = (intptr_t)device_get_ivars(dev); 969 ch->caps = ctlr->caps; 970 ch->caps2 = ctlr->caps2; 971 ch->quirks = ctlr->quirks; 972 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 973 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 974 resource_int_value(device_get_name(dev), 975 device_get_unit(dev), "pm_level", &ch->pm_level); 976 if (ch->pm_level > 3) 977 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 978 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 979 /* Limit speed for my onboard JMicron external port. 980 * It is not eSATA really. */ 981 if (pci_get_devid(ctlr->dev) == 0x2363197b && 982 pci_get_subvendor(ctlr->dev) == 0x1043 && 983 pci_get_subdevice(ctlr->dev) == 0x81e4 && 984 ch->unit == 0) 985 sata_rev = 1; 986 if (ch->quirks & AHCI_Q_SATA2) 987 sata_rev = 2; 988 resource_int_value(device_get_name(dev), 989 device_get_unit(dev), "sata_rev", &sata_rev); 990 for (i = 0; i < 16; i++) { 991 ch->user[i].revision = sata_rev; 992 ch->user[i].mode = 0; 993 ch->user[i].bytecount = 8192; 994 ch->user[i].tags = ch->numslots; 995 ch->user[i].caps = 0; 996 ch->curr[i] = ch->user[i]; 997 if (ch->pm_level) { 998 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 999 CTS_SATA_CAPS_H_APST | 1000 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 1001 } 1002 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA | 1003 CTS_SATA_CAPS_H_AN; 1004 } 1005 rid = 0; 1006 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1007 &rid, RF_ACTIVE))) 1008 return (ENXIO); 1009 ahci_dmainit(dev); 1010 ahci_slotsalloc(dev); 1011 ahci_ch_init(dev); 1012 mtx_lock(&ch->mtx); 1013 rid = ATA_IRQ_RID; 1014 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1015 &rid, RF_SHAREABLE | RF_ACTIVE))) { 1016 device_printf(dev, "Unable to map interrupt\n"); 1017 error = ENXIO; 1018 goto err0; 1019 } 1020 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 1021 ahci_ch_intr_locked, dev, &ch->ih))) { 1022 device_printf(dev, "Unable to setup interrupt\n"); 1023 error = ENXIO; 1024 goto err1; 1025 } 1026 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 1027 version = ATA_INL(ctlr->r_mem, AHCI_VS); 1028 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS)) 1029 ch->chcaps |= AHCI_P_CMD_FBSCP; 1030 if (bootverbose) { 1031 device_printf(dev, "Caps:%s%s%s%s%s\n", 1032 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 1033 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 1034 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 1035 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 1036 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":""); 1037 } 1038 /* Create the device queue for our SIM. */ 1039 devq = cam_simq_alloc(ch->numslots); 1040 if (devq == NULL) { 1041 device_printf(dev, "Unable to allocate simq\n"); 1042 error = ENOMEM; 1043 goto err1; 1044 } 1045 /* Construct SIM entry */ 1046 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 1047 device_get_unit(dev), &ch->mtx, 1048 min(2, ch->numslots), 1049 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 1050 devq); 1051 if (ch->sim == NULL) { 1052 cam_simq_free(devq); 1053 device_printf(dev, "unable to allocate sim\n"); 1054 error = ENOMEM; 1055 goto err1; 1056 } 1057 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 1058 device_printf(dev, "unable to register xpt bus\n"); 1059 error = ENXIO; 1060 goto err2; 1061 } 1062 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 1063 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1064 device_printf(dev, "unable to create path\n"); 1065 error = ENXIO; 1066 goto err3; 1067 } 1068 if (ch->pm_level > 3) { 1069 callout_reset(&ch->pm_timer, 1070 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 1071 ahci_ch_pm, dev); 1072 } 1073 mtx_unlock(&ch->mtx); 1074 return (0); 1075 1076err3: 1077 xpt_bus_deregister(cam_sim_path(ch->sim)); 1078err2: 1079 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1080err1: 1081 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1082err0: 1083 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1084 mtx_unlock(&ch->mtx); 1085 mtx_destroy(&ch->mtx); 1086 return (error); 1087} 1088 1089static int 1090ahci_ch_detach(device_t dev) 1091{ 1092 struct ahci_channel *ch = device_get_softc(dev); 1093 1094 mtx_lock(&ch->mtx); 1095 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 1096 /* Forget about reset. */ 1097 if (ch->resetting) { 1098 ch->resetting = 0; 1099 xpt_release_simq(ch->sim, TRUE); 1100 } 1101 xpt_free_path(ch->path); 1102 xpt_bus_deregister(cam_sim_path(ch->sim)); 1103 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1104 mtx_unlock(&ch->mtx); 1105 1106 if (ch->pm_level > 3) 1107 callout_drain(&ch->pm_timer); 1108 callout_drain(&ch->reset_timer); 1109 bus_teardown_intr(dev, ch->r_irq, ch->ih); 1110 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1111 1112 ahci_ch_deinit(dev); 1113 ahci_slotsfree(dev); 1114 ahci_dmafini(dev); 1115 1116 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1117 mtx_destroy(&ch->mtx); 1118 return (0); 1119} 1120 1121static int 1122ahci_ch_init(device_t dev) 1123{ 1124 struct ahci_channel *ch = device_get_softc(dev); 1125 uint64_t work; 1126 1127 /* Disable port interrupts */ 1128 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1129 /* Setup work areas */ 1130 work = ch->dma.work_bus + AHCI_CL_OFFSET; 1131 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 1132 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 1133 work = ch->dma.rfis_bus; 1134 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 1135 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 1136 /* Activate the channel and power/spin up device */ 1137 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 1138 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1139 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 1140 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 1141 ahci_start_fr(dev); 1142 ahci_start(dev, 1); 1143 return (0); 1144} 1145 1146static int 1147ahci_ch_deinit(device_t dev) 1148{ 1149 struct ahci_channel *ch = device_get_softc(dev); 1150 1151 /* Disable port interrupts. */ 1152 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1153 /* Reset command register. */ 1154 ahci_stop(dev); 1155 ahci_stop_fr(dev); 1156 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 1157 /* Allow everything, including partial and slumber modes. */ 1158 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 1159 /* Request slumber mode transition and give some time to get there. */ 1160 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 1161 DELAY(100); 1162 /* Disable PHY. */ 1163 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 1164 return (0); 1165} 1166 1167static int 1168ahci_ch_suspend(device_t dev) 1169{ 1170 struct ahci_channel *ch = device_get_softc(dev); 1171 1172 mtx_lock(&ch->mtx); 1173 xpt_freeze_simq(ch->sim, 1); 1174 /* Forget about reset. */ 1175 if (ch->resetting) { 1176 ch->resetting = 0; 1177 callout_stop(&ch->reset_timer); 1178 xpt_release_simq(ch->sim, TRUE); 1179 } 1180 while (ch->oslots) 1181 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 1182 ahci_ch_deinit(dev); 1183 mtx_unlock(&ch->mtx); 1184 return (0); 1185} 1186 1187static int 1188ahci_ch_resume(device_t dev) 1189{ 1190 struct ahci_channel *ch = device_get_softc(dev); 1191 1192 mtx_lock(&ch->mtx); 1193 ahci_ch_init(dev); 1194 ahci_reset(dev); 1195 xpt_release_simq(ch->sim, TRUE); 1196 mtx_unlock(&ch->mtx); 1197 return (0); 1198} 1199 1200devclass_t ahcich_devclass; 1201static device_method_t ahcich_methods[] = { 1202 DEVMETHOD(device_probe, ahci_ch_probe), 1203 DEVMETHOD(device_attach, ahci_ch_attach), 1204 DEVMETHOD(device_detach, ahci_ch_detach), 1205 DEVMETHOD(device_suspend, ahci_ch_suspend), 1206 DEVMETHOD(device_resume, ahci_ch_resume), 1207 { 0, 0 } 1208}; 1209static driver_t ahcich_driver = { 1210 "ahcich", 1211 ahcich_methods, 1212 sizeof(struct ahci_channel) 1213}; 1214DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0); 1215 1216struct ahci_dc_cb_args { 1217 bus_addr_t maddr; 1218 int error; 1219}; 1220 1221static void 1222ahci_dmainit(device_t dev) 1223{ 1224 struct ahci_channel *ch = device_get_softc(dev); 1225 struct ahci_dc_cb_args dcba; 1226 size_t rfsize; 1227 1228 /* Command area. */ 1229 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1230 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1231 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1232 0, NULL, NULL, &ch->dma.work_tag)) 1233 goto error; 1234 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 1235 BUS_DMA_ZERO, &ch->dma.work_map)) 1236 goto error; 1237 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1238 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1239 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1240 goto error; 1241 } 1242 ch->dma.work_bus = dcba.maddr; 1243 /* FIS receive area. */ 1244 if (ch->chcaps & AHCI_P_CMD_FBSCP) 1245 rfsize = 4096; 1246 else 1247 rfsize = 256; 1248 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 1249 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1250 NULL, NULL, rfsize, 1, rfsize, 1251 0, NULL, NULL, &ch->dma.rfis_tag)) 1252 goto error; 1253 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1254 &ch->dma.rfis_map)) 1255 goto error; 1256 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1257 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1258 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1259 goto error; 1260 } 1261 ch->dma.rfis_bus = dcba.maddr; 1262 /* Data area. */ 1263 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1264 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1265 NULL, NULL, 1266 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1267 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1268 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 1269 goto error; 1270 } 1271 return; 1272 1273error: 1274 device_printf(dev, "WARNING - DMA initialization failed\n"); 1275 ahci_dmafini(dev); 1276} 1277 1278static void 1279ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1280{ 1281 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1282 1283 if (!(dcba->error = error)) 1284 dcba->maddr = segs[0].ds_addr; 1285} 1286 1287static void 1288ahci_dmafini(device_t dev) 1289{ 1290 struct ahci_channel *ch = device_get_softc(dev); 1291 1292 if (ch->dma.data_tag) { 1293 bus_dma_tag_destroy(ch->dma.data_tag); 1294 ch->dma.data_tag = NULL; 1295 } 1296 if (ch->dma.rfis_bus) { 1297 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1298 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1299 ch->dma.rfis_bus = 0; 1300 ch->dma.rfis_map = NULL; 1301 ch->dma.rfis = NULL; 1302 } 1303 if (ch->dma.work_bus) { 1304 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1305 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1306 ch->dma.work_bus = 0; 1307 ch->dma.work_map = NULL; 1308 ch->dma.work = NULL; 1309 } 1310 if (ch->dma.work_tag) { 1311 bus_dma_tag_destroy(ch->dma.work_tag); 1312 ch->dma.work_tag = NULL; 1313 } 1314} 1315 1316static void 1317ahci_slotsalloc(device_t dev) 1318{ 1319 struct ahci_channel *ch = device_get_softc(dev); 1320 int i; 1321 1322 /* Alloc and setup command/dma slots */ 1323 bzero(ch->slot, sizeof(ch->slot)); 1324 for (i = 0; i < ch->numslots; i++) { 1325 struct ahci_slot *slot = &ch->slot[i]; 1326 1327 slot->dev = dev; 1328 slot->slot = i; 1329 slot->state = AHCI_SLOT_EMPTY; 1330 slot->ccb = NULL; 1331 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1332 1333 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1334 device_printf(ch->dev, "FAILURE - create data_map\n"); 1335 } 1336} 1337 1338static void 1339ahci_slotsfree(device_t dev) 1340{ 1341 struct ahci_channel *ch = device_get_softc(dev); 1342 int i; 1343 1344 /* Free all dma slots */ 1345 for (i = 0; i < ch->numslots; i++) { 1346 struct ahci_slot *slot = &ch->slot[i]; 1347 1348 callout_drain(&slot->timeout); 1349 if (slot->dma.data_map) { 1350 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1351 slot->dma.data_map = NULL; 1352 } 1353 } 1354} 1355 1356static int 1357ahci_phy_check_events(device_t dev, u_int32_t serr) 1358{ 1359 struct ahci_channel *ch = device_get_softc(dev); 1360 1361 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 1362 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) { 1363 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1364 union ccb *ccb; 1365 1366 if (bootverbose) { 1367 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 1368 device_printf(dev, "CONNECT requested\n"); 1369 else 1370 device_printf(dev, "DISCONNECT requested\n"); 1371 } 1372 ahci_reset(dev); 1373 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1374 return (0); 1375 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1376 cam_sim_path(ch->sim), 1377 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1378 xpt_free_ccb(ccb); 1379 return (0); 1380 } 1381 xpt_rescan(ccb); 1382 return (1); 1383 } 1384 return (0); 1385} 1386 1387static void 1388ahci_cpd_check_events(device_t dev) 1389{ 1390 struct ahci_channel *ch = device_get_softc(dev); 1391 u_int32_t status; 1392 union ccb *ccb; 1393 1394 if (ch->pm_level == 0) 1395 return; 1396 1397 status = ATA_INL(ch->r_mem, AHCI_P_CMD); 1398 if ((status & AHCI_P_CMD_CPD) == 0) 1399 return; 1400 1401 if (bootverbose) { 1402 if (status & AHCI_P_CMD_CPS) { 1403 device_printf(dev, "COLD CONNECT requested\n"); 1404 } else 1405 device_printf(dev, "COLD DISCONNECT requested\n"); 1406 } 1407 ahci_reset(dev); 1408 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1409 return; 1410 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim), 1411 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1412 xpt_free_ccb(ccb); 1413 return; 1414 } 1415 xpt_rescan(ccb); 1416} 1417 1418static void 1419ahci_notify_events(device_t dev, u_int32_t status) 1420{ 1421 struct ahci_channel *ch = device_get_softc(dev); 1422 struct cam_path *dpath; 1423 int i; 1424 1425 if (ch->caps & AHCI_CAP_SSNTF) 1426 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1427 if (bootverbose) 1428 device_printf(dev, "SNTF 0x%04x\n", status); 1429 for (i = 0; i < 16; i++) { 1430 if ((status & (1 << i)) == 0) 1431 continue; 1432 if (xpt_create_path(&dpath, NULL, 1433 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1434 xpt_async(AC_SCSI_AEN, dpath, NULL); 1435 xpt_free_path(dpath); 1436 } 1437 } 1438} 1439 1440static void 1441ahci_ch_intr_locked(void *data) 1442{ 1443 device_t dev = (device_t)data; 1444 struct ahci_channel *ch = device_get_softc(dev); 1445 1446 mtx_lock(&ch->mtx); 1447 xpt_batch_start(ch->sim); 1448 ahci_ch_intr(data); 1449 xpt_batch_done(ch->sim); 1450 mtx_unlock(&ch->mtx); 1451} 1452 1453static void 1454ahci_ch_pm(void *arg) 1455{ 1456 device_t dev = (device_t)arg; 1457 struct ahci_channel *ch = device_get_softc(dev); 1458 uint32_t work; 1459 1460 if (ch->numrslots != 0) 1461 return; 1462 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1463 if (ch->pm_level == 4) 1464 work |= AHCI_P_CMD_PARTIAL; 1465 else 1466 work |= AHCI_P_CMD_SLUMBER; 1467 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1468} 1469 1470static void 1471ahci_ch_intr(void *data) 1472{ 1473 device_t dev = (device_t)data; 1474 struct ahci_channel *ch = device_get_softc(dev); 1475 uint32_t istatus, cstatus, serr = 0, sntf = 0, ok, err; 1476 enum ahci_err_type et; 1477 int i, ccs, port, reset = 0; 1478 1479 /* Read and clear interrupt statuses. */ 1480 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1481 if (istatus == 0) 1482 return; 1483 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1484 /* Read command statuses. */ 1485 if (ch->numtslots != 0) 1486 cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1487 else 1488 cstatus = 0; 1489 if (ch->numrslots != ch->numtslots) 1490 cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI); 1491 /* Read SNTF in one of possible ways. */ 1492 if ((istatus & AHCI_P_IX_SDB) && 1493 (ch->pm_present || ch->curr[0].atapi != 0)) { 1494 if (ch->caps & AHCI_CAP_SSNTF) 1495 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1496 else if (ch->fbs_enabled) { 1497 u_int8_t *fis = ch->dma.rfis + 0x58; 1498 1499 for (i = 0; i < 16; i++) { 1500 if (fis[1] & 0x80) { 1501 fis[1] &= 0x7f; 1502 sntf |= 1 << i; 1503 } 1504 fis += 256; 1505 } 1506 } else { 1507 u_int8_t *fis = ch->dma.rfis + 0x58; 1508 1509 if (fis[1] & 0x80) 1510 sntf = (1 << (fis[1] & 0x0f)); 1511 } 1512 } 1513 /* Process PHY events */ 1514 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1515 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1516 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1517 if (serr) { 1518 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1519 reset = ahci_phy_check_events(dev, serr); 1520 } 1521 } 1522 /* Process cold presence detection events */ 1523 if ((istatus & AHCI_P_IX_CPD) && !reset) 1524 ahci_cpd_check_events(dev); 1525 /* Process command errors */ 1526 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1527 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1528 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1529 >> AHCI_P_CMD_CCS_SHIFT; 1530//device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1531// __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1532// serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1533 port = -1; 1534 if (ch->fbs_enabled) { 1535 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1536 if (fbs & AHCI_P_FBS_SDE) { 1537 port = (fbs & AHCI_P_FBS_DWE) 1538 >> AHCI_P_FBS_DWE_SHIFT; 1539 } else { 1540 for (i = 0; i < 16; i++) { 1541 if (ch->numrslotspd[i] == 0) 1542 continue; 1543 if (port == -1) 1544 port = i; 1545 else if (port != i) { 1546 port = -2; 1547 break; 1548 } 1549 } 1550 } 1551 } 1552 err = ch->rslots & cstatus; 1553 } else { 1554 ccs = 0; 1555 err = 0; 1556 port = -1; 1557 } 1558 /* Complete all successfull commands. */ 1559 ok = ch->rslots & ~cstatus; 1560 for (i = 0; i < ch->numslots; i++) { 1561 if ((ok >> i) & 1) 1562 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1563 } 1564 /* On error, complete the rest of commands with error statuses. */ 1565 if (err) { 1566 if (ch->frozen) { 1567 union ccb *fccb = ch->frozen; 1568 ch->frozen = NULL; 1569 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1570 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1571 xpt_freeze_devq(fccb->ccb_h.path, 1); 1572 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1573 } 1574 xpt_done(fccb); 1575 } 1576 for (i = 0; i < ch->numslots; i++) { 1577 /* XXX: reqests in loading state. */ 1578 if (((err >> i) & 1) == 0) 1579 continue; 1580 if (port >= 0 && 1581 ch->slot[i].ccb->ccb_h.target_id != port) 1582 continue; 1583 if (istatus & AHCI_P_IX_TFE) { 1584 if (port != -2) { 1585 /* Task File Error */ 1586 if (ch->numtslotspd[ 1587 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1588 /* Untagged operation. */ 1589 if (i == ccs) 1590 et = AHCI_ERR_TFE; 1591 else 1592 et = AHCI_ERR_INNOCENT; 1593 } else { 1594 /* Tagged operation. */ 1595 et = AHCI_ERR_NCQ; 1596 } 1597 } else { 1598 et = AHCI_ERR_TFE; 1599 ch->fatalerr = 1; 1600 } 1601 } else if (istatus & AHCI_P_IX_IF) { 1602 if (ch->numtslots == 0 && i != ccs && port != -2) 1603 et = AHCI_ERR_INNOCENT; 1604 else 1605 et = AHCI_ERR_SATA; 1606 } else 1607 et = AHCI_ERR_INVALID; 1608 ahci_end_transaction(&ch->slot[i], et); 1609 } 1610 /* 1611 * We can't reinit port if there are some other 1612 * commands active, use resume to complete them. 1613 */ 1614 if (ch->rslots != 0 && !ch->recoverycmd) 1615 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1616 } 1617 /* Process NOTIFY events */ 1618 if (sntf) 1619 ahci_notify_events(dev, sntf); 1620} 1621 1622/* Must be called with channel locked. */ 1623static int 1624ahci_check_collision(device_t dev, union ccb *ccb) 1625{ 1626 struct ahci_channel *ch = device_get_softc(dev); 1627 int t = ccb->ccb_h.target_id; 1628 1629 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1630 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1631 /* Tagged command while we have no supported tag free. */ 1632 if (((~ch->oslots) & (0xffffffff >> (32 - 1633 ch->curr[t].tags))) == 0) 1634 return (1); 1635 /* If we have FBS */ 1636 if (ch->fbs_enabled) { 1637 /* Tagged command while untagged are active. */ 1638 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1639 return (1); 1640 } else { 1641 /* Tagged command while untagged are active. */ 1642 if (ch->numrslots != 0 && ch->numtslots == 0) 1643 return (1); 1644 /* Tagged command while tagged to other target is active. */ 1645 if (ch->numtslots != 0 && 1646 ch->taggedtarget != ccb->ccb_h.target_id) 1647 return (1); 1648 } 1649 } else { 1650 /* If we have FBS */ 1651 if (ch->fbs_enabled) { 1652 /* Untagged command while tagged are active. */ 1653 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1654 return (1); 1655 } else { 1656 /* Untagged command while tagged are active. */ 1657 if (ch->numrslots != 0 && ch->numtslots != 0) 1658 return (1); 1659 } 1660 } 1661 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1662 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1663 /* Atomic command while anything active. */ 1664 if (ch->numrslots != 0) 1665 return (1); 1666 } 1667 /* We have some atomic command running. */ 1668 if (ch->aslots != 0) 1669 return (1); 1670 return (0); 1671} 1672 1673/* Must be called with channel locked. */ 1674static void 1675ahci_begin_transaction(device_t dev, union ccb *ccb) 1676{ 1677 struct ahci_channel *ch = device_get_softc(dev); 1678 struct ahci_slot *slot; 1679 int tag, tags; 1680 1681 /* Choose empty slot. */ 1682 tags = ch->numslots; 1683 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1684 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1685 tags = ch->curr[ccb->ccb_h.target_id].tags; 1686 tag = ch->lastslot; 1687 while (1) { 1688 if (tag >= tags) 1689 tag = 0; 1690 if (ch->slot[tag].state == AHCI_SLOT_EMPTY) 1691 break; 1692 tag++; 1693 }; 1694 ch->lastslot = tag; 1695 /* Occupy chosen slot. */ 1696 slot = &ch->slot[tag]; 1697 slot->ccb = ccb; 1698 /* Stop PM timer. */ 1699 if (ch->numrslots == 0 && ch->pm_level > 3) 1700 callout_stop(&ch->pm_timer); 1701 /* Update channel stats. */ 1702 ch->oslots |= (1 << slot->slot); 1703 ch->numrslots++; 1704 ch->numrslotspd[ccb->ccb_h.target_id]++; 1705 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1706 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1707 ch->numtslots++; 1708 ch->numtslotspd[ccb->ccb_h.target_id]++; 1709 ch->taggedtarget = ccb->ccb_h.target_id; 1710 } 1711 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1712 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1713 ch->aslots |= (1 << slot->slot); 1714 slot->dma.nsegs = 0; 1715 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1716 slot->state = AHCI_SLOT_LOADING; 1717 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb, 1718 ahci_dmasetprd, slot, 0); 1719 } else 1720 ahci_execute_transaction(slot); 1721} 1722 1723/* Locked by busdma engine. */ 1724static void 1725ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1726{ 1727 struct ahci_slot *slot = arg; 1728 struct ahci_channel *ch = device_get_softc(slot->dev); 1729 struct ahci_cmd_tab *ctp; 1730 struct ahci_dma_prd *prd; 1731 int i; 1732 1733 if (error) { 1734 device_printf(slot->dev, "DMA load error\n"); 1735 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1736 return; 1737 } 1738 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1739 /* Get a piece of the workspace for this request */ 1740 ctp = (struct ahci_cmd_tab *) 1741 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1742 /* Fill S/G table */ 1743 prd = &ctp->prd_tab[0]; 1744 for (i = 0; i < nsegs; i++) { 1745 prd[i].dba = htole64(segs[i].ds_addr); 1746 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1747 } 1748 slot->dma.nsegs = nsegs; 1749 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1750 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1751 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1752 ahci_execute_transaction(slot); 1753} 1754 1755/* Must be called with channel locked. */ 1756static void 1757ahci_execute_transaction(struct ahci_slot *slot) 1758{ 1759 device_t dev = slot->dev; 1760 struct ahci_channel *ch = device_get_softc(dev); 1761 struct ahci_cmd_tab *ctp; 1762 struct ahci_cmd_list *clp; 1763 union ccb *ccb = slot->ccb; 1764 int port = ccb->ccb_h.target_id & 0x0f; 1765 int fis_size, i, softreset; 1766 uint8_t *fis = ch->dma.rfis + 0x40; 1767 uint8_t val; 1768 1769 /* Get a piece of the workspace for this request */ 1770 ctp = (struct ahci_cmd_tab *) 1771 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1772 /* Setup the FIS for this request */ 1773 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) { 1774 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1775 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1776 return; 1777 } 1778 /* Setup the command list entry */ 1779 clp = (struct ahci_cmd_list *) 1780 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1781 clp->cmd_flags = htole16( 1782 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1783 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1784 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1785 (fis_size / sizeof(u_int32_t)) | 1786 (port << 12)); 1787 clp->prd_length = htole16(slot->dma.nsegs); 1788 /* Special handling for Soft Reset command. */ 1789 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1790 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1791 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1792 softreset = 1; 1793 /* Kick controller into sane state */ 1794 ahci_stop(dev); 1795 ahci_clo(dev); 1796 ahci_start(dev, 0); 1797 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1798 } else { 1799 softreset = 2; 1800 /* Prepare FIS receive area for check. */ 1801 for (i = 0; i < 20; i++) 1802 fis[i] = 0xff; 1803 } 1804 } else 1805 softreset = 0; 1806 clp->bytecount = 0; 1807 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1808 (AHCI_CT_SIZE * slot->slot)); 1809 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1810 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1811 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1812 BUS_DMASYNC_PREREAD); 1813 /* Set ACTIVE bit for NCQ commands. */ 1814 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1815 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1816 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1817 } 1818 /* If FBS is enabled, set PMP port. */ 1819 if (ch->fbs_enabled) { 1820 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1821 (port << AHCI_P_FBS_DEV_SHIFT)); 1822 } 1823 /* Issue command to the controller. */ 1824 slot->state = AHCI_SLOT_RUNNING; 1825 ch->rslots |= (1 << slot->slot); 1826 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1827 /* Device reset commands doesn't interrupt. Poll them. */ 1828 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1829 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) { 1830 int count, timeout = ccb->ccb_h.timeout * 100; 1831 enum ahci_err_type et = AHCI_ERR_NONE; 1832 1833 for (count = 0; count < timeout; count++) { 1834 DELAY(10); 1835 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1836 break; 1837 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) && 1838 softreset != 1) { 1839#if 0 1840 device_printf(ch->dev, 1841 "Poll error on slot %d, TFD: %04x\n", 1842 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1843#endif 1844 et = AHCI_ERR_TFE; 1845 break; 1846 } 1847 /* Workaround for ATI SB600/SB700 chipsets. */ 1848 if (ccb->ccb_h.target_id == 15 && 1849 pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1850 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1851 et = AHCI_ERR_TIMEOUT; 1852 break; 1853 } 1854 } 1855 1856 /* Marvell controllers do not wait for readyness. */ 1857 if ((ch->quirks & AHCI_Q_NOBSYRES) && softreset == 2 && 1858 et == AHCI_ERR_NONE) { 1859 while ((val = fis[2]) & ATA_S_BUSY) { 1860 DELAY(10); 1861 if (count++ >= timeout) 1862 break; 1863 } 1864 } 1865 1866 if (timeout && (count >= timeout)) { 1867 device_printf(dev, "Poll timeout on slot %d port %d\n", 1868 slot->slot, port); 1869 device_printf(dev, "is %08x cs %08x ss %08x " 1870 "rs %08x tfd %02x serr %08x cmd %08x\n", 1871 ATA_INL(ch->r_mem, AHCI_P_IS), 1872 ATA_INL(ch->r_mem, AHCI_P_CI), 1873 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1874 ATA_INL(ch->r_mem, AHCI_P_TFD), 1875 ATA_INL(ch->r_mem, AHCI_P_SERR), 1876 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1877 et = AHCI_ERR_TIMEOUT; 1878 } 1879 1880 /* Kick controller into sane state and enable FBS. */ 1881 if (softreset == 2) 1882 ch->eslots |= (1 << slot->slot); 1883 ahci_end_transaction(slot, et); 1884 return; 1885 } 1886 /* Start command execution timeout */ 1887 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 1888 (timeout_t*)ahci_timeout, slot); 1889 return; 1890} 1891 1892/* Must be called with channel locked. */ 1893static void 1894ahci_process_timeout(device_t dev) 1895{ 1896 struct ahci_channel *ch = device_get_softc(dev); 1897 int i; 1898 1899 mtx_assert(&ch->mtx, MA_OWNED); 1900 /* Handle the rest of commands. */ 1901 for (i = 0; i < ch->numslots; i++) { 1902 /* Do we have a running request on slot? */ 1903 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1904 continue; 1905 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 1906 } 1907} 1908 1909/* Must be called with channel locked. */ 1910static void 1911ahci_rearm_timeout(device_t dev) 1912{ 1913 struct ahci_channel *ch = device_get_softc(dev); 1914 int i; 1915 1916 mtx_assert(&ch->mtx, MA_OWNED); 1917 for (i = 0; i < ch->numslots; i++) { 1918 struct ahci_slot *slot = &ch->slot[i]; 1919 1920 /* Do we have a running request on slot? */ 1921 if (slot->state < AHCI_SLOT_RUNNING) 1922 continue; 1923 if ((ch->toslots & (1 << i)) == 0) 1924 continue; 1925 callout_reset(&slot->timeout, 1926 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1927 (timeout_t*)ahci_timeout, slot); 1928 } 1929} 1930 1931/* Locked by callout mechanism. */ 1932static void 1933ahci_timeout(struct ahci_slot *slot) 1934{ 1935 device_t dev = slot->dev; 1936 struct ahci_channel *ch = device_get_softc(dev); 1937 uint32_t sstatus; 1938 int ccs; 1939 int i; 1940 1941 /* Check for stale timeout. */ 1942 if (slot->state < AHCI_SLOT_RUNNING) 1943 return; 1944 1945 /* Check if slot was not being executed last time we checked. */ 1946 if (slot->state < AHCI_SLOT_EXECUTING) { 1947 /* Check if slot started executing. */ 1948 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1949 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1950 >> AHCI_P_CMD_CCS_SHIFT; 1951 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 1952 ch->fbs_enabled || ch->wrongccs) 1953 slot->state = AHCI_SLOT_EXECUTING; 1954 else if ((ch->rslots & (1 << ccs)) == 0) { 1955 ch->wrongccs = 1; 1956 slot->state = AHCI_SLOT_EXECUTING; 1957 } 1958 1959 callout_reset(&slot->timeout, 1960 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1961 (timeout_t*)ahci_timeout, slot); 1962 return; 1963 } 1964 1965 device_printf(dev, "Timeout on slot %d port %d\n", 1966 slot->slot, slot->ccb->ccb_h.target_id & 0x0f); 1967 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x " 1968 "serr %08x cmd %08x\n", 1969 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1970 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1971 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR), 1972 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1973 1974 /* Handle frozen command. */ 1975 if (ch->frozen) { 1976 union ccb *fccb = ch->frozen; 1977 ch->frozen = NULL; 1978 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1979 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1980 xpt_freeze_devq(fccb->ccb_h.path, 1); 1981 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1982 } 1983 xpt_done(fccb); 1984 } 1985 if (!ch->fbs_enabled && !ch->wrongccs) { 1986 /* Without FBS we know real timeout source. */ 1987 ch->fatalerr = 1; 1988 /* Handle command with timeout. */ 1989 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 1990 /* Handle the rest of commands. */ 1991 for (i = 0; i < ch->numslots; i++) { 1992 /* Do we have a running request on slot? */ 1993 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1994 continue; 1995 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1996 } 1997 } else { 1998 /* With FBS we wait for other commands timeout and pray. */ 1999 if (ch->toslots == 0) 2000 xpt_freeze_simq(ch->sim, 1); 2001 ch->toslots |= (1 << slot->slot); 2002 if ((ch->rslots & ~ch->toslots) == 0) 2003 ahci_process_timeout(dev); 2004 else 2005 device_printf(dev, " ... waiting for slots %08x\n", 2006 ch->rslots & ~ch->toslots); 2007 } 2008} 2009 2010/* Must be called with channel locked. */ 2011static void 2012ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 2013{ 2014 device_t dev = slot->dev; 2015 struct ahci_channel *ch = device_get_softc(dev); 2016 union ccb *ccb = slot->ccb; 2017 struct ahci_cmd_list *clp; 2018 int lastto; 2019 uint32_t sig; 2020 2021 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 2022 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2023 clp = (struct ahci_cmd_list *) 2024 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 2025 /* Read result registers to the result struct 2026 * May be incorrect if several commands finished same time, 2027 * so read only when sure or have to. 2028 */ 2029 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2030 struct ata_res *res = &ccb->ataio.res; 2031 2032 if ((et == AHCI_ERR_TFE) || 2033 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 2034 u_int8_t *fis = ch->dma.rfis + 0x40; 2035 2036 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 2037 BUS_DMASYNC_POSTREAD); 2038 if (ch->fbs_enabled) { 2039 fis += ccb->ccb_h.target_id * 256; 2040 res->status = fis[2]; 2041 res->error = fis[3]; 2042 } else { 2043 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 2044 2045 res->status = tfd; 2046 res->error = tfd >> 8; 2047 } 2048 res->lba_low = fis[4]; 2049 res->lba_mid = fis[5]; 2050 res->lba_high = fis[6]; 2051 res->device = fis[7]; 2052 res->lba_low_exp = fis[8]; 2053 res->lba_mid_exp = fis[9]; 2054 res->lba_high_exp = fis[10]; 2055 res->sector_count = fis[12]; 2056 res->sector_count_exp = fis[13]; 2057 2058 /* 2059 * Some weird controllers do not return signature in 2060 * FIS receive area. Read it from PxSIG register. 2061 */ 2062 if ((ch->quirks & AHCI_Q_ALTSIG) && 2063 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2064 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 2065 sig = ATA_INL(ch->r_mem, AHCI_P_SIG); 2066 res->lba_high = sig >> 24; 2067 res->lba_mid = sig >> 16; 2068 res->lba_low = sig >> 8; 2069 res->sector_count = sig; 2070 } 2071 } else 2072 bzero(res, sizeof(*res)); 2073 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 2074 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2075 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2076 ccb->ataio.resid = 2077 ccb->ataio.dxfer_len - le32toh(clp->bytecount); 2078 } 2079 } else { 2080 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2081 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2082 ccb->csio.resid = 2083 ccb->csio.dxfer_len - le32toh(clp->bytecount); 2084 } 2085 } 2086 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2087 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 2088 (ccb->ccb_h.flags & CAM_DIR_IN) ? 2089 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2090 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 2091 } 2092 if (et != AHCI_ERR_NONE) 2093 ch->eslots |= (1 << slot->slot); 2094 /* In case of error, freeze device for proper recovery. */ 2095 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) && 2096 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 2097 xpt_freeze_devq(ccb->ccb_h.path, 1); 2098 ccb->ccb_h.status |= CAM_DEV_QFRZN; 2099 } 2100 /* Set proper result status. */ 2101 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2102 switch (et) { 2103 case AHCI_ERR_NONE: 2104 ccb->ccb_h.status |= CAM_REQ_CMP; 2105 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 2106 ccb->csio.scsi_status = SCSI_STATUS_OK; 2107 break; 2108 case AHCI_ERR_INVALID: 2109 ch->fatalerr = 1; 2110 ccb->ccb_h.status |= CAM_REQ_INVALID; 2111 break; 2112 case AHCI_ERR_INNOCENT: 2113 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 2114 break; 2115 case AHCI_ERR_TFE: 2116 case AHCI_ERR_NCQ: 2117 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2118 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2119 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2120 } else { 2121 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 2122 } 2123 break; 2124 case AHCI_ERR_SATA: 2125 ch->fatalerr = 1; 2126 if (!ch->recoverycmd) { 2127 xpt_freeze_simq(ch->sim, 1); 2128 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2129 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2130 } 2131 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 2132 break; 2133 case AHCI_ERR_TIMEOUT: 2134 if (!ch->recoverycmd) { 2135 xpt_freeze_simq(ch->sim, 1); 2136 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2137 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2138 } 2139 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 2140 break; 2141 default: 2142 ch->fatalerr = 1; 2143 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 2144 } 2145 /* Free slot. */ 2146 ch->oslots &= ~(1 << slot->slot); 2147 ch->rslots &= ~(1 << slot->slot); 2148 ch->aslots &= ~(1 << slot->slot); 2149 slot->state = AHCI_SLOT_EMPTY; 2150 slot->ccb = NULL; 2151 /* Update channel stats. */ 2152 ch->numrslots--; 2153 ch->numrslotspd[ccb->ccb_h.target_id]--; 2154 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2155 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 2156 ch->numtslots--; 2157 ch->numtslotspd[ccb->ccb_h.target_id]--; 2158 } 2159 /* Cancel timeout state if request completed normally. */ 2160 if (et != AHCI_ERR_TIMEOUT) { 2161 lastto = (ch->toslots == (1 << slot->slot)); 2162 ch->toslots &= ~(1 << slot->slot); 2163 if (lastto) 2164 xpt_release_simq(ch->sim, TRUE); 2165 } 2166 /* If it was first request of reset sequence and there is no error, 2167 * proceed to second request. */ 2168 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2169 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2170 (ccb->ataio.cmd.control & ATA_A_RESET) && 2171 et == AHCI_ERR_NONE) { 2172 ccb->ataio.cmd.control &= ~ATA_A_RESET; 2173 ahci_begin_transaction(dev, ccb); 2174 return; 2175 } 2176 /* If it was our READ LOG command - process it. */ 2177 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 2178 ahci_process_read_log(dev, ccb); 2179 /* If it was our REQUEST SENSE command - process it. */ 2180 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 2181 ahci_process_request_sense(dev, ccb); 2182 /* If it was NCQ or ATAPI command error, put result on hold. */ 2183 } else if (et == AHCI_ERR_NCQ || 2184 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 2185 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 2186 ch->hold[slot->slot] = ccb; 2187 ch->numhslots++; 2188 } else 2189 xpt_done(ccb); 2190 /* If we have no other active commands, ... */ 2191 if (ch->rslots == 0) { 2192 /* if there was fatal error - reset port. */ 2193 if (ch->toslots != 0 || ch->fatalerr) { 2194 ahci_reset(dev); 2195 } else { 2196 /* if we have slots in error, we can reinit port. */ 2197 if (ch->eslots != 0) { 2198 ahci_stop(dev); 2199 ahci_clo(dev); 2200 ahci_start(dev, 1); 2201 } 2202 /* if there commands on hold, we can do READ LOG. */ 2203 if (!ch->recoverycmd && ch->numhslots) 2204 ahci_issue_recovery(dev); 2205 } 2206 /* If all the rest of commands are in timeout - give them chance. */ 2207 } else if ((ch->rslots & ~ch->toslots) == 0 && 2208 et != AHCI_ERR_TIMEOUT) 2209 ahci_rearm_timeout(dev); 2210 /* Unfreeze frozen command. */ 2211 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) { 2212 union ccb *fccb = ch->frozen; 2213 ch->frozen = NULL; 2214 ahci_begin_transaction(dev, fccb); 2215 xpt_release_simq(ch->sim, TRUE); 2216 } 2217 /* Start PM timer. */ 2218 if (ch->numrslots == 0 && ch->pm_level > 3 && 2219 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 2220 callout_schedule(&ch->pm_timer, 2221 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 2222 } 2223} 2224 2225static void 2226ahci_issue_recovery(device_t dev) 2227{ 2228 struct ahci_channel *ch = device_get_softc(dev); 2229 union ccb *ccb; 2230 struct ccb_ataio *ataio; 2231 struct ccb_scsiio *csio; 2232 int i; 2233 2234 /* Find some held command. */ 2235 for (i = 0; i < ch->numslots; i++) { 2236 if (ch->hold[i]) 2237 break; 2238 } 2239 ccb = xpt_alloc_ccb_nowait(); 2240 if (ccb == NULL) { 2241 device_printf(dev, "Unable to allocate recovery command\n"); 2242completeall: 2243 /* We can't do anything -- complete held commands. */ 2244 for (i = 0; i < ch->numslots; i++) { 2245 if (ch->hold[i] == NULL) 2246 continue; 2247 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2248 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 2249 xpt_done(ch->hold[i]); 2250 ch->hold[i] = NULL; 2251 ch->numhslots--; 2252 } 2253 ahci_reset(dev); 2254 return; 2255 } 2256 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 2257 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2258 /* READ LOG */ 2259 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 2260 ccb->ccb_h.func_code = XPT_ATA_IO; 2261 ccb->ccb_h.flags = CAM_DIR_IN; 2262 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2263 ataio = &ccb->ataio; 2264 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 2265 if (ataio->data_ptr == NULL) { 2266 xpt_free_ccb(ccb); 2267 device_printf(dev, 2268 "Unable to allocate memory for READ LOG command\n"); 2269 goto completeall; 2270 } 2271 ataio->dxfer_len = 512; 2272 bzero(&ataio->cmd, sizeof(ataio->cmd)); 2273 ataio->cmd.flags = CAM_ATAIO_48BIT; 2274 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2275 ataio->cmd.sector_count = 1; 2276 ataio->cmd.sector_count_exp = 0; 2277 ataio->cmd.lba_low = 0x10; 2278 ataio->cmd.lba_mid = 0; 2279 ataio->cmd.lba_mid_exp = 0; 2280 } else { 2281 /* REQUEST SENSE */ 2282 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 2283 ccb->ccb_h.recovery_slot = i; 2284 ccb->ccb_h.func_code = XPT_SCSI_IO; 2285 ccb->ccb_h.flags = CAM_DIR_IN; 2286 ccb->ccb_h.status = 0; 2287 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2288 csio = &ccb->csio; 2289 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 2290 csio->dxfer_len = ch->hold[i]->csio.sense_len; 2291 csio->cdb_len = 6; 2292 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 2293 csio->cdb_io.cdb_bytes[0] = 0x03; 2294 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 2295 } 2296 /* Freeze SIM while doing recovery. */ 2297 ch->recoverycmd = 1; 2298 xpt_freeze_simq(ch->sim, 1); 2299 ahci_begin_transaction(dev, ccb); 2300} 2301 2302static void 2303ahci_process_read_log(device_t dev, union ccb *ccb) 2304{ 2305 struct ahci_channel *ch = device_get_softc(dev); 2306 uint8_t *data; 2307 struct ata_res *res; 2308 int i; 2309 2310 ch->recoverycmd = 0; 2311 2312 data = ccb->ataio.data_ptr; 2313 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2314 (data[0] & 0x80) == 0) { 2315 for (i = 0; i < ch->numslots; i++) { 2316 if (!ch->hold[i]) 2317 continue; 2318 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2319 continue; 2320 if ((data[0] & 0x1F) == i) { 2321 res = &ch->hold[i]->ataio.res; 2322 res->status = data[2]; 2323 res->error = data[3]; 2324 res->lba_low = data[4]; 2325 res->lba_mid = data[5]; 2326 res->lba_high = data[6]; 2327 res->device = data[7]; 2328 res->lba_low_exp = data[8]; 2329 res->lba_mid_exp = data[9]; 2330 res->lba_high_exp = data[10]; 2331 res->sector_count = data[12]; 2332 res->sector_count_exp = data[13]; 2333 } else { 2334 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2335 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2336 } 2337 xpt_done(ch->hold[i]); 2338 ch->hold[i] = NULL; 2339 ch->numhslots--; 2340 } 2341 } else { 2342 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2343 device_printf(dev, "Error while READ LOG EXT\n"); 2344 else if ((data[0] & 0x80) == 0) { 2345 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 2346 } 2347 for (i = 0; i < ch->numslots; i++) { 2348 if (!ch->hold[i]) 2349 continue; 2350 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2351 continue; 2352 xpt_done(ch->hold[i]); 2353 ch->hold[i] = NULL; 2354 ch->numhslots--; 2355 } 2356 } 2357 free(ccb->ataio.data_ptr, M_AHCI); 2358 xpt_free_ccb(ccb); 2359 xpt_release_simq(ch->sim, TRUE); 2360} 2361 2362static void 2363ahci_process_request_sense(device_t dev, union ccb *ccb) 2364{ 2365 struct ahci_channel *ch = device_get_softc(dev); 2366 int i; 2367 2368 ch->recoverycmd = 0; 2369 2370 i = ccb->ccb_h.recovery_slot; 2371 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 2372 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 2373 } else { 2374 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2375 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 2376 } 2377 xpt_done(ch->hold[i]); 2378 ch->hold[i] = NULL; 2379 ch->numhslots--; 2380 xpt_free_ccb(ccb); 2381 xpt_release_simq(ch->sim, TRUE); 2382} 2383 2384static void 2385ahci_start(device_t dev, int fbs) 2386{ 2387 struct ahci_channel *ch = device_get_softc(dev); 2388 u_int32_t cmd; 2389 2390 /* Clear SATA error register */ 2391 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2392 /* Clear any interrupts pending on this channel */ 2393 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2394 /* Configure FIS-based switching if supported. */ 2395 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2396 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2397 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2398 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2399 } 2400 /* Start operations on this channel */ 2401 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2402 cmd &= ~AHCI_P_CMD_PMA; 2403 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2404 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2405} 2406 2407static void 2408ahci_stop(device_t dev) 2409{ 2410 struct ahci_channel *ch = device_get_softc(dev); 2411 u_int32_t cmd; 2412 int timeout; 2413 2414 /* Kill all activity on this channel */ 2415 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2416 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2417 /* Wait for activity stop. */ 2418 timeout = 0; 2419 do { 2420 DELAY(10); 2421 if (timeout++ > 50000) { 2422 device_printf(dev, "stopping AHCI engine failed\n"); 2423 break; 2424 } 2425 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2426 ch->eslots = 0; 2427} 2428 2429static void 2430ahci_clo(device_t dev) 2431{ 2432 struct ahci_channel *ch = device_get_softc(dev); 2433 u_int32_t cmd; 2434 int timeout; 2435 2436 /* Issue Command List Override if supported */ 2437 if (ch->caps & AHCI_CAP_SCLO) { 2438 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2439 cmd |= AHCI_P_CMD_CLO; 2440 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2441 timeout = 0; 2442 do { 2443 DELAY(10); 2444 if (timeout++ > 50000) { 2445 device_printf(dev, "executing CLO failed\n"); 2446 break; 2447 } 2448 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2449 } 2450} 2451 2452static void 2453ahci_stop_fr(device_t dev) 2454{ 2455 struct ahci_channel *ch = device_get_softc(dev); 2456 u_int32_t cmd; 2457 int timeout; 2458 2459 /* Kill all FIS reception on this channel */ 2460 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2461 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2462 /* Wait for FIS reception stop. */ 2463 timeout = 0; 2464 do { 2465 DELAY(10); 2466 if (timeout++ > 50000) { 2467 device_printf(dev, "stopping AHCI FR engine failed\n"); 2468 break; 2469 } 2470 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2471} 2472 2473static void 2474ahci_start_fr(device_t dev) 2475{ 2476 struct ahci_channel *ch = device_get_softc(dev); 2477 u_int32_t cmd; 2478 2479 /* Start FIS reception on this channel */ 2480 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2481 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2482} 2483 2484static int 2485ahci_wait_ready(device_t dev, int t, int t0) 2486{ 2487 struct ahci_channel *ch = device_get_softc(dev); 2488 int timeout = 0; 2489 uint32_t val; 2490 2491 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2492 (ATA_S_BUSY | ATA_S_DRQ)) { 2493 if (timeout > t) { 2494 if (t != 0) { 2495 device_printf(dev, 2496 "AHCI reset: device not ready after %dms " 2497 "(tfd = %08x)\n", 2498 MAX(t, 0) + t0, val); 2499 } 2500 return (EBUSY); 2501 } 2502 DELAY(1000); 2503 timeout++; 2504 } 2505 if (bootverbose) 2506 device_printf(dev, "AHCI reset: device ready after %dms\n", 2507 timeout + t0); 2508 return (0); 2509} 2510 2511static void 2512ahci_reset_to(void *arg) 2513{ 2514 device_t dev = arg; 2515 struct ahci_channel *ch = device_get_softc(dev); 2516 2517 if (ch->resetting == 0) 2518 return; 2519 ch->resetting--; 2520 if (ahci_wait_ready(dev, ch->resetting == 0 ? -1 : 0, 2521 (310 - ch->resetting) * 100) == 0) { 2522 ch->resetting = 0; 2523 ahci_start(dev, 1); 2524 xpt_release_simq(ch->sim, TRUE); 2525 return; 2526 } 2527 if (ch->resetting == 0) { 2528 ahci_clo(dev); 2529 ahci_start(dev, 1); 2530 xpt_release_simq(ch->sim, TRUE); 2531 return; 2532 } 2533 callout_schedule(&ch->reset_timer, hz / 10); 2534} 2535 2536static void 2537ahci_reset(device_t dev) 2538{ 2539 struct ahci_channel *ch = device_get_softc(dev); 2540 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2541 int i; 2542 2543 xpt_freeze_simq(ch->sim, 1); 2544 if (bootverbose) 2545 device_printf(dev, "AHCI reset...\n"); 2546 /* Forget about previous reset. */ 2547 if (ch->resetting) { 2548 ch->resetting = 0; 2549 callout_stop(&ch->reset_timer); 2550 xpt_release_simq(ch->sim, TRUE); 2551 } 2552 /* Requeue freezed command. */ 2553 if (ch->frozen) { 2554 union ccb *fccb = ch->frozen; 2555 ch->frozen = NULL; 2556 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2557 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2558 xpt_freeze_devq(fccb->ccb_h.path, 1); 2559 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2560 } 2561 xpt_done(fccb); 2562 } 2563 /* Kill the engine and requeue all running commands. */ 2564 ahci_stop(dev); 2565 for (i = 0; i < ch->numslots; i++) { 2566 /* Do we have a running request on slot? */ 2567 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2568 continue; 2569 /* XXX; Commands in loading state. */ 2570 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2571 } 2572 for (i = 0; i < ch->numslots; i++) { 2573 if (!ch->hold[i]) 2574 continue; 2575 xpt_done(ch->hold[i]); 2576 ch->hold[i] = NULL; 2577 ch->numhslots--; 2578 } 2579 if (ch->toslots != 0) 2580 xpt_release_simq(ch->sim, TRUE); 2581 ch->eslots = 0; 2582 ch->toslots = 0; 2583 ch->wrongccs = 0; 2584 ch->fatalerr = 0; 2585 /* Tell the XPT about the event */ 2586 xpt_async(AC_BUS_RESET, ch->path, NULL); 2587 /* Disable port interrupts */ 2588 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2589 /* Reset and reconnect PHY, */ 2590 if (!ahci_sata_phy_reset(dev)) { 2591 if (bootverbose) 2592 device_printf(dev, 2593 "AHCI reset: device not found\n"); 2594 ch->devices = 0; 2595 /* Enable wanted port interrupts */ 2596 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2597 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2598 AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2599 xpt_release_simq(ch->sim, TRUE); 2600 return; 2601 } 2602 if (bootverbose) 2603 device_printf(dev, "AHCI reset: device found\n"); 2604 /* Wait for clearing busy status. */ 2605 if (ahci_wait_ready(dev, dumping ? 31000 : 0, 0)) { 2606 if (dumping) 2607 ahci_clo(dev); 2608 else 2609 ch->resetting = 310; 2610 } 2611 ch->devices = 1; 2612 /* Enable wanted port interrupts */ 2613 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2614 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2615 AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2616 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2617 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC | 2618 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2619 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2620 if (ch->resetting) 2621 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, dev); 2622 else { 2623 ahci_start(dev, 1); 2624 xpt_release_simq(ch->sim, TRUE); 2625 } 2626} 2627 2628static int 2629ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2630{ 2631 struct ahci_channel *ch = device_get_softc(dev); 2632 u_int8_t *fis = &ctp->cfis[0]; 2633 2634 bzero(ctp->cfis, 16); 2635 fis[0] = 0x27; /* host to device */ 2636 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2637 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2638 fis[1] |= 0x80; 2639 fis[2] = ATA_PACKET_CMD; 2640 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2641 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2642 fis[3] = ATA_F_DMA; 2643 else { 2644 fis[5] = ccb->csio.dxfer_len; 2645 fis[6] = ccb->csio.dxfer_len >> 8; 2646 } 2647 fis[7] = ATA_D_LBA; 2648 fis[15] = ATA_A_4BIT; 2649 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2650 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2651 ctp->acmd, ccb->csio.cdb_len); 2652 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len); 2653 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2654 fis[1] |= 0x80; 2655 fis[2] = ccb->ataio.cmd.command; 2656 fis[3] = ccb->ataio.cmd.features; 2657 fis[4] = ccb->ataio.cmd.lba_low; 2658 fis[5] = ccb->ataio.cmd.lba_mid; 2659 fis[6] = ccb->ataio.cmd.lba_high; 2660 fis[7] = ccb->ataio.cmd.device; 2661 fis[8] = ccb->ataio.cmd.lba_low_exp; 2662 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2663 fis[10] = ccb->ataio.cmd.lba_high_exp; 2664 fis[11] = ccb->ataio.cmd.features_exp; 2665 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2666 fis[12] = tag << 3; 2667 fis[13] = 0; 2668 } else { 2669 fis[12] = ccb->ataio.cmd.sector_count; 2670 fis[13] = ccb->ataio.cmd.sector_count_exp; 2671 } 2672 fis[15] = ATA_A_4BIT; 2673 } else { 2674 fis[15] = ccb->ataio.cmd.control; 2675 } 2676 return (20); 2677} 2678 2679static int 2680ahci_sata_connect(struct ahci_channel *ch) 2681{ 2682 u_int32_t status; 2683 int timeout, found = 0; 2684 2685 /* Wait up to 100ms for "connect well" */ 2686 for (timeout = 0; timeout < 1000 ; timeout++) { 2687 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2688 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 2689 found = 1; 2690 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2691 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2692 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2693 break; 2694 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2695 if (bootverbose) { 2696 device_printf(ch->dev, "SATA offline status=%08x\n", 2697 status); 2698 } 2699 return (0); 2700 } 2701 if (found == 0 && timeout >= 100) 2702 break; 2703 DELAY(100); 2704 } 2705 if (timeout >= 1000 || !found) { 2706 if (bootverbose) { 2707 device_printf(ch->dev, 2708 "SATA connect timeout time=%dus status=%08x\n", 2709 timeout * 100, status); 2710 } 2711 return (0); 2712 } 2713 if (bootverbose) { 2714 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2715 timeout * 100, status); 2716 } 2717 /* Clear SATA error register */ 2718 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2719 return (1); 2720} 2721 2722static int 2723ahci_sata_phy_reset(device_t dev) 2724{ 2725 struct ahci_channel *ch = device_get_softc(dev); 2726 int sata_rev; 2727 uint32_t val; 2728 2729 if (ch->listening) { 2730 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2731 val |= AHCI_P_CMD_SUD; 2732 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2733 ch->listening = 0; 2734 } 2735 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2736 if (sata_rev == 1) 2737 val = ATA_SC_SPD_SPEED_GEN1; 2738 else if (sata_rev == 2) 2739 val = ATA_SC_SPD_SPEED_GEN2; 2740 else if (sata_rev == 3) 2741 val = ATA_SC_SPD_SPEED_GEN3; 2742 else 2743 val = 0; 2744 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2745 ATA_SC_DET_RESET | val | 2746 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2747 DELAY(1000); 2748 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2749 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2750 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2751 if (!ahci_sata_connect(ch)) { 2752 if (ch->caps & AHCI_CAP_SSS) { 2753 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2754 val &= ~AHCI_P_CMD_SUD; 2755 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2756 ch->listening = 1; 2757 } else if (ch->pm_level > 0) 2758 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2759 return (0); 2760 } 2761 return (1); 2762} 2763 2764static int 2765ahci_check_ids(device_t dev, union ccb *ccb) 2766{ 2767 struct ahci_channel *ch = device_get_softc(dev); 2768 2769 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2770 ccb->ccb_h.status = CAM_TID_INVALID; 2771 xpt_done(ccb); 2772 return (-1); 2773 } 2774 if (ccb->ccb_h.target_lun != 0) { 2775 ccb->ccb_h.status = CAM_LUN_INVALID; 2776 xpt_done(ccb); 2777 return (-1); 2778 } 2779 return (0); 2780} 2781 2782static void 2783ahciaction(struct cam_sim *sim, union ccb *ccb) 2784{ 2785 device_t dev, parent; 2786 struct ahci_channel *ch; 2787 2788 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2789 ccb->ccb_h.func_code)); 2790 2791 ch = (struct ahci_channel *)cam_sim_softc(sim); 2792 dev = ch->dev; 2793 switch (ccb->ccb_h.func_code) { 2794 /* Common cases first */ 2795 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2796 case XPT_SCSI_IO: 2797 if (ahci_check_ids(dev, ccb)) 2798 return; 2799 if (ch->devices == 0 || 2800 (ch->pm_present == 0 && 2801 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2802 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2803 break; 2804 } 2805 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2806 /* Check for command collision. */ 2807 if (ahci_check_collision(dev, ccb)) { 2808 /* Freeze command. */ 2809 ch->frozen = ccb; 2810 /* We have only one frozen slot, so freeze simq also. */ 2811 xpt_freeze_simq(ch->sim, 1); 2812 return; 2813 } 2814 ahci_begin_transaction(dev, ccb); 2815 return; 2816 case XPT_EN_LUN: /* Enable LUN as a target */ 2817 case XPT_TARGET_IO: /* Execute target I/O request */ 2818 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2819 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2820 case XPT_ABORT: /* Abort the specified CCB */ 2821 /* XXX Implement */ 2822 ccb->ccb_h.status = CAM_REQ_INVALID; 2823 break; 2824 case XPT_SET_TRAN_SETTINGS: 2825 { 2826 struct ccb_trans_settings *cts = &ccb->cts; 2827 struct ahci_device *d; 2828 2829 if (ahci_check_ids(dev, ccb)) 2830 return; 2831 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2832 d = &ch->curr[ccb->ccb_h.target_id]; 2833 else 2834 d = &ch->user[ccb->ccb_h.target_id]; 2835 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2836 d->revision = cts->xport_specific.sata.revision; 2837 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2838 d->mode = cts->xport_specific.sata.mode; 2839 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2840 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2841 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2842 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2843 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2844 ch->pm_present = cts->xport_specific.sata.pm_present; 2845 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2846 d->atapi = cts->xport_specific.sata.atapi; 2847 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2848 d->caps = cts->xport_specific.sata.caps; 2849 ccb->ccb_h.status = CAM_REQ_CMP; 2850 break; 2851 } 2852 case XPT_GET_TRAN_SETTINGS: 2853 /* Get default/user set transfer settings for the target */ 2854 { 2855 struct ccb_trans_settings *cts = &ccb->cts; 2856 struct ahci_device *d; 2857 uint32_t status; 2858 2859 if (ahci_check_ids(dev, ccb)) 2860 return; 2861 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2862 d = &ch->curr[ccb->ccb_h.target_id]; 2863 else 2864 d = &ch->user[ccb->ccb_h.target_id]; 2865 cts->protocol = PROTO_UNSPECIFIED; 2866 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2867 cts->transport = XPORT_SATA; 2868 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2869 cts->proto_specific.valid = 0; 2870 cts->xport_specific.sata.valid = 0; 2871 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2872 (ccb->ccb_h.target_id == 15 || 2873 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2874 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2875 if (status & 0x0f0) { 2876 cts->xport_specific.sata.revision = 2877 (status & 0x0f0) >> 4; 2878 cts->xport_specific.sata.valid |= 2879 CTS_SATA_VALID_REVISION; 2880 } 2881 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2882 if (ch->pm_level) { 2883 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 2884 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2885 if (ch->caps2 & AHCI_CAP2_APST) 2886 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 2887 } 2888 if ((ch->caps & AHCI_CAP_SNCQ) && 2889 (ch->quirks & AHCI_Q_NOAA) == 0) 2890 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 2891 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 2892 cts->xport_specific.sata.caps &= 2893 ch->user[ccb->ccb_h.target_id].caps; 2894 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2895 } else { 2896 cts->xport_specific.sata.revision = d->revision; 2897 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2898 cts->xport_specific.sata.caps = d->caps; 2899 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2900 } 2901 cts->xport_specific.sata.mode = d->mode; 2902 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2903 cts->xport_specific.sata.bytecount = d->bytecount; 2904 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2905 cts->xport_specific.sata.pm_present = ch->pm_present; 2906 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2907 cts->xport_specific.sata.tags = d->tags; 2908 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2909 cts->xport_specific.sata.atapi = d->atapi; 2910 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2911 ccb->ccb_h.status = CAM_REQ_CMP; 2912 break; 2913 } 2914 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2915 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2916 ahci_reset(dev); 2917 ccb->ccb_h.status = CAM_REQ_CMP; 2918 break; 2919 case XPT_TERM_IO: /* Terminate the I/O process */ 2920 /* XXX Implement */ 2921 ccb->ccb_h.status = CAM_REQ_INVALID; 2922 break; 2923 case XPT_PATH_INQ: /* Path routing inquiry */ 2924 { 2925 struct ccb_pathinq *cpi = &ccb->cpi; 2926 2927 parent = device_get_parent(dev); 2928 cpi->version_num = 1; /* XXX??? */ 2929 cpi->hba_inquiry = PI_SDTR_ABLE; 2930 if (ch->caps & AHCI_CAP_SNCQ) 2931 cpi->hba_inquiry |= PI_TAG_ABLE; 2932 if (ch->caps & AHCI_CAP_SPM) 2933 cpi->hba_inquiry |= PI_SATAPM; 2934 cpi->target_sprt = 0; 2935 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED; 2936 cpi->hba_eng_cnt = 0; 2937 if (ch->caps & AHCI_CAP_SPM) 2938 cpi->max_target = 15; 2939 else 2940 cpi->max_target = 0; 2941 cpi->max_lun = 0; 2942 cpi->initiator_id = 0; 2943 cpi->bus_id = cam_sim_bus(sim); 2944 cpi->base_transfer_speed = 150000; 2945 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2946 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2947 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2948 cpi->unit_number = cam_sim_unit(sim); 2949 cpi->transport = XPORT_SATA; 2950 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2951 cpi->protocol = PROTO_ATA; 2952 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2953 cpi->maxio = MAXPHYS; 2954 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2955 if (pci_get_devid(parent) == 0x43801002) 2956 cpi->maxio = min(cpi->maxio, 128 * 512); 2957 cpi->hba_vendor = pci_get_vendor(parent); 2958 cpi->hba_device = pci_get_device(parent); 2959 cpi->hba_subvendor = pci_get_subvendor(parent); 2960 cpi->hba_subdevice = pci_get_subdevice(parent); 2961 cpi->ccb_h.status = CAM_REQ_CMP; 2962 break; 2963 } 2964 default: 2965 ccb->ccb_h.status = CAM_REQ_INVALID; 2966 break; 2967 } 2968 xpt_done(ccb); 2969} 2970 2971static void 2972ahcipoll(struct cam_sim *sim) 2973{ 2974 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2975 2976 ahci_ch_intr(ch->dev); 2977 if (ch->resetting != 0 && 2978 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 2979 ch->resetpolldiv = 1000; 2980 ahci_reset_to(ch->dev); 2981 } 2982} 2983