ahci_generic.c revision 253475
1/*- 2 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ahci/ahci.c 253475 2013-07-19 21:37:40Z jfv $"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/bus.h> 35#include <sys/conf.h> 36#include <sys/endian.h> 37#include <sys/malloc.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <machine/stdarg.h> 41#include <machine/resource.h> 42#include <machine/bus.h> 43#include <sys/rman.h> 44#include <dev/pci/pcivar.h> 45#include <dev/pci/pcireg.h> 46#include "ahci.h" 47 48#include <cam/cam.h> 49#include <cam/cam_ccb.h> 50#include <cam/cam_sim.h> 51#include <cam/cam_xpt_sim.h> 52#include <cam/cam_debug.h> 53 54/* local prototypes */ 55static int ahci_setup_interrupt(device_t dev); 56static void ahci_intr(void *data); 57static void ahci_intr_one(void *data); 58static int ahci_suspend(device_t dev); 59static int ahci_resume(device_t dev); 60static int ahci_ch_init(device_t dev); 61static int ahci_ch_deinit(device_t dev); 62static int ahci_ch_suspend(device_t dev); 63static int ahci_ch_resume(device_t dev); 64static void ahci_ch_pm(void *arg); 65static void ahci_ch_intr_locked(void *data); 66static void ahci_ch_intr(void *data); 67static int ahci_ctlr_reset(device_t dev); 68static int ahci_ctlr_setup(device_t dev); 69static void ahci_begin_transaction(device_t dev, union ccb *ccb); 70static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 71static void ahci_execute_transaction(struct ahci_slot *slot); 72static void ahci_timeout(struct ahci_slot *slot); 73static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 74static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 75static void ahci_dmainit(device_t dev); 76static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 77static void ahci_dmafini(device_t dev); 78static void ahci_slotsalloc(device_t dev); 79static void ahci_slotsfree(device_t dev); 80static void ahci_reset(device_t dev); 81static void ahci_start(device_t dev, int fbs); 82static void ahci_stop(device_t dev); 83static void ahci_clo(device_t dev); 84static void ahci_start_fr(device_t dev); 85static void ahci_stop_fr(device_t dev); 86 87static int ahci_sata_connect(struct ahci_channel *ch); 88static int ahci_sata_phy_reset(device_t dev); 89static int ahci_wait_ready(device_t dev, int t, int t0); 90 91static void ahci_issue_recovery(device_t dev); 92static void ahci_process_read_log(device_t dev, union ccb *ccb); 93static void ahci_process_request_sense(device_t dev, union ccb *ccb); 94 95static void ahciaction(struct cam_sim *sim, union ccb *ccb); 96static void ahcipoll(struct cam_sim *sim); 97 98static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 99 100static struct { 101 uint32_t id; 102 uint8_t rev; 103 const char *name; 104 int quirks; 105#define AHCI_Q_NOFORCE 1 106#define AHCI_Q_NOPMP 2 107#define AHCI_Q_NONCQ 4 108#define AHCI_Q_1CH 8 109#define AHCI_Q_2CH 16 110#define AHCI_Q_4CH 32 111#define AHCI_Q_EDGEIS 64 112#define AHCI_Q_SATA2 128 113#define AHCI_Q_NOBSYRES 256 114#define AHCI_Q_NOAA 512 115#define AHCI_Q_NOCOUNT 1024 116#define AHCI_Q_ALTSIG 2048 117#define AHCI_Q_NOMSI 4096 118 119#define AHCI_Q_BIT_STRING \ 120 "\020" \ 121 "\001NOFORCE" \ 122 "\002NOPMP" \ 123 "\003NONCQ" \ 124 "\0041CH" \ 125 "\0052CH" \ 126 "\0064CH" \ 127 "\007EDGEIS" \ 128 "\010SATA2" \ 129 "\011NOBSYRES" \ 130 "\012NOAA" \ 131 "\013NOCOUNT" \ 132 "\014ALTSIG" \ 133 "\015NOMSI" 134} ahci_ids[] = { 135 {0x43801002, 0x00, "ATI IXP600", AHCI_Q_NOMSI}, 136 {0x43901002, 0x00, "ATI IXP700", 0}, 137 {0x43911002, 0x00, "ATI IXP700", 0}, 138 {0x43921002, 0x00, "ATI IXP700", 0}, 139 {0x43931002, 0x00, "ATI IXP700", 0}, 140 {0x43941002, 0x00, "ATI IXP800", 0}, 141 {0x43951002, 0x00, "ATI IXP800", 0}, 142 {0x78001022, 0x00, "AMD Hudson-2", 0}, 143 {0x78011022, 0x00, "AMD Hudson-2", 0}, 144 {0x78021022, 0x00, "AMD Hudson-2", 0}, 145 {0x78031022, 0x00, "AMD Hudson-2", 0}, 146 {0x78041022, 0x00, "AMD Hudson-2", 0}, 147 {0x06121b21, 0x00, "ASMedia ASM1061", 0}, 148 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE}, 149 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE}, 150 {0x26818086, 0x00, "Intel ESB2", 0}, 151 {0x26828086, 0x00, "Intel ESB2", 0}, 152 {0x26838086, 0x00, "Intel ESB2", 0}, 153 {0x27c18086, 0x00, "Intel ICH7", 0}, 154 {0x27c38086, 0x00, "Intel ICH7", 0}, 155 {0x27c58086, 0x00, "Intel ICH7M", 0}, 156 {0x27c68086, 0x00, "Intel ICH7M", 0}, 157 {0x28218086, 0x00, "Intel ICH8", 0}, 158 {0x28228086, 0x00, "Intel ICH8", 0}, 159 {0x28248086, 0x00, "Intel ICH8", 0}, 160 {0x28298086, 0x00, "Intel ICH8M", 0}, 161 {0x282a8086, 0x00, "Intel ICH8M", 0}, 162 {0x29228086, 0x00, "Intel ICH9", 0}, 163 {0x29238086, 0x00, "Intel ICH9", 0}, 164 {0x29248086, 0x00, "Intel ICH9", 0}, 165 {0x29258086, 0x00, "Intel ICH9", 0}, 166 {0x29278086, 0x00, "Intel ICH9", 0}, 167 {0x29298086, 0x00, "Intel ICH9M", 0}, 168 {0x292a8086, 0x00, "Intel ICH9M", 0}, 169 {0x292b8086, 0x00, "Intel ICH9M", 0}, 170 {0x292c8086, 0x00, "Intel ICH9M", 0}, 171 {0x292f8086, 0x00, "Intel ICH9M", 0}, 172 {0x294d8086, 0x00, "Intel ICH9", 0}, 173 {0x294e8086, 0x00, "Intel ICH9M", 0}, 174 {0x3a058086, 0x00, "Intel ICH10", 0}, 175 {0x3a228086, 0x00, "Intel ICH10", 0}, 176 {0x3a258086, 0x00, "Intel ICH10", 0}, 177 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0}, 178 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0}, 179 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0}, 180 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0}, 181 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0}, 182 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0}, 183 {0x1c028086, 0x00, "Intel Cougar Point", 0}, 184 {0x1c038086, 0x00, "Intel Cougar Point", 0}, 185 {0x1c048086, 0x00, "Intel Cougar Point", 0}, 186 {0x1c058086, 0x00, "Intel Cougar Point", 0}, 187 {0x1d028086, 0x00, "Intel Patsburg", 0}, 188 {0x1d048086, 0x00, "Intel Patsburg", 0}, 189 {0x1d068086, 0x00, "Intel Patsburg", 0}, 190 {0x28268086, 0x00, "Intel Patsburg (RAID)", 0}, 191 {0x1e028086, 0x00, "Intel Panther Point", 0}, 192 {0x1e038086, 0x00, "Intel Panther Point", 0}, 193 {0x1e048086, 0x00, "Intel Panther Point", 0}, 194 {0x1e058086, 0x00, "Intel Panther Point", 0}, 195 {0x1e068086, 0x00, "Intel Panther Point", 0}, 196 {0x1e078086, 0x00, "Intel Panther Point", 0}, 197 {0x1e0e8086, 0x00, "Intel Panther Point", 0}, 198 {0x1e0f8086, 0x00, "Intel Panther Point", 0}, 199 {0x23a38086, 0x00, "Intel Coleto Creek", 0}, 200 {0x8c028086, 0x00, "Intel Lynx Point", 0}, 201 {0x8c038086, 0x00, "Intel Lynx Point", 0}, 202 {0x8c048086, 0x00, "Intel Lynx Point", 0}, 203 {0x8c058086, 0x00, "Intel Lynx Point", 0}, 204 {0x8c068086, 0x00, "Intel Lynx Point", 0}, 205 {0x8c078086, 0x00, "Intel Lynx Point", 0}, 206 {0x8c0e8086, 0x00, "Intel Lynx Point", 0}, 207 {0x8c0f8086, 0x00, "Intel Lynx Point", 0}, 208 {0x23238086, 0x00, "Intel DH89xxCC", 0}, 209 {0x2360197b, 0x00, "JMicron JMB360", 0}, 210 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE}, 211 {0x2362197b, 0x00, "JMicron JMB362", 0}, 212 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE}, 213 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE}, 214 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE}, 215 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE}, 216 {0x611111ab, 0x00, "Marvell 88SE6111", AHCI_Q_NOFORCE | AHCI_Q_1CH | 217 AHCI_Q_EDGEIS}, 218 {0x612111ab, 0x00, "Marvell 88SE6121", AHCI_Q_NOFORCE | AHCI_Q_2CH | 219 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 220 {0x614111ab, 0x00, "Marvell 88SE6141", AHCI_Q_NOFORCE | AHCI_Q_4CH | 221 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 222 {0x614511ab, 0x00, "Marvell 88SE6145", AHCI_Q_NOFORCE | AHCI_Q_4CH | 223 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 224 {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_NOBSYRES}, 225 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 226 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES}, 227 {0x91251b4b, 0x00, "Marvell 88SE9125", AHCI_Q_NOBSYRES}, 228 {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 229 {0x91301b4b, 0x00, "Marvell 88SE9130", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 230 {0x91721b4b, 0x00, "Marvell 88SE9172", AHCI_Q_NOBSYRES}, 231 {0x91821b4b, 0x00, "Marvell 88SE9182", AHCI_Q_NOBSYRES}, 232 {0x91a01b4b, 0x00, "Marvell 88SE91Ax", AHCI_Q_NOBSYRES}, 233 {0x92151b4b, 0x00, "Marvell 88SE9215", AHCI_Q_NOBSYRES}, 234 {0x92201b4b, 0x00, "Marvell 88SE9220", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 235 {0x92301b4b, 0x00, "Marvell 88SE9230", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 236 {0x92351b4b, 0x00, "Marvell 88SE9235", AHCI_Q_NOBSYRES}, 237 {0x06201103, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 238 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 239 {0x06221103, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 240 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 241 {0x06401103, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 242 {0x06401b4b, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 243 {0x06441103, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 244 {0x06441b4b, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 245 {0x06411103, 0x00, "HighPoint RocketRAID 640L", AHCI_Q_NOBSYRES}, 246 {0x06421103, 0x00, "HighPoint RocketRAID 642L", AHCI_Q_NOBSYRES}, 247 {0x06451103, 0x00, "HighPoint RocketRAID 644L", AHCI_Q_NOBSYRES}, 248 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 249 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 250 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 251 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 252 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 253 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 254 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 255 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 256 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 257 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 258 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 259 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 260 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 261 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 262 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 263 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 264 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 265 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 266 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 267 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 268 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 269 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 270 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 271 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 272 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 273 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 274 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 275 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 276 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 277 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 278 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 279 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 280 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 281 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 282 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 283 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 284 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 285 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 286 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 287 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 288 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 289 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 290 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 291 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 292 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 293 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 294 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 295 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 296 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 297 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 298 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 299 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 300 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 301 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 302 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 303 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 304 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 305 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 306 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA}, 307 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 308 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 309 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 310 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 311 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 312 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 313 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 314 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 315 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 316 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 317 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 318 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 319 {0x11841039, 0x00, "SiS 966", 0}, 320 {0x11851039, 0x00, "SiS 968", 0}, 321 {0x01861039, 0x00, "SiS 968", 0}, 322 {0x00000000, 0x00, NULL, 0} 323}; 324 325#define recovery_type spriv_field0 326#define RECOVERY_NONE 0 327#define RECOVERY_READ_LOG 1 328#define RECOVERY_REQUEST_SENSE 2 329#define recovery_slot spriv_field1 330 331static int force_ahci = 1; 332TUNABLE_INT("hw.ahci.force", &force_ahci); 333 334static int 335ahci_probe(device_t dev) 336{ 337 char buf[64]; 338 int i, valid = 0; 339 uint32_t devid = pci_get_devid(dev); 340 uint8_t revid = pci_get_revid(dev); 341 342 /* Is this a possible AHCI candidate? */ 343 if (pci_get_class(dev) == PCIC_STORAGE && 344 pci_get_subclass(dev) == PCIS_STORAGE_SATA && 345 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0) 346 valid = 1; 347 /* Is this a known AHCI chip? */ 348 for (i = 0; ahci_ids[i].id != 0; i++) { 349 if (ahci_ids[i].id == devid && 350 ahci_ids[i].rev <= revid && 351 (valid || (force_ahci == 1 && 352 !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) { 353 /* Do not attach JMicrons with single PCI function. */ 354 if (pci_get_vendor(dev) == 0x197b && 355 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0) 356 return (ENXIO); 357 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 358 ahci_ids[i].name); 359 device_set_desc_copy(dev, buf); 360 return (BUS_PROBE_VENDOR); 361 } 362 } 363 if (!valid) 364 return (ENXIO); 365 device_set_desc_copy(dev, "AHCI SATA controller"); 366 return (BUS_PROBE_VENDOR); 367} 368 369static int 370ahci_ata_probe(device_t dev) 371{ 372 char buf[64]; 373 int i; 374 uint32_t devid = pci_get_devid(dev); 375 uint8_t revid = pci_get_revid(dev); 376 377 if ((intptr_t)device_get_ivars(dev) >= 0) 378 return (ENXIO); 379 /* Is this a known AHCI chip? */ 380 for (i = 0; ahci_ids[i].id != 0; i++) { 381 if (ahci_ids[i].id == devid && 382 ahci_ids[i].rev <= revid) { 383 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 384 ahci_ids[i].name); 385 device_set_desc_copy(dev, buf); 386 return (BUS_PROBE_VENDOR); 387 } 388 } 389 device_set_desc_copy(dev, "AHCI SATA controller"); 390 return (BUS_PROBE_VENDOR); 391} 392 393static int 394ahci_attach(device_t dev) 395{ 396 struct ahci_controller *ctlr = device_get_softc(dev); 397 device_t child; 398 int error, unit, speed, i; 399 uint32_t devid = pci_get_devid(dev); 400 uint8_t revid = pci_get_revid(dev); 401 u_int32_t version; 402 403 ctlr->dev = dev; 404 i = 0; 405 while (ahci_ids[i].id != 0 && 406 (ahci_ids[i].id != devid || 407 ahci_ids[i].rev > revid)) 408 i++; 409 ctlr->quirks = ahci_ids[i].quirks; 410 resource_int_value(device_get_name(dev), 411 device_get_unit(dev), "ccc", &ctlr->ccc); 412 /* if we have a memory BAR(5) we are likely on an AHCI part */ 413 ctlr->r_rid = PCIR_BAR(5); 414 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 415 &ctlr->r_rid, RF_ACTIVE))) 416 return ENXIO; 417 /* Setup our own memory management for channels. */ 418 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 419 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 420 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 421 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 422 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 423 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 424 return (error); 425 } 426 if ((error = rman_manage_region(&ctlr->sc_iomem, 427 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 428 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 429 rman_fini(&ctlr->sc_iomem); 430 return (error); 431 } 432 pci_enable_busmaster(dev); 433 /* Reset controller */ 434 if ((error = ahci_ctlr_reset(dev)) != 0) { 435 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 436 rman_fini(&ctlr->sc_iomem); 437 return (error); 438 }; 439 /* Get the HW capabilities */ 440 version = ATA_INL(ctlr->r_mem, AHCI_VS); 441 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 442 if (version >= 0x00010200) 443 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 444 if (ctlr->caps & AHCI_CAP_EMS) 445 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 446 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 447 448 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */ 449 if ((ctlr->quirks & AHCI_Q_NOBSYRES) && 450 (ctlr->quirks & AHCI_Q_ALTSIG) && 451 (ctlr->caps & AHCI_CAP_SPM) == 0) 452 ctlr->quirks &= ~AHCI_Q_NOBSYRES; 453 454 if (ctlr->quirks & AHCI_Q_1CH) { 455 ctlr->caps &= ~AHCI_CAP_NPMASK; 456 ctlr->ichannels &= 0x01; 457 } 458 if (ctlr->quirks & AHCI_Q_2CH) { 459 ctlr->caps &= ~AHCI_CAP_NPMASK; 460 ctlr->caps |= 1; 461 ctlr->ichannels &= 0x03; 462 } 463 if (ctlr->quirks & AHCI_Q_4CH) { 464 ctlr->caps &= ~AHCI_CAP_NPMASK; 465 ctlr->caps |= 3; 466 ctlr->ichannels &= 0x0f; 467 } 468 ctlr->channels = MAX(flsl(ctlr->ichannels), 469 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 470 if (ctlr->quirks & AHCI_Q_NOPMP) 471 ctlr->caps &= ~AHCI_CAP_SPM; 472 if (ctlr->quirks & AHCI_Q_NONCQ) 473 ctlr->caps &= ~AHCI_CAP_SNCQ; 474 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 475 ctlr->ccc = 0; 476 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC); 477 478 /* Create controller-wide DMA tag. */ 479 if (bus_dma_tag_create(bus_get_dma_tag(dev), 0, 0, 480 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR : 481 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 482 BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, 483 0, NULL, NULL, &ctlr->dma_tag)) { 484 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, 485 ctlr->r_mem); 486 rman_fini(&ctlr->sc_iomem); 487 return ENXIO; 488 } 489 490 ahci_ctlr_setup(dev); 491 /* Setup interrupts. */ 492 if (ahci_setup_interrupt(dev)) { 493 bus_dma_tag_destroy(ctlr->dma_tag); 494 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 495 rman_fini(&ctlr->sc_iomem); 496 return ENXIO; 497 } 498 /* Announce HW capabilities. */ 499 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 500 device_printf(dev, 501 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 502 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 503 ((version >> 4) & 0xf0) + (version & 0x0f), 504 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 505 ((speed == 1) ? "1.5":((speed == 2) ? "3": 506 ((speed == 3) ? "6":"?"))), 507 (ctlr->caps & AHCI_CAP_SPM) ? 508 "supported" : "not supported", 509 (ctlr->caps & AHCI_CAP_FBSS) ? 510 " with FBS" : ""); 511 if (ctlr->quirks != 0) { 512 device_printf(dev, "quirks=0x%b\n", ctlr->quirks, 513 AHCI_Q_BIT_STRING); 514 } 515 if (bootverbose) { 516 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 517 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 518 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 519 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 520 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 521 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 522 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 523 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 524 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 525 ((speed == 1) ? "1.5":((speed == 2) ? "3": 526 ((speed == 3) ? "6":"?")))); 527 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 528 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 529 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 530 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 531 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 532 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 533 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 534 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 535 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 536 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 537 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 538 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 539 } 540 if (bootverbose && version >= 0x00010200) { 541 device_printf(dev, "Caps2:%s%s%s\n", 542 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 543 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 544 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 545 } 546 /* Attach all channels on this controller */ 547 for (unit = 0; unit < ctlr->channels; unit++) { 548 child = device_add_child(dev, "ahcich", -1); 549 if (child == NULL) { 550 device_printf(dev, "failed to add channel device\n"); 551 continue; 552 } 553 device_set_ivars(child, (void *)(intptr_t)unit); 554 if ((ctlr->ichannels & (1 << unit)) == 0) 555 device_disable(child); 556 } 557 if (ctlr->caps & AHCI_CAP_EMS) { 558 child = device_add_child(dev, "ahciem", -1); 559 if (child == NULL) 560 device_printf(dev, "failed to add enclosure device\n"); 561 else 562 device_set_ivars(child, (void *)(intptr_t)-1); 563 } 564 bus_generic_attach(dev); 565 return 0; 566} 567 568static int 569ahci_detach(device_t dev) 570{ 571 struct ahci_controller *ctlr = device_get_softc(dev); 572 int i; 573 574 /* Detach & delete all children */ 575 device_delete_children(dev); 576 577 /* Free interrupts. */ 578 for (i = 0; i < ctlr->numirqs; i++) { 579 if (ctlr->irqs[i].r_irq) { 580 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 581 ctlr->irqs[i].handle); 582 bus_release_resource(dev, SYS_RES_IRQ, 583 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 584 } 585 } 586 pci_release_msi(dev); 587 bus_dma_tag_destroy(ctlr->dma_tag); 588 /* Free memory. */ 589 rman_fini(&ctlr->sc_iomem); 590 if (ctlr->r_mem) 591 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 592 return (0); 593} 594 595static int 596ahci_ctlr_reset(device_t dev) 597{ 598 struct ahci_controller *ctlr = device_get_softc(dev); 599 int timeout; 600 601 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == 0x28298086 && 602 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 603 pci_write_config(dev, 0x92, 0x01, 1); 604 /* Enable AHCI mode */ 605 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 606 /* Reset AHCI controller */ 607 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 608 for (timeout = 1000; timeout > 0; timeout--) { 609 DELAY(1000); 610 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 611 break; 612 } 613 if (timeout == 0) { 614 device_printf(dev, "AHCI controller reset failure\n"); 615 return ENXIO; 616 } 617 /* Reenable AHCI mode */ 618 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 619 return (0); 620} 621 622static int 623ahci_ctlr_setup(device_t dev) 624{ 625 struct ahci_controller *ctlr = device_get_softc(dev); 626 /* Clear interrupts */ 627 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 628 /* Configure CCC */ 629 if (ctlr->ccc) { 630 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 631 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 632 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 633 (4 << AHCI_CCCC_CC_SHIFT) | 634 AHCI_CCCC_EN); 635 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 636 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 637 if (bootverbose) { 638 device_printf(dev, 639 "CCC with %dms/4cmd enabled on vector %d\n", 640 ctlr->ccc, ctlr->cccv); 641 } 642 } 643 /* Enable AHCI interrupts */ 644 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 645 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 646 return (0); 647} 648 649static int 650ahci_suspend(device_t dev) 651{ 652 struct ahci_controller *ctlr = device_get_softc(dev); 653 654 bus_generic_suspend(dev); 655 /* Disable interupts, so the state change(s) doesn't trigger */ 656 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 657 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 658 return 0; 659} 660 661static int 662ahci_resume(device_t dev) 663{ 664 int res; 665 666 if ((res = ahci_ctlr_reset(dev)) != 0) 667 return (res); 668 ahci_ctlr_setup(dev); 669 return (bus_generic_resume(dev)); 670} 671 672static int 673ahci_setup_interrupt(device_t dev) 674{ 675 struct ahci_controller *ctlr = device_get_softc(dev); 676 int i, msi = 1; 677 678 /* Process hints. */ 679 if (ctlr->quirks & AHCI_Q_NOMSI) 680 msi = 0; 681 resource_int_value(device_get_name(dev), 682 device_get_unit(dev), "msi", &msi); 683 if (msi < 0) 684 msi = 0; 685 else if (msi == 1) 686 msi = min(1, pci_msi_count(dev)); 687 else if (msi > 1) 688 msi = pci_msi_count(dev); 689 /* Allocate MSI if needed/present. */ 690 if (msi && pci_alloc_msi(dev, &msi) == 0) { 691 ctlr->numirqs = msi; 692 } else { 693 msi = 0; 694 ctlr->numirqs = 1; 695 } 696 /* Check for single MSI vector fallback. */ 697 if (ctlr->numirqs > 1 && 698 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 699 device_printf(dev, "Falling back to one MSI\n"); 700 ctlr->numirqs = 1; 701 } 702 /* Allocate all IRQs. */ 703 for (i = 0; i < ctlr->numirqs; i++) { 704 ctlr->irqs[i].ctlr = ctlr; 705 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0); 706 if (ctlr->numirqs == 1 || i >= ctlr->channels || 707 (ctlr->ccc && i == ctlr->cccv)) 708 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 709 else if (i == ctlr->numirqs - 1) 710 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 711 else 712 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 713 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 714 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 715 device_printf(dev, "unable to map interrupt\n"); 716 return ENXIO; 717 } 718 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 719 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr, 720 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 721 /* SOS XXX release r_irq */ 722 device_printf(dev, "unable to setup interrupt\n"); 723 return ENXIO; 724 } 725 if (ctlr->numirqs > 1) { 726 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 727 ctlr->irqs[i].handle, 728 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 729 "ch%d" : "%d", i); 730 } 731 } 732 return (0); 733} 734 735/* 736 * Common case interrupt handler. 737 */ 738static void 739ahci_intr(void *data) 740{ 741 struct ahci_controller_irq *irq = data; 742 struct ahci_controller *ctlr = irq->ctlr; 743 u_int32_t is, ise = 0; 744 void *arg; 745 int unit; 746 747 if (irq->mode == AHCI_IRQ_MODE_ALL) { 748 unit = 0; 749 if (ctlr->ccc) 750 is = ctlr->ichannels; 751 else 752 is = ATA_INL(ctlr->r_mem, AHCI_IS); 753 } else { /* AHCI_IRQ_MODE_AFTER */ 754 unit = irq->r_irq_rid - 1; 755 is = ATA_INL(ctlr->r_mem, AHCI_IS); 756 } 757 /* CCC interrupt is edge triggered. */ 758 if (ctlr->ccc) 759 ise = 1 << ctlr->cccv; 760 /* Some controllers have edge triggered IS. */ 761 if (ctlr->quirks & AHCI_Q_EDGEIS) 762 ise |= is; 763 if (ise != 0) 764 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 765 for (; unit < ctlr->channels; unit++) { 766 if ((is & (1 << unit)) != 0 && 767 (arg = ctlr->interrupt[unit].argument)) { 768 ctlr->interrupt[unit].function(arg); 769 } 770 } 771 /* AHCI declares level triggered IS. */ 772 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 773 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 774} 775 776/* 777 * Simplified interrupt handler for multivector MSI mode. 778 */ 779static void 780ahci_intr_one(void *data) 781{ 782 struct ahci_controller_irq *irq = data; 783 struct ahci_controller *ctlr = irq->ctlr; 784 void *arg; 785 int unit; 786 787 unit = irq->r_irq_rid - 1; 788 /* Some controllers have edge triggered IS. */ 789 if (ctlr->quirks & AHCI_Q_EDGEIS) 790 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 791 if ((arg = ctlr->interrupt[unit].argument)) 792 ctlr->interrupt[unit].function(arg); 793 /* AHCI declares level triggered IS. */ 794 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 795 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 796} 797 798static struct resource * 799ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 800 u_long start, u_long end, u_long count, u_int flags) 801{ 802 struct ahci_controller *ctlr = device_get_softc(dev); 803 struct resource *res; 804 long st; 805 int offset, size, unit; 806 807 unit = (intptr_t)device_get_ivars(child); 808 res = NULL; 809 switch (type) { 810 case SYS_RES_MEMORY: 811 if (unit >= 0) { 812 offset = AHCI_OFFSET + (unit << 7); 813 size = 128; 814 } else if (*rid == 0) { 815 offset = AHCI_EM_CTL; 816 size = 4; 817 } else { 818 offset = (ctlr->emloc & 0xffff0000) >> 14; 819 size = (ctlr->emloc & 0x0000ffff) << 2; 820 if (*rid != 1) { 821 if (*rid == 2 && (ctlr->capsem & 822 (AHCI_EM_XMT | AHCI_EM_SMB)) == 0) 823 offset += size; 824 else 825 break; 826 } 827 } 828 st = rman_get_start(ctlr->r_mem); 829 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 830 st + offset + size - 1, size, RF_ACTIVE, child); 831 if (res) { 832 bus_space_handle_t bsh; 833 bus_space_tag_t bst; 834 bsh = rman_get_bushandle(ctlr->r_mem); 835 bst = rman_get_bustag(ctlr->r_mem); 836 bus_space_subregion(bst, bsh, offset, 128, &bsh); 837 rman_set_bushandle(res, bsh); 838 rman_set_bustag(res, bst); 839 } 840 break; 841 case SYS_RES_IRQ: 842 if (*rid == ATA_IRQ_RID) 843 res = ctlr->irqs[0].r_irq; 844 break; 845 } 846 return (res); 847} 848 849static int 850ahci_release_resource(device_t dev, device_t child, int type, int rid, 851 struct resource *r) 852{ 853 854 switch (type) { 855 case SYS_RES_MEMORY: 856 rman_release_resource(r); 857 return (0); 858 case SYS_RES_IRQ: 859 if (rid != ATA_IRQ_RID) 860 return ENOENT; 861 return (0); 862 } 863 return (EINVAL); 864} 865 866static int 867ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 868 int flags, driver_filter_t *filter, driver_intr_t *function, 869 void *argument, void **cookiep) 870{ 871 struct ahci_controller *ctlr = device_get_softc(dev); 872 int unit = (intptr_t)device_get_ivars(child); 873 874 if (filter != NULL) { 875 printf("ahci.c: we cannot use a filter here\n"); 876 return (EINVAL); 877 } 878 ctlr->interrupt[unit].function = function; 879 ctlr->interrupt[unit].argument = argument; 880 return (0); 881} 882 883static int 884ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 885 void *cookie) 886{ 887 struct ahci_controller *ctlr = device_get_softc(dev); 888 int unit = (intptr_t)device_get_ivars(child); 889 890 ctlr->interrupt[unit].function = NULL; 891 ctlr->interrupt[unit].argument = NULL; 892 return (0); 893} 894 895static int 896ahci_print_child(device_t dev, device_t child) 897{ 898 int retval, channel; 899 900 retval = bus_print_child_header(dev, child); 901 channel = (int)(intptr_t)device_get_ivars(child); 902 if (channel >= 0) 903 retval += printf(" at channel %d", channel); 904 retval += bus_print_child_footer(dev, child); 905 return (retval); 906} 907 908static int 909ahci_child_location_str(device_t dev, device_t child, char *buf, 910 size_t buflen) 911{ 912 int channel; 913 914 channel = (int)(intptr_t)device_get_ivars(child); 915 if (channel >= 0) 916 snprintf(buf, buflen, "channel=%d", channel); 917 return (0); 918} 919 920static bus_dma_tag_t 921ahci_get_dma_tag(device_t dev, device_t child) 922{ 923 struct ahci_controller *ctlr = device_get_softc(dev); 924 925 return (ctlr->dma_tag); 926} 927 928devclass_t ahci_devclass; 929static device_method_t ahci_methods[] = { 930 DEVMETHOD(device_probe, ahci_probe), 931 DEVMETHOD(device_attach, ahci_attach), 932 DEVMETHOD(device_detach, ahci_detach), 933 DEVMETHOD(device_suspend, ahci_suspend), 934 DEVMETHOD(device_resume, ahci_resume), 935 DEVMETHOD(bus_print_child, ahci_print_child), 936 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 937 DEVMETHOD(bus_release_resource, ahci_release_resource), 938 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 939 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 940 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 941 DEVMETHOD(bus_get_dma_tag, ahci_get_dma_tag), 942 { 0, 0 } 943}; 944static driver_t ahci_driver = { 945 "ahci", 946 ahci_methods, 947 sizeof(struct ahci_controller) 948}; 949DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 950static device_method_t ahci_ata_methods[] = { 951 DEVMETHOD(device_probe, ahci_ata_probe), 952 DEVMETHOD(device_attach, ahci_attach), 953 DEVMETHOD(device_detach, ahci_detach), 954 DEVMETHOD(device_suspend, ahci_suspend), 955 DEVMETHOD(device_resume, ahci_resume), 956 DEVMETHOD(bus_print_child, ahci_print_child), 957 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 958 DEVMETHOD(bus_release_resource, ahci_release_resource), 959 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 960 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 961 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 962 { 0, 0 } 963}; 964static driver_t ahci_ata_driver = { 965 "ahci", 966 ahci_ata_methods, 967 sizeof(struct ahci_controller) 968}; 969DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0); 970MODULE_VERSION(ahci, 1); 971MODULE_DEPEND(ahci, cam, 1, 1, 1); 972 973static int 974ahci_ch_probe(device_t dev) 975{ 976 977 device_set_desc_copy(dev, "AHCI channel"); 978 return (0); 979} 980 981static int 982ahci_ch_attach(device_t dev) 983{ 984 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 985 struct ahci_channel *ch = device_get_softc(dev); 986 struct cam_devq *devq; 987 int rid, error, i, sata_rev = 0; 988 u_int32_t version; 989 990 ch->dev = dev; 991 ch->unit = (intptr_t)device_get_ivars(dev); 992 ch->caps = ctlr->caps; 993 ch->caps2 = ctlr->caps2; 994 ch->quirks = ctlr->quirks; 995 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 996 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 997 resource_int_value(device_get_name(dev), 998 device_get_unit(dev), "pm_level", &ch->pm_level); 999 if (ch->pm_level > 3) 1000 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 1001 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 1002 /* Limit speed for my onboard JMicron external port. 1003 * It is not eSATA really. */ 1004 if (pci_get_devid(ctlr->dev) == 0x2363197b && 1005 pci_get_subvendor(ctlr->dev) == 0x1043 && 1006 pci_get_subdevice(ctlr->dev) == 0x81e4 && 1007 ch->unit == 0) 1008 sata_rev = 1; 1009 if (ch->quirks & AHCI_Q_SATA2) 1010 sata_rev = 2; 1011 resource_int_value(device_get_name(dev), 1012 device_get_unit(dev), "sata_rev", &sata_rev); 1013 for (i = 0; i < 16; i++) { 1014 ch->user[i].revision = sata_rev; 1015 ch->user[i].mode = 0; 1016 ch->user[i].bytecount = 8192; 1017 ch->user[i].tags = ch->numslots; 1018 ch->user[i].caps = 0; 1019 ch->curr[i] = ch->user[i]; 1020 if (ch->pm_level) { 1021 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 1022 CTS_SATA_CAPS_H_APST | 1023 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 1024 } 1025 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA | 1026 CTS_SATA_CAPS_H_AN; 1027 } 1028 rid = 0; 1029 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1030 &rid, RF_ACTIVE))) 1031 return (ENXIO); 1032 ahci_dmainit(dev); 1033 ahci_slotsalloc(dev); 1034 ahci_ch_init(dev); 1035 mtx_lock(&ch->mtx); 1036 rid = ATA_IRQ_RID; 1037 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1038 &rid, RF_SHAREABLE | RF_ACTIVE))) { 1039 device_printf(dev, "Unable to map interrupt\n"); 1040 error = ENXIO; 1041 goto err0; 1042 } 1043 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 1044 ahci_ch_intr_locked, dev, &ch->ih))) { 1045 device_printf(dev, "Unable to setup interrupt\n"); 1046 error = ENXIO; 1047 goto err1; 1048 } 1049 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 1050 version = ATA_INL(ctlr->r_mem, AHCI_VS); 1051 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS)) 1052 ch->chcaps |= AHCI_P_CMD_FBSCP; 1053 if (bootverbose) { 1054 device_printf(dev, "Caps:%s%s%s%s%s\n", 1055 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 1056 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 1057 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 1058 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 1059 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":""); 1060 } 1061 /* Create the device queue for our SIM. */ 1062 devq = cam_simq_alloc(ch->numslots); 1063 if (devq == NULL) { 1064 device_printf(dev, "Unable to allocate simq\n"); 1065 error = ENOMEM; 1066 goto err1; 1067 } 1068 /* Construct SIM entry */ 1069 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 1070 device_get_unit(dev), &ch->mtx, 1071 min(2, ch->numslots), 1072 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 1073 devq); 1074 if (ch->sim == NULL) { 1075 cam_simq_free(devq); 1076 device_printf(dev, "unable to allocate sim\n"); 1077 error = ENOMEM; 1078 goto err1; 1079 } 1080 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 1081 device_printf(dev, "unable to register xpt bus\n"); 1082 error = ENXIO; 1083 goto err2; 1084 } 1085 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 1086 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1087 device_printf(dev, "unable to create path\n"); 1088 error = ENXIO; 1089 goto err3; 1090 } 1091 if (ch->pm_level > 3) { 1092 callout_reset(&ch->pm_timer, 1093 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 1094 ahci_ch_pm, dev); 1095 } 1096 mtx_unlock(&ch->mtx); 1097 return (0); 1098 1099err3: 1100 xpt_bus_deregister(cam_sim_path(ch->sim)); 1101err2: 1102 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1103err1: 1104 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1105err0: 1106 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1107 mtx_unlock(&ch->mtx); 1108 mtx_destroy(&ch->mtx); 1109 return (error); 1110} 1111 1112static int 1113ahci_ch_detach(device_t dev) 1114{ 1115 struct ahci_channel *ch = device_get_softc(dev); 1116 1117 mtx_lock(&ch->mtx); 1118 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 1119 /* Forget about reset. */ 1120 if (ch->resetting) { 1121 ch->resetting = 0; 1122 xpt_release_simq(ch->sim, TRUE); 1123 } 1124 xpt_free_path(ch->path); 1125 xpt_bus_deregister(cam_sim_path(ch->sim)); 1126 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1127 mtx_unlock(&ch->mtx); 1128 1129 if (ch->pm_level > 3) 1130 callout_drain(&ch->pm_timer); 1131 callout_drain(&ch->reset_timer); 1132 bus_teardown_intr(dev, ch->r_irq, ch->ih); 1133 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1134 1135 ahci_ch_deinit(dev); 1136 ahci_slotsfree(dev); 1137 ahci_dmafini(dev); 1138 1139 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1140 mtx_destroy(&ch->mtx); 1141 return (0); 1142} 1143 1144static int 1145ahci_ch_init(device_t dev) 1146{ 1147 struct ahci_channel *ch = device_get_softc(dev); 1148 uint64_t work; 1149 1150 /* Disable port interrupts */ 1151 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1152 /* Setup work areas */ 1153 work = ch->dma.work_bus + AHCI_CL_OFFSET; 1154 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 1155 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 1156 work = ch->dma.rfis_bus; 1157 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 1158 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 1159 /* Activate the channel and power/spin up device */ 1160 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 1161 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1162 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 1163 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 1164 ahci_start_fr(dev); 1165 ahci_start(dev, 1); 1166 return (0); 1167} 1168 1169static int 1170ahci_ch_deinit(device_t dev) 1171{ 1172 struct ahci_channel *ch = device_get_softc(dev); 1173 1174 /* Disable port interrupts. */ 1175 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1176 /* Reset command register. */ 1177 ahci_stop(dev); 1178 ahci_stop_fr(dev); 1179 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 1180 /* Allow everything, including partial and slumber modes. */ 1181 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 1182 /* Request slumber mode transition and give some time to get there. */ 1183 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 1184 DELAY(100); 1185 /* Disable PHY. */ 1186 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 1187 return (0); 1188} 1189 1190static int 1191ahci_ch_suspend(device_t dev) 1192{ 1193 struct ahci_channel *ch = device_get_softc(dev); 1194 1195 mtx_lock(&ch->mtx); 1196 xpt_freeze_simq(ch->sim, 1); 1197 /* Forget about reset. */ 1198 if (ch->resetting) { 1199 ch->resetting = 0; 1200 callout_stop(&ch->reset_timer); 1201 xpt_release_simq(ch->sim, TRUE); 1202 } 1203 while (ch->oslots) 1204 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 1205 ahci_ch_deinit(dev); 1206 mtx_unlock(&ch->mtx); 1207 return (0); 1208} 1209 1210static int 1211ahci_ch_resume(device_t dev) 1212{ 1213 struct ahci_channel *ch = device_get_softc(dev); 1214 1215 mtx_lock(&ch->mtx); 1216 ahci_ch_init(dev); 1217 ahci_reset(dev); 1218 xpt_release_simq(ch->sim, TRUE); 1219 mtx_unlock(&ch->mtx); 1220 return (0); 1221} 1222 1223devclass_t ahcich_devclass; 1224static device_method_t ahcich_methods[] = { 1225 DEVMETHOD(device_probe, ahci_ch_probe), 1226 DEVMETHOD(device_attach, ahci_ch_attach), 1227 DEVMETHOD(device_detach, ahci_ch_detach), 1228 DEVMETHOD(device_suspend, ahci_ch_suspend), 1229 DEVMETHOD(device_resume, ahci_ch_resume), 1230 { 0, 0 } 1231}; 1232static driver_t ahcich_driver = { 1233 "ahcich", 1234 ahcich_methods, 1235 sizeof(struct ahci_channel) 1236}; 1237DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0); 1238 1239struct ahci_dc_cb_args { 1240 bus_addr_t maddr; 1241 int error; 1242}; 1243 1244static void 1245ahci_dmainit(device_t dev) 1246{ 1247 struct ahci_channel *ch = device_get_softc(dev); 1248 struct ahci_dc_cb_args dcba; 1249 size_t rfsize; 1250 1251 /* Command area. */ 1252 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1253 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1254 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1255 0, NULL, NULL, &ch->dma.work_tag)) 1256 goto error; 1257 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 1258 BUS_DMA_ZERO, &ch->dma.work_map)) 1259 goto error; 1260 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1261 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1262 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1263 goto error; 1264 } 1265 ch->dma.work_bus = dcba.maddr; 1266 /* FIS receive area. */ 1267 if (ch->chcaps & AHCI_P_CMD_FBSCP) 1268 rfsize = 4096; 1269 else 1270 rfsize = 256; 1271 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 1272 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1273 NULL, NULL, rfsize, 1, rfsize, 1274 0, NULL, NULL, &ch->dma.rfis_tag)) 1275 goto error; 1276 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1277 &ch->dma.rfis_map)) 1278 goto error; 1279 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1280 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1281 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1282 goto error; 1283 } 1284 ch->dma.rfis_bus = dcba.maddr; 1285 /* Data area. */ 1286 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1287 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1288 NULL, NULL, 1289 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1290 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1291 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 1292 goto error; 1293 } 1294 return; 1295 1296error: 1297 device_printf(dev, "WARNING - DMA initialization failed\n"); 1298 ahci_dmafini(dev); 1299} 1300 1301static void 1302ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1303{ 1304 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1305 1306 if (!(dcba->error = error)) 1307 dcba->maddr = segs[0].ds_addr; 1308} 1309 1310static void 1311ahci_dmafini(device_t dev) 1312{ 1313 struct ahci_channel *ch = device_get_softc(dev); 1314 1315 if (ch->dma.data_tag) { 1316 bus_dma_tag_destroy(ch->dma.data_tag); 1317 ch->dma.data_tag = NULL; 1318 } 1319 if (ch->dma.rfis_bus) { 1320 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1321 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1322 ch->dma.rfis_bus = 0; 1323 ch->dma.rfis_map = NULL; 1324 ch->dma.rfis = NULL; 1325 } 1326 if (ch->dma.work_bus) { 1327 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1328 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1329 ch->dma.work_bus = 0; 1330 ch->dma.work_map = NULL; 1331 ch->dma.work = NULL; 1332 } 1333 if (ch->dma.work_tag) { 1334 bus_dma_tag_destroy(ch->dma.work_tag); 1335 ch->dma.work_tag = NULL; 1336 } 1337} 1338 1339static void 1340ahci_slotsalloc(device_t dev) 1341{ 1342 struct ahci_channel *ch = device_get_softc(dev); 1343 int i; 1344 1345 /* Alloc and setup command/dma slots */ 1346 bzero(ch->slot, sizeof(ch->slot)); 1347 for (i = 0; i < ch->numslots; i++) { 1348 struct ahci_slot *slot = &ch->slot[i]; 1349 1350 slot->dev = dev; 1351 slot->slot = i; 1352 slot->state = AHCI_SLOT_EMPTY; 1353 slot->ccb = NULL; 1354 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1355 1356 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1357 device_printf(ch->dev, "FAILURE - create data_map\n"); 1358 } 1359} 1360 1361static void 1362ahci_slotsfree(device_t dev) 1363{ 1364 struct ahci_channel *ch = device_get_softc(dev); 1365 int i; 1366 1367 /* Free all dma slots */ 1368 for (i = 0; i < ch->numslots; i++) { 1369 struct ahci_slot *slot = &ch->slot[i]; 1370 1371 callout_drain(&slot->timeout); 1372 if (slot->dma.data_map) { 1373 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1374 slot->dma.data_map = NULL; 1375 } 1376 } 1377} 1378 1379static int 1380ahci_phy_check_events(device_t dev, u_int32_t serr) 1381{ 1382 struct ahci_channel *ch = device_get_softc(dev); 1383 1384 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 1385 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) { 1386 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1387 union ccb *ccb; 1388 1389 if (bootverbose) { 1390 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 1391 device_printf(dev, "CONNECT requested\n"); 1392 else 1393 device_printf(dev, "DISCONNECT requested\n"); 1394 } 1395 ahci_reset(dev); 1396 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1397 return (0); 1398 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1399 cam_sim_path(ch->sim), 1400 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1401 xpt_free_ccb(ccb); 1402 return (0); 1403 } 1404 xpt_rescan(ccb); 1405 return (1); 1406 } 1407 return (0); 1408} 1409 1410static void 1411ahci_cpd_check_events(device_t dev) 1412{ 1413 struct ahci_channel *ch = device_get_softc(dev); 1414 u_int32_t status; 1415 union ccb *ccb; 1416 1417 if (ch->pm_level == 0) 1418 return; 1419 1420 status = ATA_INL(ch->r_mem, AHCI_P_CMD); 1421 if ((status & AHCI_P_CMD_CPD) == 0) 1422 return; 1423 1424 if (bootverbose) { 1425 if (status & AHCI_P_CMD_CPS) { 1426 device_printf(dev, "COLD CONNECT requested\n"); 1427 } else 1428 device_printf(dev, "COLD DISCONNECT requested\n"); 1429 } 1430 ahci_reset(dev); 1431 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1432 return; 1433 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim), 1434 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1435 xpt_free_ccb(ccb); 1436 return; 1437 } 1438 xpt_rescan(ccb); 1439} 1440 1441static void 1442ahci_notify_events(device_t dev, u_int32_t status) 1443{ 1444 struct ahci_channel *ch = device_get_softc(dev); 1445 struct cam_path *dpath; 1446 int i; 1447 1448 if (ch->caps & AHCI_CAP_SSNTF) 1449 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1450 if (bootverbose) 1451 device_printf(dev, "SNTF 0x%04x\n", status); 1452 for (i = 0; i < 16; i++) { 1453 if ((status & (1 << i)) == 0) 1454 continue; 1455 if (xpt_create_path(&dpath, NULL, 1456 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1457 xpt_async(AC_SCSI_AEN, dpath, NULL); 1458 xpt_free_path(dpath); 1459 } 1460 } 1461} 1462 1463static void 1464ahci_ch_intr_locked(void *data) 1465{ 1466 device_t dev = (device_t)data; 1467 struct ahci_channel *ch = device_get_softc(dev); 1468 1469 mtx_lock(&ch->mtx); 1470 xpt_batch_start(ch->sim); 1471 ahci_ch_intr(data); 1472 xpt_batch_done(ch->sim); 1473 mtx_unlock(&ch->mtx); 1474} 1475 1476static void 1477ahci_ch_pm(void *arg) 1478{ 1479 device_t dev = (device_t)arg; 1480 struct ahci_channel *ch = device_get_softc(dev); 1481 uint32_t work; 1482 1483 if (ch->numrslots != 0) 1484 return; 1485 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1486 if (ch->pm_level == 4) 1487 work |= AHCI_P_CMD_PARTIAL; 1488 else 1489 work |= AHCI_P_CMD_SLUMBER; 1490 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1491} 1492 1493static void 1494ahci_ch_intr(void *data) 1495{ 1496 device_t dev = (device_t)data; 1497 struct ahci_channel *ch = device_get_softc(dev); 1498 uint32_t istatus, cstatus, serr = 0, sntf = 0, ok, err; 1499 enum ahci_err_type et; 1500 int i, ccs, port, reset = 0; 1501 1502 /* Read and clear interrupt statuses. */ 1503 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1504 if (istatus == 0) 1505 return; 1506 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1507 /* Read command statuses. */ 1508 if (ch->numtslots != 0) 1509 cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1510 else 1511 cstatus = 0; 1512 if (ch->numrslots != ch->numtslots) 1513 cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI); 1514 /* Read SNTF in one of possible ways. */ 1515 if ((istatus & AHCI_P_IX_SDB) && 1516 (ch->pm_present || ch->curr[0].atapi != 0)) { 1517 if (ch->caps & AHCI_CAP_SSNTF) 1518 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1519 else if (ch->fbs_enabled) { 1520 u_int8_t *fis = ch->dma.rfis + 0x58; 1521 1522 for (i = 0; i < 16; i++) { 1523 if (fis[1] & 0x80) { 1524 fis[1] &= 0x7f; 1525 sntf |= 1 << i; 1526 } 1527 fis += 256; 1528 } 1529 } else { 1530 u_int8_t *fis = ch->dma.rfis + 0x58; 1531 1532 if (fis[1] & 0x80) 1533 sntf = (1 << (fis[1] & 0x0f)); 1534 } 1535 } 1536 /* Process PHY events */ 1537 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1538 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1539 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1540 if (serr) { 1541 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1542 reset = ahci_phy_check_events(dev, serr); 1543 } 1544 } 1545 /* Process cold presence detection events */ 1546 if ((istatus & AHCI_P_IX_CPD) && !reset) 1547 ahci_cpd_check_events(dev); 1548 /* Process command errors */ 1549 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1550 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1551 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1552 >> AHCI_P_CMD_CCS_SHIFT; 1553//device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1554// __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1555// serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1556 port = -1; 1557 if (ch->fbs_enabled) { 1558 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1559 if (fbs & AHCI_P_FBS_SDE) { 1560 port = (fbs & AHCI_P_FBS_DWE) 1561 >> AHCI_P_FBS_DWE_SHIFT; 1562 } else { 1563 for (i = 0; i < 16; i++) { 1564 if (ch->numrslotspd[i] == 0) 1565 continue; 1566 if (port == -1) 1567 port = i; 1568 else if (port != i) { 1569 port = -2; 1570 break; 1571 } 1572 } 1573 } 1574 } 1575 err = ch->rslots & cstatus; 1576 } else { 1577 ccs = 0; 1578 err = 0; 1579 port = -1; 1580 } 1581 /* Complete all successfull commands. */ 1582 ok = ch->rslots & ~cstatus; 1583 for (i = 0; i < ch->numslots; i++) { 1584 if ((ok >> i) & 1) 1585 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1586 } 1587 /* On error, complete the rest of commands with error statuses. */ 1588 if (err) { 1589 if (ch->frozen) { 1590 union ccb *fccb = ch->frozen; 1591 ch->frozen = NULL; 1592 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1593 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1594 xpt_freeze_devq(fccb->ccb_h.path, 1); 1595 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1596 } 1597 xpt_done(fccb); 1598 } 1599 for (i = 0; i < ch->numslots; i++) { 1600 /* XXX: reqests in loading state. */ 1601 if (((err >> i) & 1) == 0) 1602 continue; 1603 if (port >= 0 && 1604 ch->slot[i].ccb->ccb_h.target_id != port) 1605 continue; 1606 if (istatus & AHCI_P_IX_TFE) { 1607 if (port != -2) { 1608 /* Task File Error */ 1609 if (ch->numtslotspd[ 1610 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1611 /* Untagged operation. */ 1612 if (i == ccs) 1613 et = AHCI_ERR_TFE; 1614 else 1615 et = AHCI_ERR_INNOCENT; 1616 } else { 1617 /* Tagged operation. */ 1618 et = AHCI_ERR_NCQ; 1619 } 1620 } else { 1621 et = AHCI_ERR_TFE; 1622 ch->fatalerr = 1; 1623 } 1624 } else if (istatus & AHCI_P_IX_IF) { 1625 if (ch->numtslots == 0 && i != ccs && port != -2) 1626 et = AHCI_ERR_INNOCENT; 1627 else 1628 et = AHCI_ERR_SATA; 1629 } else 1630 et = AHCI_ERR_INVALID; 1631 ahci_end_transaction(&ch->slot[i], et); 1632 } 1633 /* 1634 * We can't reinit port if there are some other 1635 * commands active, use resume to complete them. 1636 */ 1637 if (ch->rslots != 0 && !ch->recoverycmd) 1638 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1639 } 1640 /* Process NOTIFY events */ 1641 if (sntf) 1642 ahci_notify_events(dev, sntf); 1643} 1644 1645/* Must be called with channel locked. */ 1646static int 1647ahci_check_collision(device_t dev, union ccb *ccb) 1648{ 1649 struct ahci_channel *ch = device_get_softc(dev); 1650 int t = ccb->ccb_h.target_id; 1651 1652 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1653 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1654 /* Tagged command while we have no supported tag free. */ 1655 if (((~ch->oslots) & (0xffffffff >> (32 - 1656 ch->curr[t].tags))) == 0) 1657 return (1); 1658 /* If we have FBS */ 1659 if (ch->fbs_enabled) { 1660 /* Tagged command while untagged are active. */ 1661 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1662 return (1); 1663 } else { 1664 /* Tagged command while untagged are active. */ 1665 if (ch->numrslots != 0 && ch->numtslots == 0) 1666 return (1); 1667 /* Tagged command while tagged to other target is active. */ 1668 if (ch->numtslots != 0 && 1669 ch->taggedtarget != ccb->ccb_h.target_id) 1670 return (1); 1671 } 1672 } else { 1673 /* If we have FBS */ 1674 if (ch->fbs_enabled) { 1675 /* Untagged command while tagged are active. */ 1676 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1677 return (1); 1678 } else { 1679 /* Untagged command while tagged are active. */ 1680 if (ch->numrslots != 0 && ch->numtslots != 0) 1681 return (1); 1682 } 1683 } 1684 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1685 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1686 /* Atomic command while anything active. */ 1687 if (ch->numrslots != 0) 1688 return (1); 1689 } 1690 /* We have some atomic command running. */ 1691 if (ch->aslots != 0) 1692 return (1); 1693 return (0); 1694} 1695 1696/* Must be called with channel locked. */ 1697static void 1698ahci_begin_transaction(device_t dev, union ccb *ccb) 1699{ 1700 struct ahci_channel *ch = device_get_softc(dev); 1701 struct ahci_slot *slot; 1702 int tag, tags; 1703 1704 /* Choose empty slot. */ 1705 tags = ch->numslots; 1706 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1707 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1708 tags = ch->curr[ccb->ccb_h.target_id].tags; 1709 tag = ch->lastslot; 1710 while (1) { 1711 if (tag >= tags) 1712 tag = 0; 1713 if (ch->slot[tag].state == AHCI_SLOT_EMPTY) 1714 break; 1715 tag++; 1716 }; 1717 ch->lastslot = tag; 1718 /* Occupy chosen slot. */ 1719 slot = &ch->slot[tag]; 1720 slot->ccb = ccb; 1721 /* Stop PM timer. */ 1722 if (ch->numrslots == 0 && ch->pm_level > 3) 1723 callout_stop(&ch->pm_timer); 1724 /* Update channel stats. */ 1725 ch->oslots |= (1 << slot->slot); 1726 ch->numrslots++; 1727 ch->numrslotspd[ccb->ccb_h.target_id]++; 1728 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1729 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1730 ch->numtslots++; 1731 ch->numtslotspd[ccb->ccb_h.target_id]++; 1732 ch->taggedtarget = ccb->ccb_h.target_id; 1733 } 1734 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1735 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1736 ch->aslots |= (1 << slot->slot); 1737 slot->dma.nsegs = 0; 1738 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1739 slot->state = AHCI_SLOT_LOADING; 1740 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb, 1741 ahci_dmasetprd, slot, 0); 1742 } else 1743 ahci_execute_transaction(slot); 1744} 1745 1746/* Locked by busdma engine. */ 1747static void 1748ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1749{ 1750 struct ahci_slot *slot = arg; 1751 struct ahci_channel *ch = device_get_softc(slot->dev); 1752 struct ahci_cmd_tab *ctp; 1753 struct ahci_dma_prd *prd; 1754 int i; 1755 1756 if (error) { 1757 device_printf(slot->dev, "DMA load error\n"); 1758 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1759 return; 1760 } 1761 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1762 /* Get a piece of the workspace for this request */ 1763 ctp = (struct ahci_cmd_tab *) 1764 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1765 /* Fill S/G table */ 1766 prd = &ctp->prd_tab[0]; 1767 for (i = 0; i < nsegs; i++) { 1768 prd[i].dba = htole64(segs[i].ds_addr); 1769 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1770 } 1771 slot->dma.nsegs = nsegs; 1772 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1773 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1774 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1775 ahci_execute_transaction(slot); 1776} 1777 1778/* Must be called with channel locked. */ 1779static void 1780ahci_execute_transaction(struct ahci_slot *slot) 1781{ 1782 device_t dev = slot->dev; 1783 struct ahci_channel *ch = device_get_softc(dev); 1784 struct ahci_cmd_tab *ctp; 1785 struct ahci_cmd_list *clp; 1786 union ccb *ccb = slot->ccb; 1787 int port = ccb->ccb_h.target_id & 0x0f; 1788 int fis_size, i, softreset; 1789 uint8_t *fis = ch->dma.rfis + 0x40; 1790 uint8_t val; 1791 1792 /* Get a piece of the workspace for this request */ 1793 ctp = (struct ahci_cmd_tab *) 1794 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1795 /* Setup the FIS for this request */ 1796 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) { 1797 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1798 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1799 return; 1800 } 1801 /* Setup the command list entry */ 1802 clp = (struct ahci_cmd_list *) 1803 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1804 clp->cmd_flags = htole16( 1805 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1806 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1807 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1808 (fis_size / sizeof(u_int32_t)) | 1809 (port << 12)); 1810 clp->prd_length = htole16(slot->dma.nsegs); 1811 /* Special handling for Soft Reset command. */ 1812 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1813 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1814 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1815 softreset = 1; 1816 /* Kick controller into sane state */ 1817 ahci_stop(dev); 1818 ahci_clo(dev); 1819 ahci_start(dev, 0); 1820 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1821 } else { 1822 softreset = 2; 1823 /* Prepare FIS receive area for check. */ 1824 for (i = 0; i < 20; i++) 1825 fis[i] = 0xff; 1826 } 1827 } else 1828 softreset = 0; 1829 clp->bytecount = 0; 1830 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1831 (AHCI_CT_SIZE * slot->slot)); 1832 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1833 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1834 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1835 BUS_DMASYNC_PREREAD); 1836 /* Set ACTIVE bit for NCQ commands. */ 1837 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1838 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1839 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1840 } 1841 /* If FBS is enabled, set PMP port. */ 1842 if (ch->fbs_enabled) { 1843 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1844 (port << AHCI_P_FBS_DEV_SHIFT)); 1845 } 1846 /* Issue command to the controller. */ 1847 slot->state = AHCI_SLOT_RUNNING; 1848 ch->rslots |= (1 << slot->slot); 1849 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1850 /* Device reset commands doesn't interrupt. Poll them. */ 1851 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1852 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) { 1853 int count, timeout = ccb->ccb_h.timeout * 100; 1854 enum ahci_err_type et = AHCI_ERR_NONE; 1855 1856 for (count = 0; count < timeout; count++) { 1857 DELAY(10); 1858 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1859 break; 1860 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) && 1861 softreset != 1) { 1862#if 0 1863 device_printf(ch->dev, 1864 "Poll error on slot %d, TFD: %04x\n", 1865 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1866#endif 1867 et = AHCI_ERR_TFE; 1868 break; 1869 } 1870 /* Workaround for ATI SB600/SB700 chipsets. */ 1871 if (ccb->ccb_h.target_id == 15 && 1872 pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1873 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1874 et = AHCI_ERR_TIMEOUT; 1875 break; 1876 } 1877 } 1878 1879 /* Marvell controllers do not wait for readyness. */ 1880 if ((ch->quirks & AHCI_Q_NOBSYRES) && softreset == 2 && 1881 et == AHCI_ERR_NONE) { 1882 while ((val = fis[2]) & ATA_S_BUSY) { 1883 DELAY(10); 1884 if (count++ >= timeout) 1885 break; 1886 } 1887 } 1888 1889 if (timeout && (count >= timeout)) { 1890 device_printf(dev, "Poll timeout on slot %d port %d\n", 1891 slot->slot, port); 1892 device_printf(dev, "is %08x cs %08x ss %08x " 1893 "rs %08x tfd %02x serr %08x cmd %08x\n", 1894 ATA_INL(ch->r_mem, AHCI_P_IS), 1895 ATA_INL(ch->r_mem, AHCI_P_CI), 1896 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1897 ATA_INL(ch->r_mem, AHCI_P_TFD), 1898 ATA_INL(ch->r_mem, AHCI_P_SERR), 1899 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1900 et = AHCI_ERR_TIMEOUT; 1901 } 1902 1903 /* Kick controller into sane state and enable FBS. */ 1904 if (softreset == 2) 1905 ch->eslots |= (1 << slot->slot); 1906 ahci_end_transaction(slot, et); 1907 return; 1908 } 1909 /* Start command execution timeout */ 1910 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 1911 (timeout_t*)ahci_timeout, slot); 1912 return; 1913} 1914 1915/* Must be called with channel locked. */ 1916static void 1917ahci_process_timeout(device_t dev) 1918{ 1919 struct ahci_channel *ch = device_get_softc(dev); 1920 int i; 1921 1922 mtx_assert(&ch->mtx, MA_OWNED); 1923 /* Handle the rest of commands. */ 1924 for (i = 0; i < ch->numslots; i++) { 1925 /* Do we have a running request on slot? */ 1926 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1927 continue; 1928 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 1929 } 1930} 1931 1932/* Must be called with channel locked. */ 1933static void 1934ahci_rearm_timeout(device_t dev) 1935{ 1936 struct ahci_channel *ch = device_get_softc(dev); 1937 int i; 1938 1939 mtx_assert(&ch->mtx, MA_OWNED); 1940 for (i = 0; i < ch->numslots; i++) { 1941 struct ahci_slot *slot = &ch->slot[i]; 1942 1943 /* Do we have a running request on slot? */ 1944 if (slot->state < AHCI_SLOT_RUNNING) 1945 continue; 1946 if ((ch->toslots & (1 << i)) == 0) 1947 continue; 1948 callout_reset(&slot->timeout, 1949 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1950 (timeout_t*)ahci_timeout, slot); 1951 } 1952} 1953 1954/* Locked by callout mechanism. */ 1955static void 1956ahci_timeout(struct ahci_slot *slot) 1957{ 1958 device_t dev = slot->dev; 1959 struct ahci_channel *ch = device_get_softc(dev); 1960 uint32_t sstatus; 1961 int ccs; 1962 int i; 1963 1964 /* Check for stale timeout. */ 1965 if (slot->state < AHCI_SLOT_RUNNING) 1966 return; 1967 1968 /* Check if slot was not being executed last time we checked. */ 1969 if (slot->state < AHCI_SLOT_EXECUTING) { 1970 /* Check if slot started executing. */ 1971 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1972 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1973 >> AHCI_P_CMD_CCS_SHIFT; 1974 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 1975 ch->fbs_enabled || ch->wrongccs) 1976 slot->state = AHCI_SLOT_EXECUTING; 1977 else if ((ch->rslots & (1 << ccs)) == 0) { 1978 ch->wrongccs = 1; 1979 slot->state = AHCI_SLOT_EXECUTING; 1980 } 1981 1982 callout_reset(&slot->timeout, 1983 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1984 (timeout_t*)ahci_timeout, slot); 1985 return; 1986 } 1987 1988 device_printf(dev, "Timeout on slot %d port %d\n", 1989 slot->slot, slot->ccb->ccb_h.target_id & 0x0f); 1990 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x " 1991 "serr %08x cmd %08x\n", 1992 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1993 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1994 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR), 1995 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1996 1997 /* Handle frozen command. */ 1998 if (ch->frozen) { 1999 union ccb *fccb = ch->frozen; 2000 ch->frozen = NULL; 2001 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2002 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2003 xpt_freeze_devq(fccb->ccb_h.path, 1); 2004 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2005 } 2006 xpt_done(fccb); 2007 } 2008 if (!ch->fbs_enabled && !ch->wrongccs) { 2009 /* Without FBS we know real timeout source. */ 2010 ch->fatalerr = 1; 2011 /* Handle command with timeout. */ 2012 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 2013 /* Handle the rest of commands. */ 2014 for (i = 0; i < ch->numslots; i++) { 2015 /* Do we have a running request on slot? */ 2016 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2017 continue; 2018 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2019 } 2020 } else { 2021 /* With FBS we wait for other commands timeout and pray. */ 2022 if (ch->toslots == 0) 2023 xpt_freeze_simq(ch->sim, 1); 2024 ch->toslots |= (1 << slot->slot); 2025 if ((ch->rslots & ~ch->toslots) == 0) 2026 ahci_process_timeout(dev); 2027 else 2028 device_printf(dev, " ... waiting for slots %08x\n", 2029 ch->rslots & ~ch->toslots); 2030 } 2031} 2032 2033/* Must be called with channel locked. */ 2034static void 2035ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 2036{ 2037 device_t dev = slot->dev; 2038 struct ahci_channel *ch = device_get_softc(dev); 2039 union ccb *ccb = slot->ccb; 2040 struct ahci_cmd_list *clp; 2041 int lastto; 2042 uint32_t sig; 2043 2044 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 2045 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2046 clp = (struct ahci_cmd_list *) 2047 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 2048 /* Read result registers to the result struct 2049 * May be incorrect if several commands finished same time, 2050 * so read only when sure or have to. 2051 */ 2052 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2053 struct ata_res *res = &ccb->ataio.res; 2054 2055 if ((et == AHCI_ERR_TFE) || 2056 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 2057 u_int8_t *fis = ch->dma.rfis + 0x40; 2058 2059 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 2060 BUS_DMASYNC_POSTREAD); 2061 if (ch->fbs_enabled) { 2062 fis += ccb->ccb_h.target_id * 256; 2063 res->status = fis[2]; 2064 res->error = fis[3]; 2065 } else { 2066 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 2067 2068 res->status = tfd; 2069 res->error = tfd >> 8; 2070 } 2071 res->lba_low = fis[4]; 2072 res->lba_mid = fis[5]; 2073 res->lba_high = fis[6]; 2074 res->device = fis[7]; 2075 res->lba_low_exp = fis[8]; 2076 res->lba_mid_exp = fis[9]; 2077 res->lba_high_exp = fis[10]; 2078 res->sector_count = fis[12]; 2079 res->sector_count_exp = fis[13]; 2080 2081 /* 2082 * Some weird controllers do not return signature in 2083 * FIS receive area. Read it from PxSIG register. 2084 */ 2085 if ((ch->quirks & AHCI_Q_ALTSIG) && 2086 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2087 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 2088 sig = ATA_INL(ch->r_mem, AHCI_P_SIG); 2089 res->lba_high = sig >> 24; 2090 res->lba_mid = sig >> 16; 2091 res->lba_low = sig >> 8; 2092 res->sector_count = sig; 2093 } 2094 } else 2095 bzero(res, sizeof(*res)); 2096 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 2097 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2098 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2099 ccb->ataio.resid = 2100 ccb->ataio.dxfer_len - le32toh(clp->bytecount); 2101 } 2102 } else { 2103 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2104 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2105 ccb->csio.resid = 2106 ccb->csio.dxfer_len - le32toh(clp->bytecount); 2107 } 2108 } 2109 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2110 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 2111 (ccb->ccb_h.flags & CAM_DIR_IN) ? 2112 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2113 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 2114 } 2115 if (et != AHCI_ERR_NONE) 2116 ch->eslots |= (1 << slot->slot); 2117 /* In case of error, freeze device for proper recovery. */ 2118 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) && 2119 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 2120 xpt_freeze_devq(ccb->ccb_h.path, 1); 2121 ccb->ccb_h.status |= CAM_DEV_QFRZN; 2122 } 2123 /* Set proper result status. */ 2124 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2125 switch (et) { 2126 case AHCI_ERR_NONE: 2127 ccb->ccb_h.status |= CAM_REQ_CMP; 2128 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 2129 ccb->csio.scsi_status = SCSI_STATUS_OK; 2130 break; 2131 case AHCI_ERR_INVALID: 2132 ch->fatalerr = 1; 2133 ccb->ccb_h.status |= CAM_REQ_INVALID; 2134 break; 2135 case AHCI_ERR_INNOCENT: 2136 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 2137 break; 2138 case AHCI_ERR_TFE: 2139 case AHCI_ERR_NCQ: 2140 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2141 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2142 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2143 } else { 2144 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 2145 } 2146 break; 2147 case AHCI_ERR_SATA: 2148 ch->fatalerr = 1; 2149 if (!ch->recoverycmd) { 2150 xpt_freeze_simq(ch->sim, 1); 2151 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2152 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2153 } 2154 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 2155 break; 2156 case AHCI_ERR_TIMEOUT: 2157 if (!ch->recoverycmd) { 2158 xpt_freeze_simq(ch->sim, 1); 2159 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2160 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2161 } 2162 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 2163 break; 2164 default: 2165 ch->fatalerr = 1; 2166 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 2167 } 2168 /* Free slot. */ 2169 ch->oslots &= ~(1 << slot->slot); 2170 ch->rslots &= ~(1 << slot->slot); 2171 ch->aslots &= ~(1 << slot->slot); 2172 slot->state = AHCI_SLOT_EMPTY; 2173 slot->ccb = NULL; 2174 /* Update channel stats. */ 2175 ch->numrslots--; 2176 ch->numrslotspd[ccb->ccb_h.target_id]--; 2177 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2178 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 2179 ch->numtslots--; 2180 ch->numtslotspd[ccb->ccb_h.target_id]--; 2181 } 2182 /* Cancel timeout state if request completed normally. */ 2183 if (et != AHCI_ERR_TIMEOUT) { 2184 lastto = (ch->toslots == (1 << slot->slot)); 2185 ch->toslots &= ~(1 << slot->slot); 2186 if (lastto) 2187 xpt_release_simq(ch->sim, TRUE); 2188 } 2189 /* If it was first request of reset sequence and there is no error, 2190 * proceed to second request. */ 2191 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2192 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2193 (ccb->ataio.cmd.control & ATA_A_RESET) && 2194 et == AHCI_ERR_NONE) { 2195 ccb->ataio.cmd.control &= ~ATA_A_RESET; 2196 ahci_begin_transaction(dev, ccb); 2197 return; 2198 } 2199 /* If it was our READ LOG command - process it. */ 2200 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 2201 ahci_process_read_log(dev, ccb); 2202 /* If it was our REQUEST SENSE command - process it. */ 2203 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 2204 ahci_process_request_sense(dev, ccb); 2205 /* If it was NCQ or ATAPI command error, put result on hold. */ 2206 } else if (et == AHCI_ERR_NCQ || 2207 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 2208 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 2209 ch->hold[slot->slot] = ccb; 2210 ch->numhslots++; 2211 } else 2212 xpt_done(ccb); 2213 /* If we have no other active commands, ... */ 2214 if (ch->rslots == 0) { 2215 /* if there was fatal error - reset port. */ 2216 if (ch->toslots != 0 || ch->fatalerr) { 2217 ahci_reset(dev); 2218 } else { 2219 /* if we have slots in error, we can reinit port. */ 2220 if (ch->eslots != 0) { 2221 ahci_stop(dev); 2222 ahci_clo(dev); 2223 ahci_start(dev, 1); 2224 } 2225 /* if there commands on hold, we can do READ LOG. */ 2226 if (!ch->recoverycmd && ch->numhslots) 2227 ahci_issue_recovery(dev); 2228 } 2229 /* If all the rest of commands are in timeout - give them chance. */ 2230 } else if ((ch->rslots & ~ch->toslots) == 0 && 2231 et != AHCI_ERR_TIMEOUT) 2232 ahci_rearm_timeout(dev); 2233 /* Unfreeze frozen command. */ 2234 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) { 2235 union ccb *fccb = ch->frozen; 2236 ch->frozen = NULL; 2237 ahci_begin_transaction(dev, fccb); 2238 xpt_release_simq(ch->sim, TRUE); 2239 } 2240 /* Start PM timer. */ 2241 if (ch->numrslots == 0 && ch->pm_level > 3 && 2242 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 2243 callout_schedule(&ch->pm_timer, 2244 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 2245 } 2246} 2247 2248static void 2249ahci_issue_recovery(device_t dev) 2250{ 2251 struct ahci_channel *ch = device_get_softc(dev); 2252 union ccb *ccb; 2253 struct ccb_ataio *ataio; 2254 struct ccb_scsiio *csio; 2255 int i; 2256 2257 /* Find some held command. */ 2258 for (i = 0; i < ch->numslots; i++) { 2259 if (ch->hold[i]) 2260 break; 2261 } 2262 ccb = xpt_alloc_ccb_nowait(); 2263 if (ccb == NULL) { 2264 device_printf(dev, "Unable to allocate recovery command\n"); 2265completeall: 2266 /* We can't do anything -- complete held commands. */ 2267 for (i = 0; i < ch->numslots; i++) { 2268 if (ch->hold[i] == NULL) 2269 continue; 2270 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2271 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 2272 xpt_done(ch->hold[i]); 2273 ch->hold[i] = NULL; 2274 ch->numhslots--; 2275 } 2276 ahci_reset(dev); 2277 return; 2278 } 2279 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 2280 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2281 /* READ LOG */ 2282 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 2283 ccb->ccb_h.func_code = XPT_ATA_IO; 2284 ccb->ccb_h.flags = CAM_DIR_IN; 2285 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2286 ataio = &ccb->ataio; 2287 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 2288 if (ataio->data_ptr == NULL) { 2289 xpt_free_ccb(ccb); 2290 device_printf(dev, 2291 "Unable to allocate memory for READ LOG command\n"); 2292 goto completeall; 2293 } 2294 ataio->dxfer_len = 512; 2295 bzero(&ataio->cmd, sizeof(ataio->cmd)); 2296 ataio->cmd.flags = CAM_ATAIO_48BIT; 2297 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2298 ataio->cmd.sector_count = 1; 2299 ataio->cmd.sector_count_exp = 0; 2300 ataio->cmd.lba_low = 0x10; 2301 ataio->cmd.lba_mid = 0; 2302 ataio->cmd.lba_mid_exp = 0; 2303 } else { 2304 /* REQUEST SENSE */ 2305 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 2306 ccb->ccb_h.recovery_slot = i; 2307 ccb->ccb_h.func_code = XPT_SCSI_IO; 2308 ccb->ccb_h.flags = CAM_DIR_IN; 2309 ccb->ccb_h.status = 0; 2310 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2311 csio = &ccb->csio; 2312 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 2313 csio->dxfer_len = ch->hold[i]->csio.sense_len; 2314 csio->cdb_len = 6; 2315 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 2316 csio->cdb_io.cdb_bytes[0] = 0x03; 2317 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 2318 } 2319 /* Freeze SIM while doing recovery. */ 2320 ch->recoverycmd = 1; 2321 xpt_freeze_simq(ch->sim, 1); 2322 ahci_begin_transaction(dev, ccb); 2323} 2324 2325static void 2326ahci_process_read_log(device_t dev, union ccb *ccb) 2327{ 2328 struct ahci_channel *ch = device_get_softc(dev); 2329 uint8_t *data; 2330 struct ata_res *res; 2331 int i; 2332 2333 ch->recoverycmd = 0; 2334 2335 data = ccb->ataio.data_ptr; 2336 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2337 (data[0] & 0x80) == 0) { 2338 for (i = 0; i < ch->numslots; i++) { 2339 if (!ch->hold[i]) 2340 continue; 2341 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2342 continue; 2343 if ((data[0] & 0x1F) == i) { 2344 res = &ch->hold[i]->ataio.res; 2345 res->status = data[2]; 2346 res->error = data[3]; 2347 res->lba_low = data[4]; 2348 res->lba_mid = data[5]; 2349 res->lba_high = data[6]; 2350 res->device = data[7]; 2351 res->lba_low_exp = data[8]; 2352 res->lba_mid_exp = data[9]; 2353 res->lba_high_exp = data[10]; 2354 res->sector_count = data[12]; 2355 res->sector_count_exp = data[13]; 2356 } else { 2357 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2358 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2359 } 2360 xpt_done(ch->hold[i]); 2361 ch->hold[i] = NULL; 2362 ch->numhslots--; 2363 } 2364 } else { 2365 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2366 device_printf(dev, "Error while READ LOG EXT\n"); 2367 else if ((data[0] & 0x80) == 0) { 2368 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 2369 } 2370 for (i = 0; i < ch->numslots; i++) { 2371 if (!ch->hold[i]) 2372 continue; 2373 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2374 continue; 2375 xpt_done(ch->hold[i]); 2376 ch->hold[i] = NULL; 2377 ch->numhslots--; 2378 } 2379 } 2380 free(ccb->ataio.data_ptr, M_AHCI); 2381 xpt_free_ccb(ccb); 2382 xpt_release_simq(ch->sim, TRUE); 2383} 2384 2385static void 2386ahci_process_request_sense(device_t dev, union ccb *ccb) 2387{ 2388 struct ahci_channel *ch = device_get_softc(dev); 2389 int i; 2390 2391 ch->recoverycmd = 0; 2392 2393 i = ccb->ccb_h.recovery_slot; 2394 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 2395 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 2396 } else { 2397 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2398 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 2399 } 2400 xpt_done(ch->hold[i]); 2401 ch->hold[i] = NULL; 2402 ch->numhslots--; 2403 xpt_free_ccb(ccb); 2404 xpt_release_simq(ch->sim, TRUE); 2405} 2406 2407static void 2408ahci_start(device_t dev, int fbs) 2409{ 2410 struct ahci_channel *ch = device_get_softc(dev); 2411 u_int32_t cmd; 2412 2413 /* Clear SATA error register */ 2414 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2415 /* Clear any interrupts pending on this channel */ 2416 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2417 /* Configure FIS-based switching if supported. */ 2418 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2419 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2420 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2421 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2422 } 2423 /* Start operations on this channel */ 2424 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2425 cmd &= ~AHCI_P_CMD_PMA; 2426 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2427 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2428} 2429 2430static void 2431ahci_stop(device_t dev) 2432{ 2433 struct ahci_channel *ch = device_get_softc(dev); 2434 u_int32_t cmd; 2435 int timeout; 2436 2437 /* Kill all activity on this channel */ 2438 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2439 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2440 /* Wait for activity stop. */ 2441 timeout = 0; 2442 do { 2443 DELAY(10); 2444 if (timeout++ > 50000) { 2445 device_printf(dev, "stopping AHCI engine failed\n"); 2446 break; 2447 } 2448 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2449 ch->eslots = 0; 2450} 2451 2452static void 2453ahci_clo(device_t dev) 2454{ 2455 struct ahci_channel *ch = device_get_softc(dev); 2456 u_int32_t cmd; 2457 int timeout; 2458 2459 /* Issue Command List Override if supported */ 2460 if (ch->caps & AHCI_CAP_SCLO) { 2461 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2462 cmd |= AHCI_P_CMD_CLO; 2463 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2464 timeout = 0; 2465 do { 2466 DELAY(10); 2467 if (timeout++ > 50000) { 2468 device_printf(dev, "executing CLO failed\n"); 2469 break; 2470 } 2471 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2472 } 2473} 2474 2475static void 2476ahci_stop_fr(device_t dev) 2477{ 2478 struct ahci_channel *ch = device_get_softc(dev); 2479 u_int32_t cmd; 2480 int timeout; 2481 2482 /* Kill all FIS reception on this channel */ 2483 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2484 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2485 /* Wait for FIS reception stop. */ 2486 timeout = 0; 2487 do { 2488 DELAY(10); 2489 if (timeout++ > 50000) { 2490 device_printf(dev, "stopping AHCI FR engine failed\n"); 2491 break; 2492 } 2493 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2494} 2495 2496static void 2497ahci_start_fr(device_t dev) 2498{ 2499 struct ahci_channel *ch = device_get_softc(dev); 2500 u_int32_t cmd; 2501 2502 /* Start FIS reception on this channel */ 2503 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2504 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2505} 2506 2507static int 2508ahci_wait_ready(device_t dev, int t, int t0) 2509{ 2510 struct ahci_channel *ch = device_get_softc(dev); 2511 int timeout = 0; 2512 uint32_t val; 2513 2514 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2515 (ATA_S_BUSY | ATA_S_DRQ)) { 2516 if (timeout > t) { 2517 if (t != 0) { 2518 device_printf(dev, 2519 "AHCI reset: device not ready after %dms " 2520 "(tfd = %08x)\n", 2521 MAX(t, 0) + t0, val); 2522 } 2523 return (EBUSY); 2524 } 2525 DELAY(1000); 2526 timeout++; 2527 } 2528 if (bootverbose) 2529 device_printf(dev, "AHCI reset: device ready after %dms\n", 2530 timeout + t0); 2531 return (0); 2532} 2533 2534static void 2535ahci_reset_to(void *arg) 2536{ 2537 device_t dev = arg; 2538 struct ahci_channel *ch = device_get_softc(dev); 2539 2540 if (ch->resetting == 0) 2541 return; 2542 ch->resetting--; 2543 if (ahci_wait_ready(dev, ch->resetting == 0 ? -1 : 0, 2544 (310 - ch->resetting) * 100) == 0) { 2545 ch->resetting = 0; 2546 ahci_start(dev, 1); 2547 xpt_release_simq(ch->sim, TRUE); 2548 return; 2549 } 2550 if (ch->resetting == 0) { 2551 ahci_clo(dev); 2552 ahci_start(dev, 1); 2553 xpt_release_simq(ch->sim, TRUE); 2554 return; 2555 } 2556 callout_schedule(&ch->reset_timer, hz / 10); 2557} 2558 2559static void 2560ahci_reset(device_t dev) 2561{ 2562 struct ahci_channel *ch = device_get_softc(dev); 2563 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2564 int i; 2565 2566 xpt_freeze_simq(ch->sim, 1); 2567 if (bootverbose) 2568 device_printf(dev, "AHCI reset...\n"); 2569 /* Forget about previous reset. */ 2570 if (ch->resetting) { 2571 ch->resetting = 0; 2572 callout_stop(&ch->reset_timer); 2573 xpt_release_simq(ch->sim, TRUE); 2574 } 2575 /* Requeue freezed command. */ 2576 if (ch->frozen) { 2577 union ccb *fccb = ch->frozen; 2578 ch->frozen = NULL; 2579 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2580 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2581 xpt_freeze_devq(fccb->ccb_h.path, 1); 2582 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2583 } 2584 xpt_done(fccb); 2585 } 2586 /* Kill the engine and requeue all running commands. */ 2587 ahci_stop(dev); 2588 for (i = 0; i < ch->numslots; i++) { 2589 /* Do we have a running request on slot? */ 2590 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2591 continue; 2592 /* XXX; Commands in loading state. */ 2593 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2594 } 2595 for (i = 0; i < ch->numslots; i++) { 2596 if (!ch->hold[i]) 2597 continue; 2598 xpt_done(ch->hold[i]); 2599 ch->hold[i] = NULL; 2600 ch->numhslots--; 2601 } 2602 if (ch->toslots != 0) 2603 xpt_release_simq(ch->sim, TRUE); 2604 ch->eslots = 0; 2605 ch->toslots = 0; 2606 ch->wrongccs = 0; 2607 ch->fatalerr = 0; 2608 /* Tell the XPT about the event */ 2609 xpt_async(AC_BUS_RESET, ch->path, NULL); 2610 /* Disable port interrupts */ 2611 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2612 /* Reset and reconnect PHY, */ 2613 if (!ahci_sata_phy_reset(dev)) { 2614 if (bootverbose) 2615 device_printf(dev, 2616 "AHCI reset: device not found\n"); 2617 ch->devices = 0; 2618 /* Enable wanted port interrupts */ 2619 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2620 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2621 AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2622 xpt_release_simq(ch->sim, TRUE); 2623 return; 2624 } 2625 if (bootverbose) 2626 device_printf(dev, "AHCI reset: device found\n"); 2627 /* Wait for clearing busy status. */ 2628 if (ahci_wait_ready(dev, dumping ? 31000 : 0, 0)) { 2629 if (dumping) 2630 ahci_clo(dev); 2631 else 2632 ch->resetting = 310; 2633 } 2634 ch->devices = 1; 2635 /* Enable wanted port interrupts */ 2636 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2637 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2638 AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2639 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2640 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC | 2641 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2642 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2643 if (ch->resetting) 2644 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, dev); 2645 else { 2646 ahci_start(dev, 1); 2647 xpt_release_simq(ch->sim, TRUE); 2648 } 2649} 2650 2651static int 2652ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2653{ 2654 struct ahci_channel *ch = device_get_softc(dev); 2655 u_int8_t *fis = &ctp->cfis[0]; 2656 2657 bzero(ctp->cfis, 16); 2658 fis[0] = 0x27; /* host to device */ 2659 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2660 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2661 fis[1] |= 0x80; 2662 fis[2] = ATA_PACKET_CMD; 2663 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2664 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2665 fis[3] = ATA_F_DMA; 2666 else { 2667 fis[5] = ccb->csio.dxfer_len; 2668 fis[6] = ccb->csio.dxfer_len >> 8; 2669 } 2670 fis[7] = ATA_D_LBA; 2671 fis[15] = ATA_A_4BIT; 2672 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2673 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2674 ctp->acmd, ccb->csio.cdb_len); 2675 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len); 2676 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2677 fis[1] |= 0x80; 2678 fis[2] = ccb->ataio.cmd.command; 2679 fis[3] = ccb->ataio.cmd.features; 2680 fis[4] = ccb->ataio.cmd.lba_low; 2681 fis[5] = ccb->ataio.cmd.lba_mid; 2682 fis[6] = ccb->ataio.cmd.lba_high; 2683 fis[7] = ccb->ataio.cmd.device; 2684 fis[8] = ccb->ataio.cmd.lba_low_exp; 2685 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2686 fis[10] = ccb->ataio.cmd.lba_high_exp; 2687 fis[11] = ccb->ataio.cmd.features_exp; 2688 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2689 fis[12] = tag << 3; 2690 fis[13] = 0; 2691 } else { 2692 fis[12] = ccb->ataio.cmd.sector_count; 2693 fis[13] = ccb->ataio.cmd.sector_count_exp; 2694 } 2695 fis[15] = ATA_A_4BIT; 2696 } else { 2697 fis[15] = ccb->ataio.cmd.control; 2698 } 2699 return (20); 2700} 2701 2702static int 2703ahci_sata_connect(struct ahci_channel *ch) 2704{ 2705 u_int32_t status; 2706 int timeout, found = 0; 2707 2708 /* Wait up to 100ms for "connect well" */ 2709 for (timeout = 0; timeout < 1000 ; timeout++) { 2710 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2711 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 2712 found = 1; 2713 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2714 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2715 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2716 break; 2717 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2718 if (bootverbose) { 2719 device_printf(ch->dev, "SATA offline status=%08x\n", 2720 status); 2721 } 2722 return (0); 2723 } 2724 if (found == 0 && timeout >= 100) 2725 break; 2726 DELAY(100); 2727 } 2728 if (timeout >= 1000 || !found) { 2729 if (bootverbose) { 2730 device_printf(ch->dev, 2731 "SATA connect timeout time=%dus status=%08x\n", 2732 timeout * 100, status); 2733 } 2734 return (0); 2735 } 2736 if (bootverbose) { 2737 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2738 timeout * 100, status); 2739 } 2740 /* Clear SATA error register */ 2741 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2742 return (1); 2743} 2744 2745static int 2746ahci_sata_phy_reset(device_t dev) 2747{ 2748 struct ahci_channel *ch = device_get_softc(dev); 2749 int sata_rev; 2750 uint32_t val; 2751 2752 if (ch->listening) { 2753 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2754 val |= AHCI_P_CMD_SUD; 2755 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2756 ch->listening = 0; 2757 } 2758 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2759 if (sata_rev == 1) 2760 val = ATA_SC_SPD_SPEED_GEN1; 2761 else if (sata_rev == 2) 2762 val = ATA_SC_SPD_SPEED_GEN2; 2763 else if (sata_rev == 3) 2764 val = ATA_SC_SPD_SPEED_GEN3; 2765 else 2766 val = 0; 2767 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2768 ATA_SC_DET_RESET | val | 2769 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2770 DELAY(1000); 2771 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2772 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2773 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2774 if (!ahci_sata_connect(ch)) { 2775 if (ch->caps & AHCI_CAP_SSS) { 2776 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2777 val &= ~AHCI_P_CMD_SUD; 2778 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2779 ch->listening = 1; 2780 } else if (ch->pm_level > 0) 2781 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2782 return (0); 2783 } 2784 return (1); 2785} 2786 2787static int 2788ahci_check_ids(device_t dev, union ccb *ccb) 2789{ 2790 struct ahci_channel *ch = device_get_softc(dev); 2791 2792 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2793 ccb->ccb_h.status = CAM_TID_INVALID; 2794 xpt_done(ccb); 2795 return (-1); 2796 } 2797 if (ccb->ccb_h.target_lun != 0) { 2798 ccb->ccb_h.status = CAM_LUN_INVALID; 2799 xpt_done(ccb); 2800 return (-1); 2801 } 2802 return (0); 2803} 2804 2805static void 2806ahciaction(struct cam_sim *sim, union ccb *ccb) 2807{ 2808 device_t dev, parent; 2809 struct ahci_channel *ch; 2810 2811 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2812 ccb->ccb_h.func_code)); 2813 2814 ch = (struct ahci_channel *)cam_sim_softc(sim); 2815 dev = ch->dev; 2816 switch (ccb->ccb_h.func_code) { 2817 /* Common cases first */ 2818 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2819 case XPT_SCSI_IO: 2820 if (ahci_check_ids(dev, ccb)) 2821 return; 2822 if (ch->devices == 0 || 2823 (ch->pm_present == 0 && 2824 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2825 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2826 break; 2827 } 2828 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2829 /* Check for command collision. */ 2830 if (ahci_check_collision(dev, ccb)) { 2831 /* Freeze command. */ 2832 ch->frozen = ccb; 2833 /* We have only one frozen slot, so freeze simq also. */ 2834 xpt_freeze_simq(ch->sim, 1); 2835 return; 2836 } 2837 ahci_begin_transaction(dev, ccb); 2838 return; 2839 case XPT_EN_LUN: /* Enable LUN as a target */ 2840 case XPT_TARGET_IO: /* Execute target I/O request */ 2841 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2842 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2843 case XPT_ABORT: /* Abort the specified CCB */ 2844 /* XXX Implement */ 2845 ccb->ccb_h.status = CAM_REQ_INVALID; 2846 break; 2847 case XPT_SET_TRAN_SETTINGS: 2848 { 2849 struct ccb_trans_settings *cts = &ccb->cts; 2850 struct ahci_device *d; 2851 2852 if (ahci_check_ids(dev, ccb)) 2853 return; 2854 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2855 d = &ch->curr[ccb->ccb_h.target_id]; 2856 else 2857 d = &ch->user[ccb->ccb_h.target_id]; 2858 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2859 d->revision = cts->xport_specific.sata.revision; 2860 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2861 d->mode = cts->xport_specific.sata.mode; 2862 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2863 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2864 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2865 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2866 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2867 ch->pm_present = cts->xport_specific.sata.pm_present; 2868 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2869 d->atapi = cts->xport_specific.sata.atapi; 2870 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2871 d->caps = cts->xport_specific.sata.caps; 2872 ccb->ccb_h.status = CAM_REQ_CMP; 2873 break; 2874 } 2875 case XPT_GET_TRAN_SETTINGS: 2876 /* Get default/user set transfer settings for the target */ 2877 { 2878 struct ccb_trans_settings *cts = &ccb->cts; 2879 struct ahci_device *d; 2880 uint32_t status; 2881 2882 if (ahci_check_ids(dev, ccb)) 2883 return; 2884 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2885 d = &ch->curr[ccb->ccb_h.target_id]; 2886 else 2887 d = &ch->user[ccb->ccb_h.target_id]; 2888 cts->protocol = PROTO_UNSPECIFIED; 2889 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2890 cts->transport = XPORT_SATA; 2891 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2892 cts->proto_specific.valid = 0; 2893 cts->xport_specific.sata.valid = 0; 2894 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2895 (ccb->ccb_h.target_id == 15 || 2896 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2897 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2898 if (status & 0x0f0) { 2899 cts->xport_specific.sata.revision = 2900 (status & 0x0f0) >> 4; 2901 cts->xport_specific.sata.valid |= 2902 CTS_SATA_VALID_REVISION; 2903 } 2904 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2905 if (ch->pm_level) { 2906 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 2907 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2908 if (ch->caps2 & AHCI_CAP2_APST) 2909 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 2910 } 2911 if ((ch->caps & AHCI_CAP_SNCQ) && 2912 (ch->quirks & AHCI_Q_NOAA) == 0) 2913 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 2914 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 2915 cts->xport_specific.sata.caps &= 2916 ch->user[ccb->ccb_h.target_id].caps; 2917 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2918 } else { 2919 cts->xport_specific.sata.revision = d->revision; 2920 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2921 cts->xport_specific.sata.caps = d->caps; 2922 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2923 } 2924 cts->xport_specific.sata.mode = d->mode; 2925 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2926 cts->xport_specific.sata.bytecount = d->bytecount; 2927 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2928 cts->xport_specific.sata.pm_present = ch->pm_present; 2929 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2930 cts->xport_specific.sata.tags = d->tags; 2931 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2932 cts->xport_specific.sata.atapi = d->atapi; 2933 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2934 ccb->ccb_h.status = CAM_REQ_CMP; 2935 break; 2936 } 2937 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2938 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2939 ahci_reset(dev); 2940 ccb->ccb_h.status = CAM_REQ_CMP; 2941 break; 2942 case XPT_TERM_IO: /* Terminate the I/O process */ 2943 /* XXX Implement */ 2944 ccb->ccb_h.status = CAM_REQ_INVALID; 2945 break; 2946 case XPT_PATH_INQ: /* Path routing inquiry */ 2947 { 2948 struct ccb_pathinq *cpi = &ccb->cpi; 2949 2950 parent = device_get_parent(dev); 2951 cpi->version_num = 1; /* XXX??? */ 2952 cpi->hba_inquiry = PI_SDTR_ABLE; 2953 if (ch->caps & AHCI_CAP_SNCQ) 2954 cpi->hba_inquiry |= PI_TAG_ABLE; 2955 if (ch->caps & AHCI_CAP_SPM) 2956 cpi->hba_inquiry |= PI_SATAPM; 2957 cpi->target_sprt = 0; 2958 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED; 2959 cpi->hba_eng_cnt = 0; 2960 if (ch->caps & AHCI_CAP_SPM) 2961 cpi->max_target = 15; 2962 else 2963 cpi->max_target = 0; 2964 cpi->max_lun = 0; 2965 cpi->initiator_id = 0; 2966 cpi->bus_id = cam_sim_bus(sim); 2967 cpi->base_transfer_speed = 150000; 2968 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2969 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2970 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2971 cpi->unit_number = cam_sim_unit(sim); 2972 cpi->transport = XPORT_SATA; 2973 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2974 cpi->protocol = PROTO_ATA; 2975 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2976 cpi->maxio = MAXPHYS; 2977 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2978 if (pci_get_devid(parent) == 0x43801002) 2979 cpi->maxio = min(cpi->maxio, 128 * 512); 2980 cpi->hba_vendor = pci_get_vendor(parent); 2981 cpi->hba_device = pci_get_device(parent); 2982 cpi->hba_subvendor = pci_get_subvendor(parent); 2983 cpi->hba_subdevice = pci_get_subdevice(parent); 2984 cpi->ccb_h.status = CAM_REQ_CMP; 2985 break; 2986 } 2987 default: 2988 ccb->ccb_h.status = CAM_REQ_INVALID; 2989 break; 2990 } 2991 xpt_done(ccb); 2992} 2993 2994static void 2995ahcipoll(struct cam_sim *sim) 2996{ 2997 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2998 2999 ahci_ch_intr(ch->dev); 3000 if (ch->resetting != 0 && 3001 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 3002 ch->resetpolldiv = 1000; 3003 ahci_reset_to(ch->dev); 3004 } 3005} 3006