ahci_generic.c revision 198390
1/*- 2 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ahci/ahci.c 198390 2009-10-23 13:07:22Z mav $"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/ata.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/malloc.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <sys/sema.h> 41#include <sys/taskqueue.h> 42#include <vm/uma.h> 43#include <machine/stdarg.h> 44#include <machine/resource.h> 45#include <machine/bus.h> 46#include <sys/rman.h> 47#include <dev/pci/pcivar.h> 48#include <dev/pci/pcireg.h> 49#include "ahci.h" 50 51#include <cam/cam.h> 52#include <cam/cam_ccb.h> 53#include <cam/cam_sim.h> 54#include <cam/cam_xpt_sim.h> 55#include <cam/cam_xpt_periph.h> 56#include <cam/cam_debug.h> 57 58/* local prototypes */ 59static int ahci_setup_interrupt(device_t dev); 60static void ahci_intr(void *data); 61static void ahci_intr_one(void *data); 62static int ahci_suspend(device_t dev); 63static int ahci_resume(device_t dev); 64static int ahci_ch_suspend(device_t dev); 65static int ahci_ch_resume(device_t dev); 66static void ahci_ch_pm(void *arg); 67static void ahci_ch_intr_locked(void *data); 68static void ahci_ch_intr(void *data); 69static int ahci_ctlr_reset(device_t dev); 70static void ahci_begin_transaction(device_t dev, union ccb *ccb); 71static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 72static void ahci_execute_transaction(struct ahci_slot *slot); 73static void ahci_timeout(struct ahci_slot *slot); 74static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 75static int ahci_setup_fis(struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 76static void ahci_dmainit(device_t dev); 77static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 78static void ahci_dmafini(device_t dev); 79static void ahci_slotsalloc(device_t dev); 80static void ahci_slotsfree(device_t dev); 81static void ahci_reset(device_t dev); 82static void ahci_start(device_t dev); 83static void ahci_stop(device_t dev); 84static void ahci_clo(device_t dev); 85static void ahci_start_fr(device_t dev); 86static void ahci_stop_fr(device_t dev); 87 88static int ahci_sata_connect(struct ahci_channel *ch); 89static int ahci_sata_phy_reset(device_t dev, int quick); 90 91static void ahci_issue_read_log(device_t dev); 92static void ahci_process_read_log(device_t dev, union ccb *ccb); 93 94static void ahciaction(struct cam_sim *sim, union ccb *ccb); 95static void ahcipoll(struct cam_sim *sim); 96 97MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 98 99/* 100 * AHCI v1.x compliant SATA chipset support functions 101 */ 102static int 103ahci_probe(device_t dev) 104{ 105 106 /* is this a possible AHCI candidate ? */ 107 if (pci_get_class(dev) != PCIC_STORAGE || 108 pci_get_subclass(dev) != PCIS_STORAGE_SATA) 109 return (ENXIO); 110 111 /* is this PCI device flagged as an AHCI compliant chip ? */ 112 if (pci_get_progif(dev) != PCIP_STORAGE_SATA_AHCI_1_0) 113 return (ENXIO); 114 115 device_set_desc_copy(dev, "AHCI controller"); 116 return (BUS_PROBE_VENDOR); 117} 118 119static int 120ahci_attach(device_t dev) 121{ 122 struct ahci_controller *ctlr = device_get_softc(dev); 123 device_t child; 124 int error, unit, speed; 125 u_int32_t version; 126 127 ctlr->dev = dev; 128 resource_int_value(device_get_name(dev), 129 device_get_unit(dev), "ccc", &ctlr->ccc); 130 /* if we have a memory BAR(5) we are likely on an AHCI part */ 131 ctlr->r_rid = PCIR_BAR(5); 132 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 133 &ctlr->r_rid, RF_ACTIVE))) 134 return ENXIO; 135 /* Setup our own memory management for channels. */ 136 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 137 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 138 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 139 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 140 return (error); 141 } 142 if ((error = rman_manage_region(&ctlr->sc_iomem, 143 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 144 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 145 rman_fini(&ctlr->sc_iomem); 146 return (error); 147 } 148 /* Reset controller */ 149 if ((error = ahci_ctlr_reset(dev)) != 0) { 150 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 151 rman_fini(&ctlr->sc_iomem); 152 return (error); 153 }; 154 /* Get the number of HW channels */ 155 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 156 ctlr->channels = MAX(flsl(ctlr->ichannels), 157 (ATA_INL(ctlr->r_mem, AHCI_CAP) & AHCI_CAP_NPMASK) + 1); 158 /* Setup interrupts. */ 159 if (ahci_setup_interrupt(dev)) { 160 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 161 rman_fini(&ctlr->sc_iomem); 162 return ENXIO; 163 } 164 /* Announce HW capabilities. */ 165 version = ATA_INL(ctlr->r_mem, AHCI_VS); 166 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 167 if (version >= 0x00010020) 168 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 169 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 170 device_printf(dev, 171 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s\n", 172 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 173 ((version >> 4) & 0xf0) + (version & 0x0f), 174 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 175 ((speed == 1) ? "1.5":((speed == 2) ? "3": 176 ((speed == 3) ? "6":"?"))), 177 (ctlr->caps & AHCI_CAP_SPM) ? 178 "supported" : "not supported"); 179 if (bootverbose) { 180 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 181 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 182 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 183 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 184 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 185 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 186 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 187 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 188 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 189 ((speed == 1) ? "1.5":((speed == 2) ? "3": 190 ((speed == 3) ? "6":"?")))); 191 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 192 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 193 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 194 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 195 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 196 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 197 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 198 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 199 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 200 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 201 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 202 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 203 } 204 if (bootverbose && version >= 0x00010020) { 205 device_printf(dev, "Caps2:%s%s%s\n", 206 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 207 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 208 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 209 } 210 /* Attach all channels on this controller */ 211 for (unit = 0; unit < ctlr->channels; unit++) { 212 if ((ctlr->ichannels & (1 << unit)) == 0) 213 continue; 214 child = device_add_child(dev, "ahcich", -1); 215 if (child == NULL) 216 device_printf(dev, "failed to add channel device\n"); 217 else 218 device_set_ivars(child, (void *)(intptr_t)unit); 219 } 220 bus_generic_attach(dev); 221 return 0; 222} 223 224static int 225ahci_detach(device_t dev) 226{ 227 struct ahci_controller *ctlr = device_get_softc(dev); 228 device_t *children; 229 int nchildren, i; 230 231 /* Detach & delete all children */ 232 if (!device_get_children(dev, &children, &nchildren)) { 233 for (i = 0; i < nchildren; i++) 234 device_delete_child(dev, children[i]); 235 free(children, M_TEMP); 236 } 237 /* Free interrupts. */ 238 for (i = 0; i < ctlr->numirqs; i++) { 239 if (ctlr->irqs[i].r_irq) { 240 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 241 ctlr->irqs[i].handle); 242 bus_release_resource(dev, SYS_RES_IRQ, 243 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 244 } 245 } 246 pci_release_msi(dev); 247 /* Free memory. */ 248 rman_fini(&ctlr->sc_iomem); 249 if (ctlr->r_mem) 250 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 251 return (0); 252} 253 254static int 255ahci_ctlr_reset(device_t dev) 256{ 257 struct ahci_controller *ctlr = device_get_softc(dev); 258 int timeout; 259 260 if (pci_read_config(dev, 0x00, 4) == 0x28298086 && 261 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 262 pci_write_config(dev, 0x92, 0x01, 1); 263 /* Enable AHCI mode */ 264 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 265 /* Reset AHCI controller */ 266 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 267 for (timeout = 1000; timeout > 0; timeout--) { 268 DELAY(1000); 269 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 270 break; 271 } 272 if (timeout == 0) { 273 device_printf(dev, "AHCI controller reset failure\n"); 274 return ENXIO; 275 } 276 /* Reenable AHCI mode */ 277 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 278 /* Clear interrupts */ 279 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 280 /* Configure CCC */ 281 if (ctlr->ccc) { 282 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 283 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 284 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 285 (4 << AHCI_CCCC_CC_SHIFT) | 286 AHCI_CCCC_EN); 287 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 288 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 289 if (bootverbose) { 290 device_printf(dev, 291 "CCC with %dms/4cmd enabled on vector %d\n", 292 ctlr->ccc, ctlr->cccv); 293 } 294 } 295 /* Enable AHCI interrupts */ 296 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 297 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 298 return (0); 299} 300 301static int 302ahci_suspend(device_t dev) 303{ 304 struct ahci_controller *ctlr = device_get_softc(dev); 305 306 bus_generic_suspend(dev); 307 /* Disable interupts, so the state change(s) doesn't trigger */ 308 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 309 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 310 return 0; 311} 312 313static int 314ahci_resume(device_t dev) 315{ 316 int res; 317 318 if ((res = ahci_ctlr_reset(dev)) != 0) 319 return (res); 320 return (bus_generic_resume(dev)); 321} 322 323static int 324ahci_setup_interrupt(device_t dev) 325{ 326 struct ahci_controller *ctlr = device_get_softc(dev); 327 int i, msi = 1; 328 329 /* Process hints. */ 330 resource_int_value(device_get_name(dev), 331 device_get_unit(dev), "msi", &msi); 332 if (msi < 0) 333 msi = 0; 334 else if (msi == 1) 335 msi = min(1, pci_msi_count(dev)); 336 else if (msi > 1) 337 msi = pci_msi_count(dev); 338 /* Allocate MSI if needed/present. */ 339 if (msi && pci_alloc_msi(dev, &msi) == 0) { 340 ctlr->numirqs = msi; 341 } else { 342 msi = 0; 343 ctlr->numirqs = 1; 344 } 345 /* Check for single MSI vector fallback. */ 346 if (ctlr->numirqs > 1 && 347 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 348 device_printf(dev, "Falling back to one MSI\n"); 349 ctlr->numirqs = 1; 350 } 351 /* Allocate all IRQs. */ 352 for (i = 0; i < ctlr->numirqs; i++) { 353 ctlr->irqs[i].ctlr = ctlr; 354 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0); 355 if (ctlr->numirqs == 1 || i >= ctlr->channels || 356 (ctlr->ccc && i == ctlr->cccv)) 357 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 358 else if (i == ctlr->numirqs - 1) 359 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 360 else 361 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 362 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 363 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 364 device_printf(dev, "unable to map interrupt\n"); 365 return ENXIO; 366 } 367 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 368 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr, 369 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 370 /* SOS XXX release r_irq */ 371 device_printf(dev, "unable to setup interrupt\n"); 372 return ENXIO; 373 } 374 } 375 return (0); 376} 377 378/* 379 * Common case interrupt handler. 380 */ 381static void 382ahci_intr(void *data) 383{ 384 struct ahci_controller_irq *irq = data; 385 struct ahci_controller *ctlr = irq->ctlr; 386 u_int32_t is; 387 void *arg; 388 int unit; 389 390 if (irq->mode == AHCI_IRQ_MODE_ALL) { 391 unit = 0; 392 if (ctlr->ccc) 393 is = ctlr->ichannels; 394 else 395 is = ATA_INL(ctlr->r_mem, AHCI_IS); 396 } else { /* AHCI_IRQ_MODE_AFTER */ 397 unit = irq->r_irq_rid - 1; 398 is = ATA_INL(ctlr->r_mem, AHCI_IS); 399 } 400 for (; unit < ctlr->channels; unit++) { 401 if ((is & (1 << unit)) != 0 && 402 (arg = ctlr->interrupt[unit].argument)) { 403 ctlr->interrupt[unit].function(arg); 404 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 405 } 406 } 407} 408 409/* 410 * Simplified interrupt handler for multivector MSI mode. 411 */ 412static void 413ahci_intr_one(void *data) 414{ 415 struct ahci_controller_irq *irq = data; 416 struct ahci_controller *ctlr = irq->ctlr; 417 void *arg; 418 int unit; 419 420 unit = irq->r_irq_rid - 1; 421 if ((arg = ctlr->interrupt[unit].argument)) 422 ctlr->interrupt[unit].function(arg); 423} 424 425static struct resource * 426ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 427 u_long start, u_long end, u_long count, u_int flags) 428{ 429 struct ahci_controller *ctlr = device_get_softc(dev); 430 int unit = ((struct ahci_channel *)device_get_softc(child))->unit; 431 struct resource *res = NULL; 432 int offset = AHCI_OFFSET + (unit << 7); 433 long st; 434 435 switch (type) { 436 case SYS_RES_MEMORY: 437 st = rman_get_start(ctlr->r_mem); 438 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 439 st + offset + 127, 128, RF_ACTIVE, child); 440 if (res) { 441 bus_space_handle_t bsh; 442 bus_space_tag_t bst; 443 bsh = rman_get_bushandle(ctlr->r_mem); 444 bst = rman_get_bustag(ctlr->r_mem); 445 bus_space_subregion(bst, bsh, offset, 128, &bsh); 446 rman_set_bushandle(res, bsh); 447 rman_set_bustag(res, bst); 448 } 449 break; 450 case SYS_RES_IRQ: 451 if (*rid == ATA_IRQ_RID) 452 res = ctlr->irqs[0].r_irq; 453 break; 454 } 455 return (res); 456} 457 458static int 459ahci_release_resource(device_t dev, device_t child, int type, int rid, 460 struct resource *r) 461{ 462 463 switch (type) { 464 case SYS_RES_MEMORY: 465 rman_release_resource(r); 466 return (0); 467 case SYS_RES_IRQ: 468 if (rid != ATA_IRQ_RID) 469 return ENOENT; 470 return (0); 471 } 472 return (EINVAL); 473} 474 475static int 476ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 477 int flags, driver_filter_t *filter, driver_intr_t *function, 478 void *argument, void **cookiep) 479{ 480 struct ahci_controller *ctlr = device_get_softc(dev); 481 int unit = (intptr_t)device_get_ivars(child); 482 483 if (filter != NULL) { 484 printf("ahci.c: we cannot use a filter here\n"); 485 return (EINVAL); 486 } 487 ctlr->interrupt[unit].function = function; 488 ctlr->interrupt[unit].argument = argument; 489 return (0); 490} 491 492static int 493ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 494 void *cookie) 495{ 496 struct ahci_controller *ctlr = device_get_softc(dev); 497 int unit = (intptr_t)device_get_ivars(child); 498 499 ctlr->interrupt[unit].function = NULL; 500 ctlr->interrupt[unit].argument = NULL; 501 return (0); 502} 503 504static int 505ahci_print_child(device_t dev, device_t child) 506{ 507 int retval; 508 509 retval = bus_print_child_header(dev, child); 510 retval += printf(" at channel %d", 511 (int)(intptr_t)device_get_ivars(child)); 512 retval += bus_print_child_footer(dev, child); 513 514 return (retval); 515} 516 517devclass_t ahci_devclass; 518static device_method_t ahci_methods[] = { 519 DEVMETHOD(device_probe, ahci_probe), 520 DEVMETHOD(device_attach, ahci_attach), 521 DEVMETHOD(device_detach, ahci_detach), 522 DEVMETHOD(device_suspend, ahci_suspend), 523 DEVMETHOD(device_resume, ahci_resume), 524 DEVMETHOD(bus_print_child, ahci_print_child), 525 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 526 DEVMETHOD(bus_release_resource, ahci_release_resource), 527 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 528 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 529 { 0, 0 } 530}; 531static driver_t ahci_driver = { 532 "ahci", 533 ahci_methods, 534 sizeof(struct ahci_controller) 535}; 536DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 537MODULE_VERSION(ahci, 1); 538MODULE_DEPEND(ahci, cam, 1, 1, 1); 539 540static int 541ahci_ch_probe(device_t dev) 542{ 543 544 device_set_desc_copy(dev, "AHCI channel"); 545 return (0); 546} 547 548static int 549ahci_ch_attach(device_t dev) 550{ 551 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 552 struct ahci_channel *ch = device_get_softc(dev); 553 struct cam_devq *devq; 554 int rid, error; 555 556 ch->dev = dev; 557 ch->unit = (intptr_t)device_get_ivars(dev); 558 ch->caps = ctlr->caps; 559 ch->caps2 = ctlr->caps2; 560 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 561 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 562 resource_int_value(device_get_name(dev), 563 device_get_unit(dev), "pm_level", &ch->pm_level); 564 if (ch->pm_level > 3) 565 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 566 /* Limit speed for my onboard JMicron external port. 567 * It is not eSATA really. */ 568 if (pci_get_devid(ctlr->dev) == 0x2363197b && 569 pci_get_subvendor(ctlr->dev) == 0x1043 && 570 pci_get_subdevice(ctlr->dev) == 0x81e4 && 571 ch->unit == 0) 572 ch->sata_rev = 1; 573 resource_int_value(device_get_name(dev), 574 device_get_unit(dev), "sata_rev", &ch->sata_rev); 575 rid = ch->unit; 576 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 577 &rid, RF_ACTIVE))) 578 return (ENXIO); 579 ahci_dmainit(dev); 580 ahci_slotsalloc(dev); 581 ahci_ch_resume(dev); 582 mtx_lock(&ch->mtx); 583 rid = ATA_IRQ_RID; 584 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 585 &rid, RF_SHAREABLE | RF_ACTIVE))) { 586 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 587 device_printf(dev, "Unable to map interrupt\n"); 588 return (ENXIO); 589 } 590 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 591 ahci_ch_intr_locked, dev, &ch->ih))) { 592 device_printf(dev, "Unable to setup interrupt\n"); 593 error = ENXIO; 594 goto err1; 595 } 596 /* Create the device queue for our SIM. */ 597 devq = cam_simq_alloc(ch->numslots); 598 if (devq == NULL) { 599 device_printf(dev, "Unable to allocate simq\n"); 600 error = ENOMEM; 601 goto err1; 602 } 603 /* Construct SIM entry */ 604 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 605 device_get_unit(dev), &ch->mtx, ch->numslots, 0, devq); 606 if (ch->sim == NULL) { 607 device_printf(dev, "unable to allocate sim\n"); 608 error = ENOMEM; 609 goto err2; 610 } 611 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 612 device_printf(dev, "unable to register xpt bus\n"); 613 error = ENXIO; 614 goto err2; 615 } 616 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 617 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 618 device_printf(dev, "unable to create path\n"); 619 error = ENXIO; 620 goto err3; 621 } 622 if (ch->pm_level > 3) { 623 callout_reset(&ch->pm_timer, 624 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 625 ahci_ch_pm, dev); 626 } 627 mtx_unlock(&ch->mtx); 628 return (0); 629 630err3: 631 xpt_bus_deregister(cam_sim_path(ch->sim)); 632err2: 633 cam_sim_free(ch->sim, /*free_devq*/TRUE); 634err1: 635 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 636 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 637 mtx_unlock(&ch->mtx); 638 return (error); 639} 640 641static int 642ahci_ch_detach(device_t dev) 643{ 644 struct ahci_channel *ch = device_get_softc(dev); 645 646 mtx_lock(&ch->mtx); 647 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 648 xpt_free_path(ch->path); 649 xpt_bus_deregister(cam_sim_path(ch->sim)); 650 cam_sim_free(ch->sim, /*free_devq*/TRUE); 651 mtx_unlock(&ch->mtx); 652 653 if (ch->pm_level > 3) 654 callout_drain(&ch->pm_timer); 655 bus_teardown_intr(dev, ch->r_irq, ch->ih); 656 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 657 658 ahci_ch_suspend(dev); 659 ahci_slotsfree(dev); 660 ahci_dmafini(dev); 661 662 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 663 mtx_destroy(&ch->mtx); 664 return (0); 665} 666 667static int 668ahci_ch_suspend(device_t dev) 669{ 670 struct ahci_channel *ch = device_get_softc(dev); 671 672 /* Disable port interrupts. */ 673 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 674 /* Reset command register. */ 675 ahci_stop(dev); 676 ahci_stop_fr(dev); 677 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 678 /* Allow everything, including partial and slumber modes. */ 679 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 680 /* Request slumber mode transition and give some time to get there. */ 681 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 682 DELAY(100); 683 /* Disable PHY. */ 684 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 685 return (0); 686} 687 688static int 689ahci_ch_resume(device_t dev) 690{ 691 struct ahci_channel *ch = device_get_softc(dev); 692 uint64_t work; 693 694 /* Disable port interrupts */ 695 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 696 /* Setup work areas */ 697 work = ch->dma.work_bus + AHCI_CL_OFFSET; 698 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 699 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 700 work = ch->dma.rfis_bus; 701 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 702 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 703 /* Activate the channel and power/spin up device */ 704 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 705 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 706 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 707 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 708 ahci_start_fr(dev); 709 ahci_start(dev); 710 return (0); 711} 712 713devclass_t ahcich_devclass; 714static device_method_t ahcich_methods[] = { 715 DEVMETHOD(device_probe, ahci_ch_probe), 716 DEVMETHOD(device_attach, ahci_ch_attach), 717 DEVMETHOD(device_detach, ahci_ch_detach), 718 DEVMETHOD(device_suspend, ahci_ch_suspend), 719 DEVMETHOD(device_resume, ahci_ch_resume), 720 { 0, 0 } 721}; 722static driver_t ahcich_driver = { 723 "ahcich", 724 ahcich_methods, 725 sizeof(struct ahci_channel) 726}; 727DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahci_devclass, 0, 0); 728 729struct ahci_dc_cb_args { 730 bus_addr_t maddr; 731 int error; 732}; 733 734static void 735ahci_dmainit(device_t dev) 736{ 737 struct ahci_channel *ch = device_get_softc(dev); 738 struct ahci_dc_cb_args dcba; 739 740 if (ch->caps & AHCI_CAP_64BIT) 741 ch->dma.max_address = BUS_SPACE_MAXADDR; 742 else 743 ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT; 744 /* Command area. */ 745 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 746 ch->dma.max_address, BUS_SPACE_MAXADDR, 747 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 748 0, NULL, NULL, &ch->dma.work_tag)) 749 goto error; 750 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0, 751 &ch->dma.work_map)) 752 goto error; 753 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 754 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 755 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 756 goto error; 757 } 758 ch->dma.work_bus = dcba.maddr; 759 /* FIS receive area. */ 760 if (bus_dma_tag_create(bus_get_dma_tag(dev), 4096, 0, 761 ch->dma.max_address, BUS_SPACE_MAXADDR, 762 NULL, NULL, 4096, 1, 4096, 763 0, NULL, NULL, &ch->dma.rfis_tag)) 764 goto error; 765 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 766 &ch->dma.rfis_map)) 767 goto error; 768 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 769 4096, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 770 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 771 goto error; 772 } 773 ch->dma.rfis_bus = dcba.maddr; 774 /* Data area. */ 775 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 776 ch->dma.max_address, BUS_SPACE_MAXADDR, 777 NULL, NULL, 778 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 779 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 780 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 781 goto error; 782 } 783 return; 784 785error: 786 device_printf(dev, "WARNING - DMA initialization failed\n"); 787 ahci_dmafini(dev); 788} 789 790static void 791ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 792{ 793 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 794 795 if (!(dcba->error = error)) 796 dcba->maddr = segs[0].ds_addr; 797} 798 799static void 800ahci_dmafini(device_t dev) 801{ 802 struct ahci_channel *ch = device_get_softc(dev); 803 804 if (ch->dma.data_tag) { 805 bus_dma_tag_destroy(ch->dma.data_tag); 806 ch->dma.data_tag = NULL; 807 } 808 if (ch->dma.rfis_bus) { 809 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 810 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 811 ch->dma.rfis_bus = 0; 812 ch->dma.rfis_map = NULL; 813 ch->dma.rfis = NULL; 814 } 815 if (ch->dma.work_bus) { 816 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 817 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 818 ch->dma.work_bus = 0; 819 ch->dma.work_map = NULL; 820 ch->dma.work = NULL; 821 } 822 if (ch->dma.work_tag) { 823 bus_dma_tag_destroy(ch->dma.work_tag); 824 ch->dma.work_tag = NULL; 825 } 826} 827 828static void 829ahci_slotsalloc(device_t dev) 830{ 831 struct ahci_channel *ch = device_get_softc(dev); 832 int i; 833 834 /* Alloc and setup command/dma slots */ 835 bzero(ch->slot, sizeof(ch->slot)); 836 for (i = 0; i < ch->numslots; i++) { 837 struct ahci_slot *slot = &ch->slot[i]; 838 839 slot->dev = dev; 840 slot->slot = i; 841 slot->state = AHCI_SLOT_EMPTY; 842 slot->ccb = NULL; 843 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 844 845 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 846 device_printf(ch->dev, "FAILURE - create data_map\n"); 847 } 848} 849 850static void 851ahci_slotsfree(device_t dev) 852{ 853 struct ahci_channel *ch = device_get_softc(dev); 854 int i; 855 856 /* Free all dma slots */ 857 for (i = 0; i < ch->numslots; i++) { 858 struct ahci_slot *slot = &ch->slot[i]; 859 860 callout_drain(&slot->timeout); 861 if (slot->dma.data_map) { 862 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 863 slot->dma.data_map = NULL; 864 } 865 } 866} 867 868static void 869ahci_phy_check_events(device_t dev, u_int32_t serr) 870{ 871 struct ahci_channel *ch = device_get_softc(dev); 872 873 if ((serr & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) { 874 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 875 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 876 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 877 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) { 878 if (bootverbose) 879 device_printf(dev, "CONNECT requested\n"); 880 ahci_reset(dev); 881 } else { 882 if (bootverbose) 883 device_printf(dev, "DISCONNECT requested\n"); 884 ch->devices = 0; 885 } 886 } 887} 888 889static void 890ahci_notify_events(device_t dev, u_int32_t status) 891{ 892 struct ahci_channel *ch = device_get_softc(dev); 893 struct cam_path *dpath; 894 int i; 895 896 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 897 if (bootverbose) 898 device_printf(dev, "SNTF 0x%04x\n", status); 899 for (i = 0; i < 16; i++) { 900 if ((status & (1 << i)) == 0) 901 continue; 902 if (xpt_create_path(&dpath, NULL, 903 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 904 xpt_async(AC_SCSI_AEN, dpath, NULL); 905 xpt_free_path(dpath); 906 } 907 } 908} 909 910static void 911ahci_ch_intr_locked(void *data) 912{ 913 device_t dev = (device_t)data; 914 struct ahci_channel *ch = device_get_softc(dev); 915 916 mtx_lock(&ch->mtx); 917 ahci_ch_intr(data); 918 mtx_unlock(&ch->mtx); 919} 920 921static void 922ahci_ch_pm(void *arg) 923{ 924 device_t dev = (device_t)arg; 925 struct ahci_channel *ch = device_get_softc(dev); 926 uint32_t work; 927 928 if (ch->numrslots != 0) 929 return; 930 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 931 if (ch->pm_level == 4) 932 work |= AHCI_P_CMD_PARTIAL; 933 else 934 work |= AHCI_P_CMD_SLUMBER; 935 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 936} 937 938static void 939ahci_ch_intr(void *data) 940{ 941 device_t dev = (device_t)data; 942 struct ahci_channel *ch = device_get_softc(dev); 943 uint32_t istatus, sstatus, cstatus, serr = 0, sntf = 0, ok, err; 944 enum ahci_err_type et; 945 int i, ccs, ncq_err = 0; 946 947 /* Read and clear interrupt statuses. */ 948 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 949 if (istatus == 0) 950 return; 951 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 952 /* Read command statuses. */ 953 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 954 cstatus = ATA_INL(ch->r_mem, AHCI_P_CI); 955 if ((istatus & AHCI_P_IX_SDB) && (ch->caps & AHCI_CAP_SSNTF)) 956 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 957 /* Process PHY events */ 958 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 959 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 960 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 961 if (serr) { 962 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 963 ahci_phy_check_events(dev, serr); 964 } 965 } 966 /* Process command errors */ 967 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 968 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 969//device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x\n", 970// __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 971// serr); 972 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 973 >> AHCI_P_CMD_CCS_SHIFT; 974 err = ch->rslots & (cstatus | sstatus); 975 /* Kick controller into sane state */ 976 ahci_stop(dev); 977 ahci_start(dev); 978 } else { 979 ccs = 0; 980 err = 0; 981 } 982 /* Complete all successfull commands. */ 983 ok = ch->rslots & ~(cstatus | sstatus); 984 for (i = 0; i < ch->numslots; i++) { 985 if ((ok >> i) & 1) 986 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 987 } 988 /* On error, complete the rest of commands with error statuses. */ 989 if (err) { 990 if (ch->frozen) { 991 union ccb *fccb = ch->frozen; 992 ch->frozen = NULL; 993 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 994 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 995 xpt_freeze_devq(fccb->ccb_h.path, 1); 996 fccb->ccb_h.status |= CAM_DEV_QFRZN; 997 } 998 xpt_done(fccb); 999 } 1000 for (i = 0; i < ch->numslots; i++) { 1001 /* XXX: reqests in loading state. */ 1002 if (((err >> i) & 1) == 0) 1003 continue; 1004 if (istatus & AHCI_P_IX_TFE) { 1005 /* Task File Error */ 1006 if (ch->numtslots == 0) { 1007 /* Untagged operation. */ 1008 if (i == ccs) 1009 et = AHCI_ERR_TFE; 1010 else 1011 et = AHCI_ERR_INNOCENT; 1012 } else { 1013 /* Tagged operation. */ 1014 et = AHCI_ERR_NCQ; 1015 ncq_err = 1; 1016 } 1017 } else if (istatus & AHCI_P_IX_IF) { 1018 if (ch->numtslots == 0 && i != ccs) 1019 et = AHCI_ERR_INNOCENT; 1020 else 1021 et = AHCI_ERR_SATA; 1022 } else 1023 et = AHCI_ERR_INVALID; 1024 ahci_end_transaction(&ch->slot[i], et); 1025 } 1026 if (ncq_err) 1027 ahci_issue_read_log(dev); 1028 } 1029 /* Process NOTIFY events */ 1030 if (sntf) 1031 ahci_notify_events(dev, sntf); 1032} 1033 1034/* Must be called with channel locked. */ 1035static int 1036ahci_check_collision(device_t dev, union ccb *ccb) 1037{ 1038 struct ahci_channel *ch = device_get_softc(dev); 1039 1040 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1041 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1042 /* Tagged command while untagged are active. */ 1043 if (ch->numrslots != 0 && ch->numtslots == 0) 1044 return (1); 1045 /* Tagged command while tagged to other target is active. */ 1046 if (ch->numtslots != 0 && 1047 ch->taggedtarget != ccb->ccb_h.target_id) 1048 return (1); 1049 } else { 1050 /* Untagged command while tagged are active. */ 1051 if (ch->numrslots != 0 && ch->numtslots != 0) 1052 return (1); 1053 } 1054 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1055 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1056 /* Atomic command while anything active. */ 1057 if (ch->numrslots != 0) 1058 return (1); 1059 } 1060 /* We have some atomic command running. */ 1061 if (ch->aslots != 0) 1062 return (1); 1063 return (0); 1064} 1065 1066/* Must be called with channel locked. */ 1067static void 1068ahci_begin_transaction(device_t dev, union ccb *ccb) 1069{ 1070 struct ahci_channel *ch = device_get_softc(dev); 1071 struct ahci_slot *slot; 1072 int tag; 1073 1074 /* Choose empty slot. */ 1075 tag = ch->lastslot; 1076 while (ch->slot[tag].state != AHCI_SLOT_EMPTY) { 1077 if (++tag >= ch->numslots) 1078 tag = 0; 1079 KASSERT(tag != ch->lastslot, ("ahci: ALL SLOTS BUSY!")); 1080 } 1081 ch->lastslot = tag; 1082 /* Occupy chosen slot. */ 1083 slot = &ch->slot[tag]; 1084 slot->ccb = ccb; 1085 /* Stop PM timer. */ 1086 if (ch->numrslots == 0 && ch->pm_level > 3) 1087 callout_stop(&ch->pm_timer); 1088 /* Update channel stats. */ 1089 ch->numrslots++; 1090 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1091 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1092 ch->numtslots++; 1093 ch->taggedtarget = ccb->ccb_h.target_id; 1094 } 1095 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1096 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1097 ch->aslots |= (1 << slot->slot); 1098 slot->dma.nsegs = 0; 1099 /* If request moves data, setup and load SG list */ 1100 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1101 void *buf; 1102 bus_size_t size; 1103 1104 slot->state = AHCI_SLOT_LOADING; 1105 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1106 buf = ccb->ataio.data_ptr; 1107 size = ccb->ataio.dxfer_len; 1108 } else { 1109 buf = ccb->csio.data_ptr; 1110 size = ccb->csio.dxfer_len; 1111 } 1112 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1113 buf, size, ahci_dmasetprd, slot, 0); 1114 } else 1115 ahci_execute_transaction(slot); 1116} 1117 1118/* Locked by busdma engine. */ 1119static void 1120ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1121{ 1122 struct ahci_slot *slot = arg; 1123 struct ahci_channel *ch = device_get_softc(slot->dev); 1124 struct ahci_cmd_tab *ctp; 1125 struct ahci_dma_prd *prd; 1126 int i; 1127 1128 if (error) { 1129 device_printf(slot->dev, "DMA load error\n"); 1130 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1131 return; 1132 } 1133 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1134 /* Get a piece of the workspace for this request */ 1135 ctp = (struct ahci_cmd_tab *) 1136 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1137 /* Fill S/G table */ 1138 prd = &ctp->prd_tab[0]; 1139 for (i = 0; i < nsegs; i++) { 1140 prd[i].dba = htole64(segs[i].ds_addr); 1141 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1142 } 1143 slot->dma.nsegs = nsegs; 1144 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1145 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1146 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1147 ahci_execute_transaction(slot); 1148} 1149 1150/* Must be called with channel locked. */ 1151static void 1152ahci_execute_transaction(struct ahci_slot *slot) 1153{ 1154 device_t dev = slot->dev; 1155 struct ahci_channel *ch = device_get_softc(dev); 1156 struct ahci_cmd_tab *ctp; 1157 struct ahci_cmd_list *clp; 1158 union ccb *ccb = slot->ccb; 1159 int port = ccb->ccb_h.target_id & 0x0f; 1160 int fis_size; 1161 1162 /* Get a piece of the workspace for this request */ 1163 ctp = (struct ahci_cmd_tab *) 1164 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1165 /* Setup the FIS for this request */ 1166 if (!(fis_size = ahci_setup_fis(ctp, ccb, slot->slot))) { 1167 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1168 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1169 return; 1170 } 1171 /* Setup the command list entry */ 1172 clp = (struct ahci_cmd_list *) 1173 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1174 clp->prd_length = slot->dma.nsegs; 1175 clp->cmd_flags = (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1176 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1177 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1178 (fis_size / sizeof(u_int32_t)) | 1179 (port << 12); 1180 /* Special handling for Soft Reset command. */ 1181 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1182 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1183 (ccb->ataio.cmd.control & ATA_A_RESET)) { 1184 /* Kick controller into sane state */ 1185 ahci_stop(dev); 1186 ahci_clo(dev); 1187 ahci_start(dev); 1188 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1189 } 1190 clp->bytecount = 0; 1191 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1192 (AHCI_CT_SIZE * slot->slot)); 1193 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1194 BUS_DMASYNC_PREWRITE); 1195 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1196 BUS_DMASYNC_PREREAD); 1197 /* Set ACTIVE bit for NCQ commands. */ 1198 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1199 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1200 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1201 } 1202 /* Issue command to the controller. */ 1203 slot->state = AHCI_SLOT_RUNNING; 1204 ch->rslots |= (1 << slot->slot); 1205 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1206 /* Device reset commands doesn't interrupt. Poll them. */ 1207 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1208 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || 1209 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL))) { 1210 int count, timeout = ccb->ccb_h.timeout; 1211 enum ahci_err_type et = AHCI_ERR_NONE; 1212 1213 for (count = 0; count < timeout; count++) { 1214 DELAY(1000); 1215 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1216 break; 1217 if (ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) { 1218 device_printf(ch->dev, 1219 "Poll error on slot %d, TFD: %04x\n", 1220 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1221 et = AHCI_ERR_TFE; 1222 break; 1223 } 1224 } 1225 if (timeout && (count >= timeout)) { 1226 device_printf(ch->dev, 1227 "Poll timeout on slot %d\n", slot->slot); 1228 et = AHCI_ERR_TIMEOUT; 1229 } 1230 if (et != AHCI_ERR_NONE) { 1231 /* Kick controller into sane state */ 1232 ahci_stop(ch->dev); 1233 ahci_start(ch->dev); 1234 } 1235 ahci_end_transaction(slot, et); 1236 return; 1237 } 1238 /* Start command execution timeout */ 1239 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 1240 (timeout_t*)ahci_timeout, slot); 1241 return; 1242} 1243 1244/* Locked by callout mechanism. */ 1245static void 1246ahci_timeout(struct ahci_slot *slot) 1247{ 1248 device_t dev = slot->dev; 1249 struct ahci_channel *ch = device_get_softc(dev); 1250 uint32_t sstatus; 1251 int ccs; 1252 int i; 1253 1254 /* Check for stale timeout. */ 1255 if (slot->state < AHCI_SLOT_RUNNING) 1256 return; 1257 1258 /* Check if slot was not being executed last time we checked. */ 1259 if (slot->state < AHCI_SLOT_EXECUTING) { 1260 /* Check if slot started executing. */ 1261 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1262 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1263 >> AHCI_P_CMD_CCS_SHIFT; 1264 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot) 1265 slot->state = AHCI_SLOT_EXECUTING; 1266 1267 callout_reset(&slot->timeout, 1268 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1269 (timeout_t*)ahci_timeout, slot); 1270 return; 1271 } 1272 1273 device_printf(dev, "Timeout on slot %d\n", slot->slot); 1274 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x\n", 1275 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1276 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1277 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR)); 1278 /* Kick controller into sane state. */ 1279 ahci_stop(ch->dev); 1280 ahci_start(ch->dev); 1281 1282 /* Handle frozen command. */ 1283 if (ch->frozen) { 1284 union ccb *fccb = ch->frozen; 1285 ch->frozen = NULL; 1286 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1287 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1288 xpt_freeze_devq(fccb->ccb_h.path, 1); 1289 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1290 } 1291 xpt_done(fccb); 1292 } 1293 /* Handle command with timeout. */ 1294 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 1295 /* Handle the rest of commands. */ 1296 for (i = 0; i < ch->numslots; i++) { 1297 /* Do we have a running request on slot? */ 1298 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1299 continue; 1300 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1301 } 1302} 1303 1304/* Must be called with channel locked. */ 1305static void 1306ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 1307{ 1308 device_t dev = slot->dev; 1309 struct ahci_channel *ch = device_get_softc(dev); 1310 union ccb *ccb = slot->ccb; 1311 1312 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1313 BUS_DMASYNC_POSTWRITE); 1314 /* Read result registers to the result struct 1315 * May be incorrect if several commands finished same time, 1316 * so read only when sure or have to. 1317 */ 1318 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1319 struct ata_res *res = &ccb->ataio.res; 1320 1321 if ((et == AHCI_ERR_TFE) || 1322 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1323 u_int8_t *fis = ch->dma.rfis + 0x40; 1324 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 1325 1326 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1327 BUS_DMASYNC_POSTREAD); 1328 res->status = tfd; 1329 res->error = tfd >> 8; 1330 res->lba_low = fis[4]; 1331 res->lba_mid = fis[5]; 1332 res->lba_high = fis[6]; 1333 res->device = fis[7]; 1334 res->lba_low_exp = fis[8]; 1335 res->lba_mid_exp = fis[9]; 1336 res->lba_high_exp = fis[10]; 1337 res->sector_count = fis[12]; 1338 res->sector_count_exp = fis[13]; 1339 } else 1340 bzero(res, sizeof(*res)); 1341 } 1342 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1343 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1344 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1345 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1346 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1347 } 1348 /* In case of error, freeze device for proper recovery. */ 1349 if ((et != AHCI_ERR_NONE) && (!ch->readlog) && 1350 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 1351 xpt_freeze_devq(ccb->ccb_h.path, 1); 1352 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1353 } 1354 /* Set proper result status. */ 1355 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1356 switch (et) { 1357 case AHCI_ERR_NONE: 1358 ccb->ccb_h.status |= CAM_REQ_CMP; 1359 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1360 ccb->csio.scsi_status = SCSI_STATUS_OK; 1361 break; 1362 case AHCI_ERR_INVALID: 1363 ccb->ccb_h.status |= CAM_REQ_INVALID; 1364 break; 1365 case AHCI_ERR_INNOCENT: 1366 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1367 break; 1368 case AHCI_ERR_TFE: 1369 case AHCI_ERR_NCQ: 1370 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1371 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1372 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1373 } else { 1374 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1375 } 1376 break; 1377 case AHCI_ERR_SATA: 1378 if (!ch->readlog) { 1379 xpt_freeze_simq(ch->sim, 1); 1380 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1381 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1382 } 1383 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1384 break; 1385 case AHCI_ERR_TIMEOUT: 1386 if (!ch->readlog) { 1387 xpt_freeze_simq(ch->sim, 1); 1388 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1389 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1390 } 1391 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1392 break; 1393 default: 1394 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1395 } 1396 /* Free slot. */ 1397 ch->rslots &= ~(1 << slot->slot); 1398 ch->aslots &= ~(1 << slot->slot); 1399 slot->state = AHCI_SLOT_EMPTY; 1400 slot->ccb = NULL; 1401 /* Update channel stats. */ 1402 ch->numrslots--; 1403 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1404 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1405 ch->numtslots--; 1406 } 1407 /* If it was first request of reset sequence and there is no error, 1408 * proceed to second request. */ 1409 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1410 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1411 (ccb->ataio.cmd.control & ATA_A_RESET) && 1412 et == AHCI_ERR_NONE) { 1413 ccb->ataio.cmd.control &= ~ATA_A_RESET; 1414 ahci_begin_transaction(dev, ccb); 1415 return; 1416 } 1417 /* If it was NCQ command error, put result on hold. */ 1418 if (et == AHCI_ERR_NCQ) { 1419 ch->hold[slot->slot] = ccb; 1420 } else if (ch->readlog) /* If it was our READ LOG command - process it. */ 1421 ahci_process_read_log(dev, ccb); 1422 else 1423 xpt_done(ccb); 1424 /* Unfreeze frozen command. */ 1425 if (ch->frozen && ch->numrslots == 0) { 1426 union ccb *fccb = ch->frozen; 1427 ch->frozen = NULL; 1428 ahci_begin_transaction(dev, fccb); 1429 xpt_release_simq(ch->sim, TRUE); 1430 } 1431 /* Start PM timer. */ 1432 if (ch->numrslots == 0 && ch->pm_level > 3) { 1433 callout_schedule(&ch->pm_timer, 1434 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 1435 } 1436} 1437 1438static void 1439ahci_issue_read_log(device_t dev) 1440{ 1441 struct ahci_channel *ch = device_get_softc(dev); 1442 union ccb *ccb; 1443 struct ccb_ataio *ataio; 1444 int i; 1445 1446 ch->readlog = 1; 1447 /* Find some holden command. */ 1448 for (i = 0; i < ch->numslots; i++) { 1449 if (ch->hold[i]) 1450 break; 1451 } 1452 ccb = xpt_alloc_ccb_nowait(); 1453 if (ccb == NULL) { 1454 device_printf(dev, "Unable allocate READ LOG command"); 1455 return; /* XXX */ 1456 } 1457 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 1458 ccb->ccb_h.func_code = XPT_ATA_IO; 1459 ccb->ccb_h.flags = CAM_DIR_IN; 1460 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1461 ataio = &ccb->ataio; 1462 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 1463 if (ataio->data_ptr == NULL) { 1464 device_printf(dev, "Unable allocate memory for READ LOG command"); 1465 return; /* XXX */ 1466 } 1467 ataio->dxfer_len = 512; 1468 bzero(&ataio->cmd, sizeof(ataio->cmd)); 1469 ataio->cmd.flags = CAM_ATAIO_48BIT; 1470 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 1471 ataio->cmd.sector_count = 1; 1472 ataio->cmd.sector_count_exp = 0; 1473 ataio->cmd.lba_low = 0x10; 1474 ataio->cmd.lba_mid = 0; 1475 ataio->cmd.lba_mid_exp = 0; 1476 /* Freeze SIM while doing READ LOG EXT. */ 1477 xpt_freeze_simq(ch->sim, 1); 1478 ahci_begin_transaction(dev, ccb); 1479} 1480 1481static void 1482ahci_process_read_log(device_t dev, union ccb *ccb) 1483{ 1484 struct ahci_channel *ch = device_get_softc(dev); 1485 uint8_t *data; 1486 struct ata_res *res; 1487 int i; 1488 1489 ch->readlog = 0; 1490 1491 data = ccb->ataio.data_ptr; 1492 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 1493 (data[0] & 0x80) == 0) { 1494 for (i = 0; i < ch->numslots; i++) { 1495 if (!ch->hold[i]) 1496 continue; 1497 if ((data[0] & 0x1F) == i) { 1498 res = &ch->hold[i]->ataio.res; 1499 res->status = data[2]; 1500 res->error = data[3]; 1501 res->lba_low = data[4]; 1502 res->lba_mid = data[5]; 1503 res->lba_high = data[6]; 1504 res->device = data[7]; 1505 res->lba_low_exp = data[8]; 1506 res->lba_mid_exp = data[9]; 1507 res->lba_high_exp = data[10]; 1508 res->sector_count = data[12]; 1509 res->sector_count_exp = data[13]; 1510 } else { 1511 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1512 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 1513 } 1514 xpt_done(ch->hold[i]); 1515 ch->hold[i] = NULL; 1516 } 1517 } else { 1518 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 1519 device_printf(dev, "Error while READ LOG EXT\n"); 1520 else if ((data[0] & 0x80) == 0) { 1521 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 1522 } 1523 for (i = 0; i < ch->numslots; i++) { 1524 if (!ch->hold[i]) 1525 continue; 1526 xpt_done(ch->hold[i]); 1527 ch->hold[i] = NULL; 1528 } 1529 } 1530 free(ccb->ataio.data_ptr, M_AHCI); 1531 xpt_free_ccb(ccb); 1532 xpt_release_simq(ch->sim, TRUE); 1533} 1534 1535static void 1536ahci_start(device_t dev) 1537{ 1538 struct ahci_channel *ch = device_get_softc(dev); 1539 u_int32_t cmd; 1540 1541 /* Clear SATA error register */ 1542 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 1543 /* Clear any interrupts pending on this channel */ 1544 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 1545 /* Start operations on this channel */ 1546 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1547 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 1548 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 1549} 1550 1551static void 1552ahci_stop(device_t dev) 1553{ 1554 struct ahci_channel *ch = device_get_softc(dev); 1555 u_int32_t cmd; 1556 int timeout; 1557 1558 /* Kill all activity on this channel */ 1559 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1560 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 1561 /* Wait for activity stop. */ 1562 timeout = 0; 1563 do { 1564 DELAY(1000); 1565 if (timeout++ > 1000) { 1566 device_printf(dev, "stopping AHCI engine failed\n"); 1567 break; 1568 } 1569 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 1570} 1571 1572static void 1573ahci_clo(device_t dev) 1574{ 1575 struct ahci_channel *ch = device_get_softc(dev); 1576 u_int32_t cmd; 1577 int timeout; 1578 1579 /* Issue Command List Override if supported */ 1580 if (ch->caps & AHCI_CAP_SCLO) { 1581 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1582 cmd |= AHCI_P_CMD_CLO; 1583 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 1584 timeout = 0; 1585 do { 1586 DELAY(1000); 1587 if (timeout++ > 1000) { 1588 device_printf(dev, "executing CLO failed\n"); 1589 break; 1590 } 1591 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 1592 } 1593} 1594 1595static void 1596ahci_stop_fr(device_t dev) 1597{ 1598 struct ahci_channel *ch = device_get_softc(dev); 1599 u_int32_t cmd; 1600 int timeout; 1601 1602 /* Kill all FIS reception on this channel */ 1603 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1604 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 1605 /* Wait for FIS reception stop. */ 1606 timeout = 0; 1607 do { 1608 DELAY(1000); 1609 if (timeout++ > 1000) { 1610 device_printf(dev, "stopping AHCI FR engine failed\n"); 1611 break; 1612 } 1613 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 1614} 1615 1616static void 1617ahci_start_fr(device_t dev) 1618{ 1619 struct ahci_channel *ch = device_get_softc(dev); 1620 u_int32_t cmd; 1621 1622 /* Start FIS reception on this channel */ 1623 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1624 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 1625} 1626 1627static int 1628ahci_wait_ready(device_t dev, int t) 1629{ 1630 struct ahci_channel *ch = device_get_softc(dev); 1631 int timeout = 0; 1632 uint32_t val; 1633 1634 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 1635 (ATA_S_BUSY | ATA_S_DRQ)) { 1636 DELAY(1000); 1637 if (timeout++ > t) { 1638 device_printf(dev, "port is not ready (timeout %dms) " 1639 "tfd = %08x\n", t, val); 1640 return (EBUSY); 1641 } 1642 } 1643 if (bootverbose) 1644 device_printf(dev, "ready wait time=%dms\n", timeout); 1645 return (0); 1646} 1647 1648static void 1649ahci_reset(device_t dev) 1650{ 1651 struct ahci_channel *ch = device_get_softc(dev); 1652 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1653 int i; 1654 1655 if (bootverbose) 1656 device_printf(dev, "AHCI reset...\n"); 1657 /* Requeue freezed command. */ 1658 if (ch->frozen) { 1659 union ccb *fccb = ch->frozen; 1660 ch->frozen = NULL; 1661 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1662 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1663 xpt_freeze_devq(fccb->ccb_h.path, 1); 1664 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1665 } 1666 xpt_done(fccb); 1667 } 1668 /* Kill the engine and requeue all running commands. */ 1669 ahci_stop(dev); 1670 for (i = 0; i < ch->numslots; i++) { 1671 /* Do we have a running request on slot? */ 1672 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1673 continue; 1674 /* XXX; Commands in loading state. */ 1675 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1676 } 1677 /* Tell the XPT about the event */ 1678 xpt_async(AC_BUS_RESET, ch->path, NULL); 1679 /* Disable port interrupts */ 1680 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1681 /* Reset and reconnect PHY, */ 1682 if (!ahci_sata_phy_reset(dev, 0)) { 1683 if (bootverbose) 1684 device_printf(dev, 1685 "AHCI reset done: phy reset found no device\n"); 1686 ch->devices = 0; 1687 /* Enable wanted port interrupts */ 1688 ATA_OUTL(ch->r_mem, AHCI_P_IE, 1689 (AHCI_P_IX_CPD | AHCI_P_IX_PRC | AHCI_P_IX_PC)); 1690 return; 1691 } 1692 /* Wait for clearing busy status. */ 1693 if (ahci_wait_ready(dev, 10000)) { 1694 device_printf(dev, "device ready timeout\n"); 1695 ahci_clo(dev); 1696 } 1697 ahci_start(dev); 1698 ch->devices = 1; 1699 /* Enable wanted port interrupts */ 1700 ATA_OUTL(ch->r_mem, AHCI_P_IE, 1701 (AHCI_P_IX_CPD | AHCI_P_IX_TFE | AHCI_P_IX_HBF | 1702 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 1703 ((ch->pm_level == 0) ? AHCI_P_IX_PRC | AHCI_P_IX_PC : 0) | 1704 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 1705 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 1706 if (bootverbose) 1707 device_printf(dev, "AHCI reset done: device found\n"); 1708} 1709 1710static int 1711ahci_setup_fis(struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 1712{ 1713 u_int8_t *fis = &ctp->cfis[0]; 1714 1715 bzero(ctp->cfis, 64); 1716 fis[0] = 0x27; /* host to device */ 1717 fis[1] = (ccb->ccb_h.target_id & 0x0f); 1718 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1719 fis[1] |= 0x80; 1720 fis[2] = ATA_PACKET_CMD; 1721 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) 1722 fis[3] = ATA_F_DMA; 1723 else { 1724 fis[5] = ccb->csio.dxfer_len; 1725 fis[6] = ccb->csio.dxfer_len >> 8; 1726 } 1727 fis[7] = ATA_D_LBA; 1728 fis[15] = ATA_A_4BIT; 1729 bzero(ctp->acmd, 32); 1730 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 1731 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 1732 ctp->acmd, ccb->csio.cdb_len); 1733 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 1734 fis[1] |= 0x80; 1735 fis[2] = ccb->ataio.cmd.command; 1736 fis[3] = ccb->ataio.cmd.features; 1737 fis[4] = ccb->ataio.cmd.lba_low; 1738 fis[5] = ccb->ataio.cmd.lba_mid; 1739 fis[6] = ccb->ataio.cmd.lba_high; 1740 fis[7] = ccb->ataio.cmd.device; 1741 fis[8] = ccb->ataio.cmd.lba_low_exp; 1742 fis[9] = ccb->ataio.cmd.lba_mid_exp; 1743 fis[10] = ccb->ataio.cmd.lba_high_exp; 1744 fis[11] = ccb->ataio.cmd.features_exp; 1745 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1746 fis[12] = tag << 3; 1747 fis[13] = 0; 1748 } else { 1749 fis[12] = ccb->ataio.cmd.sector_count; 1750 fis[13] = ccb->ataio.cmd.sector_count_exp; 1751 } 1752 fis[15] = ATA_A_4BIT; 1753 } else { 1754 fis[15] = ccb->ataio.cmd.control; 1755 } 1756 return (20); 1757} 1758 1759static int 1760ahci_sata_connect(struct ahci_channel *ch) 1761{ 1762 u_int32_t status; 1763 int timeout; 1764 1765 /* Wait up to 100ms for "connect well" */ 1766 for (timeout = 0; timeout < 100 ; timeout++) { 1767 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1768 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 1769 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 1770 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 1771 break; 1772 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 1773 if (bootverbose) { 1774 device_printf(ch->dev, "SATA offline status=%08x\n", 1775 status); 1776 } 1777 return (0); 1778 } 1779 DELAY(1000); 1780 } 1781 if (timeout >= 100) { 1782 if (bootverbose) { 1783 device_printf(ch->dev, "SATA connect timeout status=%08x\n", 1784 status); 1785 } 1786 return (0); 1787 } 1788 if (bootverbose) { 1789 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n", 1790 timeout, status); 1791 } 1792 /* Clear SATA error register */ 1793 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 1794 return (1); 1795} 1796 1797static int 1798ahci_sata_phy_reset(device_t dev, int quick) 1799{ 1800 struct ahci_channel *ch = device_get_softc(dev); 1801 uint32_t val; 1802 1803 if (quick) { 1804 val = ATA_INL(ch->r_mem, AHCI_P_SCTL); 1805 if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) 1806 return (ahci_sata_connect(ch)); 1807 } 1808 1809 if (bootverbose) 1810 device_printf(dev, "hardware reset ...\n"); 1811 if (ch->sata_rev == 1) 1812 val = ATA_SC_SPD_SPEED_GEN1; 1813 else if (ch->sata_rev == 2) 1814 val = ATA_SC_SPD_SPEED_GEN2; 1815 else if (ch->sata_rev == 3) 1816 val = ATA_SC_SPD_SPEED_GEN3; 1817 else 1818 val = 0; 1819 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 1820 ATA_SC_DET_RESET | val | 1821 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 1822 DELAY(5000); 1823 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 1824 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 1825 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 1826 DELAY(5000); 1827 return (ahci_sata_connect(ch)); 1828} 1829 1830static void 1831ahciaction(struct cam_sim *sim, union ccb *ccb) 1832{ 1833 device_t dev; 1834 struct ahci_channel *ch; 1835 1836 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 1837 ccb->ccb_h.func_code)); 1838 1839 ch = (struct ahci_channel *)cam_sim_softc(sim); 1840 dev = ch->dev; 1841 switch (ccb->ccb_h.func_code) { 1842 /* Common cases first */ 1843 case XPT_ATA_IO: /* Execute the requested I/O operation */ 1844 case XPT_SCSI_IO: 1845 if (ch->devices == 0) { 1846 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 1847 xpt_done(ccb); 1848 break; 1849 } 1850 /* Check for command collision. */ 1851 if (ahci_check_collision(dev, ccb)) { 1852 /* Freeze command. */ 1853 ch->frozen = ccb; 1854 /* We have only one frozen slot, so freeze simq also. */ 1855 xpt_freeze_simq(ch->sim, 1); 1856 return; 1857 } 1858 ahci_begin_transaction(dev, ccb); 1859 break; 1860 case XPT_EN_LUN: /* Enable LUN as a target */ 1861 case XPT_TARGET_IO: /* Execute target I/O request */ 1862 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 1863 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 1864 case XPT_ABORT: /* Abort the specified CCB */ 1865 /* XXX Implement */ 1866 ccb->ccb_h.status = CAM_REQ_INVALID; 1867 xpt_done(ccb); 1868 break; 1869 case XPT_SET_TRAN_SETTINGS: 1870 { 1871 struct ccb_trans_settings *cts = &ccb->cts; 1872 1873 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) { 1874 ch->pm_present = cts->xport_specific.sata.pm_present; 1875 } 1876 ccb->ccb_h.status = CAM_REQ_CMP; 1877 xpt_done(ccb); 1878 break; 1879 } 1880 case XPT_GET_TRAN_SETTINGS: 1881 /* Get default/user set transfer settings for the target */ 1882 { 1883 struct ccb_trans_settings *cts = &ccb->cts; 1884 uint32_t status; 1885 1886 cts->protocol = PROTO_ATA; 1887 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 1888 cts->transport = XPORT_SATA; 1889 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 1890 cts->proto_specific.valid = 0; 1891 cts->xport_specific.sata.valid = 0; 1892 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 1893 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 1894 else 1895 status = ATA_INL(ch->r_mem, AHCI_P_SCTL) & ATA_SC_SPD_MASK; 1896 if (status & ATA_SS_SPD_GEN3) { 1897 cts->xport_specific.sata.bitrate = 600000; 1898 cts->xport_specific.sata.valid |= CTS_SATA_VALID_SPEED; 1899 } else if (status & ATA_SS_SPD_GEN2) { 1900 cts->xport_specific.sata.bitrate = 300000; 1901 cts->xport_specific.sata.valid |= CTS_SATA_VALID_SPEED; 1902 } else if (status & ATA_SS_SPD_GEN1) { 1903 cts->xport_specific.sata.bitrate = 150000; 1904 cts->xport_specific.sata.valid |= CTS_SATA_VALID_SPEED; 1905 } 1906 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 1907 cts->xport_specific.sata.pm_present = 1908 (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_PMA) ? 1909 1 : 0; 1910 } else { 1911 cts->xport_specific.sata.pm_present = ch->pm_present; 1912 } 1913 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 1914 ccb->ccb_h.status = CAM_REQ_CMP; 1915 xpt_done(ccb); 1916 break; 1917 } 1918#if 0 1919 case XPT_CALC_GEOMETRY: 1920 { 1921 struct ccb_calc_geometry *ccg; 1922 uint32_t size_mb; 1923 uint32_t secs_per_cylinder; 1924 1925 ccg = &ccb->ccg; 1926 size_mb = ccg->volume_size 1927 / ((1024L * 1024L) / ccg->block_size); 1928 if (size_mb >= 1024 && (aha->extended_trans != 0)) { 1929 if (size_mb >= 2048) { 1930 ccg->heads = 255; 1931 ccg->secs_per_track = 63; 1932 } else { 1933 ccg->heads = 128; 1934 ccg->secs_per_track = 32; 1935 } 1936 } else { 1937 ccg->heads = 64; 1938 ccg->secs_per_track = 32; 1939 } 1940 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 1941 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 1942 ccb->ccb_h.status = CAM_REQ_CMP; 1943 xpt_done(ccb); 1944 break; 1945 } 1946#endif 1947 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 1948 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 1949 ahci_reset(dev); 1950 ccb->ccb_h.status = CAM_REQ_CMP; 1951 xpt_done(ccb); 1952 break; 1953 case XPT_TERM_IO: /* Terminate the I/O process */ 1954 /* XXX Implement */ 1955 ccb->ccb_h.status = CAM_REQ_INVALID; 1956 xpt_done(ccb); 1957 break; 1958 case XPT_PATH_INQ: /* Path routing inquiry */ 1959 { 1960 struct ccb_pathinq *cpi = &ccb->cpi; 1961 1962 cpi->version_num = 1; /* XXX??? */ 1963 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE; 1964 if (ch->caps & AHCI_CAP_SPM) 1965 cpi->hba_inquiry |= PI_SATAPM; 1966 cpi->target_sprt = 0; 1967 cpi->hba_misc = PIM_SEQSCAN; 1968 cpi->hba_eng_cnt = 0; 1969 if (ch->caps & AHCI_CAP_SPM) 1970 cpi->max_target = 15; 1971 else 1972 cpi->max_target = 0; 1973 cpi->max_lun = 0; 1974 cpi->initiator_id = 0; 1975 cpi->bus_id = cam_sim_bus(sim); 1976 cpi->base_transfer_speed = 150000; 1977 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 1978 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 1979 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 1980 cpi->unit_number = cam_sim_unit(sim); 1981 cpi->transport = XPORT_SATA; 1982 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 1983 cpi->protocol = PROTO_ATA; 1984 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 1985 cpi->maxio = MAXPHYS; 1986 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 1987 if (pci_get_devid(device_get_parent(dev)) == 0x43801002) 1988 cpi->maxio = min(cpi->maxio, 128 * 512); 1989 cpi->ccb_h.status = CAM_REQ_CMP; 1990 xpt_done(ccb); 1991 break; 1992 } 1993 default: 1994 ccb->ccb_h.status = CAM_REQ_INVALID; 1995 xpt_done(ccb); 1996 break; 1997 } 1998} 1999 2000static void 2001ahcipoll(struct cam_sim *sim) 2002{ 2003 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2004 2005 ahci_ch_intr(ch->dev); 2006} 2007