/linux-master/drivers/gpu/drm/amd/pm/swsmu/inc/ |
H A D | smu_v13_0_pptable.h | 109 uint32_t feature_count; //Total number of supported features 110 uint32_t setting_count; //Total number of supported settings 112 uint32_t max[SMU_13_0_MAX_ODSETTING]; //default maximum settings 113 uint32_t min[SMU_13_0_MAX_ODSETTING]; //default minimum settings 134 uint32_t count; //power_saving_clock_count = SMU_11_0_PPCLOCK_COUNT 135 uint32_t max[SMU_13_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Maximum array In MHz 136 uint32_t min[SMU_13_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Minimum array In MHz 143 uint32_t golden_pp_id; 144 uint32_t golden_revision; 146 uint32_t platform_cap [all...] |
H A D | smu_v11_0_pptable.h | 107 uint32_t feature_count; //Total number of supported features 108 uint32_t setting_count; //Total number of supported settings 110 uint32_t max[SMU_11_0_MAX_ODSETTING]; //default maximum settings 111 uint32_t min[SMU_11_0_MAX_ODSETTING]; //default minimum settings 132 uint32_t count; //power_saving_clock_count = SMU_11_0_PPCLOCK_COUNT 133 uint32_t max[SMU_11_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Maximum array In MHz 134 uint32_t min[SMU_11_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Minimum array In MHz 141 uint32_t golden_pp_id; 142 uint32_t golden_revision; 144 uint32_t platform_cap [all...] |
/linux-master/tools/perf/util/hisi-ptt-decoder/ |
H A D | hisi-ptt-pkt-decoder.c | 78 uint32_t format : 2; 79 uint32_t type : 5; 80 uint32_t t9 : 1; 81 uint32_t t8 : 1; 82 uint32_t th : 1; 83 uint32_t so : 1; 84 uint32_t len : 10; 85 uint32_t time : 11; 87 uint32_t value; 128 dw0.value = *(uint32_t *)(bu [all...] |
/linux-master/drivers/gpu/drm/vmwgfx/ |
H A D | vmwgfx_gmr.c | 44 uint32_t *cmd; 45 uint32_t *cmd_orig; 46 uint32_t define_size = sizeof(define_cmd) + sizeof(*cmd); 47 uint32_t remap_num = num_pages / VMW_PPN_PER_REMAP + ((num_pages % VMW_PPN_PER_REMAP) > 0); 48 uint32_t remap_size = VMW_PPN_SIZE * num_pages + (sizeof(remap_cmd) + sizeof(*cmd)) * remap_num; 49 uint32_t remap_pos = 0; 50 uint32_t cmd_size = define_size + remap_size; 51 uint32_t i; 109 uint32_t define_size = sizeof(define_cmd) + 4; 110 uint32_t *cm [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/ |
H A D | dccg.h | 105 uint32_t otg_inst); 107 uint32_t otg_inst); 175 uint32_t otg_inst, 195 uint32_t stream_enc_inst, 196 uint32_t link_enc_inst); 200 uint32_t stream_enc_inst, 201 uint32_t link_enc_inst); 208 uint32_t otg_inst); 211 uint32_t dsc_inst); 212 void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_ins [all...] |
/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_psp_ta.c | 36 static uint32_t get_bin_version(const uint8_t *bin) 46 uint32_t shared_buf_len) 146 uint32_t ta_type = 0; 147 uint32_t ta_bin_len = 0; 149 uint32_t copy_pos = 0; 159 ret = copy_from_user((void *)&ta_type, &buf[copy_pos], sizeof(uint32_t)); 163 copy_pos += sizeof(uint32_t); 165 ret = copy_from_user((void *)&ta_bin_len, &buf[copy_pos], sizeof(uint32_t)); 169 copy_pos += sizeof(uint32_t); 231 if (copy_to_user((char *)buf, (void *)&context->session_id, sizeof(uint32_t))) [all...] |
H A D | amdgpu_job.h | 53 uint32_t preamble_status; 54 uint32_t preemption_status; 61 uint32_t gds_base, gds_size; 62 uint32_t gws_base, gws_size; 63 uint32_t oa_base, oa_size; 77 uint32_t job_run_counter; 79 uint32_t num_ibs;
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H A D | vega20_reg_init.c | 32 uint32_t i; 34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); 35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); 37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); 38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); 39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); 40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); 41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); 42 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)( [all...] |
H A D | amdgpu_vcn.h | 104 uint32_t internal_reg_offset, addr; \ 165 uint32_t internal_reg_offset, addr; \ 277 uint32_t mem_size; 278 uint32_t log_offset; 296 uint32_t *dpg_sram_curr_addr; 317 uint32_t vcn_codec_disable_mask[AMDGPU_MAX_VCN_INSTANCES]; 336 uint32_t rptr; 337 uint32_t wptr; 362 uint32_t addr_lo; 363 uint32_t addr_h [all...] |
/linux-master/scripts/ |
H A D | sorttable.c | 67 static uint32_t (*r)(const uint32_t *); 70 static void (*w)(uint32_t, uint32_t *); 114 static uint32_t rbe(const uint32_t *x) 129 static uint32_t rle(const uint32_t *x) 144 static void wbe(uint32_t val, uint32_t * [all...] |
/linux-master/include/xen/interface/ |
H A D | grant_table.h | 74 typedef uint32_t grant_ref_t; 99 uint32_t frame; 203 uint32_t pad0; 235 uint32_t __spacer[4]; /* Pad to a power of two */ 262 typedef uint32_t grant_handle_t; 284 uint32_t flags; /* GNTMAP_* */ 327 uint32_t nr_frames; 416 uint32_t nr_frames; 417 uint32_t max_nr_frames; 451 uint32_t versio [all...] |
/linux-master/drivers/gpu/drm/amd/pm/powerplay/inc/ |
H A D | smu11_driver_if.h | 289 uint32_t Enabled; 290 uint32_t SlaveAddress; 291 uint32_t ControllerPort; 292 uint32_t ControllerName; 294 uint32_t ThermalThrottler; 295 uint32_t I2cProtocol; 296 uint32_t I2cSpeed; 300 uint32_t a; 301 uint32_t b; 302 uint32_t [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dce110/ |
H A D | dce110_timing_generator_v.c | 59 uint32_t value; 82 uint32_t value; 101 uint32_t addr = mmCRTCV_BLANK_CONTROL; 102 uint32_t value = dm_read_reg(tg->ctx, addr); 121 uint32_t addr = mmCRTCV_BLANK_CONTROL; 122 uint32_t value = dm_read_reg(tg->ctx, addr); 142 uint32_t addr = 0; 143 uint32_t value = 0; 144 uint32_t field = 0; 154 uint32_t valu [all...] |
/linux-master/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
H A D | smu11_driver_if_sienna_cichlid.h | 277 uint32_t eccPadding; 404 uint32_t Spare[8]; 405 uint32_t MmHubPadding[8]; // SMU internal use 430 uint32_t a; // store in IEEE float format in this variable 431 uint32_t b; // store in IEEE float format in this variable 432 uint32_t c; // store in IEEE float format in this variable 436 uint32_t a; // store in fixed point, [31:20] signed integer, [19:0] fractional bits 437 uint32_t b; // store in fixed point, [31:20] signed integer, [19:0] fractional bits 438 uint32_t c; // store in fixed point, [31:20] signed integer, [19:0] fractional bits 442 uint32_t [all...] |
/linux-master/include/linux/platform_data/ |
H A D | cros_ec_commands.h | 942 uint32_t version; 956 uint32_t in_data; 964 uint32_t out_data; 987 uint32_t current_image; 999 uint32_t offset; 1000 uint32_t size; 1008 uint32_t data[32]; 1090 uint32_t version_mask; 1113 uint32_t flags; /* Mask of enum ec_comms_status */ 1121 uint32_t ec_resul [all...] |
/linux-master/drivers/gpu/drm/vc4/ |
H A D | vc4_validate.c | 56 static uint32_t 74 static uint32_t 99 size_is_lt(uint32_t width, uint32_t height, int cpp) 106 vc4_use_bo(struct vc4_exec_info *exec, uint32_t hindex) 133 vc4_use_handle(struct vc4_exec_info *exec, uint32_t gem_handles_packet_index) 139 validate_bin_pos(struct vc4_exec_info *exec, void *untrusted, uint32_t pos) 147 static uint32_t 148 gl_shader_rec_size(uint32_t pointer_bits) 150 uint32_t attribute_coun [all...] |
H A D | vc4_validate_shaders.c | 51 uint32_t ip; 54 uint32_t max_ip; 67 uint32_t live_min_clamp_offsets[LIVE_REG_COUNT]; 69 uint32_t live_immediates[LIVE_REG_COUNT]; 100 static uint32_t 101 waddr_to_live_reg_index(uint32_t waddr, bool is_b) 115 static uint32_t 118 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG); 119 uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A); 120 uint32_t raddr_ [all...] |
/linux-master/drivers/gpu/drm/msm/disp/dpu1/ |
H A D | dpu_hw_util.h | 216 uint32_t enable; 264 uint32_t enable; 265 uint32_t dir_en; 275 uint32_t horz_decimate; 276 uint32_t vert_decimate; 286 uint32_t preload_x[DPU_MAX_PLANES]; 287 uint32_t preload_y[DPU_MAX_PLANES]; 288 uint32_t src_width[DPU_MAX_PLANES]; 289 uint32_t src_height[DPU_MAX_PLANES]; 291 uint32_t dst_widt [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
H A D | dcn30_dpp.h | 474 DPP_REG_FIELD_LIST_DCN3(uint32_t); 479 uint32_t CM_MEM_PWR_STATUS;\ 480 uint32_t CM_MEM_PWR_STATUS2;\ 481 uint32_t CM_MEM_PWR_CTRL2;\ 482 uint32_t CM_DEALPHA;\ 483 uint32_t CM_BIAS_CR_R;\ 484 uint32_t CM_BIAS_Y_G_CB_B;\ 485 uint32_t PRE_DEGAM;\ 486 uint32_t PRE_DEALPHA; \ 487 uint32_t PRE_REALPH [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dce/ |
H A D | dce_abm.h | 281 ABM_REG_FIELD_LIST(uint32_t); 285 uint32_t DC_ABM1_HG_SAMPLE_RATE; 286 uint32_t DC_ABM1_LS_SAMPLE_RATE; 287 uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE; 288 uint32_t DC_ABM1_HG_MISC_CTRL; 289 uint32_t DC_ABM1_IPCSC_COEFF_SEL; 290 uint32_t BL1_PWM_CURRENT_ABM_LEVEL; 291 uint32_t BL1_PWM_TARGET_ABM_LEVEL; 292 uint32_t BL1_PWM_USER_LEVEL; 293 uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRE [all...] |
H A D | dce_panel_cntl.h | 101 DCE_PANEL_CNTL_REG_FIELD_LIST(uint32_t); 105 uint32_t PWRSEQ_CNTL; 106 uint32_t PWRSEQ_STATE; 107 uint32_t BL_PWM_CNTL; 108 uint32_t BL_PWM_CNTL2; 109 uint32_t BL_PWM_PERIOD_CNTL; 110 uint32_t BL_PWM_GRP1_REG_LOCK; 111 uint32_t PWRSEQ_REF_DIV; 112 uint32_t BIOS_SCRATCH_2;
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/linux-master/drivers/gpu/drm/amd/display/dc/gpio/ |
H A D | ddc_regs.h | 125 uint32_t ddc_setup; 126 uint32_t phy_aux_cntl; 127 uint32_t dc_gpio_aux_ctrl_5; 132 uint32_t DC_I2C_DDC1_ENABLE; 133 uint32_t DC_I2C_DDC1_EDID_DETECT_ENABLE; 134 uint32_t DC_I2C_DDC1_EDID_DETECT_MODE; 136 uint32_t DC_GPIO_DDC1DATA_PD_EN; 137 uint32_t DC_GPIO_DDC1CLK_PD_EN; 138 uint32_t AUX_PAD1_MODE; 140 uint32_t DC_GPIO_SDA_PD_DI [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/ |
H A D | dcn20_dccg.h | 342 DCCG_REG_FIELD_LIST(uint32_t) 343 DCCG3_REG_FIELD_LIST(uint32_t) 344 DCCG31_REG_FIELD_LIST(uint32_t) 345 DCCG314_REG_FIELD_LIST(uint32_t) 346 DCCG32_REG_FIELD_LIST(uint32_t) 347 DCCG35_REG_FIELD_LIST(uint32_t) 351 uint32_t DPPCLK_DTO_CTRL; 352 uint32_t DPPCLK_DTO_PARAM[6]; 353 uint32_t REFCLK_CNTL; 354 uint32_t DISPCLK_FREQ_CHANGE_CNT [all...] |
/linux-master/drivers/scsi/lpfc/ |
H A D | lpfc_crtn.h | 34 void lpfc_config_async(struct lpfc_hba *, LPFC_MBOXQ_t *, uint32_t); 47 int lpfc_reg_rpi(struct lpfc_hba *, uint16_t, uint32_t, uint8_t *, 49 void lpfc_set_var(struct lpfc_hba *, LPFC_MBOXQ_t *, uint32_t, uint32_t); 50 void lpfc_unreg_login(struct lpfc_hba *, uint16_t, uint32_t, LPFC_MBOXQ_t *); 51 void lpfc_unreg_did(struct lpfc_hba *, uint16_t, uint32_t, LPFC_MBOXQ_t *); 58 void lpfc_init_link(struct lpfc_hba *, LPFC_MBOXQ_t *, uint32_t, uint32_t); 65 struct lpfc_vport *lpfc_find_vport_by_did(struct lpfc_hba *, uint32_t); 82 uint32_t lpfc_calc_cmf_latenc [all...] |
/linux-master/sound/ppc/ |
H A D | snd_ps3.h | 37 uint32_t avs_audio_ch; /* fixed */ 38 uint32_t avs_audio_rate; 39 uint32_t avs_audio_width; 40 uint32_t avs_audio_format; /* fixed */ 41 uint32_t avs_audio_source; /* fixed */
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