Lines Matching refs:uint32_t
342 DCCG_REG_FIELD_LIST(uint32_t)
343 DCCG3_REG_FIELD_LIST(uint32_t)
344 DCCG31_REG_FIELD_LIST(uint32_t)
345 DCCG314_REG_FIELD_LIST(uint32_t)
346 DCCG32_REG_FIELD_LIST(uint32_t)
347 DCCG35_REG_FIELD_LIST(uint32_t)
351 uint32_t DPPCLK_DTO_CTRL;
352 uint32_t DPPCLK_DTO_PARAM[6];
353 uint32_t REFCLK_CNTL;
354 uint32_t DISPCLK_FREQ_CHANGE_CNTL;
355 uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES];
356 uint32_t HDMICHARCLK_CLOCK_CNTL[6];
357 uint32_t PHYASYMCLK_CLOCK_CNTL;
358 uint32_t PHYBSYMCLK_CLOCK_CNTL;
359 uint32_t PHYCSYMCLK_CLOCK_CNTL;
360 uint32_t PHYDSYMCLK_CLOCK_CNTL;
361 uint32_t PHYESYMCLK_CLOCK_CNTL;
362 uint32_t DTBCLK_DTO_MODULO[MAX_PIPES];
363 uint32_t DTBCLK_DTO_PHASE[MAX_PIPES];
364 uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO;
365 uint32_t DCCG_AUDIO_DTBCLK_DTO_PHASE;
366 uint32_t DCCG_AUDIO_DTO_SOURCE;
367 uint32_t DPSTREAMCLK_CNTL;
368 uint32_t HDMISTREAMCLK_CNTL;
369 uint32_t SYMCLK32_SE_CNTL;
370 uint32_t SYMCLK32_LE_CNTL;
371 uint32_t DENTIST_DISPCLK_CNTL;
372 uint32_t DSCCLK_DTO_CTRL;
373 uint32_t DSCCLK0_DTO_PARAM;
374 uint32_t DSCCLK1_DTO_PARAM;
375 uint32_t DSCCLK2_DTO_PARAM;
376 uint32_t DSCCLK3_DTO_PARAM;
377 uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE;
378 uint32_t DPSTREAMCLK_GATE_DISABLE;
379 uint32_t DCCG_GATE_DISABLE_CNTL;
380 uint32_t DCCG_GATE_DISABLE_CNTL2;
381 uint32_t DCCG_GATE_DISABLE_CNTL3;
382 uint32_t HDMISTREAMCLK0_DTO_PARAM;
383 uint32_t DCCG_GATE_DISABLE_CNTL4;
384 uint32_t OTG_PIXEL_RATE_DIV;
385 uint32_t DTBCLK_P_CNTL;
386 uint32_t DPPCLK_CTRL;
387 uint32_t DCCG_GATE_DISABLE_CNTL5;
388 uint32_t DCCG_GATE_DISABLE_CNTL6;
389 uint32_t DCCG_GLOBAL_FGCG_REP_CNTL;
390 uint32_t SYMCLKA_CLOCK_ENABLE;
391 uint32_t SYMCLKB_CLOCK_ENABLE;
392 uint32_t SYMCLKC_CLOCK_ENABLE;
393 uint32_t SYMCLKD_CLOCK_ENABLE;
394 uint32_t SYMCLKE_CLOCK_ENABLE;
413 uint32_t otg_inst);
415 uint32_t otg_inst);