1/* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#ifndef SMU11_DRIVER_IF_H 25#define SMU11_DRIVER_IF_H 26 27// *** IMPORTANT *** 28// SMU TEAM: Always increment the interface version if 29// any structure is changed in this file 30// Be aware of that the version should be updated in 31// smu_v11_0.h, rename is also needed. 32// #define SMU11_DRIVER_IF_VERSION 0x13 33 34#define PPTABLE_V20_SMU_VERSION 3 35 36#define NUM_GFXCLK_DPM_LEVELS 16 37#define NUM_VCLK_DPM_LEVELS 8 38#define NUM_DCLK_DPM_LEVELS 8 39#define NUM_ECLK_DPM_LEVELS 8 40#define NUM_MP0CLK_DPM_LEVELS 2 41#define NUM_SOCCLK_DPM_LEVELS 8 42#define NUM_UCLK_DPM_LEVELS 4 43#define NUM_FCLK_DPM_LEVELS 8 44#define NUM_DCEFCLK_DPM_LEVELS 8 45#define NUM_DISPCLK_DPM_LEVELS 8 46#define NUM_PIXCLK_DPM_LEVELS 8 47#define NUM_PHYCLK_DPM_LEVELS 8 48#define NUM_LINK_LEVELS 2 49#define NUM_XGMI_LEVELS 2 50 51#define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1) 52#define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1) 53#define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1) 54#define MAX_ECLK_DPM_LEVEL (NUM_ECLK_DPM_LEVELS - 1) 55#define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1) 56#define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1) 57#define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 58#define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1) 59#define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1) 60#define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1) 61#define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1) 62#define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1) 63#define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1) 64#define MAX_XGMI_LEVEL (NUM_XGMI_LEVELS - 1) 65 66#define PPSMC_GeminiModeNone 0 67#define PPSMC_GeminiModeMaster 1 68#define PPSMC_GeminiModeSlave 2 69 70 71#define FEATURE_DPM_PREFETCHER_BIT 0 72#define FEATURE_DPM_GFXCLK_BIT 1 73#define FEATURE_DPM_UCLK_BIT 2 74#define FEATURE_DPM_SOCCLK_BIT 3 75#define FEATURE_DPM_UVD_BIT 4 76#define FEATURE_DPM_VCE_BIT 5 77#define FEATURE_ULV_BIT 6 78#define FEATURE_DPM_MP0CLK_BIT 7 79#define FEATURE_DPM_LINK_BIT 8 80#define FEATURE_DPM_DCEFCLK_BIT 9 81#define FEATURE_DS_GFXCLK_BIT 10 82#define FEATURE_DS_SOCCLK_BIT 11 83#define FEATURE_DS_LCLK_BIT 12 84#define FEATURE_PPT_BIT 13 85#define FEATURE_TDC_BIT 14 86#define FEATURE_THERMAL_BIT 15 87#define FEATURE_GFX_PER_CU_CG_BIT 16 88#define FEATURE_RM_BIT 17 89#define FEATURE_DS_DCEFCLK_BIT 18 90#define FEATURE_ACDC_BIT 19 91#define FEATURE_VR0HOT_BIT 20 92#define FEATURE_VR1HOT_BIT 21 93#define FEATURE_FW_CTF_BIT 22 94#define FEATURE_LED_DISPLAY_BIT 23 95#define FEATURE_FAN_CONTROL_BIT 24 96#define FEATURE_GFX_EDC_BIT 25 97#define FEATURE_GFXOFF_BIT 26 98#define FEATURE_CG_BIT 27 99#define FEATURE_DPM_FCLK_BIT 28 100#define FEATURE_DS_FCLK_BIT 29 101#define FEATURE_DS_MP1CLK_BIT 30 102#define FEATURE_DS_MP0CLK_BIT 31 103#define FEATURE_XGMI_BIT 32 104#define FEATURE_ECC_BIT 33 105#define FEATURE_SPARE_34_BIT 34 106#define FEATURE_SPARE_35_BIT 35 107#define FEATURE_SPARE_36_BIT 36 108#define FEATURE_SPARE_37_BIT 37 109#define FEATURE_SPARE_38_BIT 38 110#define FEATURE_SPARE_39_BIT 39 111#define FEATURE_SPARE_40_BIT 40 112#define FEATURE_SPARE_41_BIT 41 113#define FEATURE_SPARE_42_BIT 42 114#define FEATURE_SPARE_43_BIT 43 115#define FEATURE_SPARE_44_BIT 44 116#define FEATURE_SPARE_45_BIT 45 117#define FEATURE_SPARE_46_BIT 46 118#define FEATURE_SPARE_47_BIT 47 119#define FEATURE_SPARE_48_BIT 48 120#define FEATURE_SPARE_49_BIT 49 121#define FEATURE_SPARE_50_BIT 50 122#define FEATURE_SPARE_51_BIT 51 123#define FEATURE_SPARE_52_BIT 52 124#define FEATURE_SPARE_53_BIT 53 125#define FEATURE_SPARE_54_BIT 54 126#define FEATURE_SPARE_55_BIT 55 127#define FEATURE_SPARE_56_BIT 56 128#define FEATURE_SPARE_57_BIT 57 129#define FEATURE_SPARE_58_BIT 58 130#define FEATURE_SPARE_59_BIT 59 131#define FEATURE_SPARE_60_BIT 60 132#define FEATURE_SPARE_61_BIT 61 133#define FEATURE_SPARE_62_BIT 62 134#define FEATURE_SPARE_63_BIT 63 135 136#define NUM_FEATURES 64 137 138#define FEATURE_DPM_PREFETCHER_MASK (1 << FEATURE_DPM_PREFETCHER_BIT ) 139#define FEATURE_DPM_GFXCLK_MASK (1 << FEATURE_DPM_GFXCLK_BIT ) 140#define FEATURE_DPM_UCLK_MASK (1 << FEATURE_DPM_UCLK_BIT ) 141#define FEATURE_DPM_SOCCLK_MASK (1 << FEATURE_DPM_SOCCLK_BIT ) 142#define FEATURE_DPM_UVD_MASK (1 << FEATURE_DPM_UVD_BIT ) 143#define FEATURE_DPM_VCE_MASK (1 << FEATURE_DPM_VCE_BIT ) 144#define FEATURE_ULV_MASK (1 << FEATURE_ULV_BIT ) 145#define FEATURE_DPM_MP0CLK_MASK (1 << FEATURE_DPM_MP0CLK_BIT ) 146#define FEATURE_DPM_LINK_MASK (1 << FEATURE_DPM_LINK_BIT ) 147#define FEATURE_DPM_DCEFCLK_MASK (1 << FEATURE_DPM_DCEFCLK_BIT ) 148#define FEATURE_DS_GFXCLK_MASK (1 << FEATURE_DS_GFXCLK_BIT ) 149#define FEATURE_DS_SOCCLK_MASK (1 << FEATURE_DS_SOCCLK_BIT ) 150#define FEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT ) 151#define FEATURE_PPT_MASK (1 << FEATURE_PPT_BIT ) 152#define FEATURE_TDC_MASK (1 << FEATURE_TDC_BIT ) 153#define FEATURE_THERMAL_MASK (1 << FEATURE_THERMAL_BIT ) 154#define FEATURE_GFX_PER_CU_CG_MASK (1 << FEATURE_GFX_PER_CU_CG_BIT ) 155#define FEATURE_RM_MASK (1 << FEATURE_RM_BIT ) 156#define FEATURE_DS_DCEFCLK_MASK (1 << FEATURE_DS_DCEFCLK_BIT ) 157#define FEATURE_ACDC_MASK (1 << FEATURE_ACDC_BIT ) 158#define FEATURE_VR0HOT_MASK (1 << FEATURE_VR0HOT_BIT ) 159#define FEATURE_VR1HOT_MASK (1 << FEATURE_VR1HOT_BIT ) 160#define FEATURE_FW_CTF_MASK (1 << FEATURE_FW_CTF_BIT ) 161#define FEATURE_LED_DISPLAY_MASK (1 << FEATURE_LED_DISPLAY_BIT ) 162#define FEATURE_FAN_CONTROL_MASK (1 << FEATURE_FAN_CONTROL_BIT ) 163#define FEATURE_GFX_EDC_MASK (1 << FEATURE_GFX_EDC_BIT ) 164#define FEATURE_GFXOFF_MASK (1 << FEATURE_GFXOFF_BIT ) 165#define FEATURE_CG_MASK (1 << FEATURE_CG_BIT ) 166#define FEATURE_DPM_FCLK_MASK (1 << FEATURE_DPM_FCLK_BIT ) 167#define FEATURE_DS_FCLK_MASK (1 << FEATURE_DS_FCLK_BIT ) 168#define FEATURE_DS_MP1CLK_MASK (1 << FEATURE_DS_MP1CLK_BIT ) 169#define FEATURE_DS_MP0CLK_MASK (1 << FEATURE_DS_MP0CLK_BIT ) 170#define FEATURE_XGMI_MASK (1ULL << FEATURE_XGMI_BIT ) 171#define FEATURE_ECC_MASK (1ULL << FEATURE_ECC_BIT ) 172 173#define DPM_OVERRIDE_DISABLE_SOCCLK_PID 0x00000001 174#define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002 175#define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_SOCCLK 0x00000004 176#define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_UCLK 0x00000008 177#define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_SOCCLK 0x00000010 178#define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_UCLK 0x00000020 179#define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_SOCCLK 0x00000040 180#define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_UCLK 0x00000080 181#define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_SOCCLK 0x00000100 182#define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_UCLK 0x00000200 183#define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_SOCCLK 0x00000400 184#define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_UCLK 0x00000800 185#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK 0x00001000 186#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK 0x00002000 187#define DPM_OVERRIDE_ENABLE_GFXOFF_GFXCLK_SWITCH 0x00004000 188#define DPM_OVERRIDE_ENABLE_GFXOFF_SOCCLK_SWITCH 0x00008000 189#define DPM_OVERRIDE_ENABLE_GFXOFF_UCLK_SWITCH 0x00010000 190#define DPM_OVERRIDE_ENABLE_GFXOFF_FCLK_SWITCH 0x00020000 191 192#define I2C_CONTROLLER_ENABLED 1 193#define I2C_CONTROLLER_DISABLED 0 194 195#define VR_MAPPING_VR_SELECT_MASK 0x01 196#define VR_MAPPING_VR_SELECT_SHIFT 0x00 197 198#define VR_MAPPING_PLANE_SELECT_MASK 0x02 199#define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 200 201 202#define PSI_SEL_VR0_PLANE0_PSI0 0x01 203#define PSI_SEL_VR0_PLANE0_PSI1 0x02 204#define PSI_SEL_VR0_PLANE1_PSI0 0x04 205#define PSI_SEL_VR0_PLANE1_PSI1 0x08 206#define PSI_SEL_VR1_PLANE0_PSI0 0x10 207#define PSI_SEL_VR1_PLANE0_PSI1 0x20 208#define PSI_SEL_VR1_PLANE1_PSI0 0x40 209#define PSI_SEL_VR1_PLANE1_PSI1 0x80 210 211 212#define THROTTLER_STATUS_PADDING_BIT 0 213#define THROTTLER_STATUS_TEMP_EDGE_BIT 1 214#define THROTTLER_STATUS_TEMP_HOTSPOT_BIT 2 215#define THROTTLER_STATUS_TEMP_HBM_BIT 3 216#define THROTTLER_STATUS_TEMP_VR_GFX_BIT 4 217#define THROTTLER_STATUS_TEMP_VR_SOC_BIT 5 218#define THROTTLER_STATUS_TEMP_VR_MEM0_BIT 6 219#define THROTTLER_STATUS_TEMP_VR_MEM1_BIT 7 220#define THROTTLER_STATUS_TEMP_LIQUID_BIT 8 221#define THROTTLER_STATUS_TEMP_PLX_BIT 9 222#define THROTTLER_STATUS_TEMP_SKIN_BIT 10 223#define THROTTLER_STATUS_TDC_GFX_BIT 11 224#define THROTTLER_STATUS_TDC_SOC_BIT 12 225#define THROTTLER_STATUS_PPT_BIT 13 226#define THROTTLER_STATUS_FIT_BIT 14 227#define THROTTLER_STATUS_PPM_BIT 15 228 229 230#define TABLE_TRANSFER_OK 0x0 231#define TABLE_TRANSFER_FAILED 0xFF 232 233 234#define WORKLOAD_DEFAULT_BIT 0 235#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 236#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 237#define WORKLOAD_PPLIB_VIDEO_BIT 3 238#define WORKLOAD_PPLIB_VR_BIT 4 239#define WORKLOAD_PPLIB_COMPUTE_BIT 5 240#define WORKLOAD_PPLIB_CUSTOM_BIT 6 241#define WORKLOAD_PPLIB_COUNT 7 242 243 244#define XGMI_STATE_D0 1 245#define XGMI_STATE_D3 0 246 247typedef enum { 248 I2C_CONTROLLER_PORT_0 = 0, 249 I2C_CONTROLLER_PORT_1 = 1, 250} I2cControllerPort_e; 251 252typedef enum { 253 I2C_CONTROLLER_NAME_VR_GFX = 0, 254 I2C_CONTROLLER_NAME_VR_SOC, 255 I2C_CONTROLLER_NAME_VR_VDDCI, 256 I2C_CONTROLLER_NAME_VR_HBM, 257 I2C_CONTROLLER_NAME_LIQUID_0, 258 I2C_CONTROLLER_NAME_LIQUID_1, 259 I2C_CONTROLLER_NAME_PLX, 260 I2C_CONTROLLER_NAME_COUNT, 261} I2cControllerName_e; 262 263typedef enum { 264 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 265 I2C_CONTROLLER_THROTTLER_VR_GFX, 266 I2C_CONTROLLER_THROTTLER_VR_SOC, 267 I2C_CONTROLLER_THROTTLER_VR_VDDCI, 268 I2C_CONTROLLER_THROTTLER_VR_HBM, 269 I2C_CONTROLLER_THROTTLER_LIQUID_0, 270 I2C_CONTROLLER_THROTTLER_LIQUID_1, 271 I2C_CONTROLLER_THROTTLER_PLX, 272} I2cControllerThrottler_e; 273 274typedef enum { 275 I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 276 I2C_CONTROLLER_PROTOCOL_VR_IR35217, 277 I2C_CONTROLLER_PROTOCOL_TMP_TMP102A, 278 I2C_CONTROLLER_PROTOCOL_SPARE_0, 279 I2C_CONTROLLER_PROTOCOL_SPARE_1, 280 I2C_CONTROLLER_PROTOCOL_SPARE_2, 281} I2cControllerProtocol_e; 282 283typedef enum { 284 I2C_CONTROLLER_SPEED_SLOW = 0, 285 I2C_CONTROLLER_SPEED_FAST = 1, 286} I2cControllerSpeed_e; 287 288typedef struct { 289 uint32_t Enabled; 290 uint32_t SlaveAddress; 291 uint32_t ControllerPort; 292 uint32_t ControllerName; 293 294 uint32_t ThermalThrottler; 295 uint32_t I2cProtocol; 296 uint32_t I2cSpeed; 297} I2cControllerConfig_t; 298 299typedef struct { 300 uint32_t a; 301 uint32_t b; 302 uint32_t c; 303} QuadraticInt_t; 304 305typedef struct { 306 uint32_t m; 307 uint32_t b; 308} LinearInt_t; 309 310typedef struct { 311 uint32_t a; 312 uint32_t b; 313 uint32_t c; 314} DroopInt_t; 315 316typedef enum { 317 PPCLK_GFXCLK, 318 PPCLK_VCLK, 319 PPCLK_DCLK, 320 PPCLK_ECLK, 321 PPCLK_SOCCLK, 322 PPCLK_UCLK, 323 PPCLK_DCEFCLK, 324 PPCLK_DISPCLK, 325 PPCLK_PIXCLK, 326 PPCLK_PHYCLK, 327 PPCLK_FCLK, 328 PPCLK_COUNT, 329} PPCLK_e; 330 331typedef enum { 332 POWER_SOURCE_AC, 333 POWER_SOURCE_DC, 334 POWER_SOURCE_COUNT, 335} POWER_SOURCE_e; 336 337typedef enum { 338 VOLTAGE_MODE_AVFS = 0, 339 VOLTAGE_MODE_AVFS_SS, 340 VOLTAGE_MODE_SS, 341 VOLTAGE_MODE_COUNT, 342} VOLTAGE_MODE_e; 343 344 345typedef enum { 346 AVFS_VOLTAGE_GFX = 0, 347 AVFS_VOLTAGE_SOC, 348 AVFS_VOLTAGE_COUNT, 349} AVFS_VOLTAGE_TYPE_e; 350 351 352typedef struct { 353 uint8_t VoltageMode; 354 uint8_t SnapToDiscrete; 355 uint8_t NumDiscreteLevels; 356 uint8_t padding; 357 LinearInt_t ConversionToAvfsClk; 358 QuadraticInt_t SsCurve; 359} DpmDescriptor_t; 360 361#pragma pack(push, 1) 362typedef struct { 363 uint32_t Version; 364 365 366 uint32_t FeaturesToRun[2]; 367 368 369 uint16_t SocketPowerLimitAc0; 370 uint16_t SocketPowerLimitAc0Tau; 371 uint16_t SocketPowerLimitAc1; 372 uint16_t SocketPowerLimitAc1Tau; 373 uint16_t SocketPowerLimitAc2; 374 uint16_t SocketPowerLimitAc2Tau; 375 uint16_t SocketPowerLimitAc3; 376 uint16_t SocketPowerLimitAc3Tau; 377 uint16_t SocketPowerLimitDc; 378 uint16_t SocketPowerLimitDcTau; 379 uint16_t TdcLimitSoc; 380 uint16_t TdcLimitSocTau; 381 uint16_t TdcLimitGfx; 382 uint16_t TdcLimitGfxTau; 383 384 uint16_t TedgeLimit; 385 uint16_t ThotspotLimit; 386 uint16_t ThbmLimit; 387 uint16_t Tvr_gfxLimit; 388 uint16_t Tvr_memLimit; 389 uint16_t Tliquid1Limit; 390 uint16_t Tliquid2Limit; 391 uint16_t TplxLimit; 392 uint32_t FitLimit; 393 394 uint16_t PpmPowerLimit; 395 uint16_t PpmTemperatureThreshold; 396 397 uint8_t MemoryOnPackage; 398 uint8_t padding8_limits; 399 uint16_t Tvr_SocLimit; 400 401 uint16_t UlvVoltageOffsetSoc; 402 uint16_t UlvVoltageOffsetGfx; 403 404 uint8_t UlvSmnclkDid; 405 uint8_t UlvMp1clkDid; 406 uint8_t UlvGfxclkBypass; 407 uint8_t Padding234; 408 409 410 uint16_t MinVoltageGfx; 411 uint16_t MinVoltageSoc; 412 uint16_t MaxVoltageGfx; 413 uint16_t MaxVoltageSoc; 414 415 uint16_t LoadLineResistanceGfx; 416 uint16_t LoadLineResistanceSoc; 417 418 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 419 420 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; 421 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; 422 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; 423 uint16_t FreqTableEclk [NUM_ECLK_DPM_LEVELS ]; 424 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; 425 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; 426 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; 427 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; 428 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; 429 uint16_t FreqTablePixclk [NUM_PIXCLK_DPM_LEVELS ]; 430 uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ]; 431 432 uint16_t DcModeMaxFreq [PPCLK_COUNT ]; 433 uint16_t Padding8_Clks; 434 435 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; 436 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; 437 438 439 uint16_t GfxclkFidle; 440 uint16_t GfxclkSlewRate; 441 uint16_t CksEnableFreq; 442 uint16_t Padding789; 443 QuadraticInt_t CksVoltageOffset; 444 uint8_t Padding567[4]; 445 uint16_t GfxclkDsMaxFreq; 446 uint8_t GfxclkSource; 447 uint8_t Padding456; 448 449 uint8_t LowestUclkReservedForUlv; 450 uint8_t Padding8_Uclk[3]; 451 452 453 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; 454 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; 455 uint16_t LclkFreq[NUM_LINK_LEVELS]; 456 457 458 uint16_t EnableTdpm; 459 uint16_t TdpmHighHystTemperature; 460 uint16_t TdpmLowHystTemperature; 461 uint16_t GfxclkFreqHighTempLimit; 462 463 464 uint16_t FanStopTemp; 465 uint16_t FanStartTemp; 466 467 uint16_t FanGainEdge; 468 uint16_t FanGainHotspot; 469 uint16_t FanGainLiquid; 470 uint16_t FanGainVrGfx; 471 uint16_t FanGainVrSoc; 472 uint16_t FanGainPlx; 473 uint16_t FanGainHbm; 474 uint16_t FanPwmMin; 475 uint16_t FanAcousticLimitRpm; 476 uint16_t FanThrottlingRpm; 477 uint16_t FanMaximumRpm; 478 uint16_t FanTargetTemperature; 479 uint16_t FanTargetGfxclk; 480 uint8_t FanZeroRpmEnable; 481 uint8_t FanTachEdgePerRev; 482 483 484 485 int16_t FuzzyFan_ErrorSetDelta; 486 int16_t FuzzyFan_ErrorRateSetDelta; 487 int16_t FuzzyFan_PwmSetDelta; 488 uint16_t FuzzyFan_Reserved; 489 490 491 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 492 uint8_t Padding8_Avfs[2]; 493 494 QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; 495 DroopInt_t dBtcGbGfxCksOn; 496 DroopInt_t dBtcGbGfxCksOff; 497 DroopInt_t dBtcGbGfxAfll; 498 DroopInt_t dBtcGbSoc; 499 LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; 500 501 QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; 502 503 uint16_t DcTol[AVFS_VOLTAGE_COUNT]; 504 505 uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT]; 506 uint8_t Padding8_GfxBtc[2]; 507 508 int16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; 509 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; 510 511 512 uint8_t XgmiLinkSpeed [NUM_XGMI_LEVELS]; 513 uint8_t XgmiLinkWidth [NUM_XGMI_LEVELS]; 514 uint16_t XgmiFclkFreq [NUM_XGMI_LEVELS]; 515 uint16_t XgmiUclkFreq [NUM_XGMI_LEVELS]; 516 uint16_t XgmiSocclkFreq [NUM_XGMI_LEVELS]; 517 uint16_t XgmiSocVoltage [NUM_XGMI_LEVELS]; 518 519 uint32_t DebugOverrides; 520 QuadraticInt_t ReservedEquation0; 521 QuadraticInt_t ReservedEquation1; 522 QuadraticInt_t ReservedEquation2; 523 QuadraticInt_t ReservedEquation3; 524 525 uint16_t MinVoltageUlvGfx; 526 uint16_t MinVoltageUlvSoc; 527 528 uint16_t MGpuFanBoostLimitRpm; 529 uint16_t padding16_Fan; 530 531 uint16_t FanGainVrMem0; 532 uint16_t FanGainVrMem1; 533 534 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; 535 536 uint32_t Reserved[11]; 537 538 uint32_t Padding32[3]; 539 540 uint16_t MaxVoltageStepGfx; 541 uint16_t MaxVoltageStepSoc; 542 543 uint8_t VddGfxVrMapping; 544 uint8_t VddSocVrMapping; 545 uint8_t VddMem0VrMapping; 546 uint8_t VddMem1VrMapping; 547 548 uint8_t GfxUlvPhaseSheddingMask; 549 uint8_t SocUlvPhaseSheddingMask; 550 uint8_t ExternalSensorPresent; 551 uint8_t Padding8_V; 552 553 554 uint16_t GfxMaxCurrent; 555 int8_t GfxOffset; 556 uint8_t Padding_TelemetryGfx; 557 558 uint16_t SocMaxCurrent; 559 int8_t SocOffset; 560 uint8_t Padding_TelemetrySoc; 561 562 uint16_t Mem0MaxCurrent; 563 int8_t Mem0Offset; 564 uint8_t Padding_TelemetryMem0; 565 566 uint16_t Mem1MaxCurrent; 567 int8_t Mem1Offset; 568 uint8_t Padding_TelemetryMem1; 569 570 571 uint8_t AcDcGpio; 572 uint8_t AcDcPolarity; 573 uint8_t VR0HotGpio; 574 uint8_t VR0HotPolarity; 575 576 uint8_t VR1HotGpio; 577 uint8_t VR1HotPolarity; 578 uint8_t Padding1; 579 uint8_t Padding2; 580 581 582 583 uint8_t LedPin0; 584 uint8_t LedPin1; 585 uint8_t LedPin2; 586 uint8_t padding8_4; 587 588 589 uint8_t PllGfxclkSpreadEnabled; 590 uint8_t PllGfxclkSpreadPercent; 591 uint16_t PllGfxclkSpreadFreq; 592 593 uint8_t UclkSpreadEnabled; 594 uint8_t UclkSpreadPercent; 595 uint16_t UclkSpreadFreq; 596 597 uint8_t FclkSpreadEnabled; 598 uint8_t FclkSpreadPercent; 599 uint16_t FclkSpreadFreq; 600 601 uint8_t FllGfxclkSpreadEnabled; 602 uint8_t FllGfxclkSpreadPercent; 603 uint16_t FllGfxclkSpreadFreq; 604 605 I2cControllerConfig_t I2cControllers[I2C_CONTROLLER_NAME_COUNT]; 606 607 uint32_t BoardReserved[10]; 608 609 610 uint32_t MmHubPadding[8]; 611 612} PPTable_t; 613#pragma pack(pop) 614 615typedef struct { 616 617 uint16_t GfxclkAverageLpfTau; 618 uint16_t SocclkAverageLpfTau; 619 uint16_t UclkAverageLpfTau; 620 uint16_t GfxActivityLpfTau; 621 uint16_t UclkActivityLpfTau; 622 uint16_t SocketPowerLpfTau; 623 624 625 uint32_t MmHubPadding[8]; 626} DriverSmuConfig_t; 627 628typedef struct { 629 630 uint16_t GfxclkFmin; 631 uint16_t GfxclkFmax; 632 uint16_t GfxclkFreq1; 633 uint16_t GfxclkVolt1; 634 uint16_t GfxclkFreq2; 635 uint16_t GfxclkVolt2; 636 uint16_t GfxclkFreq3; 637 uint16_t GfxclkVolt3; 638 uint16_t UclkFmax; 639 int16_t OverDrivePct; 640 uint16_t FanMaximumRpm; 641 uint16_t FanMinimumPwm; 642 uint16_t FanTargetTemperature; 643 uint16_t MaxOpTemp; 644 uint16_t FanZeroRpmEnable; 645 uint16_t Padding; 646 647} OverDriveTable_t; 648 649typedef struct { 650 uint16_t CurrClock[PPCLK_COUNT]; 651 uint16_t AverageGfxclkFrequency; 652 uint16_t AverageSocclkFrequency; 653 uint16_t AverageUclkFrequency ; 654 uint16_t AverageGfxActivity ; 655 uint16_t AverageUclkActivity ; 656 uint8_t CurrSocVoltageOffset ; 657 uint8_t CurrGfxVoltageOffset ; 658 uint8_t CurrMemVidOffset ; 659 uint8_t Padding8 ; 660 uint16_t CurrSocketPower ; 661 uint16_t TemperatureEdge ; 662 uint16_t TemperatureHotspot ; 663 uint16_t TemperatureHBM ; 664 uint16_t TemperatureVrGfx ; 665 uint16_t TemperatureVrSoc ; 666 uint16_t TemperatureVrMem0 ; 667 uint16_t TemperatureVrMem1 ; 668 uint16_t TemperatureLiquid ; 669 uint16_t TemperaturePlx ; 670 uint32_t ThrottlerStatus ; 671 672 uint8_t LinkDpmLevel; 673 uint16_t AverageSocketPower; 674 uint8_t Padding; 675 676 677 uint32_t MmHubPadding[7]; 678} SmuMetrics_t; 679 680typedef struct { 681 uint16_t MinClock; 682 uint16_t MaxClock; 683 uint16_t MinUclk; 684 uint16_t MaxUclk; 685 686 uint8_t WmSetting; 687 uint8_t Padding[3]; 688} WatermarkRowGeneric_t; 689 690#define NUM_WM_RANGES 4 691 692typedef enum { 693 WM_SOCCLK = 0, 694 WM_DCEFCLK, 695 WM_COUNT_PP, 696} WM_CLOCK_e; 697 698typedef struct { 699 700 WatermarkRowGeneric_t WatermarkRow[WM_COUNT_PP][NUM_WM_RANGES]; 701 702 uint32_t MmHubPadding[7]; 703} Watermarks_t; 704 705typedef struct { 706 uint16_t avgPsmCount[45]; 707 uint16_t minPsmCount[45]; 708 float avgPsmVoltage[45]; 709 float minPsmVoltage[45]; 710 711 uint16_t avgScsPsmCount; 712 uint16_t minScsPsmCount; 713 float avgScsPsmVoltage; 714 float minScsPsmVoltage; 715 716 717 uint32_t MmHubPadding[6]; 718} AvfsDebugTable_t; 719 720typedef struct { 721 uint8_t AvfsVersion; 722 uint8_t AvfsEn[AVFS_VOLTAGE_COUNT]; 723 724 uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT]; 725 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 726 727 uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT]; 728 uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT]; 729 uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT]; 730 uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT]; 731 732 int32_t VFT0_m1[AVFS_VOLTAGE_COUNT]; 733 int32_t VFT0_m2[AVFS_VOLTAGE_COUNT]; 734 int32_t VFT0_b[AVFS_VOLTAGE_COUNT]; 735 736 int32_t VFT1_m1[AVFS_VOLTAGE_COUNT]; 737 int32_t VFT1_m2[AVFS_VOLTAGE_COUNT]; 738 int32_t VFT1_b[AVFS_VOLTAGE_COUNT]; 739 740 int32_t VFT2_m1[AVFS_VOLTAGE_COUNT]; 741 int32_t VFT2_m2[AVFS_VOLTAGE_COUNT]; 742 int32_t VFT2_b[AVFS_VOLTAGE_COUNT]; 743 744 int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT]; 745 int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT]; 746 int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT]; 747 748 int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT]; 749 int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT]; 750 int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT]; 751 752 uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT]; 753 uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT]; 754 uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT]; 755 756 uint32_t VInversion[AVFS_VOLTAGE_COUNT]; 757 758 759 int32_t P2V_m1[AVFS_VOLTAGE_COUNT]; 760 int32_t P2V_m2[AVFS_VOLTAGE_COUNT]; 761 int32_t P2V_b[AVFS_VOLTAGE_COUNT]; 762 763 uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; 764 765 uint32_t EnabledAvfsModules; 766 767 uint32_t MmHubPadding[7]; 768} AvfsFuseOverride_t; 769 770typedef struct { 771 772 uint8_t Gfx_ActiveHystLimit; 773 uint8_t Gfx_IdleHystLimit; 774 uint8_t Gfx_FPS; 775 uint8_t Gfx_MinActiveFreqType; 776 uint8_t Gfx_BoosterFreqType; 777 uint8_t Gfx_UseRlcBusy; 778 uint16_t Gfx_MinActiveFreq; 779 uint16_t Gfx_BoosterFreq; 780 uint16_t Gfx_PD_Data_time_constant; 781 uint32_t Gfx_PD_Data_limit_a; 782 uint32_t Gfx_PD_Data_limit_b; 783 uint32_t Gfx_PD_Data_limit_c; 784 uint32_t Gfx_PD_Data_error_coeff; 785 uint32_t Gfx_PD_Data_error_rate_coeff; 786 787 uint8_t Soc_ActiveHystLimit; 788 uint8_t Soc_IdleHystLimit; 789 uint8_t Soc_FPS; 790 uint8_t Soc_MinActiveFreqType; 791 uint8_t Soc_BoosterFreqType; 792 uint8_t Soc_UseRlcBusy; 793 uint16_t Soc_MinActiveFreq; 794 uint16_t Soc_BoosterFreq; 795 uint16_t Soc_PD_Data_time_constant; 796 uint32_t Soc_PD_Data_limit_a; 797 uint32_t Soc_PD_Data_limit_b; 798 uint32_t Soc_PD_Data_limit_c; 799 uint32_t Soc_PD_Data_error_coeff; 800 uint32_t Soc_PD_Data_error_rate_coeff; 801 802 uint8_t Mem_ActiveHystLimit; 803 uint8_t Mem_IdleHystLimit; 804 uint8_t Mem_FPS; 805 uint8_t Mem_MinActiveFreqType; 806 uint8_t Mem_BoosterFreqType; 807 uint8_t Mem_UseRlcBusy; 808 uint16_t Mem_MinActiveFreq; 809 uint16_t Mem_BoosterFreq; 810 uint16_t Mem_PD_Data_time_constant; 811 uint32_t Mem_PD_Data_limit_a; 812 uint32_t Mem_PD_Data_limit_b; 813 uint32_t Mem_PD_Data_limit_c; 814 uint32_t Mem_PD_Data_error_coeff; 815 uint32_t Mem_PD_Data_error_rate_coeff; 816 817 uint8_t Fclk_ActiveHystLimit; 818 uint8_t Fclk_IdleHystLimit; 819 uint8_t Fclk_FPS; 820 uint8_t Fclk_MinActiveFreqType; 821 uint8_t Fclk_BoosterFreqType; 822 uint8_t Fclk_UseRlcBusy; 823 uint16_t Fclk_MinActiveFreq; 824 uint16_t Fclk_BoosterFreq; 825 uint16_t Fclk_PD_Data_time_constant; 826 uint32_t Fclk_PD_Data_limit_a; 827 uint32_t Fclk_PD_Data_limit_b; 828 uint32_t Fclk_PD_Data_limit_c; 829 uint32_t Fclk_PD_Data_error_coeff; 830 uint32_t Fclk_PD_Data_error_rate_coeff; 831 832} DpmActivityMonitorCoeffInt_t; 833 834#define TABLE_PPTABLE 0 835#define TABLE_WATERMARKS 1 836#define TABLE_AVFS 2 837#define TABLE_AVFS_PSM_DEBUG 3 838#define TABLE_AVFS_FUSE_OVERRIDE 4 839#define TABLE_PMSTATUSLOG 5 840#define TABLE_SMU_METRICS 6 841#define TABLE_DRIVER_SMU_CONFIG 7 842#define TABLE_ACTIVITY_MONITOR_COEFF 8 843#define TABLE_OVERDRIVE 9 844#define TABLE_COUNT 10 845 846 847#define UCLK_SWITCH_SLOW 0 848#define UCLK_SWITCH_FAST 1 849 850 851#define SQ_Enable_MASK 0x1 852#define SQ_IR_MASK 0x2 853#define SQ_PCC_MASK 0x4 854#define SQ_EDC_MASK 0x8 855 856#define TCP_Enable_MASK 0x100 857#define TCP_IR_MASK 0x200 858#define TCP_PCC_MASK 0x400 859#define TCP_EDC_MASK 0x800 860 861#define TD_Enable_MASK 0x10000 862#define TD_IR_MASK 0x20000 863#define TD_PCC_MASK 0x40000 864#define TD_EDC_MASK 0x80000 865 866#define DB_Enable_MASK 0x1000000 867#define DB_IR_MASK 0x2000000 868#define DB_PCC_MASK 0x4000000 869#define DB_EDC_MASK 0x8000000 870 871#define SQ_Enable_SHIFT 0 872#define SQ_IR_SHIFT 1 873#define SQ_PCC_SHIFT 2 874#define SQ_EDC_SHIFT 3 875 876#define TCP_Enable_SHIFT 8 877#define TCP_IR_SHIFT 9 878#define TCP_PCC_SHIFT 10 879#define TCP_EDC_SHIFT 11 880 881#define TD_Enable_SHIFT 16 882#define TD_IR_SHIFT 17 883#define TD_PCC_SHIFT 18 884#define TD_EDC_SHIFT 19 885 886#define DB_Enable_SHIFT 24 887#define DB_IR_SHIFT 25 888#define DB_PCC_SHIFT 26 889#define DB_EDC_SHIFT 27 890 891#define REMOVE_FMAX_MARGIN_BIT 0x0 892#define REMOVE_DCTOL_MARGIN_BIT 0x1 893#define REMOVE_PLATFORM_MARGIN_BIT 0x2 894 895#endif 896