Lines Matching refs:uint32_t
277 uint32_t eccPadding;
404 uint32_t Spare[8];
405 uint32_t MmHubPadding[8]; // SMU internal use
430 uint32_t a; // store in IEEE float format in this variable
431 uint32_t b; // store in IEEE float format in this variable
432 uint32_t c; // store in IEEE float format in this variable
436 uint32_t a; // store in fixed point, [31:20] signed integer, [19:0] fractional bits
437 uint32_t b; // store in fixed point, [31:20] signed integer, [19:0] fractional bits
438 uint32_t c; // store in fixed point, [31:20] signed integer, [19:0] fractional bits
442 uint32_t m; // store in IEEE float format in this variable
443 uint32_t b; // store in IEEE float format in this variable
447 uint32_t a; // store in IEEE float format in this variable
448 uint32_t b; // store in IEEE float format in this variable
449 uint32_t c; // store in IEEE float format in this variable
462 uint32_t Fset[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //in GHz, store in IEEE float format
463 uint32_t Vdroop[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //in V , store in IEEE float format
606 uint32_t Version;
609 uint32_t FeaturesToRun[NUM_FEATURES / 32];
622 uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime)
629 uint32_t ApccPlusResidencyLimit;
635 uint32_t PaddingAPCC;
640 uint32_t ThrottlerControlMask; // See Throtter masks defines
643 uint32_t FwDStateMask; // See FW DState masks defines
692 uint32_t Paddingclks;
696 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz
721 uint32_t GfxGpoVotingAllow; //For indicating which feature changes should result in a GPO table recalculation
723 uint32_t GfxGpoPadding32[4];
734 uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.
739 uint32_t DcsParamPadding[5];
816 uint32_t DebugOverrides;
830 uint32_t VcBtcPsmA; // A_PSM
831 uint32_t VcBtcPsmB; // B_PSM
832 uint32_t VcBtcVminA; // A_VMIN
833 uint32_t VcBtcVminB; // B_VMIN
839 uint32_t SkuReserved[8];
845 uint32_t GamingClk[6];
883 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16)
928 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.
953 uint32_t BoardReserved[11];
958 uint32_t MmHubPadding[8]; // SMU internal use
966 uint32_t Version;
969 uint32_t FeaturesToRun[NUM_FEATURES / 32];
982 uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime)
989 uint32_t ApccPlusResidencyLimit;
995 uint32_t PaddingAPCC;
1000 uint32_t ThrottlerControlMask; // See Throtter masks defines
1003 uint32_t FwDStateMask; // See FW DState masks defines
1052 uint32_t Paddingclks;
1056 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz
1081 uint32_t GfxGpoVotingAllow; //For indicating which feature changes should result in a GPO table recalculation
1083 uint32_t GfxGpoPadding32[4];
1094 uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.
1099 uint32_t DcsParamPadding[5];
1176 uint32_t DebugOverrides;
1190 uint32_t VcBtcPsmA; // A_PSM
1191 uint32_t VcBtcPsmB; // B_PSM
1192 uint32_t VcBtcVminA; // A_VMIN
1193 uint32_t VcBtcVminB; // B_VMIN
1199 uint32_t SkuReserved[63];
1206 uint32_t GamingClk[6];
1244 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16)
1289 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.
1314 uint32_t BoardReserved[11];
1319 uint32_t MmHubPadding[8]; // SMU internal use
1339 uint32_t Spare[7];
1341 uint32_t MmHubPadding[8]; // SMU internal use
1368 uint32_t Spare[8];
1370 uint32_t MmHubPadding[8]; // SMU internal use
1374 uint32_t CurrClock[PPCLK_COUNT];
1402 uint32_t ThrottlerStatus ;
1415 uint32_t EnergyAccumulator;
1429 uint32_t CurrClock[PPCLK_COUNT];
1457 uint32_t AccCnt ;
1472 uint32_t EnergyAccumulator;
1486 uint32_t CurrClock[PPCLK_COUNT];
1514 uint32_t AccCnt;
1529 uint32_t EnergyAccumulator;
1540 uint32_t PublicSerialNumLower32;
1541 uint32_t PublicSerialNumUpper32;
1546 uint32_t CurrClock[PPCLK_COUNT];
1574 uint32_t AccCnt;
1589 uint32_t EnergyAccumulator;
1614 uint32_t Spare[1];
1617 uint32_t MmHubPadding[8]; // SMU internal use
1655 uint32_t MmHubPadding[8]; // SMU internal use
1668 uint32_t MmHubPadding[8]; // SMU internal use
1705 uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT];
1706 uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT];
1707 uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT];
1709 uint32_t VInversion[AVFS_VOLTAGE_COUNT]; // in mV with 2 fractional bits
1716 uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units
1718 uint32_t EnabledAvfsModules[3]; //Sienna_Cichlid - 67 AVFS modules
1724 uint32_t MmHubPadding[8]; // SMU internal use
1737 uint32_t Gfx_PD_Data_limit_a; // Q16
1738 uint32_t Gfx_PD_Data_limit_b; // Q16
1739 uint32_t Gfx_PD_Data_limit_c; // Q16
1740 uint32_t Gfx_PD_Data_error_coeff; // Q16
1741 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16
1752 uint32_t Fclk_PD_Data_limit_a; // Q16
1753 uint32_t Fclk_PD_Data_limit_b; // Q16
1754 uint32_t Fclk_PD_Data_limit_c; // Q16
1755 uint32_t Fclk_PD_Data_error_coeff; // Q16
1756 uint32_t Fclk_PD_Data_error_rate_coeff; // Q16
1767 uint32_t Mem_PD_Data_limit_a; // Q16
1768 uint32_t Mem_PD_Data_limit_b; // Q16
1769 uint32_t Mem_PD_Data_limit_c; // Q16
1770 uint32_t Mem_PD_Data_error_coeff; // Q16
1771 uint32_t Mem_PD_Data_error_rate_coeff; // Q16
1773 uint32_t Mem_UpThreshold_Limit; // Q16
1783 uint32_t MmHubPadding[8]; // SMU internal use
1828 uint32_t MmHubPadding[8]; // SMU internal use