drm/vc4/vc4_validate_shaders.c

51 	uint32_t ip;
54 	uint32_t max_ip;
67 	uint32_t live_min_clamp_offsets[LIVE_REG_COUNT];
69 	uint32_t live_immediates[LIVE_REG_COUNT];
100 static uint32_t
101 waddr_to_live_reg_index(uint32_t waddr, bool is_b)
115 static uint32_t
118 	uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
119 	uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
120 	uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
121 	uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
134 live_reg_is_upper_half(uint32_t lri)
141 is_tmu_submit(uint32_t waddr)
148 is_tmu_write(uint32_t waddr)
159 	uint32_t s = validated_shader->num_texture_samples;
188 	uint32_t waddr = (is_mul ?
191 	uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
192 	uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
196 	uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
199 		uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
200 		uint32_t clamp_reg, clamp_offset;
289 	uint32_t o = validated_shader->num_uniform_addr_offsets;
290 	uint32_t num_uniforms = validated_shader->uniforms_size / 4;
391 	uint32_t waddr = (is_mul ?
394 	uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
400 		uint32_t cond_add = QPU_GET_FIELD(inst, QPU_COND_ADD);
401 		uint32_t cond_mul = QPU_GET_FIELD(inst, QPU_COND_MUL);
482 	uint32_t op_add = QPU_GET_FIELD(inst, QPU_OP_ADD);
483 	uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
484 	uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
485 	uint32_t cond_add = QPU_GET_FIELD(inst, QPU_COND_ADD);
486 	uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
487 	uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
488 	uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
489 	uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
490 	uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
492 	uint32_t lri_add_a, lri_add, lri_mul;
557 	uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
558 	uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
581 	uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
582 	uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
604 	uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
605 	uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
606 	uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
610 		/* This can't overflow the uint32_t, because we're reading 8
637 	uint32_t max_branch_target = 0;
644 		uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
645 		uint32_t after_delay_ip = ip + 4;
646 		uint32_t branch_target_ip;
747 	uint32_t ip = validation_state->ip;
784 	uint32_t last_thread_switch_ip = -3;
785 	uint32_t ip;
813 		uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);