1/* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ 27#define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ 28 29#include "gpio_regs.h" 30 31/****************************** new register headers */ 32/*** following in header */ 33 34#define DDC_GPIO_REG_LIST_ENTRY(type, cd, id) \ 35 .type ## _reg = REG(DC_GPIO_DDC ## id ## _ ## type),\ 36 .type ## _mask = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## _MASK,\ 37 .type ## _shift = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## __SHIFT 38 39#define DDC_GPIO_REG_LIST(cd, id) \ 40 {\ 41 DDC_GPIO_REG_LIST_ENTRY(MASK, cd, id),\ 42 DDC_GPIO_REG_LIST_ENTRY(A, cd, id),\ 43 DDC_GPIO_REG_LIST_ENTRY(EN, cd, id),\ 44 DDC_GPIO_REG_LIST_ENTRY(Y, cd, id)\ 45 } 46 47#define DDC_REG_LIST(cd, id) \ 48 DDC_GPIO_REG_LIST(cd, id),\ 49 .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP) 50 51 #define DDC_REG_LIST_DCN2(cd, id) \ 52 DDC_GPIO_REG_LIST(cd, id),\ 53 .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP),\ 54 .phy_aux_cntl = REG(PHY_AUX_CNTL), \ 55 .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5) 56 57#define DDC_GPIO_VGA_REG_LIST_ENTRY(type, cd)\ 58 .type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\ 59 .type ## _mask = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## _MASK,\ 60 .type ## _shift = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## __SHIFT 61 62#define DDC_GPIO_VGA_REG_LIST(cd) \ 63 {\ 64 DDC_GPIO_VGA_REG_LIST_ENTRY(MASK, cd),\ 65 DDC_GPIO_VGA_REG_LIST_ENTRY(A, cd),\ 66 DDC_GPIO_VGA_REG_LIST_ENTRY(EN, cd),\ 67 DDC_GPIO_VGA_REG_LIST_ENTRY(Y, cd)\ 68 } 69 70#define DDC_VGA_REG_LIST(cd) \ 71 DDC_GPIO_VGA_REG_LIST(cd),\ 72 .ddc_setup = mmDC_I2C_DDCVGA_SETUP 73 74#define DDC_GPIO_I2C_REG_LIST_ENTRY(type, cd) \ 75 .type ## _reg = REG(DC_GPIO_I2CPAD_ ## type),\ 76 .type ## _mask = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## _MASK,\ 77 .type ## _shift = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## __SHIFT 78 79#define DDC_GPIO_I2C_REG_LIST(cd) \ 80 {\ 81 DDC_GPIO_I2C_REG_LIST_ENTRY(MASK, cd),\ 82 DDC_GPIO_I2C_REG_LIST_ENTRY(A, cd),\ 83 DDC_GPIO_I2C_REG_LIST_ENTRY(EN, cd),\ 84 DDC_GPIO_I2C_REG_LIST_ENTRY(Y, cd)\ 85 } 86 87#define DDC_I2C_REG_LIST(cd) \ 88 DDC_GPIO_I2C_REG_LIST(cd),\ 89 .ddc_setup = 0 90 91#define DDC_I2C_REG_LIST_DCN2(cd) \ 92 DDC_GPIO_I2C_REG_LIST(cd),\ 93 .ddc_setup = 0,\ 94 .phy_aux_cntl = REG(PHY_AUX_CNTL), \ 95 .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5) 96#define DDC_MASK_SH_LIST_COMMON(mask_sh) \ 97 SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\ 98 SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_ENABLE, mask_sh),\ 99 SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_MODE, mask_sh),\ 100 SF_DDC(DC_GPIO_DDC1_MASK, DC_GPIO_DDC1DATA_PD_EN, mask_sh),\ 101 SF_DDC(DC_GPIO_DDC1_MASK, DC_GPIO_DDC1CLK_PD_EN, mask_sh),\ 102 SF_DDC(DC_GPIO_DDC1_MASK, AUX_PAD1_MODE, mask_sh) 103 104#define DDC_MASK_SH_LIST(mask_sh) \ 105 DDC_MASK_SH_LIST_COMMON(mask_sh),\ 106 SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SDA_PD_DIS, mask_sh),\ 107 SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SCL_PD_DIS, mask_sh) 108 109#define DDC_MASK_SH_LIST_DCN2(mask_sh, cd) \ 110 {DDC_MASK_SH_LIST_COMMON(mask_sh),\ 111 0,\ 112 0,\ 113 (PHY_AUX_CNTL__AUX## cd ##_PAD_RXSEL## mask_sh),\ 114 (DC_GPIO_AUX_CTRL_5__DDC_PAD## cd ##_I2CMODE## mask_sh)} 115 116#define DDC_MASK_SH_LIST_DCN2_VGA(mask_sh) \ 117 {DDC_MASK_SH_LIST_COMMON(mask_sh),\ 118 0,\ 119 0,\ 120 0,\ 121 0} 122 123struct ddc_registers { 124 struct gpio_registers gpio; 125 uint32_t ddc_setup; 126 uint32_t phy_aux_cntl; 127 uint32_t dc_gpio_aux_ctrl_5; 128}; 129 130struct ddc_sh_mask { 131 /* i2c_dd_setup */ 132 uint32_t DC_I2C_DDC1_ENABLE; 133 uint32_t DC_I2C_DDC1_EDID_DETECT_ENABLE; 134 uint32_t DC_I2C_DDC1_EDID_DETECT_MODE; 135 /* ddc1_mask */ 136 uint32_t DC_GPIO_DDC1DATA_PD_EN; 137 uint32_t DC_GPIO_DDC1CLK_PD_EN; 138 uint32_t AUX_PAD1_MODE; 139 /* i2cpad_mask */ 140 uint32_t DC_GPIO_SDA_PD_DIS; 141 uint32_t DC_GPIO_SCL_PD_DIS; 142 //phy_aux_cntl 143 uint32_t AUX_PAD_RXSEL; 144 uint32_t DDC_PAD_I2CMODE; 145}; 146 147 148 149/*** following in dc_resource */ 150 151#define ddc_data_regs(id) \ 152{\ 153 DDC_REG_LIST(DATA, id)\ 154} 155 156#define ddc_clk_regs(id) \ 157{\ 158 DDC_REG_LIST(CLK, id)\ 159} 160 161#define ddc_vga_data_regs \ 162{\ 163 DDC_VGA_REG_LIST(DATA)\ 164} 165 166#define ddc_vga_clk_regs \ 167{\ 168 DDC_VGA_REG_LIST(CLK)\ 169} 170 171#define ddc_i2c_data_regs \ 172{\ 173 DDC_I2C_REG_LIST(SDA)\ 174} 175 176#define ddc_i2c_clk_regs \ 177{\ 178 DDC_I2C_REG_LIST(SCL)\ 179} 180#define ddc_data_regs_dcn2(id) \ 181{\ 182 DDC_REG_LIST_DCN2(DATA, id)\ 183} 184 185#define ddc_clk_regs_dcn2(id) \ 186{\ 187 DDC_REG_LIST_DCN2(CLK, id)\ 188} 189 190#define ddc_i2c_data_regs_dcn2 \ 191{\ 192 DDC_I2C_REG_LIST_DCN2(SDA)\ 193} 194 195#define ddc_i2c_clk_regs_dcn2 \ 196{\ 197 DDC_REG_LIST_DCN2(SCL)\ 198} 199 200 201#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ */ 202