1/* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#ifndef __DCN20_DCCG_H__ 27#define __DCN20_DCCG_H__ 28 29#include "dccg.h" 30 31#define DCCG_COMMON_REG_LIST_DCN_BASE() \ 32 SR(DPPCLK_DTO_CTRL),\ 33 DCCG_SRII(DTO_PARAM, DPPCLK, 0),\ 34 DCCG_SRII(DTO_PARAM, DPPCLK, 1),\ 35 DCCG_SRII(DTO_PARAM, DPPCLK, 2),\ 36 DCCG_SRII(DTO_PARAM, DPPCLK, 3),\ 37 SR(REFCLK_CNTL),\ 38 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\ 39 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\ 40 SR(DISPCLK_FREQ_CHANGE_CNTL) 41 42#define DCCG_REG_LIST_DCN2() \ 43 DCCG_COMMON_REG_LIST_DCN_BASE(),\ 44 DCCG_SRII(DTO_PARAM, DPPCLK, 4),\ 45 DCCG_SRII(DTO_PARAM, DPPCLK, 5),\ 46 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\ 47 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\ 48 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\ 49 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5) 50 51#define DCCG_SF(reg_name, field_name, post_fix)\ 52 .field_name = reg_name ## __ ## field_name ## post_fix 53 54#define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\ 55 .field_prefix ## _ ## field_name[inst] = reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix 56 57#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\ 58 .field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix 59 60#define DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \ 61 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\ 62 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\ 63 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\ 64 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\ 65 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\ 66 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\ 67 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\ 68 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\ 69 DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\ 70 DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\ 71 DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\ 72 DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh),\ 73 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\ 74 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\ 75 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\ 76 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\ 77 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\ 78 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\ 79 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\ 80 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\ 81 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\ 82 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\ 83 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\ 84 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh) 85 86 87 88 89#define DCCG_MASK_SH_LIST_DCN2(mask_sh) \ 90 DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ 91 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\ 92 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\ 93 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\ 94 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh),\ 95 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\ 96 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\ 97 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 4, mask_sh),\ 98 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 5, mask_sh),\ 99 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\ 100 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh),\ 101 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 4, mask_sh),\ 102 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 5, mask_sh) 103 104#define DCCG_MASK_SH_LIST_DCN2_1(mask_sh) \ 105 DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ 106 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\ 107 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\ 108 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\ 109 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh),\ 110 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\ 111 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\ 112 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\ 113 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh) 114 115 116#define DCCG_REG_FIELD_LIST(type) \ 117 type DPPCLK0_DTO_PHASE;\ 118 type DPPCLK0_DTO_MODULO;\ 119 type DPPCLK_DTO_ENABLE[6];\ 120 type DPPCLK_DTO_DB_EN[6];\ 121 type REFCLK_CLOCK_EN;\ 122 type REFCLK_SRC_SEL;\ 123 type DISPCLK_STEP_DELAY;\ 124 type DISPCLK_STEP_SIZE;\ 125 type DISPCLK_FREQ_RAMP_DONE;\ 126 type DISPCLK_MAX_ERRDET_CYCLES;\ 127 type DCCG_FIFO_ERRDET_RESET;\ 128 type DCCG_FIFO_ERRDET_STATE;\ 129 type DCCG_FIFO_ERRDET_OVR_EN;\ 130 type DISPCLK_CHG_FWD_CORR_DISABLE;\ 131 type DISPCLK_FREQ_CHANGE_CNTL;\ 132 type OTG_ADD_PIXEL[MAX_PIPES];\ 133 type OTG_DROP_PIXEL[MAX_PIPES]; 134 135#define DCCG3_REG_FIELD_LIST(type) \ 136 type HDMICHARCLK0_EN;\ 137 type HDMICHARCLK0_SRC_SEL;\ 138 type PHYASYMCLK_FORCE_EN;\ 139 type PHYASYMCLK_FORCE_SRC_SEL;\ 140 type PHYBSYMCLK_FORCE_EN;\ 141 type PHYBSYMCLK_FORCE_SRC_SEL;\ 142 type PHYCSYMCLK_FORCE_EN;\ 143 type PHYCSYMCLK_FORCE_SRC_SEL; 144 145#define DCCG31_REG_FIELD_LIST(type) \ 146 type PHYDSYMCLK_FORCE_EN;\ 147 type PHYDSYMCLK_FORCE_SRC_SEL;\ 148 type PHYESYMCLK_FORCE_EN;\ 149 type PHYESYMCLK_FORCE_SRC_SEL;\ 150 type DPSTREAMCLK_PIPE0_EN;\ 151 type DPSTREAMCLK_PIPE1_EN;\ 152 type DPSTREAMCLK_PIPE2_EN;\ 153 type DPSTREAMCLK_PIPE3_EN;\ 154 type HDMISTREAMCLK0_SRC_SEL;\ 155 type HDMISTREAMCLK0_DTO_FORCE_DIS;\ 156 type SYMCLK32_SE0_SRC_SEL;\ 157 type SYMCLK32_SE1_SRC_SEL;\ 158 type SYMCLK32_SE2_SRC_SEL;\ 159 type SYMCLK32_SE3_SRC_SEL;\ 160 type SYMCLK32_SE0_EN;\ 161 type SYMCLK32_SE1_EN;\ 162 type SYMCLK32_SE2_EN;\ 163 type SYMCLK32_SE3_EN;\ 164 type SYMCLK32_LE0_SRC_SEL;\ 165 type SYMCLK32_LE1_SRC_SEL;\ 166 type SYMCLK32_LE0_EN;\ 167 type SYMCLK32_LE1_EN;\ 168 type DTBCLK_DTO_ENABLE[MAX_PIPES];\ 169 type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\ 170 type PIPE_DTO_SRC_SEL[MAX_PIPES];\ 171 type DTBCLK_DTO_DIV[MAX_PIPES];\ 172 type DCCG_AUDIO_DTO_SEL;\ 173 type DCCG_AUDIO_DTO0_SOURCE_SEL;\ 174 type DENTIST_DISPCLK_CHG_MODE;\ 175 type DSCCLK0_DTO_PHASE;\ 176 type DSCCLK0_DTO_MODULO;\ 177 type DSCCLK1_DTO_PHASE;\ 178 type DSCCLK1_DTO_MODULO;\ 179 type DSCCLK2_DTO_PHASE;\ 180 type DSCCLK2_DTO_MODULO;\ 181 type DSCCLK0_DTO_ENABLE;\ 182 type DSCCLK1_DTO_ENABLE;\ 183 type DSCCLK2_DTO_ENABLE;\ 184 type SYMCLK32_ROOT_SE0_GATE_DISABLE;\ 185 type SYMCLK32_ROOT_SE1_GATE_DISABLE;\ 186 type SYMCLK32_ROOT_SE2_GATE_DISABLE;\ 187 type SYMCLK32_ROOT_SE3_GATE_DISABLE;\ 188 type SYMCLK32_SE0_GATE_DISABLE;\ 189 type SYMCLK32_SE1_GATE_DISABLE;\ 190 type SYMCLK32_SE2_GATE_DISABLE;\ 191 type SYMCLK32_SE3_GATE_DISABLE;\ 192 type SYMCLK32_ROOT_LE0_GATE_DISABLE;\ 193 type SYMCLK32_ROOT_LE1_GATE_DISABLE;\ 194 type SYMCLK32_LE0_GATE_DISABLE;\ 195 type SYMCLK32_LE1_GATE_DISABLE;\ 196 type DPSTREAMCLK_ROOT_GATE_DISABLE;\ 197 type DPSTREAMCLK_GATE_DISABLE;\ 198 type HDMISTREAMCLK0_DTO_PHASE;\ 199 type HDMISTREAMCLK0_DTO_MODULO;\ 200 type HDMICHARCLK0_GATE_DISABLE;\ 201 type HDMICHARCLK0_ROOT_GATE_DISABLE; \ 202 type PHYASYMCLK_GATE_DISABLE; \ 203 type PHYBSYMCLK_GATE_DISABLE; \ 204 type PHYCSYMCLK_GATE_DISABLE; \ 205 type PHYDSYMCLK_GATE_DISABLE; \ 206 type PHYESYMCLK_GATE_DISABLE; 207 208#define DCCG314_REG_FIELD_LIST(type) \ 209 type DSCCLK3_DTO_PHASE;\ 210 type DSCCLK3_DTO_MODULO;\ 211 type DSCCLK3_DTO_ENABLE;\ 212 type DENTIST_DISPCLK_RDIVIDER;\ 213 type DENTIST_DISPCLK_WDIVIDER; 214 215#define DCCG32_REG_FIELD_LIST(type) \ 216 type DPSTREAMCLK0_EN;\ 217 type DPSTREAMCLK1_EN;\ 218 type DPSTREAMCLK2_EN;\ 219 type DPSTREAMCLK3_EN;\ 220 type DPSTREAMCLK0_SRC_SEL;\ 221 type DPSTREAMCLK1_SRC_SEL;\ 222 type DPSTREAMCLK2_SRC_SEL;\ 223 type DPSTREAMCLK3_SRC_SEL;\ 224 type HDMISTREAMCLK0_EN;\ 225 type OTG0_PIXEL_RATE_DIVK1;\ 226 type OTG0_PIXEL_RATE_DIVK2;\ 227 type OTG1_PIXEL_RATE_DIVK1;\ 228 type OTG1_PIXEL_RATE_DIVK2;\ 229 type OTG2_PIXEL_RATE_DIVK1;\ 230 type OTG2_PIXEL_RATE_DIVK2;\ 231 type OTG3_PIXEL_RATE_DIVK1;\ 232 type OTG3_PIXEL_RATE_DIVK2;\ 233 type DTBCLK_P0_SRC_SEL;\ 234 type DTBCLK_P0_EN;\ 235 type DTBCLK_P1_SRC_SEL;\ 236 type DTBCLK_P1_EN;\ 237 type DTBCLK_P2_SRC_SEL;\ 238 type DTBCLK_P2_EN;\ 239 type DTBCLK_P3_SRC_SEL;\ 240 type DTBCLK_P3_EN;\ 241 type DENTIST_DISPCLK_CHG_DONE; 242 243#define DCCG35_REG_FIELD_LIST(type) \ 244 type DPPCLK0_EN;\ 245 type DPPCLK1_EN;\ 246 type DPPCLK2_EN;\ 247 type DPPCLK3_EN;\ 248 type DSCCLK0_EN;\ 249 type DSCCLK1_EN;\ 250 type DSCCLK2_EN;\ 251 type DSCCLK3_EN;\ 252 type DISPCLK_DCCG_GATE_DISABLE;\ 253 type DCCG_GLOBAL_FGCG_REP_DIS; \ 254 type PHYASYMCLK_EN;\ 255 type PHYASYMCLK_SRC_SEL;\ 256 type PHYBSYMCLK_EN;\ 257 type PHYBSYMCLK_SRC_SEL;\ 258 type PHYCSYMCLK_EN;\ 259 type PHYCSYMCLK_SRC_SEL;\ 260 type PHYDSYMCLK_EN;\ 261 type PHYDSYMCLK_SRC_SEL;\ 262 type PHYESYMCLK_EN;\ 263 type PHYESYMCLK_SRC_SEL;\ 264 type PHYASYMCLK_ROOT_GATE_DISABLE;\ 265 type PHYBSYMCLK_ROOT_GATE_DISABLE;\ 266 type PHYCSYMCLK_ROOT_GATE_DISABLE;\ 267 type PHYDSYMCLK_ROOT_GATE_DISABLE;\ 268 type PHYESYMCLK_ROOT_GATE_DISABLE;\ 269 type HDMISTREAMCLK0_GATE_DISABLE;\ 270 type HDMISTREAMCLK1_GATE_DISABLE;\ 271 type HDMISTREAMCLK2_GATE_DISABLE;\ 272 type HDMISTREAMCLK3_GATE_DISABLE;\ 273 type HDMISTREAMCLK4_GATE_DISABLE;\ 274 type HDMISTREAMCLK5_GATE_DISABLE;\ 275 type SYMCLKA_CLOCK_ENABLE;\ 276 type SYMCLKB_CLOCK_ENABLE;\ 277 type SYMCLKC_CLOCK_ENABLE;\ 278 type SYMCLKD_CLOCK_ENABLE;\ 279 type SYMCLKE_CLOCK_ENABLE;\ 280 type SYMCLKA_FE_EN;\ 281 type SYMCLKB_FE_EN;\ 282 type SYMCLKC_FE_EN;\ 283 type SYMCLKD_FE_EN;\ 284 type SYMCLKE_FE_EN;\ 285 type SYMCLKA_SRC_SEL;\ 286 type SYMCLKB_SRC_SEL;\ 287 type SYMCLKC_SRC_SEL;\ 288 type SYMCLKD_SRC_SEL;\ 289 type SYMCLKE_SRC_SEL;\ 290 type SYMCLKA_FE_SRC_SEL;\ 291 type SYMCLKB_FE_SRC_SEL;\ 292 type SYMCLKC_FE_SRC_SEL;\ 293 type SYMCLKD_FE_SRC_SEL;\ 294 type SYMCLKE_FE_SRC_SEL;\ 295 type DTBCLK_P0_GATE_DISABLE;\ 296 type DTBCLK_P1_GATE_DISABLE;\ 297 type DTBCLK_P2_GATE_DISABLE;\ 298 type DTBCLK_P3_GATE_DISABLE;\ 299 type DSCCLK0_ROOT_GATE_DISABLE;\ 300 type DSCCLK1_ROOT_GATE_DISABLE;\ 301 type DSCCLK2_ROOT_GATE_DISABLE;\ 302 type DSCCLK3_ROOT_GATE_DISABLE;\ 303 type SYMCLKA_FE_ROOT_GATE_DISABLE;\ 304 type SYMCLKB_FE_ROOT_GATE_DISABLE;\ 305 type SYMCLKC_FE_ROOT_GATE_DISABLE;\ 306 type SYMCLKD_FE_ROOT_GATE_DISABLE;\ 307 type SYMCLKE_FE_ROOT_GATE_DISABLE;\ 308 type DPPCLK0_ROOT_GATE_DISABLE;\ 309 type DPPCLK1_ROOT_GATE_DISABLE;\ 310 type DPPCLK2_ROOT_GATE_DISABLE;\ 311 type DPPCLK3_ROOT_GATE_DISABLE;\ 312 type HDMISTREAMCLK0_ROOT_GATE_DISABLE;\ 313 type SYMCLKA_ROOT_GATE_DISABLE;\ 314 type SYMCLKB_ROOT_GATE_DISABLE;\ 315 type SYMCLKC_ROOT_GATE_DISABLE;\ 316 type SYMCLKD_ROOT_GATE_DISABLE;\ 317 type SYMCLKE_ROOT_GATE_DISABLE;\ 318 type PHYA_REFCLK_ROOT_GATE_DISABLE;\ 319 type PHYB_REFCLK_ROOT_GATE_DISABLE;\ 320 type PHYC_REFCLK_ROOT_GATE_DISABLE;\ 321 type PHYD_REFCLK_ROOT_GATE_DISABLE;\ 322 type PHYE_REFCLK_ROOT_GATE_DISABLE;\ 323 type DPSTREAMCLK0_ROOT_GATE_DISABLE;\ 324 type DPSTREAMCLK1_ROOT_GATE_DISABLE;\ 325 type DPSTREAMCLK2_ROOT_GATE_DISABLE;\ 326 type DPSTREAMCLK3_ROOT_GATE_DISABLE;\ 327 type DPSTREAMCLK0_GATE_DISABLE;\ 328 type DPSTREAMCLK1_GATE_DISABLE;\ 329 type DPSTREAMCLK2_GATE_DISABLE;\ 330 type DPSTREAMCLK3_GATE_DISABLE;\ 331 332struct dccg_shift { 333 DCCG_REG_FIELD_LIST(uint8_t) 334 DCCG3_REG_FIELD_LIST(uint8_t) 335 DCCG31_REG_FIELD_LIST(uint8_t) 336 DCCG314_REG_FIELD_LIST(uint8_t) 337 DCCG32_REG_FIELD_LIST(uint8_t) 338 DCCG35_REG_FIELD_LIST(uint8_t) 339}; 340 341struct dccg_mask { 342 DCCG_REG_FIELD_LIST(uint32_t) 343 DCCG3_REG_FIELD_LIST(uint32_t) 344 DCCG31_REG_FIELD_LIST(uint32_t) 345 DCCG314_REG_FIELD_LIST(uint32_t) 346 DCCG32_REG_FIELD_LIST(uint32_t) 347 DCCG35_REG_FIELD_LIST(uint32_t) 348}; 349 350struct dccg_registers { 351 uint32_t DPPCLK_DTO_CTRL; 352 uint32_t DPPCLK_DTO_PARAM[6]; 353 uint32_t REFCLK_CNTL; 354 uint32_t DISPCLK_FREQ_CHANGE_CNTL; 355 uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES]; 356 uint32_t HDMICHARCLK_CLOCK_CNTL[6]; 357 uint32_t PHYASYMCLK_CLOCK_CNTL; 358 uint32_t PHYBSYMCLK_CLOCK_CNTL; 359 uint32_t PHYCSYMCLK_CLOCK_CNTL; 360 uint32_t PHYDSYMCLK_CLOCK_CNTL; 361 uint32_t PHYESYMCLK_CLOCK_CNTL; 362 uint32_t DTBCLK_DTO_MODULO[MAX_PIPES]; 363 uint32_t DTBCLK_DTO_PHASE[MAX_PIPES]; 364 uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO; 365 uint32_t DCCG_AUDIO_DTBCLK_DTO_PHASE; 366 uint32_t DCCG_AUDIO_DTO_SOURCE; 367 uint32_t DPSTREAMCLK_CNTL; 368 uint32_t HDMISTREAMCLK_CNTL; 369 uint32_t SYMCLK32_SE_CNTL; 370 uint32_t SYMCLK32_LE_CNTL; 371 uint32_t DENTIST_DISPCLK_CNTL; 372 uint32_t DSCCLK_DTO_CTRL; 373 uint32_t DSCCLK0_DTO_PARAM; 374 uint32_t DSCCLK1_DTO_PARAM; 375 uint32_t DSCCLK2_DTO_PARAM; 376 uint32_t DSCCLK3_DTO_PARAM; 377 uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE; 378 uint32_t DPSTREAMCLK_GATE_DISABLE; 379 uint32_t DCCG_GATE_DISABLE_CNTL; 380 uint32_t DCCG_GATE_DISABLE_CNTL2; 381 uint32_t DCCG_GATE_DISABLE_CNTL3; 382 uint32_t HDMISTREAMCLK0_DTO_PARAM; 383 uint32_t DCCG_GATE_DISABLE_CNTL4; 384 uint32_t OTG_PIXEL_RATE_DIV; 385 uint32_t DTBCLK_P_CNTL; 386 uint32_t DPPCLK_CTRL; 387 uint32_t DCCG_GATE_DISABLE_CNTL5; 388 uint32_t DCCG_GATE_DISABLE_CNTL6; 389 uint32_t DCCG_GLOBAL_FGCG_REP_CNTL; 390 uint32_t SYMCLKA_CLOCK_ENABLE; 391 uint32_t SYMCLKB_CLOCK_ENABLE; 392 uint32_t SYMCLKC_CLOCK_ENABLE; 393 uint32_t SYMCLKD_CLOCK_ENABLE; 394 uint32_t SYMCLKE_CLOCK_ENABLE; 395}; 396 397struct dcn_dccg { 398 struct dccg base; 399 const struct dccg_registers *regs; 400 const struct dccg_shift *dccg_shift; 401 const struct dccg_mask *dccg_mask; 402}; 403 404void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk); 405 406void dccg2_get_dccg_ref_freq(struct dccg *dccg, 407 unsigned int xtalin_freq_inKhz, 408 unsigned int *dccg_ref_freq_inKhz); 409 410void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg, 411 bool en); 412void dccg2_otg_add_pixel(struct dccg *dccg, 413 uint32_t otg_inst); 414void dccg2_otg_drop_pixel(struct dccg *dccg, 415 uint32_t otg_inst); 416 417 418void dccg2_init(struct dccg *dccg); 419 420struct dccg *dccg2_create( 421 struct dc_context *ctx, 422 const struct dccg_registers *regs, 423 const struct dccg_shift *dccg_shift, 424 const struct dccg_mask *dccg_mask); 425 426void dcn_dccg_destroy(struct dccg **dccg); 427 428#endif //__DCN20_DCCG_H__ 429