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f989fa29 |
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13-Feb-2023 |
Jonathan Gray <jsg@jsg.id.au> |
drm/amd/pm: avoid unaligned access warnings When building on OpenBSD/arm64 with clang 15, unaligned access warnings are seen when a union is embedded inside a packed struct. drm/amd/pm/powerplay/hwmgr/vega20_pptable.h:136:17: error: field smcPPTable within 'struct _ATOM_VEGA20_POWERPLAYTABLE' is less aligned than 'PPTable_t' and is usually due to 'struct _ATOM_VEGA20_POWERPLAYTABLE' being packed, which can lead to unaligned accesses [-Werror,-Wunaligned-access] PPTable_t smcPPTable; ^ Make PPTable_t packed to avoid this. Signed-off-by: Jonathan Gray <jsg@jsg.id.au> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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d6810d7d |
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03-May-2022 |
Sathishkumar S <sathishkumar.sundararaju@amd.com> |
drm/amd/pm: support ss metrics read for smu11 support reading smartshift apu and dgpu power for smu11 based asic v2: add new version of SmuMetrics and make calculation more readable (Lijo) v3: avoid calculations that result in -ve values and skip related checks v4: use the current power limit on dGPU and exclude smu 11_0_7 (Lijo) v5: remove redundant code (Lijo) Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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5e9c4451 |
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30-Mar-2022 |
Kent Russell <kent.russell@amd.com> |
drm/amdgpu: Fix unique_id references for Sienna Cichlid Since unique_id is only supported in PMFW 0x3A5300 and higher, we will only be able to use it inside Smu_Metrics_V3_t, which requires PMFW 0x3A4900 and higher. Remove the unique_id/serial_number references from the v1 and v2 tables to avoid any confusion, and return 0 if metrics_v1 or metrics_v2 are used to try to get the unique_id/serial_number. Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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ebd9c071 |
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09-Feb-2022 |
Kent Russell <kent.russell@amd.com> |
drm/amdgpu: Add unique_id support for sienna cichlid This is being added to SMU Metrics, so add the required tie-ins in the kernel. Also create the corresponding unique_id sysfs file. v2: Add FW version check, remove SMU mutex v3: Fix style warning v4: Add MP1 IP_VERSION check to FW version check Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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7952fa0d |
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02-Mar-2022 |
Danijel Slivka <danijel.slivka@amd.com> |
drm/amd/pm: new v3 SmuMetrics data structure for Sienna Cichlid structure changed in smc_fw_version >= 0x3A4900, "uint16_t VcnActivityPercentage" replaced with "uint16_t VcnUsagePercentage0" and "uint16_t VcnUsagePercentage1" Signed-off-by: Danijel Slivka <danijel.slivka@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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83f2726c |
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11-Jan-2022 |
mziya <Mohammadzafar.ziya@amd.com> |
drm/amd/pm: Update smu driver interface for sienna cichlid update smu driver if version to 0x40 V2: Interface version append with sienna_cichlid V3: Aligned with latest driver interface. Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: mziya <Mohammadzafar.ziya@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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837d542a |
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15-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: relocate the power related headers Instead of centralizing all headers in the same folder. Separate them into different folders and place them among those source files those who really need them. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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