drm/vc4/vc4_validate.c

56 static uint32_t
74 static uint32_t
99 size_is_lt(uint32_t width, uint32_t height, int cpp)
106 vc4_use_bo(struct vc4_exec_info *exec, uint32_t hindex)
133 vc4_use_handle(struct vc4_exec_info *exec, uint32_t gem_handles_packet_index)
139 validate_bin_pos(struct vc4_exec_info *exec, void *untrusted, uint32_t pos)
147 static uint32_t
148 gl_shader_rec_size(uint32_t pointer_bits)
150 	uint32_t attribute_count = pointer_bits & 7;
164 		   uint32_t offset, uint8_t tiling_format,
165 		   uint32_t width, uint32_t height, uint8_t cpp)
168 	uint32_t aligned_width, aligned_height, stride, size;
169 	uint32_t utile_w = utile_width(cpp);
170 	uint32_t utile_h = utile_height(cpp);
267 	uint32_t length = *(uint32_t *)(untrusted + 1);
268 	uint32_t offset = *(uint32_t *)(untrusted + 5);
269 	uint32_t max_index = *(uint32_t *)(untrusted + 9);
270 	uint32_t index_size = (*(uint8_t *)(untrusted + 0) >> 4) ? 2 : 1;
297 	*(uint32_t *)(validated + 5) = ib->dma_addr + offset;
305 	uint32_t length = *(uint32_t *)(untrusted + 1);
306 	uint32_t base_index = *(uint32_t *)(untrusted + 5);
307 	uint32_t max_index;
332 	uint32_t i = exec->shader_state_count++;
339 	exec->shader_state[i].addr = *(uint32_t *)untrusted;
347 	*(uint32_t *)validated = (exec->shader_rec_p +
362 	uint32_t tile_state_size;
363 	uint32_t tile_count, bin_addr;
423 	*(uint32_t *)(validated + 0) = exec->tile_alloc_offset;
425 	*(uint32_t *)(validated + 4) = (bin_addr + vc4->bin_alloc_size -
428 	*(uint32_t *)(validated + 8) = bin_addr;
494 	uint32_t len = exec->args->bin_cl_size;
495 	uint32_t dst_offset = 0;
496 	uint32_t src_offset = 0;
576 	  uint32_t texture_handle_index, bool is_cs)
579 	uint32_t p0 = *(uint32_t *)(uniform_data_u + sample->p_offset[0]);
580 	uint32_t p1 = *(uint32_t *)(uniform_data_u + sample->p_offset[1]);
581 	uint32_t p2 = (sample->p_offset[2] != ~0 ?
582 		       *(uint32_t *)(uniform_data_u + sample->p_offset[2]) : 0);
583 	uint32_t p3 = (sample->p_offset[3] != ~0 ?
584 		       *(uint32_t *)(uniform_data_u + sample->p_offset[3]) : 0);
585 	uint32_t *validated_p0 = exec->uniforms_v + sample->p_offset[0];
586 	uint32_t offset = p0 & VC4_TEX_P0_OFFSET_MASK;
587 	uint32_t miplevels = VC4_GET_FIELD(p0, VC4_TEX_P0_MIPLVLS);
588 	uint32_t width = VC4_GET_FIELD(p1, VC4_TEX_P1_WIDTH);
589 	uint32_t height = VC4_GET_FIELD(p1, VC4_TEX_P1_HEIGHT);
590 	uint32_t cpp, tiling_format, utile_w, utile_h;
591 	uint32_t i;
592 	uint32_t cube_map_stride = 0;
600 		uint32_t remaining_size = tex->base.size - p0;
699 		uint32_t level_width = max(width >> i, 1u);
700 		uint32_t level_height = max(height >> i, 1u);
701 		uint32_t aligned_width, aligned_height;
702 		uint32_t level_size;
760 	uint32_t *src_handles;
762 	static const uint32_t shader_reloc_offsets[] = {
767 	uint32_t shader_reloc_count = ARRAY_SIZE(shader_reloc_offsets);
769 	uint32_t nr_attributes, nr_relocs, packet_size;
837 		uint32_t o = shader_reloc_offsets[i];
838 		uint32_t src_offset = *(uint32_t *)(pkt_u + o);
839 		uint32_t *texture_handles_u;
841 		uint32_t tex, uni;
843 		*(uint32_t *)(pkt_v + o) = bo[i]->dma_addr + src_offset;
887 			uint32_t o = validated_shader->uniform_addr_offsets[uni];
888 			((uint32_t *)exec->uniforms_v)[o] = exec->uniforms_p;
891 		*(uint32_t *)(pkt_v + o + 4) = exec->uniforms_p;
901 		uint32_t o = 36 + i * 8;
902 		uint32_t offset = *(uint32_t *)(pkt_u + o + 0);
903 		uint32_t attr_size = *(uint8_t *)(pkt_u + o + 4) + 1;
904 		uint32_t stride = *(uint8_t *)(pkt_u + o + 5);
905 		uint32_t max_index;
911 			stride |= (*(uint32_t *)(pkt_u + 100 + i * 4)) & ~0xff;
931 		*(uint32_t *)(pkt_v + o) = vbo->dma_addr + offset;
942 	uint32_t i;