1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#ifndef __AMDGPU_VCN_H__ 25#define __AMDGPU_VCN_H__ 26 27#include "amdgpu_ras.h" 28 29#define AMDGPU_VCN_STACK_SIZE (128*1024) 30#define AMDGPU_VCN_CONTEXT_SIZE (512*1024) 31 32#define AMDGPU_VCN_FIRMWARE_OFFSET 256 33#define AMDGPU_VCN_MAX_ENC_RINGS 3 34 35#define AMDGPU_MAX_VCN_INSTANCES 4 36#define AMDGPU_MAX_VCN_ENC_RINGS (AMDGPU_VCN_MAX_ENC_RINGS * AMDGPU_MAX_VCN_INSTANCES) 37 38#define AMDGPU_VCN_HARVEST_VCN0 (1 << 0) 39#define AMDGPU_VCN_HARVEST_VCN1 (1 << 1) 40 41#define VCN_DEC_KMD_CMD 0x80000000 42#define VCN_DEC_CMD_FENCE 0x00000000 43#define VCN_DEC_CMD_TRAP 0x00000001 44#define VCN_DEC_CMD_WRITE_REG 0x00000004 45#define VCN_DEC_CMD_REG_READ_COND_WAIT 0x00000006 46#define VCN_DEC_CMD_PACKET_START 0x0000000a 47#define VCN_DEC_CMD_PACKET_END 0x0000000b 48 49#define VCN_DEC_SW_CMD_NO_OP 0x00000000 50#define VCN_DEC_SW_CMD_END 0x00000001 51#define VCN_DEC_SW_CMD_IB 0x00000002 52#define VCN_DEC_SW_CMD_FENCE 0x00000003 53#define VCN_DEC_SW_CMD_TRAP 0x00000004 54#define VCN_DEC_SW_CMD_IB_AUTO 0x00000005 55#define VCN_DEC_SW_CMD_SEMAPHORE 0x00000006 56#define VCN_DEC_SW_CMD_PREEMPT_FENCE 0x00000009 57#define VCN_DEC_SW_CMD_REG_WRITE 0x0000000b 58#define VCN_DEC_SW_CMD_REG_WAIT 0x0000000c 59 60#define VCN_ENC_CMD_NO_OP 0x00000000 61#define VCN_ENC_CMD_END 0x00000001 62#define VCN_ENC_CMD_IB 0x00000002 63#define VCN_ENC_CMD_FENCE 0x00000003 64#define VCN_ENC_CMD_TRAP 0x00000004 65#define VCN_ENC_CMD_REG_WRITE 0x0000000b 66#define VCN_ENC_CMD_REG_WAIT 0x0000000c 67 68#define VCN_AON_SOC_ADDRESS_2_0 0x1f800 69#define VCN1_AON_SOC_ADDRESS_3_0 0x48000 70#define VCN_VID_IP_ADDRESS_2_0 0x0 71#define VCN_AON_IP_ADDRESS_2_0 0x30000 72 73#define mmUVD_RBC_XX_IB_REG_CHECK 0x026b 74#define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 1 75#define mmUVD_REG_XX_MASK 0x026c 76#define mmUVD_REG_XX_MASK_BASE_IDX 1 77 78/* 1 second timeout */ 79#define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000) 80 81#define RREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, mask, sram_sel) \ 82 ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \ 83 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \ 84 UVD_DPG_LMA_CTL__MASK_EN_MASK | \ 85 ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \ 86 << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \ 87 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \ 88 RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \ 89 }) 90 91#define WREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, value, mask, sram_sel) \ 92 do { \ 93 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value); \ 94 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \ 95 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \ 96 UVD_DPG_LMA_CTL__READ_WRITE_MASK | \ 97 ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \ 98 << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \ 99 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \ 100 } while (0) 101 102#define SOC15_DPG_MODE_OFFSET(ip, inst_idx, reg) \ 103 ({ \ 104 uint32_t internal_reg_offset, addr; \ 105 bool video_range, video1_range, aon_range, aon1_range; \ 106 \ 107 addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \ 108 addr <<= 2; \ 109 video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) && \ 110 ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600))))); \ 111 video1_range = ((((0xFFFFF & addr) >= (VCN1_VID_SOC_ADDRESS_3_0)) && \ 112 ((0xFFFFF & addr) < ((VCN1_VID_SOC_ADDRESS_3_0 + 0x2600))))); \ 113 aon_range = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS_2_0)) && \ 114 ((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS_2_0 + 0x600))))); \ 115 aon1_range = ((((0xFFFFF & addr) >= (VCN1_AON_SOC_ADDRESS_3_0)) && \ 116 ((0xFFFFF & addr) < ((VCN1_AON_SOC_ADDRESS_3_0 + 0x600))))); \ 117 if (video_range) \ 118 internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS_2_0) + \ 119 (VCN_VID_IP_ADDRESS_2_0)); \ 120 else if (aon_range) \ 121 internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS_2_0) + \ 122 (VCN_AON_IP_ADDRESS_2_0)); \ 123 else if (video1_range) \ 124 internal_reg_offset = ((0xFFFFF & addr) - (VCN1_VID_SOC_ADDRESS_3_0) + \ 125 (VCN_VID_IP_ADDRESS_2_0)); \ 126 else if (aon1_range) \ 127 internal_reg_offset = ((0xFFFFF & addr) - (VCN1_AON_SOC_ADDRESS_3_0) + \ 128 (VCN_AON_IP_ADDRESS_2_0)); \ 129 else \ 130 internal_reg_offset = (0xFFFFF & addr); \ 131 \ 132 internal_reg_offset >>= 2; \ 133 }) 134 135#define RREG32_SOC15_DPG_MODE(inst_idx, offset, mask_en) \ 136 ({ \ 137 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \ 138 (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \ 139 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \ 140 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \ 141 RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA); \ 142 }) 143 144#define WREG32_SOC15_DPG_MODE(inst_idx, offset, value, mask_en, indirect) \ 145 do { \ 146 if (!indirect) { \ 147 WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \ 148 mmUVD_DPG_LMA_DATA, value); \ 149 WREG32_SOC15( \ 150 VCN, GET_INST(VCN, inst_idx), \ 151 mmUVD_DPG_LMA_CTL, \ 152 (0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \ 153 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \ 154 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \ 155 } else { \ 156 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \ 157 offset; \ 158 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \ 159 value; \ 160 } \ 161 } while (0) 162 163#define SOC24_DPG_MODE_OFFSET(ip, inst_idx, reg) \ 164 ({ \ 165 uint32_t internal_reg_offset, addr; \ 166 bool video_range, aon_range; \ 167 \ 168 addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \ 169 addr <<= 2; \ 170 video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS)) && \ 171 ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS + 0x2600))))); \ 172 aon_range = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS)) && \ 173 ((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS + 0x600))))); \ 174 if (video_range) \ 175 internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS) + \ 176 (VCN_VID_IP_ADDRESS)); \ 177 else if (aon_range) \ 178 internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS) + \ 179 (VCN_AON_IP_ADDRESS)); \ 180 else \ 181 internal_reg_offset = (0xFFFFF & addr); \ 182 \ 183 internal_reg_offset >>= 2; \ 184 }) 185 186#define WREG32_SOC24_DPG_MODE(inst_idx, offset, value, mask_en, indirect) \ 187 do { \ 188 if (!indirect) { \ 189 WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \ 190 regUVD_DPG_LMA_DATA, value); \ 191 WREG32_SOC15( \ 192 VCN, GET_INST(VCN, inst_idx), \ 193 regUVD_DPG_LMA_CTL, \ 194 (0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \ 195 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \ 196 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \ 197 } else { \ 198 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \ 199 offset; \ 200 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \ 201 value; \ 202 } \ 203 } while (0) 204 205#define AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE (1 << 2) 206#define AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT (1 << 4) 207#define AMDGPU_VCN_FW_SHARED_FLAG_0_RB (1 << 6) 208#define AMDGPU_VCN_MULTI_QUEUE_FLAG (1 << 8) 209#define AMDGPU_VCN_SW_RING_FLAG (1 << 9) 210#define AMDGPU_VCN_FW_LOGGING_FLAG (1 << 10) 211#define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11) 212#define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG (1 << 11) 213#define AMDGPU_VCN_VF_RB_SETUP_FLAG (1 << 14) 214#define AMDGPU_VCN_VF_RB_DECOUPLE_FLAG (1 << 15) 215 216#define MAX_NUM_VCN_RB_SETUP 4 217 218#define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER 0x00000001 219#define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER 0x00000001 220 221#define VCN_CODEC_DISABLE_MASK_AV1 (1 << 0) 222#define VCN_CODEC_DISABLE_MASK_VP9 (1 << 1) 223#define VCN_CODEC_DISABLE_MASK_HEVC (1 << 2) 224#define VCN_CODEC_DISABLE_MASK_H264 (1 << 3) 225 226#define AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU (0) 227#define AMDGPU_VCN_SMU_DPM_INTERFACE_APU (1) 228 229#define AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING 2 230 231enum fw_queue_mode { 232 FW_QUEUE_RING_RESET = 1, 233 FW_QUEUE_DPG_HOLD_OFF = 2, 234}; 235 236enum engine_status_constants { 237 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0, 238 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0, 239 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0 = 0x2A2A8AA0, 240 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002, 241 UVD_STATUS__UVD_BUSY = 0x00000004, 242 GB_ADDR_CONFIG_DEFAULT = 0x26010011, 243 UVD_STATUS__IDLE = 0x2, 244 UVD_STATUS__BUSY = 0x5, 245 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1, 246 UVD_STATUS__RBC_BUSY = 0x1, 247 UVD_PGFSM_STATUS_UVDJ_PWR_ON = 0, 248}; 249 250enum internal_dpg_state { 251 VCN_DPG_STATE__UNPAUSE = 0, 252 VCN_DPG_STATE__PAUSE, 253}; 254 255struct dpg_pause_state { 256 enum internal_dpg_state fw_based; 257 enum internal_dpg_state jpeg; 258}; 259 260struct amdgpu_vcn_reg{ 261 unsigned data0; 262 unsigned data1; 263 unsigned cmd; 264 unsigned nop; 265 unsigned context_id; 266 unsigned ib_vmid; 267 unsigned ib_bar_low; 268 unsigned ib_bar_high; 269 unsigned ib_size; 270 unsigned gp_scratch8; 271 unsigned scratch9; 272}; 273 274struct amdgpu_vcn_fw_shared { 275 void *cpu_addr; 276 uint64_t gpu_addr; 277 uint32_t mem_size; 278 uint32_t log_offset; 279}; 280 281struct amdgpu_vcn_inst { 282 struct amdgpu_bo *vcpu_bo; 283 void *cpu_addr; 284 uint64_t gpu_addr; 285 void *saved_bo; 286 struct amdgpu_ring ring_dec; 287 struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS]; 288 atomic_t sched_score; 289 struct amdgpu_irq_src irq; 290 struct amdgpu_irq_src ras_poison_irq; 291 struct amdgpu_vcn_reg external; 292 struct amdgpu_bo *dpg_sram_bo; 293 struct dpg_pause_state pause_state; 294 void *dpg_sram_cpu_addr; 295 uint64_t dpg_sram_gpu_addr; 296 uint32_t *dpg_sram_curr_addr; 297 atomic_t dpg_enc_submission_cnt; 298 struct amdgpu_vcn_fw_shared fw_shared; 299 uint8_t aid_id; 300}; 301 302struct amdgpu_vcn_ras { 303 struct amdgpu_ras_block_object ras_block; 304}; 305 306struct amdgpu_vcn { 307 unsigned fw_version; 308 struct delayed_work idle_work; 309 const struct firmware *fw[AMDGPU_MAX_VCN_INSTANCES]; /* VCN firmware */ 310 unsigned num_enc_rings; 311 enum amd_powergating_state cur_state; 312 bool indirect_sram; 313 314 uint8_t num_vcn_inst; 315 struct amdgpu_vcn_inst inst[AMDGPU_MAX_VCN_INSTANCES]; 316 uint8_t vcn_config[AMDGPU_MAX_VCN_INSTANCES]; 317 uint32_t vcn_codec_disable_mask[AMDGPU_MAX_VCN_INSTANCES]; 318 struct amdgpu_vcn_reg internal; 319 struct mutex vcn_pg_lock; 320 struct mutex vcn1_jpeg1_workaround; 321 atomic_t total_submission_cnt; 322 323 unsigned harvest_config; 324 int (*pause_dpg_mode)(struct amdgpu_device *adev, 325 int inst_idx, struct dpg_pause_state *new_state); 326 327 struct ras_common_if *ras_if; 328 struct amdgpu_vcn_ras *ras; 329 330 uint16_t inst_mask; 331 uint8_t num_inst_per_aid; 332}; 333 334struct amdgpu_fw_shared_rb_ptrs_struct { 335 /* to WA DPG R/W ptr issues.*/ 336 uint32_t rptr; 337 uint32_t wptr; 338}; 339 340struct amdgpu_fw_shared_multi_queue { 341 uint8_t decode_queue_mode; 342 uint8_t encode_generalpurpose_queue_mode; 343 uint8_t encode_lowlatency_queue_mode; 344 uint8_t encode_realtime_queue_mode; 345 uint8_t padding[4]; 346}; 347 348struct amdgpu_fw_shared_sw_ring { 349 uint8_t is_enabled; 350 uint8_t padding[3]; 351}; 352 353struct amdgpu_fw_shared_unified_queue_struct { 354 uint8_t is_enabled; 355 uint8_t queue_mode; 356 uint8_t queue_status; 357 uint8_t padding[5]; 358}; 359 360struct amdgpu_fw_shared_fw_logging { 361 uint8_t is_enabled; 362 uint32_t addr_lo; 363 uint32_t addr_hi; 364 uint32_t size; 365}; 366 367struct amdgpu_fw_shared_smu_interface_info { 368 uint8_t smu_interface_type; 369 uint8_t padding[3]; 370}; 371 372struct amdgpu_fw_shared { 373 uint32_t present_flag_0; 374 uint8_t pad[44]; 375 struct amdgpu_fw_shared_rb_ptrs_struct rb; 376 uint8_t pad1[1]; 377 struct amdgpu_fw_shared_multi_queue multi_queue; 378 struct amdgpu_fw_shared_sw_ring sw_ring; 379 struct amdgpu_fw_shared_fw_logging fw_log; 380 struct amdgpu_fw_shared_smu_interface_info smu_interface_info; 381}; 382 383struct amdgpu_vcn_rb_setup_info { 384 uint32_t rb_addr_lo; 385 uint32_t rb_addr_hi; 386 uint32_t rb_size; 387}; 388 389struct amdgpu_fw_shared_rb_setup { 390 uint32_t is_rb_enabled_flags; 391 392 union { 393 struct { 394 uint32_t rb_addr_lo; 395 uint32_t rb_addr_hi; 396 uint32_t rb_size; 397 uint32_t rb4_addr_lo; 398 uint32_t rb4_addr_hi; 399 uint32_t rb4_size; 400 uint32_t reserved[6]; 401 }; 402 403 struct { 404 struct amdgpu_vcn_rb_setup_info rb_info[MAX_NUM_VCN_RB_SETUP]; 405 }; 406 }; 407}; 408 409struct amdgpu_fw_shared_drm_key_wa { 410 uint8_t method; 411 uint8_t reserved[3]; 412}; 413 414struct amdgpu_fw_shared_queue_decouple { 415 uint8_t is_enabled; 416 uint8_t reserved[7]; 417}; 418 419struct amdgpu_vcn4_fw_shared { 420 uint32_t present_flag_0; 421 uint8_t pad[12]; 422 struct amdgpu_fw_shared_unified_queue_struct sq; 423 uint8_t pad1[8]; 424 struct amdgpu_fw_shared_fw_logging fw_log; 425 uint8_t pad2[20]; 426 struct amdgpu_fw_shared_rb_setup rb_setup; 427 struct amdgpu_fw_shared_smu_interface_info smu_dpm_interface; 428 struct amdgpu_fw_shared_drm_key_wa drm_key_wa; 429 uint8_t pad3[9]; 430 struct amdgpu_fw_shared_queue_decouple decouple; 431}; 432 433struct amdgpu_vcn_fwlog { 434 uint32_t rptr; 435 uint32_t wptr; 436 uint32_t buffer_size; 437 uint32_t header_size; 438 uint8_t wrapped; 439}; 440 441struct amdgpu_vcn_decode_buffer { 442 uint32_t valid_buf_flag; 443 uint32_t msg_buffer_address_hi; 444 uint32_t msg_buffer_address_lo; 445 uint32_t pad[30]; 446}; 447 448struct amdgpu_vcn_rb_metadata { 449 uint32_t size; 450 uint32_t present_flag_0; 451 452 uint8_t version; 453 uint8_t ring_id; 454 uint8_t pad[26]; 455}; 456 457#define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80 458#define VCN_BLOCK_DECODE_DISABLE_MASK 0x40 459#define VCN_BLOCK_QUEUE_DISABLE_MASK 0xC0 460 461enum vcn_ring_type { 462 VCN_ENCODE_RING, 463 VCN_DECODE_RING, 464 VCN_UNIFIED_RING, 465}; 466 467int amdgpu_vcn_early_init(struct amdgpu_device *adev); 468int amdgpu_vcn_sw_init(struct amdgpu_device *adev); 469int amdgpu_vcn_sw_fini(struct amdgpu_device *adev); 470int amdgpu_vcn_suspend(struct amdgpu_device *adev); 471int amdgpu_vcn_resume(struct amdgpu_device *adev); 472void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring); 473void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring); 474 475bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, 476 enum vcn_ring_type type, uint32_t vcn_instance); 477 478int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring); 479int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout); 480int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring); 481int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout); 482int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout); 483 484int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring); 485int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout); 486 487enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring); 488 489void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev); 490 491void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn); 492void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, 493 uint8_t i, struct amdgpu_vcn_inst *vcn); 494 495int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev, 496 struct amdgpu_irq_src *source, 497 struct amdgpu_iv_entry *entry); 498int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev, 499 struct ras_common_if *ras_block); 500int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev); 501 502int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx, 503 enum AMDGPU_UCODE_ID ucode_id); 504 505#endif 506