1/* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#ifndef __SMU11_DRIVER_IF_SIENNA_CICHLID_H__ 25#define __SMU11_DRIVER_IF_SIENNA_CICHLID_H__ 26 27// *** IMPORTANT *** 28// SMU TEAM: Always increment the interface version if 29// any structure is changed in this file 30#define SMU11_DRIVER_IF_VERSION 0x40 31 32#define PPTABLE_Sienna_Cichlid_SMU_VERSION 7 33 34#define NUM_GFXCLK_DPM_LEVELS 16 35#define NUM_SMNCLK_DPM_LEVELS 2 36#define NUM_SOCCLK_DPM_LEVELS 8 37#define NUM_MP0CLK_DPM_LEVELS 2 38#define NUM_DCLK_DPM_LEVELS 8 39#define NUM_VCLK_DPM_LEVELS 8 40#define NUM_DCEFCLK_DPM_LEVELS 8 41#define NUM_PHYCLK_DPM_LEVELS 8 42#define NUM_DISPCLK_DPM_LEVELS 8 43#define NUM_PIXCLK_DPM_LEVELS 8 44#define NUM_DTBCLK_DPM_LEVELS 8 45#define NUM_UCLK_DPM_LEVELS 4 46#define NUM_MP1CLK_DPM_LEVELS 2 47#define NUM_LINK_LEVELS 2 48#define NUM_FCLK_DPM_LEVELS 8 49#define NUM_XGMI_LEVELS 2 50#define NUM_XGMI_PSTATE_LEVELS 4 51#define NUM_OD_FAN_MAX_POINTS 6 52 53#define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1) 54#define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1) 55#define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1) 56#define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1) 57#define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1) 58#define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1) 59#define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1) 60#define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1) 61#define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1) 62#define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1) 63#define MAX_DTBCLK_DPM_LEVEL (NUM_DTBCLK_DPM_LEVELS - 1) 64#define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 65#define MAX_MP1CLK_DPM_LEVEL (NUM_MP1CLK_DPM_LEVELS - 1) 66#define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1) 67#define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1) 68 69//Gemini Modes 70#define PPSMC_GeminiModeNone 0 //Single GPU board 71#define PPSMC_GeminiModeMaster 1 //Master GPU on a Gemini board 72#define PPSMC_GeminiModeSlave 2 //Slave GPU on a Gemini board 73 74// Feature Control Defines 75// DPM 76#define FEATURE_DPM_PREFETCHER_BIT 0 77#define FEATURE_DPM_GFXCLK_BIT 1 78#define FEATURE_DPM_GFX_GPO_BIT 2 79#define FEATURE_DPM_UCLK_BIT 3 80#define FEATURE_DPM_FCLK_BIT 4 81#define FEATURE_DPM_SOCCLK_BIT 5 82#define FEATURE_DPM_MP0CLK_BIT 6 83#define FEATURE_DPM_LINK_BIT 7 84#define FEATURE_DPM_DCEFCLK_BIT 8 85#define FEATURE_DPM_XGMI_BIT 9 86#define FEATURE_MEM_VDDCI_SCALING_BIT 10 87#define FEATURE_MEM_MVDD_SCALING_BIT 11 88 89//Idle 90#define FEATURE_DS_GFXCLK_BIT 12 91#define FEATURE_DS_SOCCLK_BIT 13 92#define FEATURE_DS_FCLK_BIT 14 93#define FEATURE_DS_LCLK_BIT 15 94#define FEATURE_DS_DCEFCLK_BIT 16 95#define FEATURE_DS_UCLK_BIT 17 96#define FEATURE_GFX_ULV_BIT 18 97#define FEATURE_FW_DSTATE_BIT 19 98#define FEATURE_GFXOFF_BIT 20 99#define FEATURE_BACO_BIT 21 100#define FEATURE_MM_DPM_PG_BIT 22 101#define FEATURE_SPARE_23_BIT 23 102//Throttler/Response 103#define FEATURE_PPT_BIT 24 104#define FEATURE_TDC_BIT 25 105#define FEATURE_APCC_PLUS_BIT 26 106#define FEATURE_GTHR_BIT 27 107#define FEATURE_ACDC_BIT 28 108#define FEATURE_VR0HOT_BIT 29 109#define FEATURE_VR1HOT_BIT 30 110#define FEATURE_FW_CTF_BIT 31 111#define FEATURE_FAN_CONTROL_BIT 32 112#define FEATURE_THERMAL_BIT 33 113#define FEATURE_GFX_DCS_BIT 34 114//VF 115#define FEATURE_RM_BIT 35 116#define FEATURE_LED_DISPLAY_BIT 36 117//Other 118#define FEATURE_GFX_SS_BIT 37 119#define FEATURE_OUT_OF_BAND_MONITOR_BIT 38 120#define FEATURE_TEMP_DEPENDENT_VMIN_BIT 39 121 122#define FEATURE_MMHUB_PG_BIT 40 123#define FEATURE_ATHUB_PG_BIT 41 124#define FEATURE_APCC_DFLL_BIT 42 125#define FEATURE_DF_SUPERV_BIT 43 126#define FEATURE_RSMU_SMN_CG_BIT 44 127#define FEATURE_DF_CSTATE_BIT 45 128#define FEATURE_2_STEP_PSTATE_BIT 46 129#define FEATURE_SMNCLK_DPM_BIT 47 130#define FEATURE_PERLINK_GMIDOWN_BIT 48 131#define FEATURE_GFX_EDC_BIT 49 132#define FEATURE_GFX_PER_PART_VMIN_BIT 50 133#define FEATURE_SMART_SHIFT_BIT 51 134#define FEATURE_APT_BIT 52 135#define FEATURE_SPARE_53_BIT 53 136#define FEATURE_SPARE_54_BIT 54 137#define FEATURE_SPARE_55_BIT 55 138#define FEATURE_SPARE_56_BIT 56 139#define FEATURE_SPARE_57_BIT 57 140#define FEATURE_SPARE_58_BIT 58 141#define FEATURE_SPARE_59_BIT 59 142#define FEATURE_SPARE_60_BIT 60 143#define FEATURE_SPARE_61_BIT 61 144#define FEATURE_SPARE_62_BIT 62 145#define FEATURE_SPARE_63_BIT 63 146#define NUM_FEATURES 64 147 148//For use with feature control messages 149typedef enum { 150 FEATURE_PWR_ALL, 151 FEATURE_PWR_S5, 152 FEATURE_PWR_BACO, 153 FEATURE_PWR_SOC, 154 FEATURE_PWR_GFX, 155 FEATURE_PWR_DOMAIN_COUNT, 156} FEATURE_PWR_DOMAIN_e; 157 158 159// Debug Overrides Bitmask 160#define DPM_OVERRIDE_DISABLE_FCLK_PID 0x00000001 161#define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002 162#define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000004 163#define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_FCLK 0x00000008 164#define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_FCLK 0x00000010 165#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK 0x00000020 166#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK 0x00000040 167#define DPM_OVERRIDE_DISABLE_VOLT_LINK_DCE_FCLK 0x00000080 168#define DPM_OVERRIDE_DISABLE_VOLT_LINK_MP0_SOCCLK 0x00000100 169#define DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN 0x00000200 170#define DPM_OVERRIDE_DISABLE_MEMORY_TEMPERATURE_READ 0x00000400 171#define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCEFCLK 0x00000800 172#define DPM_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00001000 173#define DPM_OVERRIDE_DISABLE_VCN_PG 0x00002000 174#define DPM_OVERRIDE_DISABLE_FMAX_VMAX 0x00004000 175#define DPM_OVERRIDE_ENABLE_eGPU_USB_WA 0x00008000 176 177// VR Mapping Bit Defines 178#define VR_MAPPING_VR_SELECT_MASK 0x01 179#define VR_MAPPING_VR_SELECT_SHIFT 0x00 180 181#define VR_MAPPING_PLANE_SELECT_MASK 0x02 182#define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 183 184// PSI Bit Defines 185#define PSI_SEL_VR0_PLANE0_PSI0 0x01 186#define PSI_SEL_VR0_PLANE0_PSI1 0x02 187#define PSI_SEL_VR0_PLANE1_PSI0 0x04 188#define PSI_SEL_VR0_PLANE1_PSI1 0x08 189#define PSI_SEL_VR1_PLANE0_PSI0 0x10 190#define PSI_SEL_VR1_PLANE0_PSI1 0x20 191#define PSI_SEL_VR1_PLANE1_PSI0 0x40 192#define PSI_SEL_VR1_PLANE1_PSI1 0x80 193 194// Throttler Control/Status Bits 195#define THROTTLER_PADDING_BIT 0 196#define THROTTLER_TEMP_EDGE_BIT 1 197#define THROTTLER_TEMP_HOTSPOT_BIT 2 198#define THROTTLER_TEMP_MEM_BIT 3 199#define THROTTLER_TEMP_VR_GFX_BIT 4 200#define THROTTLER_TEMP_VR_MEM0_BIT 5 201#define THROTTLER_TEMP_VR_MEM1_BIT 6 202#define THROTTLER_TEMP_VR_SOC_BIT 7 203#define THROTTLER_TEMP_LIQUID0_BIT 8 204#define THROTTLER_TEMP_LIQUID1_BIT 9 205#define THROTTLER_TEMP_PLX_BIT 10 206#define THROTTLER_TDC_GFX_BIT 11 207#define THROTTLER_TDC_SOC_BIT 12 208#define THROTTLER_PPT0_BIT 13 209#define THROTTLER_PPT1_BIT 14 210#define THROTTLER_PPT2_BIT 15 211#define THROTTLER_PPT3_BIT 16 212#define THROTTLER_FIT_BIT 17 213#define THROTTLER_PPM_BIT 18 214#define THROTTLER_APCC_BIT 19 215#define THROTTLER_COUNT 20 216 217// FW DState Features Control Bits 218// FW DState Features Control Bits 219#define FW_DSTATE_SOC_ULV_BIT 0 220#define FW_DSTATE_G6_HSR_BIT 1 221#define FW_DSTATE_G6_PHY_VDDCI_OFF_BIT 2 222#define FW_DSTATE_MP0_DS_BIT 3 223#define FW_DSTATE_SMN_DS_BIT 4 224#define FW_DSTATE_MP1_DS_BIT 5 225#define FW_DSTATE_MP1_WHISPER_MODE_BIT 6 226#define FW_DSTATE_SOC_LIV_MIN_BIT 7 227#define FW_DSTATE_SOC_PLL_PWRDN_BIT 8 228#define FW_DSTATE_MEM_PLL_PWRDN_BIT 9 229#define FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT 10 230#define FW_DSTATE_MEM_PSI_BIT 11 231#define FW_DSTATE_HSR_NON_STROBE_BIT 12 232#define FW_DSTATE_MP0_ENTER_WFI_BIT 13 233 234#define FW_DSTATE_SOC_ULV_MASK (1 << FW_DSTATE_SOC_ULV_BIT ) 235#define FW_DSTATE_G6_HSR_MASK (1 << FW_DSTATE_G6_HSR_BIT ) 236#define FW_DSTATE_G6_PHY_VDDCI_OFF_MASK (1 << FW_DSTATE_G6_PHY_VDDCI_OFF_BIT ) 237#define FW_DSTATE_MP1_DS_MASK (1 << FW_DSTATE_MP1_DS_BIT ) 238#define FW_DSTATE_MP0_DS_MASK (1 << FW_DSTATE_MP0_DS_BIT ) 239#define FW_DSTATE_SMN_DS_MASK (1 << FW_DSTATE_SMN_DS_BIT ) 240#define FW_DSTATE_MP1_WHISPER_MODE_MASK (1 << FW_DSTATE_MP1_WHISPER_MODE_BIT ) 241#define FW_DSTATE_SOC_LIV_MIN_MASK (1 << FW_DSTATE_SOC_LIV_MIN_BIT ) 242#define FW_DSTATE_SOC_PLL_PWRDN_MASK (1 << FW_DSTATE_SOC_PLL_PWRDN_BIT ) 243#define FW_DSTATE_MEM_PLL_PWRDN_MASK (1 << FW_DSTATE_MEM_PLL_PWRDN_BIT ) 244#define FW_DSTATE_OPTIMIZE_MALL_REFRESH_MASK (1 << FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT ) 245#define FW_DSTATE_MEM_PSI_MASK (1 << FW_DSTATE_MEM_PSI_BIT ) 246#define FW_DSTATE_HSR_NON_STROBE_MASK (1 << FW_DSTATE_HSR_NON_STROBE_BIT ) 247#define FW_DSTATE_MP0_ENTER_WFI_MASK (1 << FW_DSTATE_MP0_ENTER_WFI_BIT ) 248 249// GFX GPO Feature Contains PACE and DEM sub features 250#define GFX_GPO_PACE_BIT 0 251#define GFX_GPO_DEM_BIT 1 252 253#define GFX_GPO_PACE_MASK (1 << GFX_GPO_PACE_BIT) 254#define GFX_GPO_DEM_MASK (1 << GFX_GPO_DEM_BIT ) 255 256#define GPO_UPDATE_REQ_UCLKDPM_MASK 0x1 257#define GPO_UPDATE_REQ_FCLKDPM_MASK 0x2 258#define GPO_UPDATE_REQ_MALLHIT_MASK 0x4 259 260 261//LED Display Mask & Control Bits 262#define LED_DISPLAY_GFX_DPM_BIT 0 263#define LED_DISPLAY_PCIE_BIT 1 264#define LED_DISPLAY_ERROR_BIT 2 265 266//RLC Pace Table total number of levels 267#define RLC_PACE_TABLE_NUM_LEVELS 16 268#define SIENNA_CICHLID_UMC_CHANNEL_NUM 16 269 270typedef struct { 271 uint64_t mca_umc_status; 272 uint64_t mca_umc_addr; 273 274 uint16_t ce_count_lo_chip; 275 uint16_t ce_count_hi_chip; 276 277 uint32_t eccPadding; 278} EccInfo_t; 279 280typedef struct { 281 EccInfo_t EccInfo[SIENNA_CICHLID_UMC_CHANNEL_NUM]; 282} EccInfoTable_t; 283 284typedef enum { 285 DRAM_BIT_WIDTH_DISABLED = 0, 286 DRAM_BIT_WIDTH_X_8, 287 DRAM_BIT_WIDTH_X_16, 288 DRAM_BIT_WIDTH_X_32, 289 DRAM_BIT_WIDTH_X_64, // NOT USED. 290 DRAM_BIT_WIDTH_X_128, 291 DRAM_BIT_WIDTH_COUNT, 292} DRAM_BIT_WIDTH_TYPE_e; 293 294//I2C Interface 295#define NUM_I2C_CONTROLLERS 16 296 297#define I2C_CONTROLLER_ENABLED 1 298#define I2C_CONTROLLER_DISABLED 0 299 300#define MAX_SW_I2C_COMMANDS 24 301 302 303typedef enum { 304 I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 305 I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 306 I2C_CONTROLLER_PORT_COUNT, 307} I2cControllerPort_e; 308 309typedef enum { 310 I2C_CONTROLLER_NAME_VR_GFX = 0, 311 I2C_CONTROLLER_NAME_VR_SOC, 312 I2C_CONTROLLER_NAME_VR_VDDCI, 313 I2C_CONTROLLER_NAME_VR_MVDD, 314 I2C_CONTROLLER_NAME_LIQUID0, 315 I2C_CONTROLLER_NAME_LIQUID1, 316 I2C_CONTROLLER_NAME_PLX, 317 I2C_CONTROLLER_NAME_OTHER, 318 I2C_CONTROLLER_NAME_COUNT, 319} I2cControllerName_e; 320 321typedef enum { 322 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 323 I2C_CONTROLLER_THROTTLER_VR_GFX, 324 I2C_CONTROLLER_THROTTLER_VR_SOC, 325 I2C_CONTROLLER_THROTTLER_VR_VDDCI, 326 I2C_CONTROLLER_THROTTLER_VR_MVDD, 327 I2C_CONTROLLER_THROTTLER_LIQUID0, 328 I2C_CONTROLLER_THROTTLER_LIQUID1, 329 I2C_CONTROLLER_THROTTLER_PLX, 330 I2C_CONTROLLER_THROTTLER_INA3221, 331 I2C_CONTROLLER_THROTTLER_COUNT, 332} I2cControllerThrottler_e; 333 334typedef enum { 335 I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 336 I2C_CONTROLLER_PROTOCOL_VR_IR35217, 337 I2C_CONTROLLER_PROTOCOL_TMP_TMP102A, 338 I2C_CONTROLLER_PROTOCOL_INA3221, 339 I2C_CONTROLLER_PROTOCOL_COUNT, 340} I2cControllerProtocol_e; 341 342typedef struct { 343 uint8_t Enabled; 344 uint8_t Speed; 345 uint8_t SlaveAddress; 346 uint8_t ControllerPort; 347 uint8_t ControllerName; 348 uint8_t ThermalThrotter; 349 uint8_t I2cProtocol; 350 uint8_t PaddingConfig; 351} I2cControllerConfig_t; 352 353typedef enum { 354 I2C_PORT_SVD_SCL = 0, 355 I2C_PORT_GPIO, 356} I2cPort_e; 357 358typedef enum { 359 I2C_SPEED_FAST_50K = 0, //50 Kbits/s 360 I2C_SPEED_FAST_100K, //100 Kbits/s 361 I2C_SPEED_FAST_400K, //400 Kbits/s 362 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 363 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 364 I2C_SPEED_HIGH_2M, //2.3 Mbits/s 365 I2C_SPEED_COUNT, 366} I2cSpeed_e; 367 368typedef enum { 369 I2C_CMD_READ = 0, 370 I2C_CMD_WRITE, 371 I2C_CMD_COUNT, 372} I2cCmdType_e; 373 374typedef enum { 375 FAN_MODE_AUTO = 0, 376 FAN_MODE_MANUAL_LINEAR, 377} FanMode_e; 378 379#define CMDCONFIG_STOP_BIT 0 380#define CMDCONFIG_RESTART_BIT 1 381#define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 382 383#define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 384#define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 385#define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 386 387typedef struct { 388 uint8_t ReadWriteData; //Return data for read. Data to send for write 389 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 390} SwI2cCmd_t; //SW I2C Command Table 391 392typedef struct { 393 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 394 uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 395 uint8_t SlaveAddress; //Slave address of device 396 uint8_t NumCmds; //Number of commands 397 398 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 399} SwI2cRequest_t; // SW I2C Request Table 400 401typedef struct { 402 SwI2cRequest_t SwI2cRequest; 403 404 uint32_t Spare[8]; 405 uint32_t MmHubPadding[8]; // SMU internal use 406} SwI2cRequestExternal_t; 407 408//D3HOT sequences 409typedef enum { 410 BACO_SEQUENCE, 411 MSR_SEQUENCE, 412 BAMACO_SEQUENCE, 413 ULPS_SEQUENCE, 414 D3HOT_SEQUENCE_COUNT, 415} D3HOTSequence_e; 416 417//THis is aligned with RSMU PGFSM Register Mapping 418typedef enum { 419 PG_DYNAMIC_MODE = 0, 420 PG_STATIC_MODE, 421} PowerGatingMode_e; 422 423//This is aligned with RSMU PGFSM Register Mapping 424typedef enum { 425 PG_POWER_DOWN = 0, 426 PG_POWER_UP, 427} PowerGatingSettings_e; 428 429typedef struct { 430 uint32_t a; // store in IEEE float format in this variable 431 uint32_t b; // store in IEEE float format in this variable 432 uint32_t c; // store in IEEE float format in this variable 433} QuadraticInt_t; 434 435typedef struct { 436 uint32_t a; // store in fixed point, [31:20] signed integer, [19:0] fractional bits 437 uint32_t b; // store in fixed point, [31:20] signed integer, [19:0] fractional bits 438 uint32_t c; // store in fixed point, [31:20] signed integer, [19:0] fractional bits 439} QuadraticFixedPoint_t; 440 441typedef struct { 442 uint32_t m; // store in IEEE float format in this variable 443 uint32_t b; // store in IEEE float format in this variable 444} LinearInt_t; 445 446typedef struct { 447 uint32_t a; // store in IEEE float format in this variable 448 uint32_t b; // store in IEEE float format in this variable 449 uint32_t c; // store in IEEE float format in this variable 450} DroopInt_t; 451 452//Piecewise linear droop model, Sienna_Cichlid currently used only for GFX DFLL 453#define NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS 5 454typedef enum { 455 PIECEWISE_LINEAR_FUSED_MODEL = 0, 456 PIECEWISE_LINEAR_PP_MODEL, 457 QUADRATIC_PP_MODEL, 458 PERPART_PIECEWISE_LINEAR_PP_MODEL, 459} DfllDroopModelSelect_e; 460 461typedef struct { 462 uint32_t Fset[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //in GHz, store in IEEE float format 463 uint32_t Vdroop[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //in V , store in IEEE float format 464}PiecewiseLinearDroopInt_t; 465 466typedef enum { 467 GFXCLK_SOURCE_PLL = 0, 468 GFXCLK_SOURCE_DFLL, 469 GFXCLK_SOURCE_COUNT, 470} GFXCLK_SOURCE_e; 471 472//Only Clks that have DPM descriptors are listed here 473typedef enum { 474 PPCLK_GFXCLK = 0, 475 PPCLK_SOCCLK, 476 PPCLK_UCLK, 477 PPCLK_FCLK, 478 PPCLK_DCLK_0, 479 PPCLK_VCLK_0, 480 PPCLK_DCLK_1, 481 PPCLK_VCLK_1, 482 PPCLK_DCEFCLK, 483 PPCLK_DISPCLK, 484 PPCLK_PIXCLK, 485 PPCLK_PHYCLK, 486 PPCLK_DTBCLK, 487 PPCLK_COUNT, 488} PPCLK_e; 489 490typedef enum { 491 VOLTAGE_MODE_AVFS = 0, 492 VOLTAGE_MODE_AVFS_SS, 493 VOLTAGE_MODE_SS, 494 VOLTAGE_MODE_COUNT, 495} VOLTAGE_MODE_e; 496 497 498typedef enum { 499 AVFS_VOLTAGE_GFX = 0, 500 AVFS_VOLTAGE_SOC, 501 AVFS_VOLTAGE_COUNT, 502} AVFS_VOLTAGE_TYPE_e; 503 504typedef enum { 505 UCLK_DIV_BY_1 = 0, 506 UCLK_DIV_BY_2, 507 UCLK_DIV_BY_4, 508 UCLK_DIV_BY_8, 509} UCLK_DIV_e; 510 511typedef enum { 512 GPIO_INT_POLARITY_ACTIVE_LOW = 0, 513 GPIO_INT_POLARITY_ACTIVE_HIGH, 514} GpioIntPolarity_e; 515 516typedef enum { 517 PWR_CONFIG_TDP = 0, 518 PWR_CONFIG_TGP, 519 PWR_CONFIG_TCP_ESTIMATED, 520 PWR_CONFIG_TCP_MEASURED, 521} PwrConfig_e; 522 523typedef enum { 524 XGMI_LINK_RATE_2 = 2, // 2Gbps 525 XGMI_LINK_RATE_4 = 4, // 4Gbps 526 XGMI_LINK_RATE_8 = 8, // 8Gbps 527 XGMI_LINK_RATE_12 = 12, // 12Gbps 528 XGMI_LINK_RATE_16 = 16, // 16Gbps 529 XGMI_LINK_RATE_17 = 17, // 17Gbps 530 XGMI_LINK_RATE_18 = 18, // 18Gbps 531 XGMI_LINK_RATE_19 = 19, // 19Gbps 532 XGMI_LINK_RATE_20 = 20, // 20Gbps 533 XGMI_LINK_RATE_21 = 21, // 21Gbps 534 XGMI_LINK_RATE_22 = 22, // 22Gbps 535 XGMI_LINK_RATE_23 = 23, // 23Gbps 536 XGMI_LINK_RATE_24 = 24, // 24Gbps 537 XGMI_LINK_RATE_25 = 25, // 25Gbps 538 XGMI_LINK_RATE_COUNT 539} XGMI_LINK_RATE_e; 540 541typedef enum { 542 XGMI_LINK_WIDTH_1 = 0, // x1 543 XGMI_LINK_WIDTH_2, // x2 544 XGMI_LINK_WIDTH_4, // x4 545 XGMI_LINK_WIDTH_8, // x8 546 XGMI_LINK_WIDTH_9, // x9 547 XGMI_LINK_WIDTH_16, // x16 548 XGMI_LINK_WIDTH_COUNT 549} XGMI_LINK_WIDTH_e; 550 551typedef struct { 552 uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only 553 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 554 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 555 uint8_t Padding; 556 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 557 QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V) 558 uint16_t SsFmin; // Fmin for SS curve. If SS curve is selected, will use V@SSFmin for F <= Fmin 559 uint16_t Padding16; 560} DpmDescriptor_t; 561 562typedef enum { 563 PPT_THROTTLER_PPT0, 564 PPT_THROTTLER_PPT1, 565 PPT_THROTTLER_PPT2, 566 PPT_THROTTLER_PPT3, 567 PPT_THROTTLER_COUNT 568} PPT_THROTTLER_e; 569 570typedef enum { 571 TEMP_EDGE, 572 TEMP_HOTSPOT, 573 TEMP_MEM, 574 TEMP_VR_GFX, 575 TEMP_VR_MEM0, 576 TEMP_VR_MEM1, 577 TEMP_VR_SOC, 578 TEMP_LIQUID0, 579 TEMP_LIQUID1, 580 TEMP_PLX, 581 TEMP_COUNT, 582} TEMP_e; 583 584typedef enum { 585 TDC_THROTTLER_GFX, 586 TDC_THROTTLER_SOC, 587 TDC_THROTTLER_COUNT 588} TDC_THROTTLER_e; 589 590typedef enum { 591 CUSTOMER_VARIANT_ROW, 592 CUSTOMER_VARIANT_FALCON, 593 CUSTOMER_VARIANT_COUNT, 594} CUSTOMER_VARIANT_e; 595 596// Used for 2-step UCLK DPM change workaround 597typedef struct { 598 uint16_t Fmin; 599 uint16_t Fmax; 600} UclkDpmChangeRange_t; 601 602#pragma pack(push, 1) 603typedef struct { 604 // MAJOR SECTION: SKU PARAMETERS 605 606 uint32_t Version; 607 608 // SECTION: Feature Enablement 609 uint32_t FeaturesToRun[NUM_FEATURES / 32]; 610 611 // SECTION: Infrastructure Limits 612 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // Watts 613 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 614 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // Watts 615 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 616 617 uint16_t TdcLimit[TDC_THROTTLER_COUNT]; // Amps 618 uint16_t TdcLimitTau[TDC_THROTTLER_COUNT]; // Time constant of LPF in ms 619 620 uint16_t TemperatureLimit[TEMP_COUNT]; // Celcius 621 622 uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime) 623 624 // SECTION: Power Configuration 625 uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured. Use defines from PwrConfig_e 626 uint8_t TotalPowerPadding[3]; 627 628 // SECTION: APCC Settings 629 uint32_t ApccPlusResidencyLimit; 630 631 //SECTION: SMNCLK DPM 632 uint16_t SmnclkDpmFreq [NUM_SMNCLK_DPM_LEVELS]; // in MHz 633 uint16_t SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS]; // mV(Q2) 634 635 uint32_t PaddingAPCC; 636 uint16_t PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //In mV(Q2) 637 uint16_t PaddingPerPartDroop; 638 639 // SECTION: Throttler settings 640 uint32_t ThrottlerControlMask; // See Throtter masks defines 641 642 // SECTION: FW DSTATE Settings 643 uint32_t FwDStateMask; // See FW DState masks defines 644 645 // SECTION: ULV Settings 646 uint16_t UlvVoltageOffsetSoc; // In mV(Q2) 647 uint16_t UlvVoltageOffsetGfx; // In mV(Q2) 648 649 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode 650 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode 651 652 uint16_t SocLIVmin; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC 653 uint16_t PaddingLIVmin; 654 655 uint8_t GceaLinkMgrIdleThreshold; //Set by SMU FW during enablment of GFXOFF. Controls delay for GFX SDP port disconnection during idle events 656 uint8_t paddingRlcUlvParams[3]; 657 658 // SECTION: Voltage Control Parameters 659 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX 660 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC 661 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX 662 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC 663 664 uint16_t LoadLineResistanceGfx; // In mOhms with 8 fractional bits 665 uint16_t LoadLineResistanceSoc; // In mOhms with 8 fractional bits 666 667 // SECTION: Temperature Dependent Vmin 668 uint16_t VDDGFX_TVmin; //Celcius 669 uint16_t VDDSOC_TVmin; //Celcius 670 uint16_t VDDGFX_Vmin_HiTemp; // mV Q2 671 uint16_t VDDGFX_Vmin_LoTemp; // mV Q2 672 uint16_t VDDSOC_Vmin_HiTemp; // mV Q2 673 uint16_t VDDSOC_Vmin_LoTemp; // mV Q2 674 675 uint16_t VDDGFX_TVminHystersis; // Celcius 676 uint16_t VDDSOC_TVminHystersis; // Celcius 677 678 //SECTION: DPM Config 1 679 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 680 681 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 682 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 683 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 684 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 685 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 686 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; // In MHz 687 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 688 uint16_t FreqTablePixclk [NUM_PIXCLK_DPM_LEVELS ]; // In MHz 689 uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ]; // In MHz 690 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 691 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 692 uint32_t Paddingclks; 693 694 DroopInt_t PerPartDroopModelGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //GHz ->Vstore in IEEE float format 695 696 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 697 698 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 699 700 // Used for MALL performance boost 701 uint16_t FclkBoostFreq; // In Mhz 702 uint16_t FclkParamPadding; 703 704 // SECTION: DPM Config 2 705 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 706 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 707 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 708 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 709 // GFXCLK DPM 710 uint16_t GfxclkFgfxoffEntry; // in Mhz 711 uint16_t GfxclkFinit; // in Mhz 712 uint16_t GfxclkFidle; // in MHz 713 uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL 714 uint8_t GfxclkPadding; 715 716 // GFX GPO 717 uint8_t GfxGpoSubFeatureMask; // bit 0 = PACE, bit 1 = DEM 718 uint8_t GfxGpoEnabledWorkPolicyMask; //Any policy that GPO can be enabled 719 uint8_t GfxGpoDisabledWorkPolicyMask; //Any policy that GPO can be disabled 720 uint8_t GfxGpoPadding[1]; 721 uint32_t GfxGpoVotingAllow; //For indicating which feature changes should result in a GPO table recalculation 722 723 uint32_t GfxGpoPadding32[4]; 724 725 uint16_t GfxDcsFopt; // Optimal GFXCLK for DCS in Mhz 726 uint16_t GfxDcsFclkFopt; // Optimal FCLK for DCS in Mhz 727 uint16_t GfxDcsUclkFopt; // Optimal UCLK for DCS in Mhz 728 729 uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 730 731 uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 732 uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 733 734 uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 735 736 uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 737 uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 738 739 uint32_t DcsParamPadding[5]; 740 741 uint16_t FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS]; // Q8.8 742 743 // UCLK section 744 uint8_t LowestUclkReservedForUlv; // Set this to 1 if UCLK DPM0 is reserved for ULV-mode only 745 uint8_t PaddingMem[3]; 746 747 uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 748 749 // Used for 2-Step UCLK change workaround 750 UclkDpmChangeRange_t UclkDpmSrcFreqRange; // In Mhz 751 UclkDpmChangeRange_t UclkDpmTargFreqRange; // In Mhz 752 uint16_t UclkDpmMidstepFreq; // In Mhz 753 uint16_t UclkMidstepPadding; 754 755 // Link DPM Settings 756 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 757 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 758 uint16_t LclkFreq[NUM_LINK_LEVELS]; 759 760 // SECTION: Fan Control 761 uint16_t FanStopTemp; //Celcius 762 uint16_t FanStartTemp; //Celcius 763 764 uint16_t FanGain[TEMP_COUNT]; 765 766 uint16_t FanPwmMin; 767 uint16_t FanAcousticLimitRpm; 768 uint16_t FanThrottlingRpm; 769 uint16_t FanMaximumRpm; 770 uint16_t MGpuFanBoostLimitRpm; 771 uint16_t FanTargetTemperature; 772 uint16_t FanTargetGfxclk; 773 uint16_t FanPadding16; 774 uint8_t FanTempInputSelect; 775 uint8_t FanPadding; 776 uint8_t FanZeroRpmEnable; 777 uint8_t FanTachEdgePerRev; 778 779 // The following are AFC override parameters. Leave at 0 to use FW defaults. 780 int16_t FuzzyFan_ErrorSetDelta; 781 int16_t FuzzyFan_ErrorRateSetDelta; 782 int16_t FuzzyFan_PwmSetDelta; 783 uint16_t FuzzyFan_Reserved; 784 785 // SECTION: AVFS 786 // Overrides 787 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 788 uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable) 789 uint8_t Padding8_Avfs; 790 791 QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve 792 DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb 793 DroopInt_t dBtcGbGfxDfll; // GHz->V BtcGb 794 DroopInt_t dBtcGbSoc; // GHz->V BtcGb 795 LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V 796 797 PiecewiseLinearDroopInt_t PiecewiseLinearDroopIntGfxDfll; //GHz ->Vstore in IEEE float format 798 799 QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V 800 801 uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2 802 803 uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT]; 804 uint8_t Padding8_GfxBtc[2]; 805 806 uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2 807 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2 808 809 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; // mV Q2 810 811 // SECTION: XGMI 812 uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low. 0-P0, 1-P1, 2-P2, 3-P3. 813 uint8_t XgmiDpmSpare[2]; 814 815 // SECTION: Advanced Options 816 uint32_t DebugOverrides; 817 QuadraticInt_t ReservedEquation0; 818 QuadraticInt_t ReservedEquation1; 819 QuadraticInt_t ReservedEquation2; 820 QuadraticInt_t ReservedEquation3; 821 822 // SECTION: Sku Reserved 823 uint8_t CustomerVariant; 824 825 //VC BTC parameters are only applicable to VDD_GFX domain 826 uint8_t VcBtcEnabled; 827 uint16_t VcBtcVminT0; // T0_VMIN 828 uint16_t VcBtcFixedVminAgingOffset; // FIXED_VMIN_AGING_OFFSET 829 uint16_t VcBtcVmin2PsmDegrationGb; // VMIN_TO_PSM_DEGRADATION_GB 830 uint32_t VcBtcPsmA; // A_PSM 831 uint32_t VcBtcPsmB; // B_PSM 832 uint32_t VcBtcVminA; // A_VMIN 833 uint32_t VcBtcVminB; // B_VMIN 834 835 //GPIO Board feature 836 uint16_t LedGpio; //GeneriA GPIO flag used to control the radeon LEDs 837 uint16_t GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 838 839 uint32_t SkuReserved[8]; 840 841 842 // MAJOR SECTION: BOARD PARAMETERS 843 844 //SECTION: Gaming Clocks 845 uint32_t GamingClk[6]; 846 847 // SECTION: I2C Control 848 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 849 850 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1 851 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1 852 uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off 853 uint8_t I2cSpare[1]; 854 855 // SECTION: SVI2 Board Parameters 856 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 857 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 858 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 859 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 860 861 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 862 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 863 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 864 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 865 866 // SECTION: Telemetry Settings 867 uint16_t GfxMaxCurrent; // in Amps 868 int8_t GfxOffset; // in Amps 869 uint8_t Padding_TelemetryGfx; 870 871 uint16_t SocMaxCurrent; // in Amps 872 int8_t SocOffset; // in Amps 873 uint8_t Padding_TelemetrySoc; 874 875 uint16_t Mem0MaxCurrent; // in Amps 876 int8_t Mem0Offset; // in Amps 877 uint8_t Padding_TelemetryMem0; 878 879 uint16_t Mem1MaxCurrent; // in Amps 880 int8_t Mem1Offset; // in Amps 881 uint8_t Padding_TelemetryMem1; 882 883 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 884 885 // SECTION: GPIO Settings 886 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 887 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 888 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 889 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 890 891 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 892 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 893 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 894 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 895 896 // LED Display Settings 897 uint8_t LedPin0; // GPIO number for LedPin[0] 898 uint8_t LedPin1; // GPIO number for LedPin[1] 899 uint8_t LedPin2; // GPIO number for LedPin[2] 900 uint8_t LedEnableMask; 901 902 uint8_t LedPcie; // GPIO number for PCIE results 903 uint8_t LedError; // GPIO number for Error Cases 904 uint8_t LedSpare1[2]; 905 906 // SECTION: Clock Spread Spectrum 907 908 // GFXCLK PLL Spread Spectrum 909 uint8_t PllGfxclkSpreadEnabled; // on or off 910 uint8_t PllGfxclkSpreadPercent; // Q4.4 911 uint16_t PllGfxclkSpreadFreq; // kHz 912 913 // GFXCLK DFLL Spread Spectrum 914 uint8_t DfllGfxclkSpreadEnabled; // on or off 915 uint8_t DfllGfxclkSpreadPercent; // Q4.4 916 uint16_t DfllGfxclkSpreadFreq; // kHz 917 918 // UCLK Spread Spectrum 919 uint16_t UclkSpreadPadding; 920 uint16_t UclkSpreadFreq; // kHz 921 922 // FCLK Spread Spectrum 923 uint8_t FclkSpreadEnabled; // on or off 924 uint8_t FclkSpreadPercent; // Q4.4 925 uint16_t FclkSpreadFreq; // kHz 926 927 // Section: Memory Config 928 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 929 930 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines 931 uint8_t PaddingMem1[3]; 932 933 // Section: Total Board Power 934 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 935 uint16_t BoardPowerPadding; 936 937 // SECTION: XGMI Training 938 uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS]; 939 uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS]; 940 941 uint16_t XgmiFclkFreq [NUM_XGMI_PSTATE_LEVELS]; 942 uint16_t XgmiSocVoltage [NUM_XGMI_PSTATE_LEVELS]; 943 944 // SECTION: UMC feature flags 945 uint8_t HsrEnabled; 946 uint8_t VddqOffEnabled; 947 uint8_t PaddingUmcFlags[2]; 948 949 // UCLK Spread Spectrum 950 uint8_t UclkSpreadPercent[16]; 951 952 // SECTION: Board Reserved 953 uint32_t BoardReserved[11]; 954 955 // SECTION: Structure Padding 956 957 // Padding for MMHUB - do not modify this 958 uint32_t MmHubPadding[8]; // SMU internal use 959 960} PPTable_t; 961#pragma pack(pop) 962 963typedef struct { 964 // MAJOR SECTION: SKU PARAMETERS 965 966 uint32_t Version; 967 968 // SECTION: Feature Enablement 969 uint32_t FeaturesToRun[NUM_FEATURES / 32]; 970 971 // SECTION: Infrastructure Limits 972 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // Watts 973 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 974 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // Watts 975 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 976 977 uint16_t TdcLimit[TDC_THROTTLER_COUNT]; // Amps 978 uint16_t TdcLimitTau[TDC_THROTTLER_COUNT]; // Time constant of LPF in ms 979 980 uint16_t TemperatureLimit[TEMP_COUNT]; // Celcius 981 982 uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime) 983 984 // SECTION: Power Configuration 985 uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured. Use defines from PwrConfig_e 986 uint8_t TotalPowerPadding[3]; 987 988 // SECTION: APCC Settings 989 uint32_t ApccPlusResidencyLimit; 990 991 //SECTION: SMNCLK DPM 992 uint16_t SmnclkDpmFreq [NUM_SMNCLK_DPM_LEVELS]; // in MHz 993 uint16_t SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS]; // mV(Q2) 994 995 uint32_t PaddingAPCC; 996 uint16_t PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //In mV(Q2) 997 uint16_t PaddingPerPartDroop; 998 999 // SECTION: Throttler settings 1000 uint32_t ThrottlerControlMask; // See Throtter masks defines 1001 1002 // SECTION: FW DSTATE Settings 1003 uint32_t FwDStateMask; // See FW DState masks defines 1004 1005 // SECTION: ULV Settings 1006 uint16_t UlvVoltageOffsetSoc; // In mV(Q2) 1007 uint16_t UlvVoltageOffsetGfx; // In mV(Q2) 1008 1009 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode 1010 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode 1011 1012 uint16_t SocLIVmin; 1013 uint16_t SocLIVminoffset; 1014 1015 uint8_t GceaLinkMgrIdleThreshold; //Set by SMU FW during enablment of GFXOFF. Controls delay for GFX SDP port disconnection during idle events 1016 uint8_t paddingRlcUlvParams[3]; 1017 1018 // SECTION: Voltage Control Parameters 1019 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX 1020 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC 1021 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX 1022 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC 1023 1024 uint16_t LoadLineResistanceGfx; // In mOhms with 8 fractional bits 1025 uint16_t LoadLineResistanceSoc; // In mOhms with 8 fractional bits 1026 1027 // SECTION: Temperature Dependent Vmin 1028 uint16_t VDDGFX_TVmin; //Celcius 1029 uint16_t VDDSOC_TVmin; //Celcius 1030 uint16_t VDDGFX_Vmin_HiTemp; // mV Q2 1031 uint16_t VDDGFX_Vmin_LoTemp; // mV Q2 1032 uint16_t VDDSOC_Vmin_HiTemp; // mV Q2 1033 uint16_t VDDSOC_Vmin_LoTemp; // mV Q2 1034 1035 uint16_t VDDGFX_TVminHystersis; // Celcius 1036 uint16_t VDDSOC_TVminHystersis; // Celcius 1037 1038 //SECTION: DPM Config 1 1039 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 1040 1041 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1042 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1043 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1044 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1045 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1046 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; // In MHz 1047 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1048 uint16_t FreqTablePixclk [NUM_PIXCLK_DPM_LEVELS ]; // In MHz 1049 uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ]; // In MHz 1050 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1051 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1052 uint32_t Paddingclks; 1053 1054 DroopInt_t PerPartDroopModelGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //GHz ->Vstore in IEEE float format 1055 1056 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1057 1058 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 1059 1060 // Used for MALL performance boost 1061 uint16_t FclkBoostFreq; // In Mhz 1062 uint16_t FclkParamPadding; 1063 1064 // SECTION: DPM Config 2 1065 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 1066 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 1067 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1068 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1069 // GFXCLK DPM 1070 uint16_t GfxclkFgfxoffEntry; // in Mhz 1071 uint16_t GfxclkFinit; // in Mhz 1072 uint16_t GfxclkFidle; // in MHz 1073 uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL 1074 uint8_t GfxclkPadding; 1075 1076 // GFX GPO 1077 uint8_t GfxGpoSubFeatureMask; // bit 0 = PACE, bit 1 = DEM 1078 uint8_t GfxGpoEnabledWorkPolicyMask; //Any policy that GPO can be enabled 1079 uint8_t GfxGpoDisabledWorkPolicyMask; //Any policy that GPO can be disabled 1080 uint8_t GfxGpoPadding[1]; 1081 uint32_t GfxGpoVotingAllow; //For indicating which feature changes should result in a GPO table recalculation 1082 1083 uint32_t GfxGpoPadding32[4]; 1084 1085 uint16_t GfxDcsFopt; // Optimal GFXCLK for DCS in Mhz 1086 uint16_t GfxDcsFclkFopt; // Optimal FCLK for DCS in Mhz 1087 uint16_t GfxDcsUclkFopt; // Optimal UCLK for DCS in Mhz 1088 1089 uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 1090 1091 uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 1092 uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 1093 1094 uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 1095 1096 uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 1097 uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 1098 1099 uint32_t DcsParamPadding[5]; 1100 1101 uint16_t FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS]; // Q8.8 1102 1103 // UCLK section 1104 uint8_t LowestUclkReservedForUlv; // Set this to 1 if UCLK DPM0 is reserved for ULV-mode only 1105 uint8_t PaddingMem[3]; 1106 1107 uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1108 1109 // Used for 2-Step UCLK change workaround 1110 UclkDpmChangeRange_t UclkDpmSrcFreqRange; // In Mhz 1111 UclkDpmChangeRange_t UclkDpmTargFreqRange; // In Mhz 1112 uint16_t UclkDpmMidstepFreq; // In Mhz 1113 uint16_t UclkMidstepPadding; 1114 1115 // Link DPM Settings 1116 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 1117 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 1118 uint16_t LclkFreq[NUM_LINK_LEVELS]; 1119 1120 // SECTION: Fan Control 1121 uint16_t FanStopTemp; //Celcius 1122 uint16_t FanStartTemp; //Celcius 1123 1124 uint16_t FanGain[TEMP_COUNT]; 1125 1126 uint16_t FanPwmMin; 1127 uint16_t FanAcousticLimitRpm; 1128 uint16_t FanThrottlingRpm; 1129 uint16_t FanMaximumRpm; 1130 uint16_t MGpuFanBoostLimitRpm; 1131 uint16_t FanTargetTemperature; 1132 uint16_t FanTargetGfxclk; 1133 uint16_t FanPadding16; 1134 uint8_t FanTempInputSelect; 1135 uint8_t FanPadding; 1136 uint8_t FanZeroRpmEnable; 1137 uint8_t FanTachEdgePerRev; 1138 1139 // The following are AFC override parameters. Leave at 0 to use FW defaults. 1140 int16_t FuzzyFan_ErrorSetDelta; 1141 int16_t FuzzyFan_ErrorRateSetDelta; 1142 int16_t FuzzyFan_PwmSetDelta; 1143 uint16_t FuzzyFan_Reserved; 1144 1145 // SECTION: AVFS 1146 // Overrides 1147 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 1148 uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable) 1149 uint8_t Padding8_Avfs; 1150 1151 QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve 1152 DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb 1153 DroopInt_t dBtcGbGfxDfll; // GHz->V BtcGb 1154 DroopInt_t dBtcGbSoc; // GHz->V BtcGb 1155 LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V 1156 1157 PiecewiseLinearDroopInt_t PiecewiseLinearDroopIntGfxDfll; //GHz ->Vstore in IEEE float format 1158 1159 QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V 1160 1161 uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2 1162 1163 uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT]; 1164 uint8_t Padding8_GfxBtc[2]; 1165 1166 uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2 1167 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2 1168 1169 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; // mV Q2 1170 1171 // SECTION: XGMI 1172 uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low. 0-P0, 1-P1, 2-P2, 3-P3. 1173 uint8_t XgmiDpmSpare[2]; 1174 1175 // SECTION: Advanced Options 1176 uint32_t DebugOverrides; 1177 QuadraticInt_t ReservedEquation0; 1178 QuadraticInt_t ReservedEquation1; 1179 QuadraticInt_t ReservedEquation2; 1180 QuadraticInt_t ReservedEquation3; 1181 1182 // SECTION: Sku Reserved 1183 uint8_t CustomerVariant; 1184 1185 //VC BTC parameters are only applicable to VDD_GFX domain 1186 uint8_t VcBtcEnabled; 1187 uint16_t VcBtcVminT0; // T0_VMIN 1188 uint16_t VcBtcFixedVminAgingOffset; // FIXED_VMIN_AGING_OFFSET 1189 uint16_t VcBtcVmin2PsmDegrationGb; // VMIN_TO_PSM_DEGRADATION_GB 1190 uint32_t VcBtcPsmA; // A_PSM 1191 uint32_t VcBtcPsmB; // B_PSM 1192 uint32_t VcBtcVminA; // A_VMIN 1193 uint32_t VcBtcVminB; // B_VMIN 1194 1195 //GPIO Board feature 1196 uint16_t LedGpio; //GeneriA GPIO flag used to control the radeon LEDs 1197 uint16_t GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 1198 1199 uint32_t SkuReserved[63]; 1200 1201 1202 1203 // MAJOR SECTION: BOARD PARAMETERS 1204 1205 //SECTION: Gaming Clocks 1206 uint32_t GamingClk[6]; 1207 1208 // SECTION: I2C Control 1209 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 1210 1211 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1 1212 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1 1213 uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off 1214 uint8_t I2cSpare[1]; 1215 1216 // SECTION: SVI2 Board Parameters 1217 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 1218 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 1219 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 1220 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 1221 1222 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1223 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1224 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1225 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1226 1227 // SECTION: Telemetry Settings 1228 uint16_t GfxMaxCurrent; // in Amps 1229 int8_t GfxOffset; // in Amps 1230 uint8_t Padding_TelemetryGfx; 1231 1232 uint16_t SocMaxCurrent; // in Amps 1233 int8_t SocOffset; // in Amps 1234 uint8_t Padding_TelemetrySoc; 1235 1236 uint16_t Mem0MaxCurrent; // in Amps 1237 int8_t Mem0Offset; // in Amps 1238 uint8_t Padding_TelemetryMem0; 1239 1240 uint16_t Mem1MaxCurrent; // in Amps 1241 int8_t Mem1Offset; // in Amps 1242 uint8_t Padding_TelemetryMem1; 1243 1244 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 1245 1246 // SECTION: GPIO Settings 1247 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 1248 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 1249 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 1250 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 1251 1252 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 1253 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 1254 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 1255 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 1256 1257 // LED Display Settings 1258 uint8_t LedPin0; // GPIO number for LedPin[0] 1259 uint8_t LedPin1; // GPIO number for LedPin[1] 1260 uint8_t LedPin2; // GPIO number for LedPin[2] 1261 uint8_t LedEnableMask; 1262 1263 uint8_t LedPcie; // GPIO number for PCIE results 1264 uint8_t LedError; // GPIO number for Error Cases 1265 uint8_t LedSpare1[2]; 1266 1267 // SECTION: Clock Spread Spectrum 1268 1269 // GFXCLK PLL Spread Spectrum 1270 uint8_t PllGfxclkSpreadEnabled; // on or off 1271 uint8_t PllGfxclkSpreadPercent; // Q4.4 1272 uint16_t PllGfxclkSpreadFreq; // kHz 1273 1274 // GFXCLK DFLL Spread Spectrum 1275 uint8_t DfllGfxclkSpreadEnabled; // on or off 1276 uint8_t DfllGfxclkSpreadPercent; // Q4.4 1277 uint16_t DfllGfxclkSpreadFreq; // kHz 1278 1279 // UCLK Spread Spectrum 1280 uint16_t UclkSpreadPadding; 1281 uint16_t UclkSpreadFreq; // kHz 1282 1283 // FCLK Spread Spectrum 1284 uint8_t FclkSpreadEnabled; // on or off 1285 uint8_t FclkSpreadPercent; // Q4.4 1286 uint16_t FclkSpreadFreq; // kHz 1287 1288 // Section: Memory Config 1289 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 1290 1291 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines 1292 uint8_t PaddingMem1[3]; 1293 1294 // Section: Total Board Power 1295 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 1296 uint16_t BoardPowerPadding; 1297 1298 // SECTION: XGMI Training 1299 uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS]; 1300 uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS]; 1301 1302 uint16_t XgmiFclkFreq [NUM_XGMI_PSTATE_LEVELS]; 1303 uint16_t XgmiSocVoltage [NUM_XGMI_PSTATE_LEVELS]; 1304 1305 // SECTION: UMC feature flags 1306 uint8_t HsrEnabled; 1307 uint8_t VddqOffEnabled; 1308 uint8_t PaddingUmcFlags[2]; 1309 1310 // UCLK Spread Spectrum 1311 uint8_t UclkSpreadPercent[16]; 1312 1313 // SECTION: Board Reserved 1314 uint32_t BoardReserved[11]; 1315 1316 // SECTION: Structure Padding 1317 1318 // Padding for MMHUB - do not modify this 1319 uint32_t MmHubPadding[8]; // SMU internal use 1320 1321 1322} PPTable_beige_goby_t; 1323 1324typedef struct { 1325 // Time constant parameters for clock averages in ms 1326 uint16_t GfxclkAverageLpfTau; 1327 uint16_t FclkAverageLpfTau; 1328 uint16_t UclkAverageLpfTau; 1329 uint16_t GfxActivityLpfTau; 1330 uint16_t UclkActivityLpfTau; 1331 uint16_t SocketPowerLpfTau; 1332 uint16_t VcnClkAverageLpfTau; 1333 uint16_t padding16; 1334} DriverSmuConfig_t; 1335 1336typedef struct { 1337 DriverSmuConfig_t DriverSmuConfig; 1338 1339 uint32_t Spare[7]; 1340 // Padding - ignore 1341 uint32_t MmHubPadding[8]; // SMU internal use 1342} DriverSmuConfigExternal_t; 1343 1344typedef struct { 1345 uint16_t GfxclkFmin; // MHz 1346 uint16_t GfxclkFmax; // MHz 1347 QuadraticInt_t CustomGfxVfCurve; // a: mV/MHz^2, b: mv/MHz, c: mV 1348 uint16_t CustomCurveFmin; // MHz 1349 uint16_t UclkFmin; // MHz 1350 uint16_t UclkFmax; // MHz 1351 int16_t OverDrivePct; // % 1352 uint16_t FanMaximumRpm; 1353 uint16_t FanMinimumPwm; 1354 uint16_t FanAcousticLimitRpm; 1355 uint16_t FanTargetTemperature; // Degree Celcius 1356 uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; 1357 uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; 1358 uint16_t MaxOpTemp; // Degree Celcius 1359 int16_t VddGfxOffset; // in mV 1360 uint8_t FanZeroRpmEnable; 1361 uint8_t FanZeroRpmStopTemp; 1362 uint8_t FanMode; 1363 uint8_t Padding[1]; 1364} OverDriveTable_t; 1365 1366typedef struct { 1367 OverDriveTable_t OverDriveTable; 1368 uint32_t Spare[8]; 1369 1370 uint32_t MmHubPadding[8]; // SMU internal use 1371} OverDriveTableExternal_t; 1372 1373typedef struct { 1374 uint32_t CurrClock[PPCLK_COUNT]; 1375 1376 uint16_t AverageGfxclkFrequencyPreDs; 1377 uint16_t AverageGfxclkFrequencyPostDs; 1378 uint16_t AverageFclkFrequencyPreDs; 1379 uint16_t AverageFclkFrequencyPostDs; 1380 uint16_t AverageUclkFrequencyPreDs ; 1381 uint16_t AverageUclkFrequencyPostDs ; 1382 1383 1384 uint16_t AverageGfxActivity ; 1385 uint16_t AverageUclkActivity ; 1386 uint8_t CurrSocVoltageOffset ; 1387 uint8_t CurrGfxVoltageOffset ; 1388 uint8_t CurrMemVidOffset ; 1389 uint8_t Padding8 ; 1390 uint16_t AverageSocketPower ; 1391 uint16_t TemperatureEdge ; 1392 uint16_t TemperatureHotspot ; 1393 uint16_t TemperatureMem ; 1394 uint16_t TemperatureVrGfx ; 1395 uint16_t TemperatureVrMem0 ; 1396 uint16_t TemperatureVrMem1 ; 1397 uint16_t TemperatureVrSoc ; 1398 uint16_t TemperatureLiquid0 ; 1399 uint16_t TemperatureLiquid1 ; 1400 uint16_t TemperaturePlx ; 1401 uint16_t Padding16 ; 1402 uint32_t ThrottlerStatus ; 1403 1404 uint8_t LinkDpmLevel; 1405 uint8_t CurrFanPwm; 1406 uint16_t CurrFanSpeed; 1407 1408 //BACO metrics, PMFW-1721 1409 //metrics for D3hot entry/exit and driver ARM msgs 1410 uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1411 uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1412 uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1413 1414 //PMFW-4362 1415 uint32_t EnergyAccumulator; 1416 uint16_t AverageVclk0Frequency ; 1417 uint16_t AverageDclk0Frequency ; 1418 uint16_t AverageVclk1Frequency ; 1419 uint16_t AverageDclk1Frequency ; 1420 uint16_t VcnActivityPercentage ; //place holder, David N. to provide full sequence 1421 uint8_t PcieRate ; 1422 uint8_t PcieWidth ; 1423 uint16_t AverageGfxclkFrequencyTarget; 1424 1425 uint16_t Padding16_2; 1426} SmuMetrics_t; 1427 1428typedef struct { 1429 uint32_t CurrClock[PPCLK_COUNT]; 1430 1431 uint16_t AverageGfxclkFrequencyPreDs; 1432 uint16_t AverageGfxclkFrequencyPostDs; 1433 uint16_t AverageFclkFrequencyPreDs; 1434 uint16_t AverageFclkFrequencyPostDs; 1435 uint16_t AverageUclkFrequencyPreDs ; 1436 uint16_t AverageUclkFrequencyPostDs ; 1437 1438 1439 uint16_t AverageGfxActivity ; 1440 uint16_t AverageUclkActivity ; 1441 uint8_t CurrSocVoltageOffset ; 1442 uint8_t CurrGfxVoltageOffset ; 1443 uint8_t CurrMemVidOffset ; 1444 uint8_t Padding8 ; 1445 uint16_t AverageSocketPower ; 1446 uint16_t TemperatureEdge ; 1447 uint16_t TemperatureHotspot ; 1448 uint16_t TemperatureMem ; 1449 uint16_t TemperatureVrGfx ; 1450 uint16_t TemperatureVrMem0 ; 1451 uint16_t TemperatureVrMem1 ; 1452 uint16_t TemperatureVrSoc ; 1453 uint16_t TemperatureLiquid0 ; 1454 uint16_t TemperatureLiquid1 ; 1455 uint16_t TemperaturePlx ; 1456 uint16_t Padding16 ; 1457 uint32_t AccCnt ; 1458 uint8_t ThrottlingPercentage[THROTTLER_COUNT]; 1459 1460 1461 uint8_t LinkDpmLevel; 1462 uint8_t CurrFanPwm; 1463 uint16_t CurrFanSpeed; 1464 1465 //BACO metrics, PMFW-1721 1466 //metrics for D3hot entry/exit and driver ARM msgs 1467 uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1468 uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1469 uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1470 1471 //PMFW-4362 1472 uint32_t EnergyAccumulator; 1473 uint16_t AverageVclk0Frequency ; 1474 uint16_t AverageDclk0Frequency ; 1475 uint16_t AverageVclk1Frequency ; 1476 uint16_t AverageDclk1Frequency ; 1477 uint16_t VcnActivityPercentage ; //place holder, David N. to provide full sequence 1478 uint8_t PcieRate ; 1479 uint8_t PcieWidth ; 1480 uint16_t AverageGfxclkFrequencyTarget; 1481 1482 uint16_t Padding16_2; 1483} SmuMetrics_V2_t; 1484 1485typedef struct { 1486 uint32_t CurrClock[PPCLK_COUNT]; 1487 1488 uint16_t AverageGfxclkFrequencyPreDs; 1489 uint16_t AverageGfxclkFrequencyPostDs; 1490 uint16_t AverageFclkFrequencyPreDs; 1491 uint16_t AverageFclkFrequencyPostDs; 1492 uint16_t AverageUclkFrequencyPreDs; 1493 uint16_t AverageUclkFrequencyPostDs; 1494 1495 1496 uint16_t AverageGfxActivity; 1497 uint16_t AverageUclkActivity; 1498 uint8_t CurrSocVoltageOffset; 1499 uint8_t CurrGfxVoltageOffset; 1500 uint8_t CurrMemVidOffset; 1501 uint8_t Padding8; 1502 uint16_t AverageSocketPower; 1503 uint16_t TemperatureEdge; 1504 uint16_t TemperatureHotspot; 1505 uint16_t TemperatureMem; 1506 uint16_t TemperatureVrGfx; 1507 uint16_t TemperatureVrMem0; 1508 uint16_t TemperatureVrMem1; 1509 uint16_t TemperatureVrSoc; 1510 uint16_t TemperatureLiquid0; 1511 uint16_t TemperatureLiquid1; 1512 uint16_t TemperaturePlx; 1513 uint16_t Padding16; 1514 uint32_t AccCnt; 1515 uint8_t ThrottlingPercentage[THROTTLER_COUNT]; 1516 1517 1518 uint8_t LinkDpmLevel; 1519 uint8_t CurrFanPwm; 1520 uint16_t CurrFanSpeed; 1521 1522 //BACO metrics, PMFW-1721 1523 //metrics for D3hot entry/exit and driver ARM msgs 1524 uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1525 uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1526 uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1527 1528 //PMFW-4362 1529 uint32_t EnergyAccumulator; 1530 uint16_t AverageVclk0Frequency; 1531 uint16_t AverageDclk0Frequency; 1532 uint16_t AverageVclk1Frequency; 1533 uint16_t AverageDclk1Frequency; 1534 uint16_t VcnUsagePercentage0; 1535 uint16_t VcnUsagePercentage1; 1536 uint8_t PcieRate; 1537 uint8_t PcieWidth; 1538 uint16_t AverageGfxclkFrequencyTarget; 1539 1540 uint32_t PublicSerialNumLower32; 1541 uint32_t PublicSerialNumUpper32; 1542 1543} SmuMetrics_V3_t; 1544 1545typedef struct { 1546 uint32_t CurrClock[PPCLK_COUNT]; 1547 1548 uint16_t AverageGfxclkFrequencyPreDs; 1549 uint16_t AverageGfxclkFrequencyPostDs; 1550 uint16_t AverageFclkFrequencyPreDs; 1551 uint16_t AverageFclkFrequencyPostDs; 1552 uint16_t AverageUclkFrequencyPreDs; 1553 uint16_t AverageUclkFrequencyPostDs; 1554 1555 1556 uint16_t AverageGfxActivity; 1557 uint16_t AverageUclkActivity; 1558 uint8_t CurrSocVoltageOffset; 1559 uint8_t CurrGfxVoltageOffset; 1560 uint8_t CurrMemVidOffset; 1561 uint8_t Padding8; 1562 uint16_t AverageSocketPower; 1563 uint16_t TemperatureEdge; 1564 uint16_t TemperatureHotspot; 1565 uint16_t TemperatureMem; 1566 uint16_t TemperatureVrGfx; 1567 uint16_t TemperatureVrMem0; 1568 uint16_t TemperatureVrMem1; 1569 uint16_t TemperatureVrSoc; 1570 uint16_t TemperatureLiquid0; 1571 uint16_t TemperatureLiquid1; 1572 uint16_t TemperaturePlx; 1573 uint16_t Padding16; 1574 uint32_t AccCnt; 1575 uint8_t ThrottlingPercentage[THROTTLER_COUNT]; 1576 1577 1578 uint8_t LinkDpmLevel; 1579 uint8_t CurrFanPwm; 1580 uint16_t CurrFanSpeed; 1581 1582 //BACO metrics, PMFW-1721 1583 //metrics for D3hot entry/exit and driver ARM msgs 1584 uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1585 uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1586 uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1587 1588 //PMFW-4362 1589 uint32_t EnergyAccumulator; 1590 uint16_t AverageVclk0Frequency; 1591 uint16_t AverageDclk0Frequency; 1592 uint16_t AverageVclk1Frequency; 1593 uint16_t AverageDclk1Frequency; 1594 uint16_t VcnUsagePercentage0; 1595 uint16_t VcnUsagePercentage1; 1596 uint8_t PcieRate; 1597 uint8_t PcieWidth; 1598 uint16_t AverageGfxclkFrequencyTarget; 1599 1600 uint8_t ApuSTAPMSmartShiftLimit; 1601 uint8_t AverageApuSocketPower; 1602 uint8_t ApuSTAPMLimit; 1603 uint8_t Padding8_2; 1604 1605} SmuMetrics_V4_t; 1606 1607typedef struct { 1608 union { 1609 SmuMetrics_t SmuMetrics; 1610 SmuMetrics_V2_t SmuMetrics_V2; 1611 SmuMetrics_V3_t SmuMetrics_V3; 1612 SmuMetrics_V4_t SmuMetrics_V4; 1613 }; 1614 uint32_t Spare[1]; 1615 1616 // Padding - ignore 1617 uint32_t MmHubPadding[8]; // SMU internal use 1618} SmuMetricsExternal_t; 1619 1620typedef struct { 1621 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) 1622 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) 1623 uint16_t MinUclk; 1624 uint16_t MaxUclk; 1625 1626 uint8_t WmSetting; 1627 uint8_t Flags; 1628 uint8_t Padding[2]; 1629 1630} WatermarkRowGeneric_t; 1631 1632#define NUM_WM_RANGES 4 1633 1634typedef enum { 1635 WM_SOCCLK = 0, 1636 WM_DCEFCLK, 1637 WM_COUNT, 1638} WM_CLOCK_e; 1639 1640typedef enum { 1641 WATERMARKS_CLOCK_RANGE = 0, 1642 WATERMARKS_DUMMY_PSTATE, 1643 WATERMARKS_MALL, 1644 WATERMARKS_COUNT, 1645} WATERMARKS_FLAGS_e; 1646 1647typedef struct { 1648 // Watermarks 1649 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; 1650} Watermarks_t; 1651 1652typedef struct { 1653 Watermarks_t Watermarks; 1654 1655 uint32_t MmHubPadding[8]; // SMU internal use 1656} WatermarksExternal_t; 1657 1658typedef struct { 1659 uint16_t avgPsmCount[67]; 1660 uint16_t minPsmCount[67]; 1661 float avgPsmVoltage[67]; 1662 float minPsmVoltage[67]; 1663} AvfsDebugTable_t; 1664 1665typedef struct { 1666 AvfsDebugTable_t AvfsDebugTable; 1667 1668 uint32_t MmHubPadding[8]; // SMU internal use 1669} AvfsDebugTableExternal_t; 1670 1671typedef struct { 1672 uint8_t AvfsVersion; 1673 uint8_t Padding; 1674 1675 uint8_t AvfsEn[AVFS_VOLTAGE_COUNT]; 1676 1677 uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT]; 1678 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 1679 1680 uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT]; 1681 uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT]; 1682 uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT]; 1683 uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT]; 1684 1685 int32_t VFT0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1686 int32_t VFT0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1687 int32_t VFT0_b[AVFS_VOLTAGE_COUNT]; // Q32 1688 1689 int32_t VFT1_m1[AVFS_VOLTAGE_COUNT]; // Q8.16 1690 int32_t VFT1_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1691 int32_t VFT1_b[AVFS_VOLTAGE_COUNT]; // Q32 1692 1693 int32_t VFT2_m1[AVFS_VOLTAGE_COUNT]; // Q8.16 1694 int32_t VFT2_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1695 int32_t VFT2_b[AVFS_VOLTAGE_COUNT]; // Q32 1696 1697 int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1698 int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1699 int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT]; // Q32 1700 1701 int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1702 int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1703 int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT]; // Q32 1704 1705 uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT]; 1706 uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT]; 1707 uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT]; 1708 1709 uint32_t VInversion[AVFS_VOLTAGE_COUNT]; // in mV with 2 fractional bits 1710 1711 1712 int32_t P2V_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1713 int32_t P2V_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1714 int32_t P2V_b[AVFS_VOLTAGE_COUNT]; // Q32 1715 1716 uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units 1717 1718 uint32_t EnabledAvfsModules[3]; //Sienna_Cichlid - 67 AVFS modules 1719} AvfsFuseOverride_t; 1720 1721typedef struct { 1722 AvfsFuseOverride_t AvfsFuseOverride; 1723 1724 uint32_t MmHubPadding[8]; // SMU internal use 1725} AvfsFuseOverrideExternal_t; 1726 1727typedef struct { 1728 uint8_t Gfx_ActiveHystLimit; 1729 uint8_t Gfx_IdleHystLimit; 1730 uint8_t Gfx_FPS; 1731 uint8_t Gfx_MinActiveFreqType; 1732 uint8_t Gfx_BoosterFreqType; 1733 uint8_t Gfx_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1734 uint16_t Gfx_MinActiveFreq; // MHz 1735 uint16_t Gfx_BoosterFreq; // MHz 1736 uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 1737 uint32_t Gfx_PD_Data_limit_a; // Q16 1738 uint32_t Gfx_PD_Data_limit_b; // Q16 1739 uint32_t Gfx_PD_Data_limit_c; // Q16 1740 uint32_t Gfx_PD_Data_error_coeff; // Q16 1741 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1742 1743 uint8_t Fclk_ActiveHystLimit; 1744 uint8_t Fclk_IdleHystLimit; 1745 uint8_t Fclk_FPS; 1746 uint8_t Fclk_MinActiveFreqType; 1747 uint8_t Fclk_BoosterFreqType; 1748 uint8_t Fclk_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1749 uint16_t Fclk_MinActiveFreq; // MHz 1750 uint16_t Fclk_BoosterFreq; // MHz 1751 uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms 1752 uint32_t Fclk_PD_Data_limit_a; // Q16 1753 uint32_t Fclk_PD_Data_limit_b; // Q16 1754 uint32_t Fclk_PD_Data_limit_c; // Q16 1755 uint32_t Fclk_PD_Data_error_coeff; // Q16 1756 uint32_t Fclk_PD_Data_error_rate_coeff; // Q16 1757 1758 uint8_t Mem_ActiveHystLimit; 1759 uint8_t Mem_IdleHystLimit; 1760 uint8_t Mem_FPS; 1761 uint8_t Mem_MinActiveFreqType; 1762 uint8_t Mem_BoosterFreqType; 1763 uint8_t Mem_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1764 uint16_t Mem_MinActiveFreq; // MHz 1765 uint16_t Mem_BoosterFreq; // MHz 1766 uint16_t Mem_PD_Data_time_constant; // Time constant of PD controller in ms 1767 uint32_t Mem_PD_Data_limit_a; // Q16 1768 uint32_t Mem_PD_Data_limit_b; // Q16 1769 uint32_t Mem_PD_Data_limit_c; // Q16 1770 uint32_t Mem_PD_Data_error_coeff; // Q16 1771 uint32_t Mem_PD_Data_error_rate_coeff; // Q16 1772 1773 uint32_t Mem_UpThreshold_Limit; // Q16 1774 uint8_t Mem_UpHystLimit; 1775 uint8_t Mem_DownHystLimit; 1776 uint16_t Mem_Fps; 1777 1778} DpmActivityMonitorCoeffInt_t; 1779 1780 1781typedef struct { 1782 DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt; 1783 uint32_t MmHubPadding[8]; // SMU internal use 1784} DpmActivityMonitorCoeffIntExternal_t; 1785 1786// Workload bits 1787#define WORKLOAD_PPLIB_DEFAULT_BIT 0 1788#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1789#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1790#define WORKLOAD_PPLIB_VIDEO_BIT 3 1791#define WORKLOAD_PPLIB_VR_BIT 4 1792#define WORKLOAD_PPLIB_COMPUTE_BIT 5 1793#define WORKLOAD_PPLIB_CUSTOM_BIT 6 1794#define WORKLOAD_PPLIB_W3D_BIT 7 1795#define WORKLOAD_PPLIB_COUNT 8 1796 1797 1798// These defines are used with the following messages: 1799// SMC_MSG_TransferTableDram2Smu 1800// SMC_MSG_TransferTableSmu2Dram 1801 1802// Table transfer status 1803#define TABLE_TRANSFER_OK 0x0 1804#define TABLE_TRANSFER_FAILED 0xFF 1805 1806// Table types 1807#define TABLE_PPTABLE 0 1808#define TABLE_WATERMARKS 1 1809#define TABLE_AVFS_PSM_DEBUG 2 1810#define TABLE_AVFS_FUSE_OVERRIDE 3 1811#define TABLE_PMSTATUSLOG 4 1812#define TABLE_SMU_METRICS 5 1813#define TABLE_DRIVER_SMU_CONFIG 6 1814#define TABLE_ACTIVITY_MONITOR_COEFF 7 1815#define TABLE_OVERDRIVE 8 1816#define TABLE_I2C_COMMANDS 9 1817#define TABLE_PACE 10 1818#define TABLE_ECCINFO 11 1819#define TABLE_COUNT 12 1820 1821typedef struct { 1822 float FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS]; 1823} RlcPaceFlopsPerByteOverride_t; 1824 1825typedef struct { 1826 RlcPaceFlopsPerByteOverride_t RlcPaceFlopsPerByteOverride; 1827 1828 uint32_t MmHubPadding[8]; // SMU internal use 1829} RlcPaceFlopsPerByteOverrideExternal_t; 1830 1831// These defines are used with the SMC_MSG_SetUclkFastSwitch message. 1832#define UCLK_SWITCH_SLOW 0 1833#define UCLK_SWITCH_FAST 1 1834#define UCLK_SWITCH_DUMMY 2 1835#endif 1836