#
6a7cbbc2 |
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06-Mar-2024 |
Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> |
drm/amdgpu/vcn: enable vcn1 fw load for VCN 4_0_6 v1 - update the fw header for each vcn instance (Veera) VCN1 has different FW binary in VCN v4_0_6. Add changes to load the VCN1 fw binary Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b6d1a063 |
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25-Apr-2023 |
Sonny Jiang <sonny.jiang@amd.com> |
drm/amdgpu: add VCN_5_0_0 IP block support Add VCN_5_0_0 IP init, ring functions, DPG support. v2: squash in warning fixes (Alex) v3: squash in block and ring init, boot, doorbell enablement, DPG support (Alex) Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
eb9d6256 |
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15-Oct-2023 |
Bokun Zhang <bokun.zhang@amd.com> |
drm/amd/amdgpu/vcn: Add RB decouple feature under SRIOV - P3 - Update VCN header for RB decouple feature - Add metadata struct, metadata will be placed after each RB Signed-off-by: Bokun Zhang <bokun.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2b6b29f3 |
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30-Sep-2023 |
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> |
drm/amdgpu: Fix complex macros error Fixes the below: ERROR: Macros with complex values should be enclosed in parentheses WARNING: macros should not use a trailing semicolon +#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c6195ef5 |
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14-Jul-2023 |
sguttula <Suresh.Guttula@amd.com> |
drm/amdgpu: Enabling FW workaround through shared memory for VCN4_0_2 This patch will enable VCN FW workaround using DRM KEY INJECT WORKAROUND method, which is helping in fixing the secure playback. Signed-off-by: sguttula <Suresh.Guttula@amd.com> Reviewed-by: Leo Liu <leo.liiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
33e88286 |
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12-Jul-2023 |
Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> |
Revert "drm/amdgpu:update kernel vcn ring test" VCN FW depncencies revert it to unblock others This reverts commit f3fa86f5c778e258cd5c01bb420d4639bb393bd0. Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> Acked-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f3fa86f5 |
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13-Jun-2023 |
Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> |
drm/amdgpu:update kernel vcn ring test add session context buffer to decoder ring test. v5 - clear the session ct buffer (Christian) v4 - data type, explain change of ib size change (Christian) v3 - indent and v2 changes correction. (Christian) v2 - put the buffer at the end of the IB (Christian) Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1ddcdb7c |
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07-Jul-2023 |
Lang Yu <Lang.Yu@amd.com> |
drm/amdgpu: use psp_execute_load_ip_fw instead Replace the old ones with psp_execute_load_ip_fw. Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Lang Yu <Lang.Yu@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2ecf927b |
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15-May-2023 |
Horatio Zhang <Hongkun.Zhang@amd.com> |
drm/amdgpu: separate ras irq from vcn instance irq for UVD_POISON Separate vcn RAS poison consumption handling from the instance irq, and register dedicated ras_poison_irq src and funcs for UVD_POISON. v2: - Separate ras irq from vcn instance irq - Improve the subject and code comments v3: - Split the patch into three parts - Improve the code comments Suggested-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Horatio Zhang <Hongkun.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
fd91d38b |
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17-Feb-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Use logical ids for VCN/JPEG v4.0.3 Address VCN/JPEG instances using logical ids. Whenever register access is required, get the physical instance using GET_INST. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Tested-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
aaf1090a |
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17-Feb-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add instance mask for VCN and JPEG Keep an instance mask formed by physical instance numbers for VCN and JPEG IPs. Populate the mask from discovery table information. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Tested-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7e0eebdc |
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14-Sep-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: extend max instances Number of instances is extended. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f9f74df5 |
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02-Jul-2022 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn: update vcn header to support multiple AIDs Add aid_id in vcn header to support multiple AIDs Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ac1d8e2f |
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15-May-2023 |
Horatio Zhang <Hongkun.Zhang@amd.com> |
drm/amdgpu: separate ras irq from vcn instance irq for UVD_POISON Separate vcn RAS poison consumption handling from the instance irq, and register dedicated ras_poison_irq src and funcs for UVD_POISON. v2: - Separate ras irq from vcn instance irq - Improve the subject and code comments v3: - Split the patch into three parts - Improve the code comments Suggested-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Horatio Zhang <Hongkun.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f81c31d9 |
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11-Mar-2023 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: Move vcn ras block init to ras sw_init Initialize vcn ras block only when vcn ip block supports ras features. Driver queries ras capabilities after early_init, ras block init needs to be moved to sw_int. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Stanley Yang <Stanley.Yang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
69939009 |
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28-Dec-2022 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Load VCN microcode during early_init Simplifies the code so that all VCN versions will get the firmware name from `amdgpu_ucode_ip_version_decode` and then use this filename to load microcode as part of the early_init process. Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2ddb629b |
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20-Oct-2022 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: define common vcn_set_ras_funcs So the code can be reused. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
167be852 |
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22-Sep-2022 |
Ruijing Dong <ruijing.dong@amd.com> |
drm/amdgpu/vcn: update vcn4 fw shared data structure update VF_RB_SETUP_FLAG, add SMU_DPM_INTERFACE_FLAG, and corresponding change in VCN4. Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
aa44beb5 |
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22-Aug-2022 |
Jane Jian <Jane.Jian@amd.com> |
drm/amdgpu/vcn: Add sriov VCN v4_0 unified queue support Enable unified queue support for sriov, abandon all previous multi-queue settings Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jane Jian <Jane.Jian@amd.com> Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4ed49c95 |
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31-May-2022 |
Ruijing Dong <ruijing.dong@amd.com> |
drm/amdgpu/vcn: add unified queue ib test - add unified queue headers - add unified queue ib tests Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0ae99221 |
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07-May-2022 |
Mohammad Zafar Ziya <Mohammadzafar.ziya@amd.com> |
drm/amdgpu/vcn: Add vcn ras poison consumption event handling Add vcn ras poison consumption event handling V2: Removed default poison consumption handling function cb Signed-off-by: Mohammad Zafar Ziya <Mohammadzafar.ziya@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8da1170a |
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13-Apr-2022 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: add VCN4 ip block support Add VCN 4.0 initialization and decoder/encoder ring functions. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b857e147 |
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03-Dec-2021 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: move out asic specific definition from common header Move out asic specific definition from common header. Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Sonny Jiang <sonny.jiang@amd.com> Signed-off-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
622469c8 |
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29-Mar-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/discovery: add a function to parse the vcn info table To get the codec disable fuse mask. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
60fce741 |
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16-Mar-2022 |
Mohammad Zafar Ziya <Mohammadzafar.ziya@amd.com> |
drm/amdgpu/vcn: Add vcn ras support VCN block ras feature support addition V2: default ras callback removed Signed-off-by: Mohammad Zafar Ziya <Mohammadzafar.ziya@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e3026a05 |
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23-Mar-2022 |
Boyuan Zhang <boyuan.zhang@amd.com> |
drm/amdgpu/vcn3: send smu interface type For VCN FW to detect ASIC type, in order to use different mailbox registers. V2: simplify codes and fix format issue. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Acked-by Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
945da79e |
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23-Mar-2022 |
Boyuan Zhang <boyuan.zhang@amd.com> |
drm/amdgpu/vcn3: send smu interface type For VCN FW to detect ASIC type, in order to use different mailbox registers. V2: simplify codes and fix format issue. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Acked-by Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
11eb648d |
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02-Mar-2022 |
Ruijing Dong <ruijing.dong@amd.com> |
drm/amdgpu/vcn: Add vcn firmware log vcn fwlog is for debugging purpose only, by default, it is disabled. Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b6065ebf |
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02-Mar-2022 |
Ruijing Dong <ruijing.dong@amd.com> |
drm/amdgpu/vcn: Update fw shared data structure Add fw log in fw shared data structure. Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c40bdfb2 |
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08-Dec-2021 |
Leslie Shi <Yuliang.Shi@amd.com> |
drm/amdgpu: fix incorrect VCN revision in SRIOV Guest OS will setup VCN instance 1 which is disabled as an enabled instance and execute initialization work on it, but this causes VCN ib ring test failure on the disabled VCN instance during modprobe: amdgpu 0000:00:08.0: amdgpu: ring vcn_enc_1.0 uses VM inv eng 5 on hub 1 amdgpu 0000:00:08.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on vcn_dec_0 (-110). amdgpu 0000:00:08.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on vcn_enc_0.0 (-110). [drm:amdgpu_device_delayed_init_work_handler [amdgpu]] *ERROR* ib ring test failed (-110). v2: drop amdgpu_discovery_get_vcn_version and rename sriov_config to vcn_config v3: modify VCN's revision in SR-IOV and bare-metal Fixes: baf3f8f3740625 ("drm/amdgpu: handle SRIOV VCN revision parsing") Signed-off-by: Leslie Shi <Yuliang.Shi@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
baf3f8f3 |
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30-Nov-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: handle SRIOV VCN revision parsing For SR-IOV, the IP discovery revision number encodes additional information. Handle that case here. v2: drop additional IP versions Reviewed-by: Guchun Chen <guchun.chen@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c5dd5667 |
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19-Oct-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: Consolidate VCN firmware setup code Roughly the same code was present in all VCN versions. Consolidate it into a single function. v2: use AMDGPU_UCODE_ID_VCN + i, check if num_inst >= 2 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com>
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#
0ad29a4e |
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27-Aug-2021 |
Satyajit Sahu <satyajit.sahu@amd.com> |
drm/amdgpu/vcn: set the priority for each encode ring VCN has multiple rings. Set the proper priority level for each encode ring while initializing. Signed-off-by: Satyajit Sahu <satyajit.sahu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
376002f4 |
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05-Jan-2021 |
Bokun Zhang <Bokun.Zhang@amd.com> |
drm/amd/amdgpu: Use IP discovery data to determine VCN enablement instead of MMSCH In the past, we use MMSCH to determine whether a VCN is enabled or not. This is not reliable since after a FLR, MMSCH may report junk data. It is better to use IP discovery data. Signed-off-by: Bokun Zhang <Bokun.Zhang@amd.com> Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c62dfdbb |
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02-Feb-2021 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: share scheduler score on VCN3 instances The VCN3 instances can do both decode as well as encode. Share the scheduler load balancing score and remove fixing encode to only the second instance. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b2576c3b |
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31-Jan-2021 |
Sonny Jiang <sonny.jiang@amd.com> |
drm/amdgpu/vcn3.0: add wptr/rptr reset/update for share memory Because of dpg, the rptr/wptr need to be saved on fw shared memory, and restore them back in RBC_RB_RPTR/WPTR in kernel at power up. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
477f25eb |
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02-Nov-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn: update header to support dec software ring Add macro, structure and function prototype to support vcn dec software ring. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
187561dd |
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08-Oct-2020 |
Veerabadhran G <vegopala@amd.com> |
drm/amdgpu: vcn and jpeg ring synchronization Synchronize the ring usage for vcn1 and jpeg1 to workaround a hardware bug. Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
56380c38 |
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08-Oct-2020 |
Veerabadhran G <vegopala@amd.com> |
drm/amdgpu: vcn and jpeg ring synchronization Synchronize the ring usage for vcn1 and jpeg1 to workaround a hardware bug. Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4908d026 |
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16-Jul-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn: merge shared memory into vcpu Merge vcn firmware shared memory bo into vcn vcpu bo. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d10985f4 |
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16-Jul-2020 |
James Zhu <James.Zhu@amd.com> |
Revert "drm/amdgpu/vcn: add shared memory restore after wake up from sleep." This reverts commit 21b704d78352c289d31697824ceea7ad0ff4ce59. To merge vcn firmware shared memory bo into vcn vcpu bo. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4d319ed6 |
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30-Mar-2020 |
Boyuan Zhang <boyuan.zhang@amd.com> |
drm/amdgpu: rename macro for VCN2.0 2.5 and 3.0 Rename SOC15_DPG_MODE_OFFSET_2_0, RREG32_SOC15_DPG_MODE_2_0 and WREG32_SOC15_DPG_MODE_2_0 for VCN2.0, VCN2.5 and VCN3.0. These three macros are used VCN2.0, VCN2.5 and VCN3.0, therefore rename it to be a general name. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
914b5f53 |
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27-Mar-2020 |
Boyuan Zhang <boyuan.zhang@amd.com> |
drm/amdgpu: rename macro for VCN1.0 Rename RREG32_SOC15_DPG_MODE and WREG32_SOC15_DPG_MODE for VCN1.0 These two macros are used specifically for VCN1.0, therefore rename it from general name to VCN1.0 specific name. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
14539809 |
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26-Mar-2020 |
Boyuan Zhang <boyuan.zhang@amd.com> |
drm/amdgpu: add internal reg offset translation for VCN inst 1 Add range for vcn instance 1 for translation for internal register offset, which is needed for VCN3.0 V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
cf14826c |
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14-Nov-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: add VCN3.0 support for Sienna_Cichlid With basic IP block functions and ring functions Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
21b704d7 |
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02-Apr-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn: add shared memory restore after wake up from sleep. VCN shared memory needs restore after wake up during S3 test. v2: Allocate shared memory saved_bo at sw_init and free it in sw_fini. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1c6d567b |
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01-Apr-2020 |
Nirmoy Das <nirmoy.das@amd.com> |
drm/amdgpu: rework sched_list generation Generate HW IP's sched_list in amdgpu_ring_init() instead of amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(), ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary. This patch also stores sched_list for all HW IPs in one big array in struct amdgpu_device which makes amdgpu_ctx_init_entity() much more leaner. v2: fix a coding style issue do not use drm hw_ip const to populate amdgpu_ring_type enum v3: remove ctx reference and move sched array and num_sched to a struct use num_scheds to detect uninitialized scheduler list v4: use array_index_nospec for user space controlled variables fix possible checkpatch.pl warnings Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2c68f0e3 |
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29-Mar-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn: Add firmware share memory support Added firmware share memory support for VCN. Current multiple queue mode is enabled only. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e3b41d82 |
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09-Feb-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn: fix race condition issue for dpg unpause mode switch Couldn't only rely on enc fence to decide switching to dpg unpaude mode. Since a enc thread may not schedule a fence in time during multiple threads running situation. v3: 1. Rename enc_submission_cnt to dpg_enc_submission_cnt 2. Add dpg_enc_submission_cnt check in idle_work_handler v4: Remove extra counter check, and reduce counter before idle work schedule Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bd718638 |
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09-Feb-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn: fix race condition issue for vcn start Fix race condition issue when multiple vcn starts are called. v2: Removed checking the return value of cancel_delayed_work_sync() to prevent possible races here. v3: Add total_submission_cnt to avoid gate power unexpectedly. v4: Remove extra counter check, and reduce counter before idle work schedule Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f4d0242b |
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05-Feb-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn2.5: fix DPG mode power off issue on instance 1 Support pause_state for multiple instance, and it will fix vcn2.5 DPG mode power off issue on instance 1. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
80ff3e10 |
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05-Feb-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn2.5: fix DPG mode power off issue on instance 1 Support pause_state for multiple instance, and it will fix vcn2.5 DPG mode power off issue on instance 1. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
55bbb747 |
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21-Jan-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn: use inst_idx relacing inst Use inst_idx relacing inst in SOC15_DPG_MODE macro to avoid confusion. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a4555732 |
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21-Jan-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn: fix typo error Fix typo error, should be inst_idx instead of inst. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
45cec87c |
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15-Jan-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn: move macro from vcn2.0 to share amdgpu_vcn (v2) Move macro from vcn2.0 to amdgpu_vcn to share with vcn2.5 v2: squash in macro fix Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5db86843 |
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15-Jan-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn: support multiple instance direct SRAM read and write (v2) Add multiple instance direct SRAM read and write support for vcn2.5 v2: squash in indexing fix Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
597e6ac3 |
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13-Jan-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn: support multiple-instance dpg pause mode Add multiple-instance dpg pause mode support for VCN2.5 Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f880799d |
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16-Dec-2019 |
Nirmoy Das <nirmoy.das@amd.com> |
amd/amdgpu: add sched array to IPs with multiple run-queues This sched array can be passed on to entity creation routine instead of manually creating such sched array on every context creation. v2: squash in missing break fix Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d58ed707 |
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12-Dec-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu/vcn1.0: use its own idle handler and begin use funcs Because VCN1.0 power management and DPG mode are managed together with JPEG1.0 under both HW and FW, so separated them from general VCN code. Also the multiple instances case got removed, since VCN1.0 HW just have a single instance. v2: override work func with vcn1.0's own Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
14f43e8f |
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11-Nov-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: move JPEG2.5 out from VCN2.5 And clean up the duplicated stuff Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
af655cc5 |
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25-Jul-2019 |
Thong Thai <thong.thai@amd.com> |
drm/amd/amdgpu/vcn_v2_0: Mark RB commands as KMD commands Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This bit was previously set by the RBC HW on older firmware. Newer firmware uses a SW RBC and this bit has to be set by the driver. Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
333fe325 |
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25-Jul-2019 |
Thong Thai <thong.thai@amd.com> |
drm/amd/amdgpu/vcn_v2_0: Mark RB commands as KMD commands Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This bit was previously set by the RBC HW on older firmware. Newer firmware uses a SW RBC and this bit has to be set by the driver. Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
cd1fd7b3 |
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09-Jul-2019 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: add harvest support for Arcturus Add VCN harvest support for Arcturus Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c01b6a1d |
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10-Jul-2019 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: modify amdgpu_vcn to support multiple instances Arcturus has dual-VCN. Need Restruct amdgpu_device::vcn to support multiple vcns. There are no any logical changes here Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
22a8f442 |
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15-Apr-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu/VCN2: put IB internal registers offset to structure So the ring functions can be shared with different VCN versions with different internal registers offsets Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
dc8ae677 |
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27-May-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu/VCN: implement indirect DPG SRAM mode SRAM will be programmed by PSP Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a77b9fdf |
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24-May-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu/VCN: add buffer for indirect SRAM usage This will be used later for indirect SRAM mode Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
19c663fc |
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23-May-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu/VCN2.0: add direct SRAM read and write This will be the basic and used for DPG mode Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
863dd269 |
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30-Apr-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu/VCN2.0: remove powergating for UVDW tile No UVDW tile any more from VCN2.0, so mark out related fields. It fixes error: "[drm] Register(0) [mmUVD_PGFSM_STATUS] failed to reach value 0x002aaaaa != 0x00aaaaaa" Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1b61de45 |
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15-Oct-2018 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: add initial VCN2.0 support (v2) VCN (Video Core Next) is the video encode/decode block. Porting over the same functions from VCN1.0 v2: squash in updates (Alex) Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9085914a |
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03-Dec-2018 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: add JPEG2.0 decode ring test Use register from JPEG tile, the UVD tile reg won't work for JPEG Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
60a2309e |
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15-Oct-2018 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: add VCN2.0 decode ib test Add internal register offset for registers involving in ib tests Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
45a1a48b |
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17-Oct-2018 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: add VCN2.0 decode ring test Add internal register offset for registers involving in ring tests Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9dc7b02a |
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12-May-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: make VCN DPG pause mode detached from general VCN It should be attached to VCN 1.0 Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
05eee12d |
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12-May-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: move the VCN DPG mode read and write to VCN Since this is VCN specific and only used by VCN Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
825da4d9 |
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02-Oct-2018 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn:Correct VCN cache window definition Correct VCN cache window definition. The old one is reused from UVD, and it is not fully correct. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0b8690b7 |
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10-Sep-2018 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu:Add DPG pause state Add DPG pause state to support VCN DPG mode. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c95f75f4 |
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13-Sep-2018 |
James Zhu <jzhums@gmail.com> |
drm/amdgpu:No action when VCN PG state is unchanged When VCN PG state is unchanged, it is unnecessary to reset power gate state Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6173040f |
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30-May-2018 |
Boyuan Zhang <boyuan.zhang@amd.com> |
drm/amdgpu: add vcn jpeg ib test Add an ib test for vcn jpeg. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b1d37606 |
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30-May-2018 |
Boyuan Zhang <boyuan.zhang@amd.com> |
drm/amdgpu: add vcn jpeg ring test Add a ring test for vcn jpeg. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
fa3087f7 |
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30-May-2018 |
Boyuan Zhang <boyuan.zhang@amd.com> |
drm/amdgpu: add vcn jpeg ring Add jpeg to amdgpu_vcn v2: remove unnecessary scheduler entity Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4c6530fd |
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25-May-2018 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: remove unnecessary scheduler entity for VCN It should be stateless, and no need for scheduler to take care specially. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d58c5d9a |
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17-May-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: Add VCN static PG support on RV Implement static powergating suport on VCN. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1b1f42d8 |
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06-Dec-2017 |
Lucas Stach <l.stach@pengutronix.de> |
drm: move amd_gpu_scheduler into common location This moves and renames the AMDGPU scheduler to a common location in DRM in order to facilitate re-use by other drivers. This is mostly a straight forward rename with no code changes. One notable exception is the function to_drm_sched_fence(), which is no longer a inline header function to avoid the need to export the drm_sched_fence_ops_scheduled and drm_sched_fence_ops_finished structures. Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8ace845f |
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21-Feb-2017 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: add vcn enc ring type and functions Add the ring function callbacks for the encode rings. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
101c6fee |
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21-Feb-2017 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: add vcn enc rings Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3639f7d8 |
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15-Feb-2017 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: change vcn dec rb command specific for decode Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7741cced |
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07-Feb-2017 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: expose vcn RB command Signed-off-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8c303c01 |
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06-Feb-2017 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: move vcn ring test to amdgpu_vcn.c Hope it will be generic for vcn later Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
95aa13f6 |
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11-May-2017 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: move amdgpu_vcn structure to vcn header Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2d531d81 |
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21-Dec-2016 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: add encode tests for vcn Add encode ring and ib tests. Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
95d0906f |
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21-Dec-2016 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: add initial vcn support and decode tests VCN is the new media block on Raven. Add core support and the ring and ib tests for decode. Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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