Lines Matching refs:uint32_t
104 uint32_t internal_reg_offset, addr; \
165 uint32_t internal_reg_offset, addr; \
277 uint32_t mem_size;
278 uint32_t log_offset;
296 uint32_t *dpg_sram_curr_addr;
317 uint32_t vcn_codec_disable_mask[AMDGPU_MAX_VCN_INSTANCES];
336 uint32_t rptr;
337 uint32_t wptr;
362 uint32_t addr_lo;
363 uint32_t addr_hi;
364 uint32_t size;
373 uint32_t present_flag_0;
384 uint32_t rb_addr_lo;
385 uint32_t rb_addr_hi;
386 uint32_t rb_size;
390 uint32_t is_rb_enabled_flags;
394 uint32_t rb_addr_lo;
395 uint32_t rb_addr_hi;
396 uint32_t rb_size;
397 uint32_t rb4_addr_lo;
398 uint32_t rb4_addr_hi;
399 uint32_t rb4_size;
400 uint32_t reserved[6];
420 uint32_t present_flag_0;
434 uint32_t rptr;
435 uint32_t wptr;
436 uint32_t buffer_size;
437 uint32_t header_size;
442 uint32_t valid_buf_flag;
443 uint32_t msg_buffer_address_hi;
444 uint32_t msg_buffer_address_lo;
445 uint32_t pad[30];
449 uint32_t size;
450 uint32_t present_flag_0;
458 uint32_t present_flag_0;
486 enum vcn_ring_type type, uint32_t vcn_instance);