/linux-master/drivers/gpu/drm/i915/ |
H A D | i915_suspend.c | 43 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); 44 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); 47 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); 50 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); 53 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); 54 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); 57 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); 95 dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB);
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/linux-master/drivers/gpu/drm/i915/display/ |
H A D | intel_fdi.c | 37 cur_state = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE; 39 cur_state = intel_de_read(dev_priv, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE; 61 cur_state = intel_de_read(dev_priv, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE; 90 cur_state = intel_de_read(i915, FDI_TX_CTL(pipe)) & FDI_TX_PLL_ENABLE; 100 cur_state = intel_de_read(i915, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE; 269 intel_de_read(i915, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK; 417 temp = intel_de_read(dev_priv, SOUTH_CHICKEN1); 422 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) & 425 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) & 472 temp = intel_de_read(dev_pri [all...] |
H A D | intel_hti.c | 19 i915->display.hti.state = intel_de_read(i915, HDPORT_STATE);
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H A D | intel_pch_display.c | 107 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe)); 117 u32 val = intel_de_read(dev_priv, hdmi_reg); 136 u32 val = intel_de_read(dev_priv, dp_reg); 227 intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder))); 229 intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder))); 231 intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder))); 234 intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder))); 236 intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder))); 238 intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder))); 240 intel_de_read(dev_pri [all...] |
H A D | intel_vga.c | 33 if (intel_de_read(dev_priv, vga_reg) & VGA_DISP_DISABLE) 52 if (!(intel_de_read(dev_priv, vga_reg) & VGA_DISP_DISABLE)) {
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H A D | intel_combo_phy.c | 59 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); 95 u32 val = intel_de_read(dev_priv, reg); 153 return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; 155 return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & 157 (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); 334 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); 348 val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN(0, phy)); 354 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
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H A D | intel_fifo_underrun.c | 102 if ((intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) 129 if (old && intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) 152 u32 err_int = intel_de_read(dev_priv, GEN7_ERR_INT); 183 intel_de_read(dev_priv, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { 239 u32 serr_int = intel_de_read(dev_priv, SERR_INT); 272 if (old && intel_de_read(dev_priv, SERR_INT) & 421 underruns = intel_de_read(dev_priv, ICL_PIPESTATUS(pipe)) &
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H A D | intel_crt.c | 89 val = intel_de_read(dev_priv, adpa_reg); 126 tmp = intel_de_read(dev_priv, crt->adpa_reg); 489 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); 513 adpa = intel_de_read(dev_priv, crt->adpa_reg); 548 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); 564 adpa = intel_de_read(dev_priv, crt->adpa_reg); 615 stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT); 713 save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder)); 714 save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)); 715 vblank = intel_de_read(dev_pri [all...] |
H A D | intel_display_power_well.c | 295 ret = intel_de_read(dev_priv, regs->bios) & req_mask ? 1 : 0; 296 ret |= intel_de_read(dev_priv, regs->driver) & req_mask ? 2 : 0; 298 ret |= intel_de_read(dev_priv, regs->kvmr) & req_mask ? 4 : 0; 299 ret |= intel_de_read(dev_priv, regs->debug) & req_mask ? 8 : 0; 321 wait_for((disabled = !(intel_de_read(dev_priv, regs->driver) & 593 val = intel_de_read(dev_priv, regs->driver); 603 val |= intel_de_read(dev_priv, regs->bios); 611 (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC9), 614 intel_de_read(dev_priv, DC_STATE_EN) & 618 intel_de_read(dev_pri [all...] |
H A D | intel_pps.c | 98 intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN, 112 DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; 122 pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; 275 return intel_de_read(dev_priv, PP_STATUS(pps_idx)) & PP_ON; 280 return intel_de_read(dev_priv, PP_CONTROL(pps_idx)) & EDP_FORCE_VDD; 295 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) & 370 return intel_de_read(i915, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT; 537 return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0; 550 return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; 570 intel_de_read(dev_pri [all...] |
H A D | icl_dsi.c | 55 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) 62 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) 134 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 183 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); 247 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 257 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); 295 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg); 441 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); 452 tmp = intel_de_read(dev_priv, 472 tmp = intel_de_read(dev_pri [all...] |
H A D | intel_dpll_mgr.c | 533 val = intel_de_read(i915, PCH_DPLL(id)); 535 hw_state->fp0 = intel_de_read(i915, PCH_FP0(id)); 536 hw_state->fp1 = intel_de_read(i915, PCH_FP1(id)); 548 val = intel_de_read(i915, PCH_DREF_CONTROL); 742 val = intel_de_read(i915, WRPLL_CTL(id)); 762 val = intel_de_read(i915, SPLL_CTL); 1222 if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT) 1404 val = intel_de_read(i915, regs[id].ctl); 1408 val = intel_de_read(i915, DPLL_CTRL1); 1413 hw_state->cfgcr1 = intel_de_read(i91 [all...] |
H A D | intel_vrr.c | 238 return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & TRANS_PUSH_SEND; 276 trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder)); 289 crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1; 290 crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1; 291 crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1;
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H A D | intel_backlight.c | 148 return intel_de_read(i915, BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; 155 return intel_de_read(i915, BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; 164 val = intel_de_read(i915, BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; 185 return intel_de_read(i915, VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; 193 return intel_de_read(i915, BXT_BLC_PWM_DUTY(panel->backlight.controller)); 211 val = intel_de_read(i915, BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; 221 tmp = intel_de_read(i915, BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; 249 tmp = intel_de_read(i915, BLC_PWM_CTL) & ~mask; 260 tmp = intel_de_read(i915, VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK; 349 tmp = intel_de_read(i91 [all...] |
H A D | intel_pch_refclk.c | 17 if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) & 23 if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) & 234 if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) 397 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); 398 u32 ctl = intel_de_read(dev_priv, SPLL_CTL); 417 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); 418 u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id)); 534 temp = intel_de_read(dev_priv, PCH_DPLL(pll->info->id)); 555 val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
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H A D | vlv_dsi.c | 124 u32 val = intel_de_read(dev_priv, reg); 243 if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port))) 349 u32 tmp = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 364 !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY); 388 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) { 449 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 639 temp = intel_de_read(dev_priv, port_ctrl); 963 bool enabled = intel_de_read(dev_priv, port_ctrl) & DPI_ENABLE; 972 enabled = intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE; 976 u32 tmp = intel_de_read(dev_pri [all...] |
H A D | intel_display_power.c | 1069 state = intel_de_read(dev_priv, reg) & DBUF_POWER_STATE; 1177 u32 val = intel_de_read(dev_priv, LCPLL_CTL); 1204 I915_STATE_WARN(dev_priv, intel_de_read(dev_priv, HSW_PWR_WELL_CTL2), 1207 intel_de_read(dev_priv, SPLL_CTL) & SPLL_PLL_ENABLE, 1210 intel_de_read(dev_priv, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, 1213 intel_de_read(dev_priv, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, 1216 intel_de_read(dev_priv, PP_STATUS(0)) & PP_ON, 1219 intel_de_read(dev_priv, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, 1223 intel_de_read(dev_priv, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, 1226 intel_de_read(dev_pri [all...] |
H A D | intel_dkl_phy.c | 52 val = intel_de_read(i915, DKL_REG_MMIO(reg));
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H A D | intel_dpio_phy.c | 293 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)); 297 val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch)); 303 val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch)); 314 val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN0(phy, ch)); 319 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)); 331 if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) 334 if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) & 342 if (!(intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { 354 u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy)); 498 val = intel_de_read(dev_pri [all...] |
H A D | intel_tc.c | 278 lane_mask = intel_de_read(i915, PORT_TX_DFLEXDPSP(tc->phy_fia)); 293 pin_mask = intel_de_read(i915, PORT_TX_DFLEXPA1(tc->phy_fia)); 310 val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); 407 val = intel_de_read(i915, PORT_TX_DFLEXDPMLE1(tc->phy_fia)); 505 fia_isr = intel_de_read(i915, PORT_TX_DFLEXDPSP(tc->phy_fia)); 506 pch_isr = intel_de_read(i915, SDEISR); 542 val = intel_de_read(i915, PORT_TX_DFLEXDPPMS(tc->phy_fia)); 561 val = intel_de_read(i915, PORT_TX_DFLEXDPCSSS(tc->phy_fia)); 586 val = intel_de_read(i915, PORT_TX_DFLEXDPCSSS(tc->phy_fia)); 743 val = intel_de_read(i91 [all...] |
H A D | intel_ddi.c | 182 ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)) & 197 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 230 ret = _wait_for(!(intel_de_read(dev_priv, 235 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), 358 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 644 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 722 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 780 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 785 tmp = intel_de_read(dev_priv, 826 tmp = intel_de_read(dev_pri [all...] |
H A D | intel_overlay.c | 332 tmp = intel_de_read(dev_priv, DOVSTA); 466 if (!(intel_de_read(dev_priv, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { 946 u32 tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS); 953 if (intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_VERT_AUTO_SCALE) 954 tmp = intel_de_read(dev_priv, PFIT_AUTO_RATIOS); 956 tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS); 1298 attrs->gamma0 = intel_de_read(dev_priv, OGAMC0); 1299 attrs->gamma1 = intel_de_read(dev_priv, OGAMC1); 1300 attrs->gamma2 = intel_de_read(dev_priv, OGAMC2); 1301 attrs->gamma3 = intel_de_read(dev_pri [all...] |
H A D | g4x_dp.c | 120 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; 170 bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN; 181 bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE; 255 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p)); 279 val = intel_de_read(dev_priv, dp_reg); 346 tmp = intel_de_read(dev_priv, intel_dp->output_reg); 351 u32 trans_dp = intel_de_read(dev_priv, 392 if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) 418 (intel_de_read(dev_priv, intel_dp->output_reg) & 678 u32 dp_reg = intel_de_read(dev_pri [all...] |
H A D | intel_display.c | 320 u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); 391 intel_de_read(dev_priv, dpll_reg) & port_mask, 433 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); 471 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); 701 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 1558 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1827 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 2122 intel_de_read(dev_priv, PFIT_CONTROL)); 2511 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2724 return intel_de_read(dev_pri [all...] |
H A D | intel_hdmi.c | 77 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, 86 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & 208 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 250 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA); 257 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 278 u32 val = intel_de_read(dev_priv, reg); 322 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 331 u32 val = intel_de_read(dev_priv, reg); 353 u32 val = intel_de_read(dev_priv, reg); 400 *data++ = intel_de_read(dev_pri [all...] |