i915/display/icl_dsi.c

55 	return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
62 	return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
134 		if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
183 	tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans));
247 		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
257 		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
295 	dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg);
441 		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
452 			tmp = intel_de_read(dev_priv,
472 		tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
488 		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
499 		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
515 		if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
607 	tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
623 	tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
639 	tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
660 	val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
691 		tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
799 		tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
831 		if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) &
1084 	tmp = intel_de_read(dev_priv, UTIL_PIN_CTL);
1146 		tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans));
1316 		tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans));
1321 		if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
1354 		if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
1505 	val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
1560 	    !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))
1694 		tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
1713 		tmp = intel_de_read(dev_priv, TRANSCONF(dsi_trans));