Lines Matching refs:intel_de_read
273 lane_mask = intel_de_read(i915, PORT_TX_DFLEXDPSP(tc->phy_fia));
288 pin_mask = intel_de_read(i915, PORT_TX_DFLEXPA1(tc->phy_fia));
305 val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port));
401 val = intel_de_read(i915, PORT_TX_DFLEXDPMLE1(tc->phy_fia));
497 fia_isr = intel_de_read(i915, PORT_TX_DFLEXDPSP(tc->phy_fia));
498 pch_isr = intel_de_read(i915, SDEISR);
534 val = intel_de_read(i915, PORT_TX_DFLEXDPPMS(tc->phy_fia));
553 val = intel_de_read(i915, PORT_TX_DFLEXDPCSSS(tc->phy_fia));
578 val = intel_de_read(i915, PORT_TX_DFLEXDPCSSS(tc->phy_fia));
735 val = intel_de_read(i915, PORT_TX_DFLEXDPSP(FIA1));
782 cpu_isr = intel_de_read(i915, GEN11_DE_HPD_ISR);
783 pch_isr = intel_de_read(i915, SDEISR);
812 val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port));
845 val = intel_de_read(i915, DDI_BUF_CTL(port));
970 pica_isr = intel_de_read(i915, PICAINTERRUPT_ISR);
971 pch_isr = intel_de_read(i915, SDEISR);
994 return intel_de_read(i915, reg) & XELPDP_TCSS_POWER_STATE;
1022 val = intel_de_read(i915, reg);
1066 val = intel_de_read(i915, reg);
1082 return intel_de_read(i915, reg) & XELPDP_TC_PHY_OWNERSHIP;
1459 return intel_de_read(i915, DDI_BUF_CTL(dig_port->base.port)) &