i915/display/intel_display_power_well.c

295 	ret = intel_de_read(dev_priv, regs->bios) & req_mask ? 1 : 0;
296 	ret |= intel_de_read(dev_priv, regs->driver) & req_mask ? 2 : 0;
298 		ret |= intel_de_read(dev_priv, regs->kvmr) & req_mask ? 4 : 0;
299 	ret |= intel_de_read(dev_priv, regs->debug) & req_mask ? 8 : 0;
321 	wait_for((disabled = !(intel_de_read(dev_priv, regs->driver) &
589 	val = intel_de_read(dev_priv, regs->driver);
599 		val |= intel_de_read(dev_priv, regs->bios);
607 		      (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC9),
610 		      intel_de_read(dev_priv, DC_STATE_EN) &
614 		      intel_de_read(dev_priv, HSW_PWR_WELL_CTL2) &
634 		      intel_de_read(dev_priv, DC_STATE_EN) &
662 		v = intel_de_read(dev_priv, DC_STATE_EN);
713 	val = intel_de_read(i915, DC_STATE_EN) & gen9_dc_mask(i915);
757 	val = intel_de_read(dev_priv, DC_STATE_EN);
807 		      (intel_de_read(dev_priv, DC_STATE_EN) &
834 		      (intel_de_read(dev_priv, UTIL_PIN_CTL) &
839 		      (intel_de_read(dev_priv, DC_STATE_EN) &
894 	u32 bios_req = intel_de_read(dev_priv, regs->bios);
898 		u32 drv_req = intel_de_read(dev_priv, regs->driver);
948 	return ((intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
949 		(intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
1047 	if ((intel_de_read(dev_priv, TRANSCONF(PIPE_A)) & TRANSCONF_ENABLE) == 0)
1049 	if ((intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE) == 0)
1063 	return intel_de_read(dev_priv, TRANSCONF(PIPE_A)) & TRANSCONF_ENABLE &&
1064 		intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE;
1199 		u32 val = intel_de_read(dev_priv, DPLL(pipe));
1358 		    (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1405 			intel_de_read(dev_priv, DISPLAY_PHY_STATUS) & phy_status_mask,
1841 	return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(dev_priv, aux_ch)) &
1875 	return intel_de_read(dev_priv, XE2LPD_PICA_PW_CTL) &