Lines Matching refs:intel_de_read
1063 state = intel_de_read(dev_priv, reg) & DBUF_POWER_STATE;
1171 u32 val = intel_de_read(dev_priv, LCPLL_CTL);
1198 I915_STATE_WARN(dev_priv, intel_de_read(dev_priv, HSW_PWR_WELL_CTL2),
1201 intel_de_read(dev_priv, SPLL_CTL) & SPLL_PLL_ENABLE,
1204 intel_de_read(dev_priv, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE,
1207 intel_de_read(dev_priv, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE,
1210 intel_de_read(dev_priv, PP_STATUS(0)) & PP_ON,
1213 intel_de_read(dev_priv, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
1217 intel_de_read(dev_priv, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
1220 intel_de_read(dev_priv, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
1223 (intel_de_read(dev_priv, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM),
1226 intel_de_read(dev_priv, PCH_GTC_CTL) & PCH_GTC_ENABLE,
1242 return intel_de_read(dev_priv, D_COMP_HSW);
1244 return intel_de_read(dev_priv, D_COMP_BDW);
1274 val = intel_de_read(dev_priv, LCPLL_CTL);
1280 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) &
1284 val = intel_de_read(dev_priv, LCPLL_CTL);
1317 val = intel_de_read(dev_priv, LCPLL_CTL);
1340 val = intel_de_read(dev_priv, LCPLL_CTL);
1350 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) &
1771 u32 status = intel_de_read(dev_priv, DPLL(PIPE_A));
1802 u32 status = intel_de_read(dev_priv, DPIO_PHY_STATUS);
1839 intel_de_read(dev_priv, DPIO_CTL) & DPIO_CMNRST)